US20080290557A1 - Mold with compensating base - Google Patents

Mold with compensating base Download PDF

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Publication number
US20080290557A1
US20080290557A1 US12/154,726 US15472608A US2008290557A1 US 20080290557 A1 US20080290557 A1 US 20080290557A1 US 15472608 A US15472608 A US 15472608A US 2008290557 A1 US2008290557 A1 US 2008290557A1
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Prior art keywords
packaging substrate
integrated circuit
circuit die
mold portion
clamping
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Granted
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US12/154,726
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US8163220B2 (en
Inventor
Michael J. Hundt
Tiao Zhou
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STMicroelectronics lnc USA
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STMicroelectronics lnc USA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S425/00—Plastic article or earthenware shaping or treating: apparatus
    • Y10S425/044—Rubber mold

Abstract

The bottom mold portion for a transfer molding system is covered with a deformable material. During mold clamping, the deformable material contacts the bottom surface of the packaging substrate on which the integrated circuit die is mounted. Deformation of this relatively soft covering on the bottom mold portion accommodates thickness variations in the packaging substrate, as well as non-planarity of the adhesive layer between the integrated circuit die and packaging substrate in exposed active area integrated circuits.

Description

  • This application is a divisional of prior U.S. patent application Ser. No. 10/961,910 filed on Oct. 8, 2004, which is a divisional of U.S. patent application Ser. No. 10/151,323 filed on May 20, 2002.
    • TECHNICAL FIELD OF THE INVENTION
  • The present invention is directed, in general, to transfer molding during integrated circuit packaging and, more specifically, to transfer molding tolerating localized lead frame or packaging substrate thickness variations.
    • BACKGROUND OF THE INVENTION
  • Conventional transfer molding systems employed for integrated circuit packaging generally utilize hardened steel mold surfaces to clamp onto the lead frame or packaging substrate, forming the mold cavity as shown in FIG. 4. Mold system 400 includes a lower mold portion 401 and an upper mold portion 402 receiving an integrated circuit die 403 affixed to a packaging substrate 404 by an adhesive, electrically connected by wire bonds to conductive traces on the packaging substrate.
  • The lower mold portion 401 has an upper surface that contacts the bottom surface of packaging substrate 404 while the upper mold portion 402 defines a cavity 405 around integrated circuit die 403, the wire bonds and a portion of the upper surface of packaging substrate 404, contacting the upper surface of the packaging substrate 404 only around a periphery of the cavity 405. Once the mold portions 401 and 402 are assembled with an integrated circuit die 403 and packaging substrate 404 received therein as shown in FIG. 4, encapsulating material such as epoxy or thermosetting resin is injected into the cavity 405, forming the packaged integrated circuit.
  • Such transfer molding systems, however, are poorly suited where the lead frame or packaging substrate has local thickness variations. Either leakage of the encapsulating material or damage to the packaging substrate 404 (e.g., damage to the conductive traces thereon) may result.
  • As with the example of FIG. 1, encapsulating material is injected into the cavity 205 to adhere to and harden around portions of the integrated circuit die 203, any wire bonds, and the packaging substrate 204 exposed to the cavity 205. However, a portion of the upper mold portion 202 in mold system 200 contacts the active area 206 of the integrated circuit die 203 to prevent injected encapsulating material from contacting that surface 206. The active area 206 is thus left exposed after packaging.
  • In the present invention, lower mold portion 201 comprises hardened steel 207 covered by a relatively soft, deformable material 208. Therefore non-planarity of the adhesive between the integrated circuit die 203 and the packaging substrate 204, and consequent “tilt” of the integrated circuit die 203 with respect to the packaging substrate 204 and the surface of upper mold portion 202 that contacts the active area 206, is compensated by deformation of the relatively soft material 208 (and possibly minor, localized deformation of packaging substrate 204). No gap between the active area 206 and upper mold surface contacting the active area remains into which injected encapsulating material may flow.
    • SUMMARY OF THE INVENTION
  • To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in transfer molding system, a bottom mold portion that is covered with a deformable material. During mold clamping, the deformable material contacts the bottom surface of the packaging substrate on which the integrated circuit die is mounted. Deformation of this relatively soft covering on the bottom mold portion accommodates thickness variations in the packaging substrate, as well as non-planarity of the adhesive layer between the integrated circuit die and packaging substrate in exposed active area integrated circuits.
  • The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
  • Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:
  • FIG. 1 depicts a transfer molding system that tolerates thickness variations in the lead frame or packaging substrate according to one embodiment of the present invention;
  • FIG. 2 depicts a transfer molding system that tolerates non-planarity of the exposed active area integrated circuit die when mounted on the lead frame or packaging substrate according to one embodiment of the present invention;
  • FIG. 3 depicts a lower mold portion for a transfer molding system according to an alternative embodiment of the present invention;
  • FIG. 4 depicts a transfer molding system; and
  • FIG. 5 depicts a transfer molding system for exposed active area integrated circuits.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIGS. 1 through 3, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged device.
  • FIG. 1 depicts a transfer molding system that tolerates thickness variations in the lead frame or packaging substrate according to one embodiment of the present invention. Mold system 100 includes a lower mold portion 101 and an upper mold portion 102 that are adapted to receive, between the two portions 101 and 102, an integrated circuit die 103 affixed to a packaging substrate 104 (e.g., a plastic sheet) by an adhesive such as epoxy. In the example shown, wire bonds electrically connect integrated circuit die 103 to conductive traces on the packaging substrate 104.
  • The lower mold portion 101 has an upper surface that contacts the bottom surface of packaging substrate 104, while the upper mold portion 102 defines a cavity 105 around integrated circuit die 103, the wire bonds and at least a portion of the upper surface of packaging substrate 104. The upper mold portion 102 contacts the upper surface of the packaging substrate 104 only around a periphery of the cavity 105. The lower mold portion 101 contacts the bottom surface of the packaging substrate 104 over at least an area corresponding to the contact area of upper mold portion 102 on the upper surface of the packaging substrate 104.
  • Once the mold portions 101 and 102 are assembled with an integrated circuit die 103 and packaging substrate 104 received therein as shown in FIG. 1, encapsulating material such as epoxy or thermosetting resin is injected into the cavity 105 via injection conduits (not shown) through the upper mold portion 102 to cavity 105. The injected encapsulating material adheres to and hardens around the integrated circuit die 103, any wire bonds, and the portion of packaging substrate 104 underlying cavity 105, forming the packaged integrated circuit.
  • In the present invention, the lower mold portion 101 includes hardened steel 107 covered by an elastomeric, deformable material 108 (e.g., neoprene rubber). The deformable material 108 contacts the bottom surface of packaging substrate 104 during mold clamping (closure), and compensates for non-planarity (e.g., general or localized thickness variations) of the packaging substrate 104.
  • FIG. 2 depicts a transfer molding system that tolerates non-planarity of the exposed active area integrated circuit die when mounted on the lead frame or packaging substrate according to one embodiment of the present invention. Mold system 200 for packaging exposed active area integrated circuits includes lower and upper mold portions 201 and 202, respectively, receiving an integrated circuit die 203 mounted on a packaging substrate 204. Upper mold portion 202 defines a cavity 205 around integrated circuit die 203 and a portion of packaging substrate 204. Wire bonds (not shown) may optionally connect the integrated circuit die 203 to conductive traces on the packaging substrate 204.
  • As with the example of FIG. 1, encapsulating material is injected into the cavity 205 to adhere to and harden around portions of the integrated circuit die 203, any wire bonds, and the packaging substrate 204 without or exposed to the cavity 205. However, a portion of the upper mold portion 202 in mold system 200 contacts the active area 206 of the integrated circuit die 203 to prevent injected encapsulating material from contacting that surface 206. The active area 206 is thus left exposed after packaging.
  • In the present invention, lower mold portion 201 comprises hardened steel 207 covered by a relatively soft, deformable 208. Therefore non-planarity of the adhesive between the integrated circuit die 203 and the packaging substrate 204, and consequent “tilt” of the integrated circuit die 203 with respect to the packaging substrate 204 and the surface of upper mold portion 202 that contacts the active area 206, is compensated by deformation of the relatively soft material 208 (and possibly minor, localized deformation of packaging substrate 204). No gap between the active area 206 and upper mold surface contacting the active area remains into which injected encapsulating material may flow.
  • FIG. 3 depicts a lower mold portion for a transfer molding system according to an alternative embodiment of the present invention. To promote adaptation of thickness variation or deformation required in order to accommodate non-planar adhesive layers, the lower mold portion 301 may optionally comprise a steel base 307 covered with a deformable material 308 having a variable upper surface.
  • Although the present invention has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, enhancements, nuances, gradations, lesser forms, alterations, revisions, improvements and knock-offs of the invention disclosed herein may be made without departing from the spirit and scope of the invention in its broadest form.

Claims (15)

1.-14. (canceled)
15. A method of packaging integrated circuits comprising:
clamping an upper mold portion and a lower mold portion around an integrated circuit die mounted on an upper surface of a packaging substrate, the upper and lower mold portions contacting upper and lower surfaces of the packaging substrate, respectively, during clamping,
bringing a surface on a projection within the upper mold portion into contact with an active area of the integrated circuit die during mold clamping, wherein the contacted active area remains exposed after encapsulation
wherein a deformable material on a surface of the lower mold portion that contacts the bottom surface of the packaging substrate deforms during mold clamping as necessary to at least partially compensate for non-planarity of either the packaging substrate or an adhesive between the integrated circuit die and the packaging substrate.
16. The method according to claim 15, wherein the deformable material deforms during mold clamping by an amount sufficient to accommodate thickness variations in the packaging substrate.
17. The method according to claim 15, wherein the deformable material deforms during mold clamping by an amount sufficient to accommodate non-planarity of an adhesive between the integrated circuit die and the packaging substrate.
18. The method according to claim 15, further comprising:
receiving the integrated circuit die within a cavity in the upper mold portion during clamping, wherein the upper mold portion contacts the upper surface of the packaging substrate around a periphery of the cavity during mold clamping.
19. (canceled)
20. The method according to claim 19, wherein the deformable material deforms during mold clamping by an amount sufficient to accommodate thickness variations in the packaging substrate, non-planarity of an adhesive between the integrated circuit die and the packaging substrate, or both.
21. A method of packaging integrated circuits comprising:
clamping an upper mold portion and a lower mold portion around an integrated circuit die mounted on an upper surface of a packaging substrate, the upper and lower mold portions contacting upper and lower surfaces of the packaging substrate, respectively, and a surface on a projection within the upper mold portion contacting an active area of the integrated circuit die during clamping, wherein the contacted active area remains exposed after encapsulation,
wherein a deformable material on a surface of the lower mold portion contacts the bottom surface of the packaging substrate during mold clamping, the deformable material having a variable an upper surface contacting the bottom of the packaging substrate that is deformed during mold clamping as necessary to at least partially compensate for non-planarity of either the packaging substrate or an adhesive between the integrated circuit die and the packaging substrate.
22. The method according to claim 21, wherein the deformable material deforms during mold clamping by an amount sufficient to accommodate thickness variations in the packaging substrate.
23. The method according to claim 21, wherein the deformable material deforms during mold clamping by an amount sufficient to accommodate non-planarity of an adhesive between the integrated circuit die and the packaging substrate.
24. The method according to claim 21, further comprising:
receiving the integrated circuit die within a cavity in the upper mold portion during clamping, wherein the upper mold portion contacts the upper surface of the packaging substrate around a periphery of the cavity during mold clamping.
25. The method according to claim 24, wherein the deformable material deforms during mold clamping by an amount sufficient to accommodate thickness variations in the packaging substrate, non-planarity of an adhesive between the integrated circuit die and the packaging substrate, or both.
26. A method comprising:
receiving a substrate between a first mold portion, and a second mold portion,
the first mold portion having a surface on a projection thereon contacting an active area of the substrate during clamping, wherein the contacted active area remains exposed after encapsulation,
the second mold portion having a base and a deformable material on at least a portion of the base, the deformable material having a surface including a region that contacts at least a portion of the substrate during mold clamping and that is variable within the region that contacts the substrate during mold clamping.
27. The method of claim 26, wherein the deformable material compensates for at least one of a variable thickness of the substrate and a non-planarity of an adhesive between an integrated circuit die and the substrate.
28. The method of claim 27, wherein the first mold portion includes a cavity capable of receiving an integrated circuit die mounted on the substrate, the first mold portion contacting a surface of the substrate around a periphery of the cavity during mold clamping.
US12/154,726 2002-05-20 2008-05-27 Method of packaging integrated circuits Expired - Lifetime US8163220B2 (en)

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US12/154,726 US8163220B2 (en) 2002-05-20 2008-05-27 Method of packaging integrated circuits

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US10/151,323 US6817854B2 (en) 2002-05-20 2002-05-20 Mold with compensating base
US10/961,910 US20050082718A1 (en) 2002-05-20 2004-10-08 Mold with compensating base
US12/154,726 US8163220B2 (en) 2002-05-20 2008-05-27 Method of packaging integrated circuits

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US12/154,726 Expired - Lifetime US8163220B2 (en) 2002-05-20 2008-05-27 Method of packaging integrated circuits

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US7241414B2 (en) * 2004-06-25 2007-07-10 Asm Technology Singapore Pte Ltd. Method and apparatus for molding a semiconductor device
US8252615B2 (en) * 2006-12-22 2012-08-28 Stats Chippac Ltd. Integrated circuit package system employing mold flash prevention technology
US8852986B2 (en) * 2007-05-16 2014-10-07 Stats Chippac Ltd. Integrated circuit package system employing resilient member mold system technology
US20120090776A1 (en) * 2010-10-14 2012-04-19 Roger Wen-Yi Hsu Method and apparatus for curved circularly polarized lens
JP5971270B2 (en) * 2014-02-27 2016-08-17 トヨタ自動車株式会社 Semiconductor device manufacturing method and manufacturing apparatus

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US20030214074A1 (en) 2003-11-20
US8163220B2 (en) 2012-04-24
US6817854B2 (en) 2004-11-16
US20050082718A1 (en) 2005-04-21

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