US20080294831A1 - Method for link bandwidth management - Google Patents
Method for link bandwidth management Download PDFInfo
- Publication number
- US20080294831A1 US20080294831A1 US12/186,408 US18640808A US2008294831A1 US 20080294831 A1 US20080294831 A1 US 20080294831A1 US 18640808 A US18640808 A US 18640808A US 2008294831 A1 US2008294831 A1 US 2008294831A1
- Authority
- US
- United States
- Prior art keywords
- bandwidth
- speed
- width
- link
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000008859 change Effects 0.000 claims abstract description 56
- 238000004891 communication Methods 0.000 claims abstract description 3
- 238000012544 monitoring process Methods 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims 4
- 230000004913 activation Effects 0.000 claims 3
- 230000007704 transition Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000977 initiatory effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
Definitions
- the present invention relates to a method for link bandwidth management, and more particularly to a method for link bandwidth management applied to a PCI express bus.
- FIG. 1 it is a computer system architecture.
- CPU 20 , memory 22 , and graphic chip 24 work very closely and they need to have faster data access to each other.
- requests and responses issued from the three devices are all controlled and managed by the north bridge chip 26 .
- the north bridge chip 26 is tied to the south bridge chip 28 , which routes traffic from the different I/O devices on the system, such as hard disk drive 30 , optical disk drive 32 , and Ethernet port 34 . The traffic from these devices is routed through the south bridge chip 28 to the north bridge chip 26 and then onto the CPU and/or memory 22 .
- a new PCI express bus specification was finished and then a PCI express bus 40 communicating the graphic chip 24 and the north bridge chip 26 was implemented in the computer system.
- a connection between a graphic chip 24 and the north bridge chip 26 on a PCI express bus 40 is called a link.
- Each link is composed of one or more lanes, and each lane is capable of transmitting one byte at a time in both directions. That means each lane is itself composed of one pair of signals: send and receive.
- PCI express packets which are composed of multiple bytes
- one device using a one-lane link on the transmitting end must break down each packet into a series of bytes, and then transmit the bytes in rapid succession. The device on the receiving end has to collect all of the bytes and then reassemble them into the original packet.
- PCI express bus 40 features is the ability to aggregate multiple individual lanes together to form a signal link. In other words, two lanes could be coupled together to form a single link capable of transmitting two bytes at a time, this doubling the link bandwidth. Also, four lanes, or eight lanes could be combined to form a single link. A link composes of a single lane is called an x1 link; a link composed of two lanes is called x2 link; a link composed of four lanes is called x4 link, etc.
- PCI express bus 40 supports x1, x2, x4, x8, x12, x16, and x32 link widths. Furthermore, PCI express bus supports two different link speeds. One is called PCI express generation 1 (Gen 1) having a clock data rate of 2.5 GHz, and the other is called PCI express generation 2 (Gen 2) having a clock data rate of 5 GHz.
- link width/speed is reset when link is down or initial power up.
- the first state is called link down state or initial power up state 50 , which is set at the time of powering up the computer system.
- link down state or initial power up state 50 which is set at the time of powering up the computer system.
- maximum link width/speed state 52 which is activated by two devices connected by the PCI express bus.
- two devices individually set the maximum link widths/speeds they support for transmitting and receiving data through the bus.
- the state changes to negotiate maximum allowed link width/speed state 54 .
- two devices negotiate an allowed maximum link width/speed according to the physical layer electrical characteristic, and channel features of both devices.
- the respective maximum link bandwidths of graphic chip and north bridge chip are x32/Gen1 and x16/Gen2.
- the maximum allowed link width/speed of PCI express bus is x16/Gen1.
- link normal operation state 58 which means the maximum allowed link bandwidth is the final operation bandwidth for the two devices to communicate normally with each other.
- the present invention provides a method for link bandwidth management targeted to achieve both good performance and high power efficiency for any specific application and to have a fast link bandwidth change for ameliorating the above-mentioned defects of conventional technology.
- the present invention provides a method for link bandwidth management between two devices in communication through a bus in a computer system, which includes: monitoring whether a change condition of the bus having a link is activated; changing a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated; and causing the bus to operate at the target bandwidth without disabling the link or powering down the computer system.
- FIG. 1 schematically shows a computer system architecture
- FIG. 2 is a scheme illustrating a conventional link width/speed negotiation sequence
- FIG. 3 is a block diagram schematically illustrating a link bandwidth management sequence of according to an embodiment of the present invention
- FIG. 4 is a scheme illustrating a logic idle calculation based on a hardware autonomous bandwidth mechanism according to an embodiment of the present invention
- FIG. 5 is a scheme illustrating a hardware autonomous bandwidth negotiation priority varying with an option according to an embodiment of the present invention.
- FIG. 6 is a scheme illustrating a link unreliable management process according to an embodiment of the present invention.
- the PCI express bus changes link width/speed when a change condition is activated.
- the change condition according to the invention can be a hardware autonomous change, a software-directed change, or an unreliable change; and each change includes link width change and link speed change.
- the software-directed change includes software-directed speed change 104 and software-directed width change 122 .
- the software application stores a required link width/speed for the PCI express bus in a register of a north bridge chip.
- the link width/speed need to be changed if the link width/speed stored in the register is different from the present link width/speed. For example, if the initial link width/speed of the PCI express bus is link A/B 100 , and the link width/speed stored in a register by a software application is link A/C, the software-directed speed change 104 will be executed. Link speed B will be changed to link speed C as a result of negotiation between two ends of the bus (North bride and Graphic Chip). Once the target link speed C passes subsequent failure speed management 110 and unreliable speed management 112 , the link width/speed of the PCI express bus will finally change to link A/C 150 , and the link is supposed to attain target link speed C whenever possible.
- link width/speed of PCI express bus is link A/B 100
- link width/speed stored in a register by a software application is link D/B
- the software-directed width change will be executed.
- Link width A will be changed to link width D as a result of negotiation between two ends of the bus (North bride and Graphic Chip).
- the link width/speed of PCI express bus will be finally changed to link D/B 160 , and the link is supposed to attain target link width D whenever possible.
- FIG. 4 depicts a state diagram schematically illustrating the hardware autonomous change according to an embodiment of the present invention.
- a north bridge chip monitors a logic idle symbol and counts the number of continuous logic idle symbols in a transmitter and a receiver of the north bridge chip. If the continuous logic idle symbol number is greater than a first programmable limit, the north bridge chip will enter calculate state 132 .
- north bridge chip In calculate state 132 , north bridge chip periodically monitors its logic idle symbol at the most busy lane in a multi-lane link (lane 0 or starting lane) and calculates a percentage of non-logic idle (PNI) to indicate link bandwidth behaviors. That PNI is OK means packet traffic is acceptable with the current link bandwidth, and the link bandwidth has no need to change. That PNI is too high means traffic is busy, and the link bandwidth needs upgrade. That PNI is too low means traffic is little, and the link bandwidth needs downgrade. For example, when PNI is greater than a second programmable value of 87.5%, the link bandwidth needs to be upgraded. When PNI is lower than a third programmable value of 12.5%, the link bandwidth needs to be downgraded. When PNI is lower than 87.5% and greater than 12.5%, it means PNI is OK and there is no need to change the link bandwidth. Therefore, the state changes from calculation state 132 to operation state 130 .
- PNI non-logic idle
- the north bridge chip may enter speed change state 134 of the bus for negotiating a target speed, and then enter speed change sequence state 136 for setting a target speed; or the north bridge chip may enter width change state 140 of the bus for negotiating a target width, and then enter width change sequence state 142 of the bus for setting a target width. After link speed or link width is changed, the north bridge chip moves back to operation state 130 of the bus with a new link bandwidth.
- speed change state 134 or width change state 140 is carried on first is based on hardware autonomous bandwidth negotiation priority as depicted in FIG. 5 .
- speed negotiation priority is higher; when the option is set to 0, width negotiation priority is higher.
- link Gen 1/x1 will be upgraded to link Gen 2/x1 first, and then the width will be upgraded from x1 to x2, x4 . . . x32, if necessary; link Gen 2/x32 will be downgraded to link Gen 2/x32 . . . x1 first, and then the speed will be downgraded to Gen 1, if necessary.
- the option can be seen as power consumption option of a link, where a wider link consumes more power than a higher speed link with a half width.
- the width of link Gen 1/x1 will be upgraded to link Gen 1/x2 . . . x32 first, and then the speed will be upgraded Gen 2/x2 . . . x32, if necessary.
- the speed of link Gen 2/x2 . . . x32 will be downgraded to link Gen 1/x2 . . . x32 first, and then the width will be downgraded to Gen 1/x1, if necessary.
- Hardware autonomous change 106 includes hardware speed change 108 and hardware width change 120 .
- Link A/B 100 will be changed to target Link A/C 150 if speed C passes subsequent failure speed management 110 and unreliable speed Management 112 .
- Link A/B 100 will be changed to target Link D/B 160 if speed C passes subsequent failure width management 126 and unreliable speed management 128 .
- FIG. 6 depicts a state diagram illustrating the unreliable change of the present invention.
- TLP Transition Layer Packet
- a limit a fourth programmable value
- the transmitter will be defined as transmitter unreliable 202 ;
- the receiver gets the same sequence number TLP and CRC (Cycle Redundancy Check) error case several times exceeding a limit (a fifth programmable value)
- the receiver will be defined as receiver unreliable 204 .
- Either transmitter unreliable 202 or receiver unreliable 204 can be seen as an unreliable link bandwidth.
- failure speed management 110 and failure width management 126 if initial link width/speed fails to operate at the negotiated target width/speed, the PCI express bus will remain at the initial width/speed. The failed width/speed will be recorded, and either software or hardware speed transition to that bandwidth is unattainable.
- unreliable speed management 112 and unreliable width management 128 if the target link width/speed is detected as an unreliable link width/speed, the PCI express bus will remain at the initial width/speed. The unreliable width/speed will be recorded, and either software or hardware speed transition to that bandwidth is unattainable.
- this invention can resolve the problems of prior art. Different link bandwidths can be set for different applications, which can help to achieve both good performance and power saving. Another problem resolved is that, for bandwidth change, there is no need to enter link down state, or device re-initialization/configuration state. Therefore, the transition time between different bandwidths is much shortened.
Abstract
A method for link bandwidth management between two devices in communication through a bus in a computer system. Whether a change condition of the bus having a link is activated is monitored. Change a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated. The bus will operate at the target bandwidth without disabling the link or powering down the computer system if subsequent failure speed management and unreliable speed management have passed.
Description
- This patent application is a continuation application (CA) of U.S. patent application Ser. No. 10/490,349, filed Jul. 20, 2006, and now pending. The contents of the related patent application are incorporated herein by reference.
- The present invention relates to a method for link bandwidth management, and more particularly to a method for link bandwidth management applied to a PCI express bus.
- As shown in
FIG. 1 , it is a computer system architecture. In a modern computer system,CPU 20,memory 22, andgraphic chip 24 work very closely and they need to have faster data access to each other. As a result, requests and responses issued from the three devices are all controlled and managed by thenorth bridge chip 26. Thenorth bridge chip 26 is tied to thesouth bridge chip 28, which routes traffic from the different I/O devices on the system, such ashard disk drive 30,optical disk drive 32, and Ethernetport 34. The traffic from these devices is routed through thesouth bridge chip 28 to thenorth bridge chip 26 and then onto the CPU and/ormemory 22. - In 2002, a new PCI express bus specification was finished and then a
PCI express bus 40 communicating thegraphic chip 24 and thenorth bridge chip 26 was implemented in the computer system. Generally speaking, a connection between agraphic chip 24 and thenorth bridge chip 26 on aPCI express bus 40 is called a link. Each link is composed of one or more lanes, and each lane is capable of transmitting one byte at a time in both directions. That means each lane is itself composed of one pair of signals: send and receive. In order to transmit PCI express packets, which are composed of multiple bytes, one device using a one-lane link on the transmitting end must break down each packet into a series of bytes, and then transmit the bytes in rapid succession. The device on the receiving end has to collect all of the bytes and then reassemble them into the original packet. - One of PCI
express bus 40 features is the ability to aggregate multiple individual lanes together to form a signal link. In other words, two lanes could be coupled together to form a single link capable of transmitting two bytes at a time, this doubling the link bandwidth. Also, four lanes, or eight lanes could be combined to form a single link. A link composes of a single lane is called an x1 link; a link composed of two lanes is called x2 link; a link composed of four lanes is called x4 link, etc.PCI express bus 40 supports x1, x2, x4, x8, x12, x16, and x32 link widths. Furthermore, PCI express bus supports two different link speeds. One is called PCI express generation 1 (Gen 1) having a clock data rate of 2.5 GHz, and the other is called PCI express generation 2 (Gen 2) having a clock data rate of 5 GHz. - As depicted in
FIG. 2 , it is a conventional method for devices connecting to a PCI express bus to negotiate a link width/speed. Conventionally, link width/speed is reset when link is down or initial power up. The first state is called link down state or initial power upstate 50, which is set at the time of powering up the computer system. Then, the state changes to set maximum link width/speed state 52, which is activated by two devices connected by the PCI express bus. In thestate 52, two devices individually set the maximum link widths/speeds they support for transmitting and receiving data through the bus. Then, the state changes to negotiate maximum allowed link width/speed state 54. Instate 54, two devices negotiate an allowed maximum link width/speed according to the physical layer electrical characteristic, and channel features of both devices. For example, instate 52, the respective maximum link bandwidths of graphic chip and north bridge chip are x32/Gen1 and x16/Gen2. After negotiation process ofstate 54, the maximum allowed link width/speed of PCI express bus is x16/Gen1. After the maximum allowed link width/speed is determined, there is generally also device initiation/configuration state 56 for devices to be useful in a real application. Afterstate 56, it goes to linknormal operation state 58, which means the maximum allowed link bandwidth is the final operation bandwidth for the two devices to communicate normally with each other. - According to
FIG. 2 , to change link width/speed, it should disable the link or power down the computer system for the state to go from linknormal operation state 58, through link down/initial power upstate 50, set maximum link width/speed state 52 negotiate maximum allowed width/speed state 54, then to device initiation/configuration state 56. Since the execution of link down/initial power upstate 50 and device initial/configuration state 56 to change link width/speed is complicated and time consuming. In real practice, the maximum allowed speed/width is always set for all applications. In other words, link bandwidth never changes, and there is no bandwidth management needed in the prior art. In other cases, the final operation bandwidth is always the maximum allowed link width/speed even if the link bandwidth is to be changed. Moreover, for bandwidth eager applications, e.g. 3D game software, the preset bandwidth may be too small; and for applications with few packets traffic, e.g. document software, the preset bandwidth is often too luxury for them, which in most cases means power waste. - The present invention provides a method for link bandwidth management targeted to achieve both good performance and high power efficiency for any specific application and to have a fast link bandwidth change for ameliorating the above-mentioned defects of conventional technology.
- The present invention provides a method for link bandwidth management between two devices in communication through a bus in a computer system, which includes: monitoring whether a change condition of the bus having a link is activated; changing a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated; and causing the bus to operate at the target bandwidth without disabling the link or powering down the computer system.
- The above contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
-
FIG. 1 schematically shows a computer system architecture; -
FIG. 2 is a scheme illustrating a conventional link width/speed negotiation sequence; -
FIG. 3 is a block diagram schematically illustrating a link bandwidth management sequence of according to an embodiment of the present invention; -
FIG. 4 is a scheme illustrating a logic idle calculation based on a hardware autonomous bandwidth mechanism according to an embodiment of the present invention; -
FIG. 5 is a scheme illustrating a hardware autonomous bandwidth negotiation priority varying with an option according to an embodiment of the present invention; and -
FIG. 6 is a scheme illustrating a link unreliable management process according to an embodiment of the present invention. - As depicted in
FIG. 3 , it is an embodiment of link bandwidth management a PCI express bus according to the present invention. In the embodiment, the PCI express bus changes link width/speed when a change condition is activated. The change condition according to the invention can be a hardware autonomous change, a software-directed change, or an unreliable change; and each change includes link width change and link speed change. - As depicted in
FIG. 3 , the software-directed change includes software-directedspeed change 104 and software-directedwidth change 122. When a computer system is executing a software application, the software application stores a required link width/speed for the PCI express bus in a register of a north bridge chip. The link width/speed need to be changed if the link width/speed stored in the register is different from the present link width/speed. For example, if the initial link width/speed of the PCI express bus is link A/B 100, and the link width/speed stored in a register by a software application is link A/C, the software-directedspeed change 104 will be executed. Link speed B will be changed to link speed C as a result of negotiation between two ends of the bus (North bride and Graphic Chip). Once the target link speed C passes subsequentfailure speed management 110 andunreliable speed management 112, the link width/speed of the PCI express bus will finally change to link A/C 150, and the link is supposed to attain target link speed C whenever possible. - Similarly, if the initial link width/speed of PCI express bus is link A/
B 100, and the link width/speed stored in a register by a software application is link D/B, the software-directed width change will be executed. Link width A will be changed to link width D as a result of negotiation between two ends of the bus (North bride and Graphic Chip). Once the target link width D passes subsequentfailure width management 126 andunreliable width management 128, the link width/speed of PCI express bus will be finally changed to link D/B 160, and the link is supposed to attain target link width D whenever possible. -
FIG. 4 depicts a state diagram schematically illustrating the hardware autonomous change according to an embodiment of the present invention. Inoperation state 130, a north bridge chip monitors a logic idle symbol and counts the number of continuous logic idle symbols in a transmitter and a receiver of the north bridge chip. If the continuous logic idle symbol number is greater than a first programmable limit, the north bridge chip will enter calculatestate 132. - In calculate
state 132, north bridge chip periodically monitors its logic idle symbol at the most busy lane in a multi-lane link (lane 0 or starting lane) and calculates a percentage of non-logic idle (PNI) to indicate link bandwidth behaviors. That PNI is OK means packet traffic is acceptable with the current link bandwidth, and the link bandwidth has no need to change. That PNI is too high means traffic is busy, and the link bandwidth needs upgrade. That PNI is too low means traffic is little, and the link bandwidth needs downgrade. For example, when PNI is greater than a second programmable value of 87.5%, the link bandwidth needs to be upgraded. When PNI is lower than a third programmable value of 12.5%, the link bandwidth needs to be downgraded. When PNI is lower than 87.5% and greater than 12.5%, it means PNI is OK and there is no need to change the link bandwidth. Therefore, the state changes fromcalculation state 132 tooperation state 130. - When PNI is too high or too low based on above method, either a speed or width change needs to be executed. The north bridge chip may enter
speed change state 134 of the bus for negotiating a target speed, and then enter speedchange sequence state 136 for setting a target speed; or the north bridge chip may enterwidth change state 140 of the bus for negotiating a target width, and then enter width change sequence state 142 of the bus for setting a target width. After link speed or link width is changed, the north bridge chip moves back tooperation state 130 of the bus with a new link bandwidth. - In addition, whether
speed change state 134 orwidth change state 140 is carried on first is based on hardware autonomous bandwidth negotiation priority as depicted inFIG. 5 . When an option is set to 1, speed negotiation priority is higher; when the option is set to 0, width negotiation priority is higher. For example, if the option is set to 1, linkGen 1/x1 will be upgraded to link Gen 2/x1 first, and then the width will be upgraded from x1 to x2, x4 . . . x32, if necessary; link Gen 2/x32 will be downgraded to link Gen 2/x32 . . . x1 first, and then the speed will be downgraded toGen 1, if necessary. Here the option can be seen as power consumption option of a link, where a wider link consumes more power than a higher speed link with a half width. - Similarly, if the option is set to 0, the width of
link Gen 1/x1 will be upgraded to linkGen 1/x2 . . . x32 first, and then the speed will be upgraded Gen 2/x2 . . . x32, if necessary. If the option is set to 1, the speed of link Gen 2/x2 . . . x32 will be downgraded to linkGen 1/x2 . . . x32 first, and then the width will be downgraded toGen 1/x1, if necessary. - Please refer again to
FIG. 3 . Hardwareautonomous change 106 includeshardware speed change 108 andhardware width change 120. Afterhardware speed change 108 is completed, Link A/B 100 will be changed to target Link A/C 150 if speed C passes subsequentfailure speed management 110 andunreliable speed Management 112. Similarly, afterhardware width change 120 is completed, Link A/B 100 will be changed to target Link D/B 160 if speed C passes subsequentfailure width management 126 andunreliable speed management 128. -
FIG. 6 depicts a state diagram illustrating the unreliable change of the present invention. When the PCI express bus operates at specified link width/speed 200, if same TLP (Transition Layer Packet) has been resent several times exceeding a limit (a fourth programmable value) by a transmitter and still fails to be ACKed (Acknowledged) by a receiver, the transmitter will be defined as transmitter unreliable 202; If the receiver gets the same sequence number TLP and CRC (Cycle Redundancy Check) error case several times exceeding a limit (a fifth programmable value), the receiver will be defined as receiver unreliable 204. Either transmitter unreliable 202 or receiver unreliable 204 can be seen as an unreliable link bandwidth. - Since a bandwidth is defined with both a link speed and a link width, when a specific bandwidth is unreliable, it cannot say if the link speed is too high, or the link width is too large. Here another option (speed unreliable option) is added. When the speed unreliable option is 0, transmitter unreliable 202 or receiver unreliable 204 will enter width
unreliable state 208, and then enter widthtransition process state 210 for changing link width. Then the PCI express bus will operate at the new link width. When the speed unreliable option is 1, transmitter unreliable 202 or receiver unreliable 204 will enter speedunreliable state 206, and then enter speedtransition process state 212 for changing link speed. Then the PCI express bus will operate at the new link speed. - Please again refer to
FIG. 3 . Ifunreliable speed change 120 is happening, the PCI express bus with Link A/B 100 will change to Link A/C 150 if the speed C passes subsequentfailure speed management 110 andunreliable speed management 112. Similarly, ifunreliable width change 124 is happening, PCI express bus with Link A/B 100 will change to Link D/B 160 if the width D passes subsequentfailure width management 126 andunreliable width management 128. - Please again refer to
FIG. 3 . Based onfailure speed management 110 andfailure width management 126, if initial link width/speed fails to operate at the negotiated target width/speed, the PCI express bus will remain at the initial width/speed. The failed width/speed will be recorded, and either software or hardware speed transition to that bandwidth is unattainable. Similarly, based onunreliable speed management 112 andunreliable width management 128, if the target link width/speed is detected as an unreliable link width/speed, the PCI express bus will remain at the initial width/speed. The unreliable width/speed will be recorded, and either software or hardware speed transition to that bandwidth is unattainable. - By introducing the method of link bandwidth management, this invention can resolve the problems of prior art. Different link bandwidths can be set for different applications, which can help to achieve both good performance and power saving. Another problem resolved is that, for bandwidth change, there is no need to enter link down state, or device re-initialization/configuration state. Therefore, the transition time between different bandwidths is much shortened.
- The present invention is intended to cover various modifications and similar arrangements included to within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Claims (12)
1. A method for link bandwidth management between two devices in communication through a bandwidth-adjustable bus in a computer system, comprising:
monitoring whether a change condition of said bus having a link is activated;
changing a bandwidth of said bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and said first speed or with said first width and a second speed when said change condition of said bus is activated; and
causing said bus to operate at said target bandwidth without disabling said link or powering down said computer system.
2. The method according to claim 1 , wherein said bus is a PCI express bus.
3. The method according to claim 1 , wherein selectable widths of said link include 1-lane width, 2-lane width, 4-lane width, 8-lane width, 16-lane width, or 32-lane width and selectable speeds of said link include a generation 1 speed having a clock data rate of 2.5 GHz and a generation 2 speed having a clock data rate of 5 GHz.
4. The method according to claim 1 , wherein said two devices are a north bridge chip and a graphic chip.
5. The method according to claim 1 , further comprising if said bus has failed to operate at said target bandwidth, causing said bus to remain operating at said original width and speed and recording said target bandwidth as an unattainable bandwidth.
6. The method according to claim 1 , further comprising if said bus operates at said target bandwidth and said target bandwidth is unreliable, causing said bus to remain operating at said original width and speed and recording said target bandwidth as an unattainable bandwidth.
7. The method according to claim 1 , wherein said change condition includes a software-directed change, a hardware autonomous change, and an unreliable change.
8. The method according to claim 7 , wherein activation of said software-directed change includes:
storing a required bandwidth data into a register when said computer system executes a software application; and
activating said software-directed change if said required bandwidth is different from said first bandwidth.
9. The method according to claim 7 , wherein activation of said hardware autonomous change includes:
calculating a percentage of non-logic idle when a number of continuous logic idle symbols in one of said two devices exceeding a first programmable limit; and
activating said hardware autonomous change if said percentage of non-logic idle is greater than a second programmable value or lower than a third programmable value.
10. The method according to claim 9 , further comprising:
changing said first bandwidth to said target bandwidth having said second width and said first speed if an option is set to a first status; and
changing said first bandwidth to said target bandwidth having said first width and said second speed if said option is set to a second status.
11. The method according to claim 7 , wherein activation of said unreliable change includes:
activating said unreliable change if a translation layer packet has been resent exceeding a fourth programmable number of times by a transmitter in one of said two devices and still fails to be acknowledged by the other of said two devices; and
activating said unreliable change if a receiver gets a translation layer packet and a cycle redundancy check error case exceeding a fifth programmable number of times.
12. The method according to claim 11 , further comprising:
changing said first bandwidth to said target bandwidth having said second width and said first speed if a speed unreliable option is set to a first status; and
changing said first bandwidth to said target bandwidth having said first width and said second speed if said speed unreliable option is set to a second status.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/186,408 US20080294831A1 (en) | 2006-07-20 | 2008-08-05 | Method for link bandwidth management |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/490,349 US7536490B2 (en) | 2006-07-20 | 2006-07-20 | Method for link bandwidth management |
US12/186,408 US20080294831A1 (en) | 2006-07-20 | 2008-08-05 | Method for link bandwidth management |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/490,349 Continuation US7536490B2 (en) | 2006-07-20 | 2006-07-20 | Method for link bandwidth management |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080294831A1 true US20080294831A1 (en) | 2008-11-27 |
Family
ID=38972699
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/490,349 Active 2026-11-17 US7536490B2 (en) | 2006-07-20 | 2006-07-20 | Method for link bandwidth management |
US12/186,408 Abandoned US20080294831A1 (en) | 2006-07-20 | 2008-08-05 | Method for link bandwidth management |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/490,349 Active 2026-11-17 US7536490B2 (en) | 2006-07-20 | 2006-07-20 | Method for link bandwidth management |
Country Status (1)
Country | Link |
---|---|
US (2) | US7536490B2 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090164684A1 (en) * | 2007-12-20 | 2009-06-25 | International Business Machines Corporation | Throttling A Point-To-Point, Serial Input/Output Expansion Subsystem Within A Computing System |
US20110161547A1 (en) * | 2009-12-24 | 2011-06-30 | Ati Technologies Ulc | Method and device for disabling a higher version of a computer bus and interconnection protocol for interoperability with a device compliant to a lower version of the computer bus and interconnection protocol |
US8437343B1 (en) | 2012-05-22 | 2013-05-07 | Intel Corporation | Optimized link training and management mechanism |
US8446903B1 (en) * | 2012-05-22 | 2013-05-21 | Intel Corporation | Providing a load/store communication protocol with a low power physical unit |
US8549205B1 (en) | 2012-05-22 | 2013-10-01 | Intel Corporation | Providing a consolidated sideband communication channel between devices |
JP2015505094A (en) * | 2011-12-21 | 2015-02-16 | インテル コーポレイション | Dynamic link width adjustment |
US8972640B2 (en) | 2012-06-27 | 2015-03-03 | Intel Corporation | Controlling a physical link of a first protocol using an extended capability structure of a second protocol |
US9261934B2 (en) | 2013-03-15 | 2016-02-16 | Intel Corporation | Dynamic response improvement of hybrid power boost technology |
US9612643B2 (en) | 2014-03-29 | 2017-04-04 | Intel Corporation | Controlling the CPU slew rates based on the battery state of charge |
US9710406B2 (en) | 2014-12-15 | 2017-07-18 | Intel Corporation | Data transmission using PCIe protocol via USB port |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7571287B2 (en) * | 2003-03-13 | 2009-08-04 | Marvell World Trade Ltd. | Multiport memory architecture, devices and systems including the same, and methods of using the same |
US8819326B1 (en) * | 2006-12-12 | 2014-08-26 | Spansion Llc | Host/client system having a scalable serial bus interface |
US7660925B2 (en) * | 2007-04-17 | 2010-02-09 | International Business Machines Corporation | Balancing PCI-express bandwidth |
US8234425B1 (en) | 2007-06-27 | 2012-07-31 | Marvell International Ltd. | Arbiter module |
US7949817B1 (en) * | 2007-07-31 | 2011-05-24 | Marvell International Ltd. | Adaptive bus profiler |
US7653773B2 (en) * | 2007-10-03 | 2010-01-26 | International Business Machines Corporation | Dynamically balancing bus bandwidth |
US8131915B1 (en) | 2008-04-11 | 2012-03-06 | Marvell Intentional Ltd. | Modifying or overwriting data stored in flash memory |
US8683085B1 (en) | 2008-05-06 | 2014-03-25 | Marvell International Ltd. | USB interface configurable for host or device mode |
US8352764B2 (en) * | 2008-09-29 | 2013-01-08 | Intel Corporation | Dynamic squelch detection power control |
CN101727419B (en) * | 2008-10-16 | 2012-08-22 | 英业达股份有限公司 | Computer capable of automatically configuring bandwidth according to types of interface expansion cards |
SG174346A1 (en) | 2009-03-19 | 2011-11-28 | Millipore Corp | Removal of microorganisms from fluid samples using nanofiber filtration media |
US8423710B1 (en) | 2009-03-23 | 2013-04-16 | Marvell International Ltd. | Sequential writes to flash memory |
US8213236B1 (en) | 2009-04-21 | 2012-07-03 | Marvell International Ltd. | Flash memory |
US8532098B2 (en) * | 2009-11-30 | 2013-09-10 | Nvidia Corporation | System and method for virtual channel communication |
US9176909B2 (en) * | 2009-12-11 | 2015-11-03 | Nvidia Corporation | Aggregating unoccupied PCI-e links to provide greater bandwidth |
US8688922B1 (en) | 2010-03-11 | 2014-04-01 | Marvell International Ltd | Hardware-supported memory management |
US8756394B1 (en) | 2010-07-07 | 2014-06-17 | Marvell International Ltd. | Multi-dimension memory timing tuner |
CN102375794B (en) * | 2010-08-18 | 2014-09-10 | 和硕联合科技股份有限公司 | Connection speed regulation method and computer system thereof |
TWI439869B (en) * | 2010-08-18 | 2014-06-01 | Pegatron Corp | Method for adjusting link speed and computer system |
CN103459006B (en) | 2011-04-01 | 2016-01-06 | Emd密理博公司 | Composite structure containing nanofiber |
US8539132B2 (en) * | 2011-05-16 | 2013-09-17 | Qualcomm Innovation Center, Inc. | Method and system for dynamically managing a bus of a portable computing device |
EP2685760B1 (en) * | 2011-07-27 | 2018-04-04 | Huawei Technologies Co., Ltd. | Device, link energy management method and link energy management system for peripheral component interconnect (pci) express |
WO2012109857A1 (en) * | 2011-07-29 | 2012-08-23 | 华为技术有限公司 | Bandwidth adjustment method, bus controller and signal converter |
US9330031B2 (en) | 2011-12-09 | 2016-05-03 | Nvidia Corporation | System and method for calibration of serial links using a serial-to-parallel loopback |
CN103384204B (en) * | 2011-12-31 | 2016-03-30 | 华为数字技术(成都)有限公司 | The processing method of serial concurrent conversion circuit failure and device |
US9524013B2 (en) | 2014-04-16 | 2016-12-20 | International Business Machines Corporation | System interconnect dynamic scaling by lane width and operating frequency balancing |
US10007441B2 (en) | 2014-04-30 | 2018-06-26 | Hewlett Packard Enterprise Development Lp | Storage system bandwidth adjustment |
US9558139B2 (en) | 2014-08-18 | 2017-01-31 | International Business Machines Corporation | System interconnect dynamic scaling handshake using spare bit-lane |
US10254814B2 (en) | 2014-09-04 | 2019-04-09 | Hewlett Packard Enterprise Development Lp | Storage system bandwidth determination |
WO2016167871A1 (en) | 2015-04-17 | 2016-10-20 | Emd Millipore Corporation | Method of purifying a biological materia of interest in a sample using nanofiber ultrafiltration membranes operated in tangential flow filtration mode |
US20170280385A1 (en) * | 2016-03-23 | 2017-09-28 | Qualcomm Incorporated | Link speed control systems for power optimization |
US20190250930A1 (en) * | 2018-02-12 | 2019-08-15 | Western Digital Technologies, Inc. | Method and apparatus for configuring a serial data link |
US11073894B2 (en) | 2019-05-24 | 2021-07-27 | Qualcomm Incorporated | System power management for peripheral component interconnect express (PCIE)-based devices |
US11586446B1 (en) * | 2020-05-20 | 2023-02-21 | Marvell Asia Pte Ltd | System and methods for hardware-based PCIe link up based on post silicon characterization |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5313467A (en) * | 1989-11-15 | 1994-05-17 | Digital Equipment Corporation | Integrated communication link having a dynamically allocatable bandwidth and protocol for transmission of allocation information over the link |
US6018810A (en) * | 1997-12-12 | 2000-01-25 | Compaq Computer Corporation | Fault-tolerant interconnection means in a computer system |
US6052754A (en) * | 1998-05-14 | 2000-04-18 | Vlsi Technology, Inc. | Centrally controlled interface scheme for promoting design reusable circuit blocks |
US20050283561A1 (en) * | 2004-06-21 | 2005-12-22 | Lee John P | Method, system, and apparatus to decrease CPU temperature through I/O bus throttling |
US20060023633A1 (en) * | 2004-07-16 | 2006-02-02 | Ati Technologies Inc. | Method and apparatus for managing power consumption relating to a differential serial communication link |
US7099969B2 (en) * | 2003-11-06 | 2006-08-29 | Dell Products L.P. | Dynamic reconfiguration of PCI Express links |
US7136953B1 (en) * | 2003-05-07 | 2006-11-14 | Nvidia Corporation | Apparatus, system, and method for bus link width optimization |
US20070008898A1 (en) * | 2005-06-29 | 2007-01-11 | Intel Corporation | Point-to-point link negotiation method and apparatus |
US7174411B1 (en) * | 2004-12-02 | 2007-02-06 | Pericom Semiconductor Corp. | Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host |
US20070047578A1 (en) * | 2005-08-29 | 2007-03-01 | Fujitsu Limited | Bandwidth control method and transmission equipment |
US7197591B2 (en) * | 2004-06-30 | 2007-03-27 | Intel Corporation | Dynamic lane, voltage and frequency adjustment for serial interconnect |
US20070094437A1 (en) * | 2005-10-26 | 2007-04-26 | Jabori Monji G | Dynamic lane management system and method |
US20070094436A1 (en) * | 2005-10-20 | 2007-04-26 | Keown William F Jr | System and method for thermal management in PCI express system |
US20070233930A1 (en) * | 2006-03-14 | 2007-10-04 | International Business Machines Corporation | System and method of resizing PCI Express bus widths on-demand |
US20070233926A1 (en) * | 2006-03-10 | 2007-10-04 | Inventec Corporation | Bus width automatic adjusting method and system |
US20070276981A1 (en) * | 2006-05-24 | 2007-11-29 | Atherton William E | Dynamically Allocating Lanes to a Plurality of PCI Express Connectors |
US7426597B1 (en) * | 2003-05-07 | 2008-09-16 | Nvidia Corporation | Apparatus, system, and method for bus link width optimization of a graphics system |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57174723A (en) * | 1981-04-22 | 1982-10-27 | Hitachi Ltd | Bus load controlling system |
JPH0276056A (en) * | 1988-09-13 | 1990-03-15 | Toshiba Corp | Information processor |
JPH0310355A (en) * | 1989-06-07 | 1991-01-17 | Fuji Electric Co Ltd | Common bus priority control method |
JP3369227B2 (en) * | 1992-11-09 | 2003-01-20 | 株式会社東芝 | Processor |
US5964883A (en) * | 1996-11-20 | 1999-10-12 | Advanced Micro Devices | Arrangement and method for handling bus clock speed variations |
JP3964528B2 (en) * | 1998-03-02 | 2007-08-22 | 富士通株式会社 | Serial bus acceleration circuit |
JP2000020462A (en) * | 1998-06-30 | 2000-01-21 | Toshiba Corp | Bus system to be applied to computer system |
US6611891B1 (en) * | 1998-11-23 | 2003-08-26 | Advanced Micro Devices, Inc. | Computer resource configuration mechanism across a multi-pipe communication link |
US6952746B2 (en) * | 2001-06-14 | 2005-10-04 | International Business Machines Corporation | Method and system for system performance optimization via heuristically optimized buses |
US7162554B1 (en) * | 2001-07-11 | 2007-01-09 | Advanced Micro Devices, Inc. | Method and apparatus for configuring a peripheral bus |
TWI245190B (en) * | 2003-11-27 | 2005-12-11 | Via Tech Inc | Method for verifying optimization of processor link |
CA2509001A1 (en) * | 2004-06-22 | 2005-12-22 | Textron Inc. | Blind bolt installation tool |
US7539801B2 (en) * | 2005-05-27 | 2009-05-26 | Ati Technologies Ulc | Computing device with flexibly configurable expansion slots, and method of operation |
US20070127410A1 (en) * | 2005-12-06 | 2007-06-07 | Jianlin Guo | QoS for AV transmission over wireless networks |
-
2006
- 2006-07-20 US US11/490,349 patent/US7536490B2/en active Active
-
2008
- 2008-08-05 US US12/186,408 patent/US20080294831A1/en not_active Abandoned
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5313467A (en) * | 1989-11-15 | 1994-05-17 | Digital Equipment Corporation | Integrated communication link having a dynamically allocatable bandwidth and protocol for transmission of allocation information over the link |
US6018810A (en) * | 1997-12-12 | 2000-01-25 | Compaq Computer Corporation | Fault-tolerant interconnection means in a computer system |
US6052754A (en) * | 1998-05-14 | 2000-04-18 | Vlsi Technology, Inc. | Centrally controlled interface scheme for promoting design reusable circuit blocks |
US7136953B1 (en) * | 2003-05-07 | 2006-11-14 | Nvidia Corporation | Apparatus, system, and method for bus link width optimization |
US7426597B1 (en) * | 2003-05-07 | 2008-09-16 | Nvidia Corporation | Apparatus, system, and method for bus link width optimization of a graphics system |
US7099969B2 (en) * | 2003-11-06 | 2006-08-29 | Dell Products L.P. | Dynamic reconfiguration of PCI Express links |
US20050283561A1 (en) * | 2004-06-21 | 2005-12-22 | Lee John P | Method, system, and apparatus to decrease CPU temperature through I/O bus throttling |
US7197591B2 (en) * | 2004-06-30 | 2007-03-27 | Intel Corporation | Dynamic lane, voltage and frequency adjustment for serial interconnect |
US20060023633A1 (en) * | 2004-07-16 | 2006-02-02 | Ati Technologies Inc. | Method and apparatus for managing power consumption relating to a differential serial communication link |
US7174411B1 (en) * | 2004-12-02 | 2007-02-06 | Pericom Semiconductor Corp. | Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host |
US20070008898A1 (en) * | 2005-06-29 | 2007-01-11 | Intel Corporation | Point-to-point link negotiation method and apparatus |
US20070047578A1 (en) * | 2005-08-29 | 2007-03-01 | Fujitsu Limited | Bandwidth control method and transmission equipment |
US20070094436A1 (en) * | 2005-10-20 | 2007-04-26 | Keown William F Jr | System and method for thermal management in PCI express system |
US20070094437A1 (en) * | 2005-10-26 | 2007-04-26 | Jabori Monji G | Dynamic lane management system and method |
US20070233926A1 (en) * | 2006-03-10 | 2007-10-04 | Inventec Corporation | Bus width automatic adjusting method and system |
US20070233930A1 (en) * | 2006-03-14 | 2007-10-04 | International Business Machines Corporation | System and method of resizing PCI Express bus widths on-demand |
US20070276981A1 (en) * | 2006-05-24 | 2007-11-29 | Atherton William E | Dynamically Allocating Lanes to a Plurality of PCI Express Connectors |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7809869B2 (en) * | 2007-12-20 | 2010-10-05 | International Business Machines Corporation | Throttling a point-to-point, serial input/output expansion subsystem within a computing system |
US20090164684A1 (en) * | 2007-12-20 | 2009-06-25 | International Business Machines Corporation | Throttling A Point-To-Point, Serial Input/Output Expansion Subsystem Within A Computing System |
US20110161547A1 (en) * | 2009-12-24 | 2011-06-30 | Ati Technologies Ulc | Method and device for disabling a higher version of a computer bus and interconnection protocol for interoperability with a device compliant to a lower version of the computer bus and interconnection protocol |
US8301813B2 (en) * | 2009-12-24 | 2012-10-30 | Ati Technologies Ulc | Method and device for disabling a higher version of a computer bus and interconnection protocol for interoperability with a device compliant to a lower version of the computer bus and interconnection protocol |
US8984192B2 (en) | 2009-12-24 | 2015-03-17 | Ati Technologies Ulc | Method and device for disabling a higher version of a computer bus and interconnection protocol for interoperability with a device compliant to a lower version of the computer bus and interconnection protocol |
JP2015505094A (en) * | 2011-12-21 | 2015-02-16 | インテル コーポレイション | Dynamic link width adjustment |
US8446903B1 (en) * | 2012-05-22 | 2013-05-21 | Intel Corporation | Providing a load/store communication protocol with a low power physical unit |
US9031064B2 (en) | 2012-05-22 | 2015-05-12 | Intel Corporation | Providing a load/store communication protocol with a low power physical unit |
US8737390B2 (en) | 2012-05-22 | 2014-05-27 | Intel Corporation | Providing a load/store communication protocol with a low power physical unit |
US8924620B2 (en) | 2012-05-22 | 2014-12-30 | Intel Corporation | Providing a consolidated sideband communication channel between devices |
US8549205B1 (en) | 2012-05-22 | 2013-10-01 | Intel Corporation | Providing a consolidated sideband communication channel between devices |
US9223735B2 (en) | 2012-05-22 | 2015-12-29 | Intel Corporation | Providing a consolidated sideband communication channel between devices |
US8437343B1 (en) | 2012-05-22 | 2013-05-07 | Intel Corporation | Optimized link training and management mechanism |
US8638783B2 (en) | 2012-05-22 | 2014-01-28 | Intel Corporation | Optimized link training and management mechanism |
US9141577B2 (en) | 2012-05-22 | 2015-09-22 | Intel Corporation | Optimized link training and management mechanism |
US8972640B2 (en) | 2012-06-27 | 2015-03-03 | Intel Corporation | Controlling a physical link of a first protocol using an extended capability structure of a second protocol |
US9390046B2 (en) | 2012-06-27 | 2016-07-12 | Intel Corporation | Controlling a physical link of a first protocol using an extended capability structure of a second protocol |
US9261934B2 (en) | 2013-03-15 | 2016-02-16 | Intel Corporation | Dynamic response improvement of hybrid power boost technology |
US9612643B2 (en) | 2014-03-29 | 2017-04-04 | Intel Corporation | Controlling the CPU slew rates based on the battery state of charge |
US9710406B2 (en) | 2014-12-15 | 2017-07-18 | Intel Corporation | Data transmission using PCIe protocol via USB port |
US9952986B2 (en) | 2014-12-15 | 2018-04-24 | Intel Corporation | Power delivery and data transmission using PCIe protocol via USB type-C port |
Also Published As
Publication number | Publication date |
---|---|
US20080022024A1 (en) | 2008-01-24 |
US7536490B2 (en) | 2009-05-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7536490B2 (en) | Method for link bandwidth management | |
US7809969B2 (en) | Using asymmetric lanes dynamically in a multi-lane serial link | |
US10180927B2 (en) | Device, system and method for communication with heterogeneous physical layers | |
US9830292B2 (en) | Architected protocol for changing link operating mode | |
US7480808B2 (en) | Method and apparatus for managing power consumption relating to a differential serial communication link | |
US9390046B2 (en) | Controlling a physical link of a first protocol using an extended capability structure of a second protocol | |
EP3133796B1 (en) | Providing a load/store communication protocol with a low power physical unit | |
US7757020B2 (en) | Point-to-point link negotiation method and apparatus | |
US8782321B2 (en) | PCI express tunneling over a multi-protocol I/O interconnect | |
US8856573B2 (en) | Setting a number (N) of fast training sequences (FTS) automatically to an optimal value | |
KR102420530B1 (en) | Alternative protocol selection | |
US20150269109A1 (en) | Method, apparatus and system for single-ended communication of transaction layer packets | |
US11960424B2 (en) | Peripheral component interconnect express (PCIe) interface device and method of operating the same | |
US11940942B2 (en) | Peripheral component interconnect express interface device and operating method thereof | |
US7849243B2 (en) | Enabling flexibility of packet length in a communication protocol | |
US20130036243A1 (en) | Host-daughtercard configuration with double data rate bus | |
US11797468B2 (en) | Peripheral component interconnect express device and computing system including the same | |
US11782497B2 (en) | Peripheral component interconnect express (PCIE) interface device and method of operating the same | |
US20230315591A1 (en) | PCIe DEVICE AND COMPUTING SYSTEM INCLUDING THE SAME | |
Curd | PCI Express for the 7 Series FPGAs |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |