US20080303155A1 - Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures - Google Patents
Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures Download PDFInfo
- Publication number
- US20080303155A1 US20080303155A1 US12/191,171 US19117108A US2008303155A1 US 20080303155 A1 US20080303155 A1 US 20080303155A1 US 19117108 A US19117108 A US 19117108A US 2008303155 A1 US2008303155 A1 US 2008303155A1
- Authority
- US
- United States
- Prior art keywords
- copper
- dielectric
- insulating layer
- opening
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention described herein relates generally to semiconductor devices and processing.
- the present invention relates to methods, materials, and structures used in forming dielectric barrier films used with copper materials in trench and via structures. More particularly, the invention relates to methods, materials, and structures for forming dielectric barrier films used with copper materials in damascene and dual damascene semiconductor processes.
- damascene and dual-damascene manufacturing processes are used to interconnect the metallization layers of multi-layer semiconductor structures.
- a metallization layer is formed on a semiconductor substrate (e.g. a wafer or semiconductor die) in accordance with metallization processes known in the art.
- the metallization layer includes patterns of circuit paths and electrical connections.
- the circuit patterns of one metallization layer are electrically connected to circuit patterns formed on other metallization layers formed above and below the layer in question.
- the metallization layers are separated by one or more layers of dielectric material. These intervening layers are collectively referred to as the inter-layer dielectric (ILD) layer. Electrical interconnections between the metallization layers are commonly made by forming vias through the ILD, and filling the vias with copper materials.
- ILD inter-layer dielectric
- FIG. 1 illustrates one particular application of conventional metal barrier layers as currently used.
- the depicted structure is a cross-section schematic view of a portion of a semiconductor substrate.
- a copper conducting line 102 of the metallization layer is shown formed in a silicon layer 101 .
- An ILD layer 103 formed of dielectric materials.
- conductive vias can be used. Such vias can be formed by creating an opening 104 in the ILD layer 103 and then creating a conductive interconnect therein.
- the opening 104 includes a metal barrier layer 105 formed on the walls of the opening. Additionally, such metal barrier layers 105 typically cover the underlying copper conducting line 102 .
- a copper interconnect (plug) 106 is typically deposited over the metal barrier layers 105 in the opening 104 to form a copper interconnect.
- the surface can then be planarized (e.g., using CMP) to prepare the surface for further processing.
- CMP planarized
- metal barrier layer and via structures are satisfactory for many applications.
- critical dimensions decrease, especially below the 1 ⁇ (micron) level, the proportion of space in the via occupied by the metal barrier layer 105 becomes greater and greater. This results in less room in the via for the highly conductive copper interconnect 106 .
- copper is significantly more conductive than existing metal barrier layers, the overall conductivity of an interconnect is significantly reduced as the proportion of metal barrier layer material goes up. This is especially so in conductive vias having diameters of 1 ⁇ or less.
- the metal barrier layer 105 extends across the bottom of the via 105 b . The interfaces between copper (e.g., 102 and 106 ) and the bottom portion 105 b of the metal barrier layer are subject to a high incidence of failure.
- a method and structure for forming a dielectric copper barrier layer are disclosed.
- One embodiment of the present invention is directed to an improved inter-layer conducting layer.
- Such a structure includes a semiconductor substrate having copper interconnect structures formed thereon.
- An overlying insulating layer is formed on the underlying copper interconnect structures.
- the insulating layer formed of a material that includes at least one of silicon and carbon.
- An opening is formed in the insulating layer to expose a portion of the underlying copper interconnect structure.
- the inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer.
- a copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure.
- Another embodiment comprises methods for forming copper interconnects with dielectric copper barrier layers.
- the method involves providing a substrate having copper interconnect structures and an insulating layer that overlies the copper interconnect structures formed thereon.
- the insulating layer has an opening that exposes an underlying copper interconnect structure and is configured to receive an inlaid conducting structure that is in electrical contact with the copper interconnect structure.
- the insulating layer is formed of a low-K dielectric material that includes at least one of silicon and carbon material.
- the method further involves forming a dielectric copper barrier layer on the inside surface of the opening to produce a barrier to copper diffusion into the insulating layer. The opening is then filled with copper material.
- FIG. 1 is a simplified figurative depiction of a semiconductor wafer in a process chamber.
- FIG. 2 is a cross-section view of a portion of a semiconductor surface having a layer of conducting material, a barrier layer, and a layer of insulating material formed thereon, all in readiness for the formation of an ARC in accordance with the principles of the present invention.
- FIG. 3( a ) is a simplified schematic cross-section view of the substrate having an opening in the insulating layer in readiness for further processing in accordance with the principles of the present invention.
- FIG. 3( b ) is a simplified figurative depiction of the substrate of FIG. 3( a ) in a process chamber during processing in accordance with the principles of the invention.
- FIG. 3( c ) is a simplified depiction of the substrate of FIG. 3( a ) having a dielectric copper barrier layer constructed in accordance with an embodiment of the present invention.
- FIG. 4 ( a ) is a simplified figurative depiction of a substrate in a process chamber during processing in accordance with an embodiment of the invention.
- FIG. 4( b ) is a simplified depiction of the substrate of FIG. 3( a ) having a dielectric copper barrier layer constructed in accordance with another embodiment of the present invention.
- FIG. 5 ( a ) is a simplified figurative depiction of a substrate in a process chamber during processing in accordance with an embodiment of the invention.
- FIGS. 5( b )- 5 ( c ) are simplified cross-section views of a portion of a substrate surface having precursor sub-layers and dielectric copper barrier layers formed thereon in accordance with the principles of the invention.
- dielectric copper barrier layers are comprised of materials that are dielectric in nature and also provide a barrier to the diffusion of copper materials.
- silicon oxycarbide, silicon carbide, and silicon carbide nitride can be used as dielectric copper barrier materials.
- densified dielectric materials can be used as dielectric copper barrier layers. Methods constructing these and related dielectric copper barrier layers will be detailed.
- Silicon carbide for purposes of this patent, is a generic name given to a class of materials comprising Si x C y .
- silicon oxycarbide for purposes of this patent, is a generic name given to a class of materials comprising Si x O y C x .
- the embodiments 200 begin by first providing a suitable substrate in readiness for processing in accordance with the principles of the invention.
- substrate refers to a semiconductor substrate structure.
- Such structures can include, for example, the bare silicon surfaces of a wafer or any of the surfaces formed thereon. Additionally, such substrates are not confined to silicon-containing substrates but can include other materials (e.g., GaAs).
- Such substrates can also comprise multi-level semiconductor structures.
- the substrate includes a semiconductor substrate 201 .
- the depicted embodiment includes a semiconductor substrate 201 having copper interconnect structures formed thereon 202 .
- an overlying insulating layer 203 being formed of a material that includes at least one of silicon and carbon.
- the insulating layer 203 has an opening 204 that exposes the underlying copper interconnect structures 202 .
- the insulating layer 203 is formed of a low-K dielectric material.
- a preferred class of materials includes organo-silicate glasses (OSG). Such materials can include without limitation, silicate organic glasses (SiOCH), silicon carbide (SiC) materials, and silicon oxycarbide materials (SiOC). However, other materials can be used.
- Example dielectric materials include silicon dioxide or combinations of silicon dioxide and other doped dielectrics (e.g., BPSG, PSG). Additionally, the principles of the present invention find particular utility when applied to use with low-K dielectric materials.
- Example materials can include, without limitation, spin-on and CVD inorganic or organic silicate materials such as silsesquioxanes, silicates, and siloxanes; and, mixtures, or blends, of organic polymers and spin-on glasses.
- Particular low-K materials include, but are not limited to: Black Diamond 1, Black Diamond 2, and Black Diamond 3 from Applied Materials (of Santa Clara, Calif.); Coral from Novellus Systems, Inc.
- a dielectric barrier layer 205 is formed on the inner surfaces of the opening 204 .
- a bulk copper layer can be deposited to form a copper interconnect (plug) 206 that is in electrical contact with the underlying copper interconnect structures 202 .
- the dielectric barrier layer 205 is intended to prevent the diffusion of copper into the insulating layer. The methodologies and materials used for forming such dielectric barrier layers 205 are described in detail hereinbelow.
- the process begins by providing a suitable substrate.
- FIG. 3( a ) depicts one example of a typical substrate 300 .
- FIG. 3( a ) is a cross-section view of a portion of the surface of the substrate 300 .
- the depicted substrate has a semiconductor substrate surface 301 with copper interconnect structures 302 formed thereon.
- Such copper interconnect structures 302 can be formed using a wide range of techniques known to those having ordinary skill in the art. Such techniques can include, but are not limited to, single and double damascene processes.
- At least one overlying insulating layer 303 overlying the copper interconnect structures 302 is provided.
- the insulating layer 303 is configured having an opening 304 that exposes the underlying copper interconnect structure 302 .
- the opening 304 is configured to receive an inlaid conducting structure that is in electrical contact with the top surface 302 t of underlying copper interconnect structure 302 .
- the insulating layer 304 is typically formed of a low-K dielectric material.
- the dielectric material includes at least one of silicon and carbon material.
- Preferred materials include silicate organic glasses and organo-silicate glasses. As has been previously noted, other materials can be used.
- the methodologies of the present invention are particularly advantageous when used with low-K dielectric layers enhanced with micro-porosities.
- the depicted substrate 300 can be formed using a number of methods known to persons having ordinary skill in the art.
- the insulating layer 303 is then treated to form a dielectric copper barrier layer on the inside surface of the opening.
- This dielectric copper barrier layer is a dielectric material that provides a barrier to copper diffusion into the insulating layer. Once the dielectric copper barrier layer is formed the opening is filled with copper material to complete the interlayer electrical connection.
- the insulating layer 303 is plasma treated to form a dielectric copper barrier layer.
- the substrate 300 is then placed in a processing chamber 310 of a suitable process machine.
- Suitable machines include, but are not limited to, high-density plasma (HDP) machines, reactive ion etch (RIE) machines, electron beam machine, or downstream plasma machines.
- HDP high-density plasma
- RIE reactive ion etch
- One example of satisfactory machine is a Trikon Omega (manufactured by Trikon Technologies, Inc. of the United Kingdom).
- an inert gas e.g., argon (Ar) or helium (He)
- argon (Ar) or helium (He) is flowed into the chamber 310 and ignited into a plasma 311 .
- Such plasma is used with a very low bias voltage. Voltage sufficient to enable plasma to reach the bottom of the trenches and vias (e.g., opening 304 ) is all that is needed.
- low bias is used to prevent the plasma from excessively sputtering the copper at the bottom of the opening. Due to the substantially non-directional nature of such plasma, such plasmas are referred to herein as substantially anisotropic plasmas. These substantially anisotropic plasmas can be sustained by maintaining low bias voltages in the range of about 0-500V (volts).
- Preferred implementations maintain bias at less than about 100V.
- the plasma power is set in the range of about 200-1200 W (watts).
- Chamber pressures are maintained in the range of about 100 mTorr to about 4 Torr.
- Flow rates for the inert gases should be in the range of about 100 SCCM (standard cubic centimeters per minute) to about 10 lpm (liters per minute).
- Process temperatures in the chamber 310 should range from about room temperature to about 400° C. With a preferred range of process temperature being about 200-300° C., with a most preferred process temperature of about 300° C.
- Such a process is extremely effective at treating many insulating layers to form dielectric copper barrier layers.
- the process is particularly advantageous for creating dielectric copper barrier layers in insulating layers constructed of dielectric materials having micro-pores formed therein.
- the use and formation of such micro-pores are a well-known means for enhancing the low-K properties of dielectric layers.
- Plasma treating dielectric layers can result in increased density of dielectric material at the treated surface. Such regions of increased density are referred to as “densified” dielectric layers. Densified materials are simply more dense than materials prior to treatment. For example, one common OSG dielectric material having micro-pores has a density of in the range of 1-1.5 g/cm 3 (grams per cubic centimeter).
- this process can be used to create a dielectric copper barrier layer in many insulating layers, the process is most advantageous when used in conjunction with insulating layers having micro-pores formed therein.
- Treatment with said plasma for about 15-100 seconds results in a dielectric copper barrier layer about 10 ⁇ to about 200 ⁇ thick.
- Such a process and the resulting layer are advantageous because such dielectric copper barrier layers are thin (on the order of about 10 ⁇ to about 200 ⁇ ) and do not form part of the interconnect metal and so do not restrict the thickness of the copper interconnect.
- the dielectric copper barrier layer does not form on the top surface (e.g., 302 t of FIG. 3( a )) underlying copper layer at the bottom of an. Therefore, such a dielectric copper barrier layer does not degrade copper interconnect electrical performance.
- some of the advantages of the present implementation are the ability to form thicker copper interconnect structures and increased electrical performance in the copper interconnect structures.
- FIG. 3( c ) depicts one embodiment of the improved structure 320 featuring a dielectric copper barrier layer.
- FIG. 3( c ) is a cross-section view of a portion of the surface of the substrate similar to that shown in FIG. 3( a ).
- the depicted embodiment has a semiconductor substrate surface 301 with copper interconnect structures 302 formed thereon.
- the least one overlying insulating layer 303 includes an opening 304 that exposes the underlying copper interconnect structure 302 .
- the opening 304 is plasma treated to form a dielectric copper barrier layer 321 on the insulating layer 303 .
- the opening 304 is then filled with copper material to form the copper interconnect 322 .
- This copper interconnect 322 can be formed using any of the conventional techniques used for forming such structures. Examples, include, but are not limited to, seed layer deposition, bulk copper deposition, and CMP. Further layers and structures can be formed on the surface depicted in FIG. 3( c ).
- dielectric copper barrier layers 321 by plasma treating the dielectric insulating layer 303 certain other dielectric copper barrier layers 321 can be formed.
- plasma treatment reduces the amount of oxygen in the surface of such layers 303 resulting in dielectric copper barrier layers 321 having a higher concentrations of silicon carbide.
- This processing is particularly suitable for silicate organic glasses (SiOCH) and other organo-silicate glasses.
- the process begins by providing a suitable substrate.
- the substrate of FIG. 3( a ) depicts one example of a suitable substrate 300 .
- the depicted substrate has a semiconductor substrate surface 301 with copper interconnect structures 302 formed thereon.
- At least one insulating layer 303 overlying the copper interconnect structures 302 is provided.
- the insulating layer 303 is configured having an opening 304 that exposes the underlying copper interconnect structure 302 .
- the opening 304 is configured to receive an inlaid conducting structure that is in electrical contact with the top surface 302 t of copper interconnect structure 302 .
- the insulating layer 304 is typically formed of a low-K dielectric material.
- the dielectric material includes at least one of silicon and carbon material, preferably silicate organic glasses and organo-silicate glasses.
- the insulating layer 303 is then treated with a reactive material to form a dielectric copper barrier layer on the inside surface of the opening.
- a reactive material includes H 2 , CO, CH 4 , and in some conditions C 0 2 .
- plasmas are formed of such materials they form “reactive” plasmas that react with the material of the insulating layer to form dielectric copper barrier materials that can act as copper diffusion barriers.
- the reactive plasma treatment can act to densify the material of the insulating layer to form dielectric copper barrier materials.
- a dielectric copper barrier layer can be formed. Once the dielectric copper barrier layer is formed the opening is filled with copper material to complete the interlayer electrical connection.
- Suitable machines include, but are not limited to, high-density plasma (HDP) machines, reactive ion etch (RIE) machines, electron beam machine, or downstream plasma machines. Again, a satisfactory machine is a Trikon Omega.
- a reactive gas e.g., CO, H 2 , CH 4 , or C 0 2
- Flow rates for the reactive gases should be in the range of about 100 SCCM to about 10 lpm, preferably about 2000 SCCM.
- the plasma is ignited using a power of in the range of about 200-1200 W, preferably in a range of about 500-600 W.
- the reactive plasma 402 is used with a very low bias voltage. A voltage sufficient to enable plasma to reach the bottom of the trenches and vias (e.g., opening 304 ) is all that is required to establish a satisfactory anisotropic reactive plasma.
- the low bias is used to prevent the plasma from excessively sputtering the copper at the bottom of the opening or excessively damaging the insulating layer 303 .
- This plasma can be sustained by maintaining a low bias voltage of in the range of about 0-500V (volts), but preferably less than about 100V.
- chamber pressures are maintained in the range of about 100 mTorr to about 4 Torr.
- Process temperatures in the chamber 401 should range from about room temperature to about 400° C. With a preferred process temperature range of about 200-300° C., with a temperature of about 300° C. being most preferred.
- a dielectric copper barrier layer is formed.
- the ignited reactive plasma 402 is very effective at removing oxygen from the surface of the insulating layer 303 . This is especially, true where the reactive gas includes H 2 .
- the concentration of silicon carbide is increased in the surface of the insulating layer 303 forming a dielectric copper barrier layer 415 on the inside surface the opening 304 .
- carbon containing reactive materials such as CH 4 , CO, and C 0 2 can increase the concentration of silicon carbide in the surface of the insulating layer 303 to form a dielectric copper barrier layer 415 on the inside surface the opening 304 .
- the reactive gas can comprise a nitrogen-containing material (e.g., NO, N 2 , ammonia, or N 0 2 ).
- the nitrogen-containing gas is introduced into the chamber 401 and ignited into a reactive plasma 402 . Again similar flow rates can be used (e.g., in the range of about 100 SCCM to about 10 lpm).
- the plasma can be ignited at a power in the range of about 200-1200 W, preferably about 500-600 W.
- the nitrogen-containing reactive plasma 402 is used with a very low bias voltage to establish an anisotropic plasma. This plasma can be sustained by maintaining a low bias voltage of in the range of about 0-500V (volts), but preferably less than about 100V.
- chamber pressures are maintained in the range of about 100 mTorr to about 4 Torr.
- Process temperatures in the chamber 401 should range from about room temperature to about 400° C. With a preferred process temperature range of about 200-300° C., with a temperature of about 300° C. being most preferred.
- Nitrogen-containing plasma can generate SiCN (silicon carbon nitrides) in the surface of the insulating layer 303 to form a dielectric copper barrier layer 415 on the inside surface the opening 304 .
- SiCN silicon carbon nitrides
- Such SiCN rich dielectric copper barrier layers 415 function well a s barriers to copper diffusion into the insulating layer 303 .
- An additional advantage of such reactive plasmas is that, like plasmas generated using inert materials, they can also densify the surface of the insulating layer 303 on the inside surface the opening 304 to form improved dielectric copper barrier layers 415 .
- the process is particularly advantageous for creating dielectric copper barrier layers in insulating layers constructed of dielectric materials having micro-pores formed therein.
- a dielectric copper barrier layer 415 of about 10 ⁇ to about 200 ⁇ thick results in a dielectric copper barrier layer 415 of about 10 ⁇ to about 200 ⁇ thick.
- the resulting layer are advantageous because such dielectric copper barrier layers are thin (on the order of about 10 ⁇ to about 200 ⁇ ) and do not restrict the thickness of the copper interconnect. Additionally, unlike conventional processes the dielectric copper barrier layer does not form on the top surface 302 t of the underlying copper layer.
- the opening 304 is then filled with copper material to form the copper interconnect 416 .
- This copper interconnect 416 can be formed using any of the conventional techniques used for forming such structures.
- This embodiment comprises forming one or more layers of dielectric copper barrier material over one another to form a suitable dielectric copper barrier layer.
- the process begins by providing a suitable substrate such as that depicted and described with respect to FIG. 3( a ).
- the substrate 300 is then placed in a processing chamber 501 of a suitable process machine.
- suitable machines include, but are not limited to, high-density plasma (HDP) machines, reactive ion etch (RIE) machines, electron beam machine, or downstream plasma machines. Again, one satisfactory machine is a Trikon Omega.
- a precursor gas 502 is flowed into the chamber 401 and deposited onto the inside surface of the opening 304 to form a precursor sub-layer 511 .
- Some preferred precursor materials are methyl silanes, vinyl silanes, and methyl-vinyl silanes.
- suitable precursor materials include compounds comprising (R 1x )(R 2y ) Si H z wherein R 1 consists of methyl groups (—CH 3 ), R 2 consists of vinyl groups (—CH ⁇ CH 2 ), H consists of hydrogen and wherein x is an integer from 0-4, y is an integer from 0-4, and z is an integer from 0-4.
- Specific examples include 4-methylsilane (Si(CH 3 ) 4 , also known as 4MS), 3-methylsilane (Si(CH 3 ) 3 H, also known as 3MS), 2-methylsilane (Si(CH 3 ) 2 H 2 , also known as 2MS), and also 1-methylsilane (Si(CH 3 )H 3 , also known as 1MS).
- vinyl silanes are also suitable. Specific examples include, without limitation, Si(C 2 H 3 ) 4 , Si(C 2 H 3 ) 3 H, Si(C 2 H 3 ) 2 H 2 , and Si(C 2 H 3 )H 3 .
- methyl-vinyl silanes can also be used.
- methyl-vinyl silanes include, but are not limited to vinyl tri-methyl silane (C 2 H 3 )(CH 3 ) 3 Si, di-vinyl di-methyl silane (C 2 H 3 ) 2 (CH 3 ) 2 Si, tri-vinyl methyl silane (C 2 H 3 ) 3 (CH 3 ) Si, and tetra-vinyl silane (C 2 H 3 ) 4 Si as well as many other similar materials known to persons having ordinary skill in the art.
- precursor materials 502 are flowed into the process chamber, typically with an inert carrier gas (e.g., argon (Ar) or helium (He)). Such precursor material deposits onto the inside of the opening 304 to form a precursor sub-layer 511 .
- the precursor gas is introduced into the chamber at a flow rate of about 100 SCCM to about 1 lpm.
- a pressure in the range of about 10 mTorr to about 2 Torr is maintained.
- a temperature of ⁇ 100° C. to about 400° C. is maintained.
- a preferred temperature is in the range of about ⁇ 30° C. to about 100° C.
- a precursor sub-layer 511 is formed on the inside of the opening 304 .
- Such sub-layers 511 can be formed having very small thicknesses on the order of about 2-5 ⁇ .
- the precursor materials are then evacuated from the chamber 503 of FIG. 5( a ).
- the precursor sub-layers are treated to generate a dielectric copper barrier sub-layer.
- inert materials are introduced to the chamber 501 after the precursor materials are evacuated from the chamber.
- the inert materials are ignited into a plasma.
- Such materials include, but are not limited to argon and helium.
- the plasma is ignited using a power of in the range of about 200-800 W.
- the plasma is used with a very low bias voltage. Bias voltages in the range of about 0-500V (volts) can be used with voltages less than about 100V being preferred. This forms an anisotropic plasma which is used to change the precursor sub-layer 511 into a dielectric copper barrier sub-layer.
- Process temperatures in the chamber 501 should range from about ⁇ 30° C. to about 400° C. With a preferred process temperature of about 100° C. to about 300° C.
- the plasma treatment reacts with the precursor sub-layer 511 to form a dielectric copper barrier sub-layer. It should be noted that the precursor sub-layer 511 can be treated in other ways to form a dielectric copper barrier sub-layer.
- Such treatment can comprise treatment with a low intensity electron beam or exposure to photons (e.g., UV radiation) to form a dielectric copper barrier sub-layer. Additionally, heating can be used to form a dielectric copper barrier sub-layer. Typically, such treatment forms a form a dielectric copper barrier sub-layer formed of silicon carbide materials.
- the inert gases 502 can be replaced by carbon monoxide or O 2 gas which is ignited into plasma which then reacts the precursor sub-layer 511 to form a dielectric copper barrier sub-layer.
- a dielectric copper barrier sub-layer formed in this manner commonly includes silicon oxycarbide.
- the inert gas 502 can be replaced by a nitrogen-containing material which is ignited into plasma which then reacts the precursor sub-layer 511 to form a dielectric copper barrier sub-layer.
- a dielectric copper barrier sub-layer formed in this manner commonly includes SiCN.
- Suitable nitrogen-containing materials include, N 2 , NO, N 0 2 , with N 2 being preferred.
- the precursor materials can form on the exposed top portion 521 t underlying copper interconnect structure 521 . In such cases the bias voltage is increased to sputter the precursor and/or dielectric copper barrier material off the underlying copper interconnect structure 521 .
- FIG. 5( c ) One such embodiment is depicted in FIG. 5( c ).
- the initial substrate is much the same as depicted and described with respect to FIG. 3( a ).
- a semiconductor substrate 301 having a copper interconnect structure 302 formed thereon is depicted.
- a plurality of dielectric copper barrier sub-layers 531 , 532 , and 533 are formed on the inside surface of the opening 304 in the insulating layer 303 .
- Final dielectric copper barrier layers 534 are typically formed to thicknesses ranging from about 20 ⁇ to about 300 ⁇ . Such layers are typically, formed using a plurality of 2 ⁇ thick sub-layers.
Abstract
Description
- This application is a divisional of co-pending prior U.S. patent application Ser. No. 11/131,003, entitled “DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES”, filed on May 16, 2005, which is a divisional application of prior U.S. application Ser. No. 10/321,938, entitled “DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES”, filed on Dec. 16, 2002, now U.S. Pat. No. 6,939,800. All of the above are incorporated herein by reference in their entirety for all purposes.
- The invention described herein relates generally to semiconductor devices and processing. In particular, the present invention relates to methods, materials, and structures used in forming dielectric barrier films used with copper materials in trench and via structures. More particularly, the invention relates to methods, materials, and structures for forming dielectric barrier films used with copper materials in damascene and dual damascene semiconductor processes.
- In recent years, copper materials have found increasing use in semiconductor manufacturing technologies. Such methods commonly include the so-called damascene and dual-damascene manufacturing processes. Generally, such processes generally involve forming openings in a process layer, filling the layer with copper, and then planarizing the surface to complete the process. In one common implementation, such damascene (and dual damascene) processes are used to interconnect the metallization layers of multi-layer semiconductor structures.
- Briefly, a metallization layer is formed on a semiconductor substrate (e.g. a wafer or semiconductor die) in accordance with metallization processes known in the art. The metallization layer includes patterns of circuit paths and electrical connections. In multi-layer structures, the circuit patterns of one metallization layer are electrically connected to circuit patterns formed on other metallization layers formed above and below the layer in question. Typically, the metallization layers are separated by one or more layers of dielectric material. These intervening layers are collectively referred to as the inter-layer dielectric (ILD) layer. Electrical interconnections between the metallization layers are commonly made by forming vias through the ILD, and filling the vias with copper materials.
- As is known to those having ordinary skill in the art, when copper materials are used, metal barrier layers are needed to prevent copper from diffusing into the ILD layer and “poisoning” the ILD. Commonly, such metal barrier materials comprise metals or metal compounds (e.g., TiN, TaN, and other metal containing barrier materials). Such materials form excellent barriers to copper diffusion.
FIG. 1 illustrates one particular application of conventional metal barrier layers as currently used. The depicted structure is a cross-section schematic view of a portion of a semiconductor substrate. A copper conductingline 102 of the metallization layer is shown formed in asilicon layer 101. Overlying thesilicon layer 101 and metallization layer is anILD layer 103 formed of dielectric materials. In a multi-layer structure, subsequent metallization layers are commonly formed on top of theILD layer 103. In order to establish electrical connection between the layers, conductive vias can be used. Such vias can be formed by creating anopening 104 in the ILDlayer 103 and then creating a conductive interconnect therein. In the depicted implementation, the opening 104 includes ametal barrier layer 105 formed on the walls of the opening. Additionally, suchmetal barrier layers 105 typically cover the underlying copper conductingline 102. Once themetal barrier layer 105 is formed, a copper interconnect (plug) 106 is typically deposited over themetal barrier layers 105 in theopening 104 to form a copper interconnect. The surface can then be planarized (e.g., using CMP) to prepare the surface for further processing. Such structures find wide usage and applicability in current semiconductor fabrication. - Such metal barrier layer and via structures are satisfactory for many applications. However, as critical dimensions decrease, especially below the 1μ (micron) level, the proportion of space in the via occupied by the
metal barrier layer 105 becomes greater and greater. This results in less room in the via for the highlyconductive copper interconnect 106. Because copper is significantly more conductive than existing metal barrier layers, the overall conductivity of an interconnect is significantly reduced as the proportion of metal barrier layer material goes up. This is especially so in conductive vias having diameters of 1μ or less. Moreover, in existing processes themetal barrier layer 105 extends across the bottom of thevia 105 b. The interfaces between copper (e.g., 102 and 106) and thebottom portion 105 b of the metal barrier layer are subject to a high incidence of failure. - Thus, for these and other reasons, there is a need for improvements in copper barrier layer structures.
- In accordance with the principles of the present invention, a method and structure for forming a dielectric copper barrier layer are disclosed. One embodiment of the present invention is directed to an improved inter-layer conducting layer. Such a structure includes a semiconductor substrate having copper interconnect structures formed thereon. An overlying insulating layer is formed on the underlying copper interconnect structures. The insulating layer formed of a material that includes at least one of silicon and carbon. An opening is formed in the insulating layer to expose a portion of the underlying copper interconnect structure. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure.
- Another embodiment comprises methods for forming copper interconnects with dielectric copper barrier layers. The method involves providing a substrate having copper interconnect structures and an insulating layer that overlies the copper interconnect structures formed thereon. The insulating layer has an opening that exposes an underlying copper interconnect structure and is configured to receive an inlaid conducting structure that is in electrical contact with the copper interconnect structure. The insulating layer is formed of a low-K dielectric material that includes at least one of silicon and carbon material. The method further involves forming a dielectric copper barrier layer on the inside surface of the opening to produce a barrier to copper diffusion into the insulating layer. The opening is then filled with copper material.
- These and other aspects of the present invention are described in greater detail in the detailed description of the drawings set forth herein below.
- The following detailed description will be more readily understood in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a simplified figurative depiction of a semiconductor wafer in a process chamber. -
FIG. 2 is a cross-section view of a portion of a semiconductor surface having a layer of conducting material, a barrier layer, and a layer of insulating material formed thereon, all in readiness for the formation of an ARC in accordance with the principles of the present invention. -
FIG. 3( a) is a simplified schematic cross-section view of the substrate having an opening in the insulating layer in readiness for further processing in accordance with the principles of the present invention. -
FIG. 3( b) is a simplified figurative depiction of the substrate ofFIG. 3( a) in a process chamber during processing in accordance with the principles of the invention. -
FIG. 3( c) is a simplified depiction of the substrate ofFIG. 3( a) having a dielectric copper barrier layer constructed in accordance with an embodiment of the present invention. -
FIG. 4 (a) is a simplified figurative depiction of a substrate in a process chamber during processing in accordance with an embodiment of the invention. -
FIG. 4( b) is a simplified depiction of the substrate ofFIG. 3( a) having a dielectric copper barrier layer constructed in accordance with another embodiment of the present invention. -
FIG. 5 (a) is a simplified figurative depiction of a substrate in a process chamber during processing in accordance with an embodiment of the invention. -
FIGS. 5( b)-5(c) are simplified cross-section views of a portion of a substrate surface having precursor sub-layers and dielectric copper barrier layers formed thereon in accordance with the principles of the invention. - It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the Figures are not necessarily to scale.
- The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth hereinbelow are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention.
- In the following detailed description, various materials and method embodiments for forming dielectric copper barrier layers will be disclosed. Such dielectric copper barrier layers are comprised of materials that are dielectric in nature and also provide a barrier to the diffusion of copper materials. In particular, silicon oxycarbide, silicon carbide, and silicon carbide nitride can be used as dielectric copper barrier materials. Additionally, densified dielectric materials can be used as dielectric copper barrier layers. Methods constructing these and related dielectric copper barrier layers will be detailed. Silicon carbide, for purposes of this patent, is a generic name given to a class of materials comprising SixCy. Also, silicon oxycarbide, for purposes of this patent, is a generic name given to a class of materials comprising SixOyCx.
- As depicted in
FIG. 2 , theembodiments 200 begin by first providing a suitable substrate in readiness for processing in accordance with the principles of the invention. As used herein, substrate refers to a semiconductor substrate structure. Such structures can include, for example, the bare silicon surfaces of a wafer or any of the surfaces formed thereon. Additionally, such substrates are not confined to silicon-containing substrates but can include other materials (e.g., GaAs). Such substrates can also comprise multi-level semiconductor structures. In the depicted embodiment, the substrate includes asemiconductor substrate 201. The depicted embodiment includes asemiconductor substrate 201 having copper interconnect structures formed thereon 202. Over thesemiconductor substrate 201 lies an overlying insulatinglayer 203 being formed of a material that includes at least one of silicon and carbon. The insulatinglayer 203 has anopening 204 that exposes the underlyingcopper interconnect structures 202. In preferred implementations the insulatinglayer 203 is formed of a low-K dielectric material. Many materials are suitable for use in accordance with the principles of the invention. A preferred class of materials includes organo-silicate glasses (OSG). Such materials can include without limitation, silicate organic glasses (SiOCH), silicon carbide (SiC) materials, and silicon oxycarbide materials (SiOC). However, other materials can be used. Example dielectric materials include silicon dioxide or combinations of silicon dioxide and other doped dielectrics (e.g., BPSG, PSG). Additionally, the principles of the present invention find particular utility when applied to use with low-K dielectric materials. Example materials can include, without limitation, spin-on and CVD inorganic or organic silicate materials such as silsesquioxanes, silicates, and siloxanes; and, mixtures, or blends, of organic polymers and spin-on glasses. Particular low-K materials include, but are not limited to: Black Diamond 1, Black Diamond 2, and Black Diamond 3 from Applied Materials (of Santa Clara, Calif.); Coral from Novellus Systems, Inc. (of San Jose, Calif.); Aurora from ASM International (of the Netherlands); Orion from Trikon Technologies (of the United Kingdom); AKD from JSR; XLK from Dow Coming (of Midland Mich.); and HOSP or Nanoglass from Honeywell, Inc. (of Morristown, HJ). This list of materials is not intended to be exhaustive but rather illustrative. Additionally, the principles of the present invention find utility when used with materials that incorporate micro-pores to enhance their low-K properties. - On the inner surfaces of the opening 204 a
dielectric barrier layer 205 is formed. Once thedielectric barrier layer 205 is formed, a bulk copper layer can be deposited to form a copper interconnect (plug) 206 that is in electrical contact with the underlyingcopper interconnect structures 202. Thedielectric barrier layer 205 is intended to prevent the diffusion of copper into the insulating layer. The methodologies and materials used for forming such dielectric barrier layers 205 are described in detail hereinbelow. - One approach for forming dielectric barrier layers is disclosed with respect to
FIGS. 3( a)-3(c). The process begins by providing a suitable substrate.FIG. 3( a) depicts one example of atypical substrate 300.FIG. 3( a) is a cross-section view of a portion of the surface of thesubstrate 300. The depicted substrate has asemiconductor substrate surface 301 withcopper interconnect structures 302 formed thereon. Suchcopper interconnect structures 302 can be formed using a wide range of techniques known to those having ordinary skill in the art. Such techniques can include, but are not limited to, single and double damascene processes. At least one overlying insulatinglayer 303 overlying thecopper interconnect structures 302 is provided. The insulatinglayer 303 is configured having anopening 304 that exposes the underlyingcopper interconnect structure 302. Theopening 304 is configured to receive an inlaid conducting structure that is in electrical contact with thetop surface 302 t of underlyingcopper interconnect structure 302. The insulatinglayer 304 is typically formed of a low-K dielectric material. In preferred embodiment the dielectric material includes at least one of silicon and carbon material. Preferred materials include silicate organic glasses and organo-silicate glasses. As has been previously noted, other materials can be used. The methodologies of the present invention are particularly advantageous when used with low-K dielectric layers enhanced with micro-porosities. The depictedsubstrate 300 can be formed using a number of methods known to persons having ordinary skill in the art. - The insulating
layer 303 is then treated to form a dielectric copper barrier layer on the inside surface of the opening. This dielectric copper barrier layer is a dielectric material that provides a barrier to copper diffusion into the insulating layer. Once the dielectric copper barrier layer is formed the opening is filled with copper material to complete the interlayer electrical connection. - Methods of treating the insulating
layer 303 to form a dielectric copper barrier layer will now be discussed. In one implementation, the insulatinglayer 303 is plasma treated to form a dielectric copper barrier layer. Referring toFIG. 3( b), thesubstrate 300 is then placed in aprocessing chamber 310 of a suitable process machine. Suitable machines include, but are not limited to, high-density plasma (HDP) machines, reactive ion etch (RIE) machines, electron beam machine, or downstream plasma machines. One example of satisfactory machine is a Trikon Omega (manufactured by Trikon Technologies, Inc. of the United Kingdom). - In one implementation, an inert gas (e.g., argon (Ar) or helium (He)) is flowed into the
chamber 310 and ignited into aplasma 311. Such plasma is used with a very low bias voltage. Voltage sufficient to enable plasma to reach the bottom of the trenches and vias (e.g., opening 304) is all that is needed. In this implementation, low bias is used to prevent the plasma from excessively sputtering the copper at the bottom of the opening. Due to the substantially non-directional nature of such plasma, such plasmas are referred to herein as substantially anisotropic plasmas. These substantially anisotropic plasmas can be sustained by maintaining low bias voltages in the range of about 0-500V (volts). Preferred implementations maintain bias at less than about 100V. The plasma power is set in the range of about 200-1200 W (watts). Chamber pressures are maintained in the range of about 100 mTorr to about 4 Torr. Flow rates for the inert gases should be in the range of about 100 SCCM (standard cubic centimeters per minute) to about 10 lpm (liters per minute). Process temperatures in thechamber 310 should range from about room temperature to about 400° C. With a preferred range of process temperature being about 200-300° C., with a most preferred process temperature of about 300° C. - Such a process is extremely effective at treating many insulating layers to form dielectric copper barrier layers. The process is particularly advantageous for creating dielectric copper barrier layers in insulating layers constructed of dielectric materials having micro-pores formed therein. The use and formation of such micro-pores are a well-known means for enhancing the low-K properties of dielectric layers. Plasma treating dielectric layers can result in increased density of dielectric material at the treated surface. Such regions of increased density are referred to as “densified” dielectric layers. Densified materials are simply more dense than materials prior to treatment. For example, one common OSG dielectric material having micro-pores has a density of in the range of 1-1.5 g/cm3 (grams per cubic centimeter). After treatment plasma treatment, surface regions of the OSG dielectric material have a density of greater than about 2 g/cm3. Thus, such plasma treated dielectric material is said to be “densified”. This substantial increase in density increases the dielectric layers resistance to copper diffusion into the dielectric material forming the balance of the dielectric layer. Thus, such densified dielectric material forms a dielectric copper barrier layer.
- Although this process can be used to create a dielectric copper barrier layer in many insulating layers, the process is most advantageous when used in conjunction with insulating layers having micro-pores formed therein. Treatment with said plasma for about 15-100 seconds results in a dielectric copper barrier layer about 10 Å to about 200 Å thick. Such a process and the resulting layer are advantageous because such dielectric copper barrier layers are thin (on the order of about 10 Å to about 200 Å) and do not form part of the interconnect metal and so do not restrict the thickness of the copper interconnect. Additionally, the dielectric copper barrier layer does not form on the top surface (e.g., 302 t of
FIG. 3( a)) underlying copper layer at the bottom of an. Therefore, such a dielectric copper barrier layer does not degrade copper interconnect electrical performance. Thus, some of the advantages of the present implementation are the ability to form thicker copper interconnect structures and increased electrical performance in the copper interconnect structures. -
FIG. 3( c) depicts one embodiment of theimproved structure 320 featuring a dielectric copper barrier layer.FIG. 3( c) is a cross-section view of a portion of the surface of the substrate similar to that shown inFIG. 3( a). The depicted embodiment has asemiconductor substrate surface 301 withcopper interconnect structures 302 formed thereon. The least one overlying insulatinglayer 303 includes anopening 304 that exposes the underlyingcopper interconnect structure 302. Theopening 304 is plasma treated to form a dielectriccopper barrier layer 321 on the insulatinglayer 303. Theopening 304 is then filled with copper material to form thecopper interconnect 322. Thiscopper interconnect 322 can be formed using any of the conventional techniques used for forming such structures. Examples, include, but are not limited to, seed layer deposition, bulk copper deposition, and CMP. Further layers and structures can be formed on the surface depicted inFIG. 3( c). - With continued reference to
FIGS. 3( a)-3(c), by plasma treating the dielectric insulatinglayer 303 certain other dielectric copper barrier layers 321 can be formed. For example, indielectric layers 303 having oxygen and silicon in the layers, such plasma treatment reduces the amount of oxygen in the surface ofsuch layers 303 resulting in dielectric copper barrier layers 321 having a higher concentrations of silicon carbide. This processing is particularly suitable for silicate organic glasses (SiOCH) and other organo-silicate glasses. - Another approach for forming dielectric barrier layers is disclosed with respect to
FIGS. 3( a), 4(a) and 4(b). As before, the process begins by providing a suitable substrate. The substrate ofFIG. 3( a) depicts one example of asuitable substrate 300. The depicted substrate has asemiconductor substrate surface 301 withcopper interconnect structures 302 formed thereon. At least one insulatinglayer 303 overlying thecopper interconnect structures 302 is provided. The insulatinglayer 303 is configured having anopening 304 that exposes the underlyingcopper interconnect structure 302. As before, theopening 304 is configured to receive an inlaid conducting structure that is in electrical contact with thetop surface 302 t ofcopper interconnect structure 302. The insulatinglayer 304 is typically formed of a low-K dielectric material. As before the dielectric material includes at least one of silicon and carbon material, preferably silicate organic glasses and organo-silicate glasses. - The insulating
layer 303 is then treated with a reactive material to form a dielectric copper barrier layer on the inside surface of the opening. One type of reactive materials includes H2, CO, CH4, and in some conditions C0 2. When plasmas are formed of such materials they form “reactive” plasmas that react with the material of the insulating layer to form dielectric copper barrier materials that can act as copper diffusion barriers. Moreover, the reactive plasma treatment can act to densify the material of the insulating layer to form dielectric copper barrier materials. Thus, a dielectric copper barrier layer can be formed. Once the dielectric copper barrier layer is formed the opening is filled with copper material to complete the interlayer electrical connection. - Methods of treating the insulating
layer 303 with reactive plasmas to form a dielectric copper barrier layer will now be discussed. Referring toFIG. 4( a), thesubstrate 300 is then placed in aprocessing chamber 401 of a suitable process machine. Suitable machines include, but are not limited to, high-density plasma (HDP) machines, reactive ion etch (RIE) machines, electron beam machine, or downstream plasma machines. Again, a satisfactory machine is a Trikon Omega. - In one implementation, a reactive gas (e.g., CO, H2, CH4, or C0 2) is introduced into the
chamber 401 and ignited into areactive plasma 402. Flow rates for the reactive gases should be in the range of about 100 SCCM to about 10 lpm, preferably about 2000 SCCM. The plasma is ignited using a power of in the range of about 200-1200 W, preferably in a range of about 500-600 W. As before, thereactive plasma 402 is used with a very low bias voltage. A voltage sufficient to enable plasma to reach the bottom of the trenches and vias (e.g., opening 304) is all that is required to establish a satisfactory anisotropic reactive plasma. The low bias is used to prevent the plasma from excessively sputtering the copper at the bottom of the opening or excessively damaging theinsulating layer 303. This plasma can be sustained by maintaining a low bias voltage of in the range of about 0-500V (volts), but preferably less than about 100V. Typically, chamber pressures are maintained in the range of about 100 mTorr to about 4 Torr. Process temperatures in thechamber 401 should range from about room temperature to about 400° C. With a preferred process temperature range of about 200-300° C., with a temperature of about 300° C. being most preferred. - Referring to
FIG. 4( b), a dielectric copper barrier layer is formed. The ignitedreactive plasma 402 is very effective at removing oxygen from the surface of the insulatinglayer 303. This is especially, true where the reactive gas includes H2. As a result the concentration of silicon carbide is increased in the surface of the insulatinglayer 303 forming a dielectriccopper barrier layer 415 on the inside surface theopening 304. Also, carbon containing reactive materials such as CH4, CO, and C0 2 can increase the concentration of silicon carbide in the surface of the insulatinglayer 303 to form a dielectriccopper barrier layer 415 on the inside surface theopening 304. - In a related embodiment, the reactive gas can comprise a nitrogen-containing material (e.g., NO, N2, ammonia, or N0 2). The nitrogen-containing gas is introduced into the
chamber 401 and ignited into areactive plasma 402. Again similar flow rates can be used (e.g., in the range of about 100 SCCM to about 10 lpm). The plasma can be ignited at a power in the range of about 200-1200 W, preferably about 500-600 W. As before, the nitrogen-containingreactive plasma 402 is used with a very low bias voltage to establish an anisotropic plasma. This plasma can be sustained by maintaining a low bias voltage of in the range of about 0-500V (volts), but preferably less than about 100V. Again, chamber pressures are maintained in the range of about 100 mTorr to about 4 Torr. Process temperatures in thechamber 401 should range from about room temperature to about 400° C. With a preferred process temperature range of about 200-300° C., with a temperature of about 300° C. being most preferred. Nitrogen-containing plasma can generate SiCN (silicon carbon nitrides) in the surface of the insulatinglayer 303 to form a dielectriccopper barrier layer 415 on the inside surface theopening 304. Such SiCN rich dielectric copper barrier layers 415 function well a s barriers to copper diffusion into the insulatinglayer 303. - An additional advantage of such reactive plasmas is that, like plasmas generated using inert materials, they can also densify the surface of the insulating
layer 303 on the inside surface theopening 304 to form improved dielectric copper barrier layers 415. Thus, as discussed above, the process is particularly advantageous for creating dielectric copper barrier layers in insulating layers constructed of dielectric materials having micro-pores formed therein. - Exposing a insulating
layer 303 to reactive plasma for about 15-100 seconds results in a dielectriccopper barrier layer 415 of about 10 Å to about 200 Å thick. As before, the resulting layer are advantageous because such dielectric copper barrier layers are thin (on the order of about 10 Å to about 200 Å) and do not restrict the thickness of the copper interconnect. Additionally, unlike conventional processes the dielectric copper barrier layer does not form on thetop surface 302 t of the underlying copper layer. Once the dielectriccopper barrier layer 415 is formed, theopening 304 is then filled with copper material to form thecopper interconnect 416. Thiscopper interconnect 416 can be formed using any of the conventional techniques used for forming such structures. - Yet another approach for forming dielectric barrier layers is disclosed with respect to
FIGS. 3( a), 5(a) and 5(b). This embodiment comprises forming one or more layers of dielectric copper barrier material over one another to form a suitable dielectric copper barrier layer. Again, the process begins by providing a suitable substrate such as that depicted and described with respect toFIG. 3( a). As depicted inFIG. 5( a), thesubstrate 300 is then placed in aprocessing chamber 501 of a suitable process machine. As before, suitable machines include, but are not limited to, high-density plasma (HDP) machines, reactive ion etch (RIE) machines, electron beam machine, or downstream plasma machines. Again, one satisfactory machine is a Trikon Omega. - Referring to
FIGS. 5( a) and 5(b), in one implementation, aprecursor gas 502 is flowed into thechamber 401 and deposited onto the inside surface of theopening 304 to form aprecursor sub-layer 511. Some preferred precursor materials are methyl silanes, vinyl silanes, and methyl-vinyl silanes. For example, suitable precursor materials include compounds comprising (R1x)(R2y) Si Hz wherein R1 consists of methyl groups (—CH3), R2 consists of vinyl groups (—CH═CH2), H consists of hydrogen and wherein x is an integer from 0-4, y is an integer from 0-4, and z is an integer from 0-4. Specific examples include 4-methylsilane (Si(CH3)4, also known as 4MS), 3-methylsilane (Si(CH3)3H, also known as 3MS), 2-methylsilane (Si(CH3)2H2, also known as 2MS), and also 1-methylsilane (Si(CH3)H3, also known as 1MS). However, vinyl silanes are also suitable. Specific examples include, without limitation, Si(C2H3)4, Si(C2H3)3H, Si(C2H3)2H2, and Si(C2H3)H3. Moreover, methyl-vinyl silanes can also be used. Typical examples of such methyl-vinyl silanes include, but are not limited to vinyl tri-methyl silane (C2H3)(CH3)3 Si, di-vinyl di-methyl silane (C2H3)2(CH3)2 Si, tri-vinyl methyl silane (C2H3)3(CH3) Si, and tetra-vinyl silane (C2H3)4 Si as well as many other similar materials known to persons having ordinary skill in the art. - In one exemplar process,
precursor materials 502 are flowed into the process chamber, typically with an inert carrier gas (e.g., argon (Ar) or helium (He)). Such precursor material deposits onto the inside of theopening 304 to form aprecursor sub-layer 511. In one embodiment, the precursor gas is introduced into the chamber at a flow rate of about 100 SCCM to about 1 lpm. As the precursor materials are flowed into the process chamber, a pressure in the range of about 10 mTorr to about 2 Torr is maintained. A temperature of −100° C. to about 400° C. is maintained. A preferred temperature is in the range of about −30° C. to about 100° C. Under these conditions aprecursor sub-layer 511 is formed on the inside of theopening 304.Such sub-layers 511 can be formed having very small thicknesses on the order of about 2-5 Å. The precursor materials are then evacuated from thechamber 503 ofFIG. 5( a). - Once the chamber is evacuated, the precursor sub-layers are treated to generate a dielectric copper barrier sub-layer. In one embodiment, inert materials are introduced to the
chamber 501 after the precursor materials are evacuated from the chamber. The inert materials are ignited into a plasma. Such materials include, but are not limited to argon and helium. The plasma is ignited using a power of in the range of about 200-800 W. Once formed, the plasma is used with a very low bias voltage. Bias voltages in the range of about 0-500V (volts) can be used with voltages less than about 100V being preferred. This forms an anisotropic plasma which is used to change theprecursor sub-layer 511 into a dielectric copper barrier sub-layer. During such process chamber pressures are maintained in the range of about 100 mTorr to about 2 Torr. Flow rates for the inert gases should also be in the range of about 100 SCCM to about 10 lpm, with flow rates in the range of 1-2 lpm being preferred. Process temperatures in thechamber 501 should range from about −30° C. to about 400° C. With a preferred process temperature of about 100° C. to about 300° C. As indicated, the plasma treatment reacts with theprecursor sub-layer 511 to form a dielectric copper barrier sub-layer. It should be noted that theprecursor sub-layer 511 can be treated in other ways to form a dielectric copper barrier sub-layer. Such treatment can comprise treatment with a low intensity electron beam or exposure to photons (e.g., UV radiation) to form a dielectric copper barrier sub-layer. Additionally, heating can be used to form a dielectric copper barrier sub-layer. Typically, such treatment forms a form a dielectric copper barrier sub-layer formed of silicon carbide materials. In an alternative embodiment, theinert gases 502 can be replaced by carbon monoxide or O2 gas which is ignited into plasma which then reacts theprecursor sub-layer 511 to form a dielectric copper barrier sub-layer. A dielectric copper barrier sub-layer formed in this manner commonly includes silicon oxycarbide. In yet another implementation, theinert gas 502 can be replaced by a nitrogen-containing material which is ignited into plasma which then reacts theprecursor sub-layer 511 to form a dielectric copper barrier sub-layer. A dielectric copper barrier sub-layer formed in this manner commonly includes SiCN. Suitable nitrogen-containing materials include, N2, NO, N0 2, with N2 being preferred. In some implementations, the precursor materials can form on the exposedtop portion 521 t underlyingcopper interconnect structure 521. In such cases the bias voltage is increased to sputter the precursor and/or dielectric copper barrier material off the underlyingcopper interconnect structure 521. - Once the dielectric copper barrier sub-layer formed. The forgoing process can be repeated to form additional precursor sub-layers which are reacted to form additional dielectric copper barrier sub-layers over the underlying dielectric copper barrier sub-layers. One such embodiment is depicted in
FIG. 5( c). The initial substrate is much the same as depicted and described with respect toFIG. 3( a). Asemiconductor substrate 301 having acopper interconnect structure 302 formed thereon is depicted. A plurality of dielectriccopper barrier sub-layers opening 304 in the insulatinglayer 303. The several dielectriccopper barrier sub-layers copper barrier layer 534. Final dielectric copper barrier layers 534 are typically formed to thicknesses ranging from about 20 Å to about 300 Å. Such layers are typically, formed using a plurality of 2 Å thick sub-layers. - The present invention has been particularly shown and described with respect to certain preferred embodiments and specific features thereof. However, it should be noted that the above-described embodiments are intended to describe the principles of the invention, not limit its scope. Therefore, as is readily apparent to those of ordinary skill in the art, various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims. Other embodiments and variations to the depicted embodiments will be apparent to those skilled in the art and may be made without departing from the spirit and scope of the invention as defined in the following claims. Further, reference in the claims to an element in the singular is not intended to mean “one and only one” unless explicitly stated, but rather, “one or more”.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/191,171 US7646077B2 (en) | 2002-12-16 | 2008-08-13 | Methods and structure for forming copper barrier layers integral with semiconductor substrates structures |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/321,938 US6939800B1 (en) | 2002-12-16 | 2002-12-16 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
US11/131,003 US7427563B2 (en) | 2002-12-16 | 2005-05-16 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
US12/191,171 US7646077B2 (en) | 2002-12-16 | 2008-08-13 | Methods and structure for forming copper barrier layers integral with semiconductor substrates structures |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/131,003 Division US7427563B2 (en) | 2002-12-16 | 2005-05-16 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080303155A1 true US20080303155A1 (en) | 2008-12-11 |
US7646077B2 US7646077B2 (en) | 2010-01-12 |
Family
ID=34885820
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/321,938 Expired - Fee Related US6939800B1 (en) | 2002-12-16 | 2002-12-16 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
US11/131,003 Expired - Lifetime US7427563B2 (en) | 2002-12-16 | 2005-05-16 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
US12/191,171 Expired - Lifetime US7646077B2 (en) | 2002-12-16 | 2008-08-13 | Methods and structure for forming copper barrier layers integral with semiconductor substrates structures |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/321,938 Expired - Fee Related US6939800B1 (en) | 2002-12-16 | 2002-12-16 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
US11/131,003 Expired - Lifetime US7427563B2 (en) | 2002-12-16 | 2005-05-16 | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
Country Status (1)
Country | Link |
---|---|
US (3) | US6939800B1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8647535B2 (en) | 2011-01-07 | 2014-02-11 | International Business Machines Corporation | Conductive metal and diffusion barrier seed compositions, and methods of use in semiconductor and interlevel dielectric substrates |
US20140239246A1 (en) * | 2013-02-28 | 2014-08-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
US20150017799A1 (en) * | 2012-09-21 | 2015-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
US9831171B2 (en) * | 2014-11-12 | 2017-11-28 | Infineon Technologies Ag | Capacitors with barrier dielectric layers, and methods of formation thereof |
KR20190136879A (en) * | 2018-05-31 | 2019-12-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Barrier layer formation for conductive feature |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6821571B2 (en) * | 1999-06-18 | 2004-11-23 | Applied Materials Inc. | Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers |
US6939800B1 (en) * | 2002-12-16 | 2005-09-06 | Lsi Logic Corporation | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
JP3898133B2 (en) * | 2003-01-14 | 2007-03-28 | Necエレクトロニクス株式会社 | A method of forming a SiCHN film. |
US7573133B2 (en) * | 2003-12-09 | 2009-08-11 | Uri Cohen | Interconnect structures and methods for their fabrication |
US7253125B1 (en) | 2004-04-16 | 2007-08-07 | Novellus Systems, Inc. | Method to improve mechanical strength of low-k dielectric film using modulated UV exposure |
US7244674B2 (en) * | 2004-04-27 | 2007-07-17 | Agency For Science Technology And Research | Process of forming a composite diffusion barrier in copper/organic low-k damascene technology |
US7384693B2 (en) * | 2004-04-28 | 2008-06-10 | Intel Corporation | Diamond-like carbon films with low dielectric constant and high mechanical strength |
US20060081965A1 (en) * | 2004-10-15 | 2006-04-20 | Ju-Ai Ruan | Plasma treatment of an etch stop layer |
US9659769B1 (en) | 2004-10-22 | 2017-05-23 | Novellus Systems, Inc. | Tensile dielectric films using UV curing |
US7510982B1 (en) | 2005-01-31 | 2009-03-31 | Novellus Systems, Inc. | Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles |
US8980769B1 (en) | 2005-04-26 | 2015-03-17 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US8282768B1 (en) | 2005-04-26 | 2012-10-09 | Novellus Systems, Inc. | Purging of porogen from UV cure chamber |
US8137465B1 (en) | 2005-04-26 | 2012-03-20 | Novellus Systems, Inc. | Single-chamber sequential curing of semiconductor wafers |
US8889233B1 (en) | 2005-04-26 | 2014-11-18 | Novellus Systems, Inc. | Method for reducing stress in porous dielectric films |
US8454750B1 (en) | 2005-04-26 | 2013-06-04 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
DE102005052052B4 (en) * | 2005-10-31 | 2008-02-07 | Advanced Micro Devices, Inc., Sunnyvale | Electrodeposition layer for metallization layer with improved adhesion, etch selectivity and density and method for producing a dielectric layer stack |
US20070126120A1 (en) * | 2005-12-06 | 2007-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
US7892972B2 (en) * | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
US9087877B2 (en) * | 2006-10-24 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-k interconnect structures with reduced RC delay |
US8465991B2 (en) | 2006-10-30 | 2013-06-18 | Novellus Systems, Inc. | Carbon containing low-k dielectric constant recovery using UV treatment |
US7851232B2 (en) * | 2006-10-30 | 2010-12-14 | Novellus Systems, Inc. | UV treatment for carbon-containing low-k dielectric repair in semiconductor processing |
US10037905B2 (en) * | 2009-11-12 | 2018-07-31 | Novellus Systems, Inc. | UV and reducing treatment for K recovery and surface clean in semiconductor processing |
US8242028B1 (en) | 2007-04-03 | 2012-08-14 | Novellus Systems, Inc. | UV treatment of etch stop and hard mask films for selectivity and hermeticity enhancement |
US8211510B1 (en) | 2007-08-31 | 2012-07-03 | Novellus Systems, Inc. | Cascaded cure approach to fabricate highly tensile silicon nitride films |
US7964442B2 (en) | 2007-10-09 | 2011-06-21 | Applied Materials, Inc. | Methods to obtain low k dielectric barrier with superior etch resistivity |
JP4423379B2 (en) * | 2008-03-25 | 2010-03-03 | 合同会社先端配線材料研究所 | Copper wiring, semiconductor device, and method of forming copper wiring |
JP5554951B2 (en) * | 2008-09-11 | 2014-07-23 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US9050623B1 (en) | 2008-09-12 | 2015-06-09 | Novellus Systems, Inc. | Progressive UV cure |
US8610283B2 (en) * | 2009-10-05 | 2013-12-17 | International Business Machines Corporation | Semiconductor device having a copper plug |
US8415805B2 (en) | 2010-12-17 | 2013-04-09 | Skyworks Solutions, Inc. | Etched wafers and methods of forming the same |
US20120153477A1 (en) * | 2010-12-17 | 2012-06-21 | Skyworks Solutions, Inc. | Methods for metal plating and related devices |
US9324634B2 (en) | 2011-11-08 | 2016-04-26 | International Business Machines Corporation | Semiconductor interconnect structure having a graphene-based barrier metal layer |
US8980740B2 (en) * | 2013-03-06 | 2015-03-17 | Globalfoundries Inc. | Barrier layer conformality in copper interconnects |
US9460997B2 (en) | 2013-12-31 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for semiconductor devices |
US9502255B2 (en) | 2014-10-17 | 2016-11-22 | Lam Research Corporation | Low-k damage repair and pore sealing agents with photosensitive end groups |
TWI575660B (en) * | 2015-06-11 | 2017-03-21 | 旺宏電子股份有限公司 | Circuit and method for forming the same |
US9847221B1 (en) | 2016-09-29 | 2017-12-19 | Lam Research Corporation | Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing |
US11276764B1 (en) * | 2020-08-09 | 2022-03-15 | Global Communication Semiconductors, Llc | Method of making high frequency InGaP/GaAs HBTs |
US11652055B2 (en) * | 2021-06-23 | 2023-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure with hybrid barrier layer |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5789867A (en) * | 1994-01-19 | 1998-08-04 | Tel America, Inc. | Apparatus and method for igniting plasma in a process module |
US6114259A (en) * | 1999-07-27 | 2000-09-05 | Lsi Logic Corporation | Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage |
US6159871A (en) * | 1998-05-29 | 2000-12-12 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6342448B1 (en) * | 2000-05-31 | 2002-01-29 | Taiwan Semiconductor Manufacturing Company | Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process |
US6365527B1 (en) * | 2000-10-06 | 2002-04-02 | United Microelectronics Corp. | Method for depositing silicon carbide in semiconductor devices |
US6413877B1 (en) * | 2000-12-22 | 2002-07-02 | Lam Research Corporation | Method of preventing damage to organo-silicate-glass materials during resist stripping |
US20020140101A1 (en) * | 2001-03-27 | 2002-10-03 | Advanced Micro Devices, Inc. | Stabilizing fluorine etching of low-k materials |
US6794311B2 (en) * | 2000-07-14 | 2004-09-21 | Applied Materials Inc. | Method and apparatus for treating low k dielectric layers to reduce diffusion |
US6939800B1 (en) * | 2002-12-16 | 2005-09-06 | Lsi Logic Corporation | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
US6974766B1 (en) * | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6528423B1 (en) * | 2001-10-26 | 2003-03-04 | Lsi Logic Corporation | Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material |
US6537896B1 (en) * | 2001-12-04 | 2003-03-25 | Lsi Logic Corporation | Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material |
US6541397B1 (en) * | 2002-03-29 | 2003-04-01 | Applied Materials, Inc. | Removable amorphous carbon CMP stop |
-
2002
- 2002-12-16 US US10/321,938 patent/US6939800B1/en not_active Expired - Fee Related
-
2005
- 2005-05-16 US US11/131,003 patent/US7427563B2/en not_active Expired - Lifetime
-
2008
- 2008-08-13 US US12/191,171 patent/US7646077B2/en not_active Expired - Lifetime
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5789867A (en) * | 1994-01-19 | 1998-08-04 | Tel America, Inc. | Apparatus and method for igniting plasma in a process module |
US6159871A (en) * | 1998-05-29 | 2000-12-12 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6974766B1 (en) * | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US6114259A (en) * | 1999-07-27 | 2000-09-05 | Lsi Logic Corporation | Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage |
US6342448B1 (en) * | 2000-05-31 | 2002-01-29 | Taiwan Semiconductor Manufacturing Company | Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process |
US6794311B2 (en) * | 2000-07-14 | 2004-09-21 | Applied Materials Inc. | Method and apparatus for treating low k dielectric layers to reduce diffusion |
US6365527B1 (en) * | 2000-10-06 | 2002-04-02 | United Microelectronics Corp. | Method for depositing silicon carbide in semiconductor devices |
US6413877B1 (en) * | 2000-12-22 | 2002-07-02 | Lam Research Corporation | Method of preventing damage to organo-silicate-glass materials during resist stripping |
US20020140101A1 (en) * | 2001-03-27 | 2002-10-03 | Advanced Micro Devices, Inc. | Stabilizing fluorine etching of low-k materials |
US6939800B1 (en) * | 2002-12-16 | 2005-09-06 | Lsi Logic Corporation | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
US7427563B2 (en) * | 2002-12-16 | 2008-09-23 | Lsi Corporation | Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8735284B2 (en) | 2011-01-07 | 2014-05-27 | International Business Machines Corporation | Conductive metal and diffusion barrier seed compositions, and methods of use in semiconductor and interlevel dielectric substrates |
US8647535B2 (en) | 2011-01-07 | 2014-02-11 | International Business Machines Corporation | Conductive metal and diffusion barrier seed compositions, and methods of use in semiconductor and interlevel dielectric substrates |
US9842767B2 (en) * | 2012-09-21 | 2017-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming an interconnection |
US20150017799A1 (en) * | 2012-09-21 | 2015-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
US9954168B2 (en) * | 2013-02-28 | 2018-04-24 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
US20170110659A1 (en) * | 2013-02-28 | 2017-04-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
US9583538B2 (en) * | 2013-02-28 | 2017-02-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device having crossing interconnects separated by stacked films |
US20140239246A1 (en) * | 2013-02-28 | 2014-08-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing same |
US10147878B2 (en) | 2013-02-28 | 2018-12-04 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
US10505113B2 (en) | 2013-02-28 | 2019-12-10 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
US11355705B2 (en) | 2013-02-28 | 2022-06-07 | Kioxia Corporation | Semiconductor memory device and method for manufacturing same |
US9831171B2 (en) * | 2014-11-12 | 2017-11-28 | Infineon Technologies Ag | Capacitors with barrier dielectric layers, and methods of formation thereof |
KR20190136879A (en) * | 2018-05-31 | 2019-12-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Barrier layer formation for conductive feature |
KR102210976B1 (en) | 2018-05-31 | 2021-02-03 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Barrier layer formation for conductive feature |
US11043413B2 (en) | 2018-05-31 | 2021-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer formation for conductive feature |
US11183424B2 (en) | 2018-05-31 | 2021-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer formation for conductive feature |
Also Published As
Publication number | Publication date |
---|---|
US6939800B1 (en) | 2005-09-06 |
US7427563B2 (en) | 2008-09-23 |
US7646077B2 (en) | 2010-01-12 |
US20050208758A1 (en) | 2005-09-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7646077B2 (en) | Methods and structure for forming copper barrier layers integral with semiconductor substrates structures | |
US7728433B2 (en) | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures | |
US7851384B2 (en) | Method to mitigate impact of UV and E-beam exposure on semiconductor device film properties by use of a bilayer film | |
US6136680A (en) | Methods to improve copper-fluorinated silica glass interconnects | |
US7265038B2 (en) | Method for forming a multi-layer seed layer for improved Cu ECP | |
US6939797B2 (en) | Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof | |
US7378350B2 (en) | Formation of low resistance via contacts in interconnect structures | |
US7176571B2 (en) | Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure | |
US6566262B1 (en) | Method for creating self-aligned alloy capping layers for copper interconnect structures | |
KR100652334B1 (en) | A method for depositing a metal layer on a semiconductor interconnect structure having a capping layer | |
IL162435A (en) | Bilayer hdp cvd/pe cvd cap in advanced beol interconnect structure and method thereof | |
WO2007062383A2 (en) | Integration of pore sealing liner into dual-damascene methods and devices | |
US20010042922A1 (en) | Semiconductor device and method for making the same | |
US20090176367A1 (en) | OPTIMIZED SiCN CAPPING LAYER | |
US20080188074A1 (en) | Peeling-free porous capping material | |
US20040251547A1 (en) | Method of a non-metal barrier copper damascene integration | |
US6734110B1 (en) | Damascene method employing composite etch stop layer | |
US6713874B1 (en) | Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics | |
US6998343B1 (en) | Method for creating barrier layers for copper diffusion | |
US7199048B2 (en) | Method for preventing metalorganic precursor penetration into porous dielectrics | |
US6726996B2 (en) | Laminated diffusion barrier | |
US6576545B1 (en) | Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers | |
JP2004214566A (en) | Method for manufacturing semiconductor device and semiconductor device | |
US20070155186A1 (en) | OPTIMIZED SiCN CAPPING LAYER | |
US7763538B2 (en) | Dual plasma treatment barrier film to reduce low-k damage |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031 Effective date: 20140506 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388 Effective date: 20140814 |
|
AS | Assignment |
Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 Owner name: LSI CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0001 Effective date: 20171208 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0608 Effective date: 20171208 |
|
AS | Assignment |
Owner name: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERA Free format text: SECURITY INTEREST;ASSIGNORS:HILCO PATENT ACQUISITION 56, LLC;BELL SEMICONDUCTOR, LLC;BELL NORTHERN RESEARCH, LLC;REEL/FRAME:045216/0020 Effective date: 20180124 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: BELL NORTHERN RESEARCH, LLC, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:060885/0001 Effective date: 20220401 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:060885/0001 Effective date: 20220401 Owner name: HILCO PATENT ACQUISITION 56, LLC, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:060885/0001 Effective date: 20220401 Owner name: BELL NORTHERN RESEARCH, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 Owner name: HILCO PATENT ACQUISITION 56, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 |