US20090032888A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20090032888A1 US20090032888A1 US12/251,959 US25195908A US2009032888A1 US 20090032888 A1 US20090032888 A1 US 20090032888A1 US 25195908 A US25195908 A US 25195908A US 2009032888 A1 US2009032888 A1 US 2009032888A1
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- sidewall spacer
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- 239000004065 semiconductor Substances 0.000 title claims description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 32
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- 239000007789 gas Substances 0.000 description 22
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- 239000008367 deionised water Substances 0.000 description 20
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- 238000005530 etching Methods 0.000 description 16
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- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 14
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- 229910001868 water Inorganic materials 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
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- 229910052760 oxygen Inorganic materials 0.000 description 9
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- 239000002019 doping agent Substances 0.000 description 8
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- 235000011167 hydrochloric acid Nutrition 0.000 description 6
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonium chloride Substances [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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- 238000007704 wet chemistry method Methods 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Definitions
- the present disclosure relates generally to semiconductor devices having sidewall structures.
- FIGS. 1-9 illustrate cross-sectional views of a substrate location during various processing stages used to form a transistor in accordance with a specific embodiment of the present disclosure.
- FIG. 10 illustrates a portion of a device formed using the methods described in accordance with a specific embodiment of the present disclosure.
- location 10 is exposed to a solution containing HF, after anneal 40 followed by forming an epitaxial layer 42 at source/drain locations of the transistor being formed. After the epitaxial layer is formed dopants are implanted to form doped regions 46 that facilitate formation of deep source/drain regions of the transistor location.
- the HF containing solution can include an aqueous solution of deionized water and hydrofluoric acid (HF or hydrogen fluoride in water) aqueous solution of approximately 30:1 (volumetric ratio) at 21 degrees Celsius, for a time period ranging from between 50-60 seconds.
- the weight percentage of HF recommended for the HF aqueous solution is 49% in a balance of deionized water (H 2 O).
- contaminates on the surface of a substrate are subjected to a cleaning process comprising applying a plasma to a surface of the active regions produce a reduction reaction with the contaminates in an upper portion of the surface of the active regions.
- the plasma comprises H 2 . While the plasma is being applied to the upper portion of the exposed active regions, the resultant products or vapor byproducts of the reduction reaction are removed by the normal vacuum process within the chamber. Therefore, contaminates contained in the vapor byproducts and are vented away, leaving the upper portion of the surface of the active regions suitably clean for the ensuing epitaxial process.
- the plasma process parameters comprise a gas flow of 450 sccm H2 and 300 sccm argon, at a chamber temperature of 400 degrees Celsius, with a high frequency (HF) power setting of 700 W, and a low frequency (LF) power setting of between approximately 50 to 100 W.
- Chamber pressure is 1 Torr, and the spacing between the surface of the active region and the faceplate of the tool (not shown) should be 300 mils.
- plasma process parameters comprise a gas flow ranging from between 100-800 sccm H 2 and from between 100 and 600 sccm argon. Chamber temperatures can range between 300 to 450 degrees Celsius, and HF power settings from between 400-900 W, with LF power settings varying from between 0-150 W.
- etch chambers or the like.
- Differences in chamber design, power settings, and species, e.g., H 2 with or H 2 without helium or nitrogen, will result in different thickness of the layer after anneal.
- the layer after anneal will be between 20 and 50 Angstroms thick.
- This plasma cleaning process also results in passivation of Si—H bonds in the layer after anneal. No wet cleaning dip with hydrofluoric (HF) acid prior to SEG is necessary.
- HF hydrofluoric
- the reduced temperature of this H 2 plasma cleaning treatment results in a reduction of the SEG process thermal budget of more than 100 degrees Celsius.
- pre-SEG cleaning processes are conducted at approximately 900 degrees Celsius or greater.
- the cleaning process occurs at less than approximately 800 degrees Celsius.
- the cleaning process occurs at less than approximately 500 degrees Celsius or less.
- the cleaning processes of the present disclosure could be conducted at less than approximately 700 degrees Celsius or less, or even at less than approximately 600 degrees Celsius or less.
- An O 2 plasma production utilizes O 2 gas at a flow rate of 400 sccm, a pressure of 5 Torr, an HF of 300 W, an LF of 100 W, and a temperature of 400 degrees Celsius, with the time ranging from between about 10 to about 120 seconds.
- the spacing between the surface of the active regions and the faceplate of the vapor deposition apparatus (not shown) should be 400 mils.
- the plasma production utilizes O 2 gas at a flow rate of between 100 and 1000 sccm, a pressure ranging from between 2-10 Torr, an HF ranging between 200-500 W, an LF ranging between 50-200 W, a temperature ranging between 300-450 degrees Celsius, for a time ranging from between approximately 10 to approximately 120 seconds.
- an overflow rinse utilizing deionized water is performed for a period ranging from approximately 120 to 600 seconds with a typical rinse being about 400 seconds.
- the cleaning process of portion 100 results in etching away of the surface contamination/debris located on substrate 10 resulting from offset spacer formation and/or dopant implantation.
- the upper semiconductor surface, i.e. silicon surface, of substrate 10 is also slightly etched, for example, from one to several mono layers of silicon, during the HF etch.
- the SC-1 utilizes an aqueous solution of ammonium hydroxide:hydrogen peroxide:deionized water at a ratio of approximately 1:1-4:6-40, at a temperature of approximately 60 degrees Celsius for approximately 72 minutes, to etch approximately 100 Angstroms of silicon.
- ammonium hydroxide NH 4 OH
- ammonia solution typically contains between 12% and 44% ammonia before dilution
- dilute ammonia or concentrated ammonia.
- a first quick dry rinse is conducted for approximately 3 minutes.
- the SC-2 utilizes a solution of hydrochloric acid:hydrogen peroxide:deionized water at an initial ratio of approximately 1:1:50 at a temperature of approximately 60 degrees for about 5 minutes.
- a second quick dry rinse is then conducted.
- hydrochloric acid HCl
- hydrochloric acid are hydrogen chloride, anhydrous hydrogen chloride, aqueous hydrogen chloride, chlorohydric acid, spirit of salts, and muriatic acid.
- the temperature range of the SC-1 is expected to be approximately 55 to 85 degrees Celsius, with the etch occurring in a shorter period of time at higher temperatures than at lower temperatures. It is expected that the SC-1 etching will be better controlled at temperatures in the range of 55-80 degrees Celsius and better still at temperatures in the range of 55-75 degrees Celsius. Generally, it is expected that the substrate will be exposed to the SC-1 etch process for longer that 60 minutes. When the oxidizer stops protecting the silicon surface, the ammonium hydroxide (NH 4 OH) starts to etch the silicon. Thus, a small amount of silicon can be etched in a controlled manner.
- the SC-1 can be performed in a re-usable bath where the solution is re-circulated and heated to maintain the desired temperature.
- a passivation layer formed by the H 2 O 2 prevents this attack by the NH 4 OH.
- H 2 O 2 decomposes in the course to form O 2 and H 2 O.
- the first quick dry rinse is conducted for approximately 3 minutes.
- the subsequent SC-2 utilizes a solution of hydrochloric acid:hydrogen peroxide:deionized water at a ratio of approximately 1:1:50 at a temperature of approximately 60 degrees for about 5 minutes.
- a quick dry rinse with deionized water, followed by an IPA dry process, is performed following the SC-2.
- the IPA dry process uses a heated IPA vapor at approximately 82 degrees Celsius.
- the IPA vapor is generated in a separate chamber with 100% N 2 bubbled through 100% IPA (heated to 82 degrees Celsius).
- the IPA condenses on the wafer, and the solution drips off the bottom of the wafer.
- the IPA vapor concentration is slowly diluted to 100% N 2 before the wafers are removed from the rinsing/drying tank.
- the substrate will be further recessed (etched) as a result of the cleaning process.
- an HF: H2O etch can be conducted at an aqueous solution ratio of 200:1 for about 65 seconds, which typically results in approximately 30 Angstroms of oxide removal.
- the HF: H2O etch 8 is followed by a rinse with deionized water for approximately a 10 minute duration.
- the deionized water rinse is followed by an IPA dry as described in the preceding paragraph.
- the source/drain regions of the substrate are ready for ion implantation or selective epitaxial growth.
- the SC-1 process comprises a pre-rinse with deionized water of approximately 30 seconds duration.
- the pre-rinse is followed by a SC-1 solution at a ratio of approximately 1:1-4:6-40, which includes the subranges of 0.25:1:5, 0.5:1:5, 1:1:5, 1:1:6, 1:4:20, and 1:1:40, ammonium hydroxide: hydrogen peroxide: deionized water at a temperature of approximately 60 degrees Celsius for approximately 5 minutes.
- a quick dump rinse (QDR) is then performed for approximately 3 minutes.
- an SC-2 cleaning process is performed.
- the SC-2 cleaning process includes utilizing an aqueous solution of hydrochloric acid:hydrogen peroxide:deionized water at a ratio of approximately 1:1:50 at a temperature of approximately 60 degrees Celsius for approximately 5 minutes.
- a QDR is then performed, and portion 200 is ready for the third cleaning.
- the weight percent composition of the hydrochloric acid: hydrogen peroxide: deionized water is 29% (weight percent) hydrochloric acid and 30% (weight percent) hydrogen peroxide in a balance of deionized water.
- the above-described cleaning process has been found to facilitate formation of an epitaxial layer on a semiconductor surface, specifically silicon. Because various etch processes can etch N- and P-type regions at different rates, it can be useful to amorphize an upper-most surface of the source/drain regions prior to the above-described clean to reduce any preferential etch differences between substrate regions of differing dopant types.
- the above-described clean process can etch the N-type silicon preferentially, as compared to the P-type silicon, resulting in a quality difference of the SEG between the N and P regions after SEG processing.
- Etch rate differences between N- and P-type regions can allow for contaminates to remain in the lesser-etched region.
- an etch process that does not etch P-type regions at the same rate as N-type regions can result in P-regions maintaining embedded carbon that is incorporated from previous process steps. Without appropriate etching of silicon in the P-type regions during the clean, the carbon will remain, and the SEG will grow inconsistently.
- Amorphizing the source/drain regions can reduce etch differences associated with the above-described cleaning process as well as other processes that are used to etch doped substrate regions, thereby improving the quality of both the N and P regions.
- N- and P-type extensions formed in the source/drain regions are amorphized by being implanted with the Xe, at a dose of 2E14 and energy of 10 keV, to create an amorphous depth of 100 A.
- a spacer structure having an undercut can be used to reduce or inhibit facet formation during a selective epitaxial growth process.
- Such a process can allow for greater lateral uniformity of junction or silicide features during implantation or silicidation processes, and can be accomplished by using a spacer formed with a bi-layer of materials, e.g., a thin liner, such as portion 29 of FIG. 1 , of one material underlying another layer of material from which the ‘main’ spacer is formed.
- the thin liner and other material layer are selected such that the two materials are selectively etchable with respect to the other, for example, a thin oxide liner and a nitride layer.
- oxygen can be added to the gas mixture flowing into the plasma reactor during etch.
- the addition of oxygen during the etching process is an amount between 2 percent and 15 percent by volume.
- the plasma reactor may be of any type which provides ion bombardment, e.g., capacitively-coupled parallel-plate reactor, or inductively coupled plasma with wafer (RF) bias.
- the wall temperature of the plasma reactor during etching is between 20 degrees C. and 60 degrees C., while the wafer platen (chuck) temperature is between 50 degrees C. and 80 degrees C.
- the gas mixture has a total gas flow during etching of between 75 sccm and 150 sccm for 200 mm wafers.
- the total gas flow would require an increase for 300 mm wafers, in order to compensate for the increase in the plasma reactor chamber volume.
- the chamber pressure is in the range of 50-150 mtorr for 200 mm wafers using capacitively coupled plasma reactor systems. It should be noted that the chamber pressure necessarily depends upon the size of the chamber, as well as the manufacturer of the plasma reactor equipment.
- the examples presented herein reference Applied Material's MERIE (magnetically enhanced reactive ion etch) systems.
- the amount of oxygen added is dependant upon the particular etch chemistry chosen.
- An exemplary etch chemistry could be CF4, HBr, and He—O2, with gas flow ratios, by volume, of CF4:HBr:He—O2 of approximately 10:(2-6):(1-6).
- the ratio of He—O2 used is 70/30 percent by volume, however, other appropriate ratios would work as well.
- addition of oxygen during the etching process is an amount between 2% and 15% by volume. The addition of oxygen does not greatly alter the resultant spacer 16 profile, although small alterations are possible. This could, however, be compensated for by changing (i.e., increasing or decreasing) the thickness of nitride layer.
- the addition of oxygen during the etching process does not require adjustments of other etch process parameters.
- the addition of oxygen enhances the etch selectivity of the nitride layer 14 to the liner oxide layer 15 .
- the etch selectivity for silicon nitride is between 1:2 and 1:3.
Abstract
A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
Description
- The present application is a divisional of U.S. patent application Ser. No. 11/209,871 (Attorney Docket number 1458-H1949) entitled “METHOD OF FORMING A SEMICONDUCTOR DEVICE,” filed on Aug. 23, 2005, which is a continuation-in-part of U.S. patent application Ser. No. 10/969,774 (now abandoned) entitled “DEVICE COMPRISING AN EPITAXIAL LAYER AND METHOD THEREOF”, filed on Oct. 20, 2004.
- The present disclosure relates generally to semiconductor devices having sidewall structures.
- As critical dimensions of semiconductor-based transistors become smaller the effects of surface contamination on various processing stages can become more pronounced. For example, increased junction leakage can occur subsequent to silicidation of an epitaxial layer when the epitaxial layer is disposed upon a rough surface as a result of surface contamination. Therefore, a method of manufacturing overcoming problems such as this would be useful.
- It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity.
-
FIGS. 1-9 illustrate cross-sectional views of a substrate location during various processing stages used to form a transistor in accordance with a specific embodiment of the present disclosure; and -
FIG. 10 illustrates a portion of a device formed using the methods described in accordance with a specific embodiment of the present disclosure. - The use of the same reference symbols in different drawings indicates similar or identical items.
- In accordance with a specific embodiment of the present disclosure a sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. Improved epitaxial regions are realized as a result of hardening the sidewall spacer structure prior to epitaxial formation. The present disclosure will be better understood with respect to
FIGS. 1-8 . -
FIGS. 1 through 9 illustrate, in cross section, alocation 10 of a workpiece where a transistor of a semiconductor device is being manufactured according to specific embodiments of the present disclosure. At the manufacturing stage illustrated inFIG. 1 , deposition, photolithography, and etch processes have been conducted onlocation 10 such that aconductive gate structure 14 of the transistor being manufactured has been formed overlying a gatedielectric layer 12 that overlies asubstrate 5.Substrate 5 is typically a semiconductor substrate that is a mono-crystalline silicon substrate, a gallium arsenide substrate, a silicon-on-insulator substrate, a silicon-on-sapphire substrate, or the like. The gatedielectric layer 12 is typically an oxide layer physically separating theconductive gate structure 14 from theunderlying substrate 5 where a channel location of the transistor being formed resides. The gate dielectric will typically have a thickness in the range of 0.5 to 5 Angstroms. - The
conductive gate structure 14 will typically contain polysilicon, though it may contain other materials and multiple layers.Conductive gate structure 14 is illustrated inFIG. 1 to have a left sidewall and a right sidewall substantially parallel to each other, and perpendicular to a planer interface between thegate oxide layer 12 and thesubstrate 5. A length of theconductive gate structure 14 is the distance between its left and right sidewalls as illustrated inFIG. 1 and will typically be in the range of 10 to 500 nm. -
FIGS. 2-7 illustrate a specific embodiment of forming a sidewall spacer structure having two spacers adjacent toconductive gate structure 14.FIG. 2 illustrateslocation 10 subsequent to formingliner 16 overlyingconductive gate structures 14 and alayer 18 overlyinglayer 16 from which a sidewall offset spacer will be formed.Layer 16 is thinner thanlayer 18, and is referred to as a liner, or liner layer.Layer 16 is typically a dielectric material such as an oxide, a nitride (i.e., Silicon oxynitride), or polysilicon that protectsconductive gate structure 14 andsubstrate 5 from subsequent processing and need not be present depending upon subsequent processing steps. The material oflayer 18 is typically chosen to be selectively etchable relative to the material oflayer 16, and is used to create a sidewall spacer referred to as a sidewall offset spacer. In one embodiment, whenlayer 16 is an oxide,layer 18 will be a nitride, such as a silicon oxynitride; alternately, ifliner 16 is a nitride,layer 18 will be an oxide.Materials forming layers layer 18 will etchlayer 18 at a faster rate thanlayer 16. -
FIG. 3 illustrateslocation 10 subsequent to etching oflayer 18 thereby forming asidewall offset spacer 19 that is adjacent toconductive gate structure 14. An anisotropic etch is typically used to remove portions oflayer 18 not formingsidewall offset spacer 19. The anisotropic etch oflayer 18, as illustrated in the embodiment ofFIG. 3 , results insidewall offset spacer 19 having a “D” shape, so called because a width ofspacer 19 narrows in a non-linear manner at locations further from gate dielectric 12 to provide a profile similar to the top half of the capital letter “D”. The etch process that formssidewall offset spacer 19 illustrated inFIG. 3 selectivelyetches layer 18 relative tolayer 16, thereby leavinglayer 16. However, in an alternate embodiment the etch that formssidewall offset spacer 19 can also remove portions oflayer 16, though typically it is desirable to leavelayer 16 to protect active silicon regions from exposure to the etch that removeslayer 18. -
FIG. 4 illustrateslocation 10 subsequent to etching portions oflayer 16, thereby exposing a top portion ofconductive gate structure 14 and active silicon at source/drain locations of the transistor being formed, thus leavingsidewall liner 17, which is that portion oflayer 16 abuttingoffset spacer 19 to form a sidewall spacer structure.Conductive gate structure 14, gate dielectric 13,offset spacer 19, andliner 17 are all part of a gate structure at the transistor location. A dopant has been implanted, either prior or subsequent to removal oflayer 16, to form a dopedregion 20 that facilitates formation of a source/drain (S/D) extension region.Doped region 20 will have either an N-type or P-type conductivity depending upon whether an NMOS or PMOS transistor is being formed. -
FIG. 5 illustrateslocation 10 subsequent to disposing alayer 30 overlying the single gate structure ofFIG. 4 and alayer 32overlying layer 30.Layer 30 is typically a liner comprising a dielectric material, such as an oxide or a nitride that protects the previously formed gate structure from subsequent processing, and need not be present depending upon subsequent processing.Layer 32 is typically formed from a material that is selectively etchablerelative liner 30, such as an oxide or a nitride, and will be etched to create a second sidewall spacer. In accordance with a specific embodiment of the present disclosure,liner 30 is an oxide andlayer 32 is a material containing nitrogen. For example,layer 32 can be a silicon nitride, such as silicon oxynitride. -
FIG. 6 illustrateslocation 10 subsequent to etching oflayer 32 to form asidewall spacer 33 that contains Nitrogen.Sidewall spacer 19 is betweensidewall spacer 33 andconductive gate 14. An anisotropic etch is typically used to remove portions oflayer 32 not formingsidewall spacer 33, thereby forming asidewall spacer 33 with a “D” shape. A subsequent etch is performed to remove portions ofliner 30 to expose a top surface ofconductive gate structure 14 and a surface ofsubstrate 5 as illustrated inFIG. 7 . This subsequent etch leaves aportion 31 oflayer 30 as part of a sidewall spacer structure that includesspacer 33. -
FIG. 8 illustrates a sidewall spacer structure that includes bothsidewall spacers anneal 40 to harden thenitrogen containing spacer 33 from subsequent cleaning processes. In one embodiment, theanneal 40 is a rapid thermal anneal (RTA) that spikes at a maximum temperature without holding the temperature for a substantial amount of time. For example, the RTA typically will reach a temperature in the range of 400-1200° C. in less than approximately 40 seconds. In one embodiment, an anneal temperature of 850-1000° C. and a time of 1-10 seconds. Other temperature ranges for the RTA include 950-1050° C. Whileanneal 40 has been found to be advantageous, in other embodiments it can be omitted. - In one embodiment,
location 10 is exposed to a solution containing HF, afteranneal 40 followed by forming anepitaxial layer 42 at source/drain locations of the transistor being formed. After the epitaxial layer is formed dopants are implanted to form dopedregions 46 that facilitate formation of deep source/drain regions of the transistor location. The HF containing solution can include an aqueous solution of deionized water and hydrofluoric acid (HF or hydrogen fluoride in water) aqueous solution of approximately 30:1 (volumetric ratio) at 21 degrees Celsius, for a time period ranging from between 50-60 seconds. The weight percentage of HF recommended for the HF aqueous solution is 49% in a balance of deionized water (H2O). Bulk HF aqueous solution can be purchased from various chemical suppliers in the HF weight percent range of 10% to 49%. In semiconductor fabrication facilities, this aqueous HF aqueous solution is typically diluted in the range 10:1 to 200:1. A 10:1 HF is 1 part aqueous HF (at 49% weight percent) and 10 parts H2O. The thickness of the epitaxial layer depends upon device requirements, but typically has a thickness in the range of 30-300 nm, and more typically in the range of 30-100 nm. Dopants implanted to formregions 46 will include P-Type or N-Type dopants based upon whether a NMOS or PMOS transistor is being formed. - In an
alternate embodiment location 10 is implanted with dopants at source/drain locations of the transistor location prior to theanneal 40, and thelocation 10 is exposed to a solution containing HF subsequent to anneal 40 and prior to formation of an epitaxial layer.FIG. 9 illustrateslocation 10 after formation of theepitaxial layer 42 at source/drain active regions of transistor being formed (i.e., abutting the source/drain region). Note that in the particular embodiment anepitaxial layer 44 is also formed overlyingconductive gate structure 14. In a typical embodiment,epitaxial layers epitaxial layers 42 are defined by the outer surfaces of the sidewall gate structure to which they abut as well as by structures, i.e., isolation regions, not illustrated in the figures. -
FIG. 9 further illustratessemiconductor substrate 5 comprising a semiconductor-on-insulator (SOI) substrate, wherelayer 6 represents a semiconductor layer, such as silicon, overlying aninsulator region layer 7, such as an oxide, andlayer 7overlying layer 8, which is a support substrate, which can also be a semiconductor material, such as silicon. -
FIG. 10 illustrates location 11 after completion of device processing. Specifically,FIG. 11 includesdielectric layers layers Dielectric layer 73 is an upper most protective layer of the completed device, and is commonly referred to as a passivation layer. A first metal layer includesmetal trace 62; a second metal layer includes conductive trace 51. - The method described herein provides for a flexible implementation. Although the disclosure has been described using certain specific examples, it will be apparent to those skilled in the art that the invention is not limited to these few examples. Fore example, various types of deposition and etch techniques are currently available which could be suitable for use in employing the method as taught herein. Note also, that although an embodiment of the present invention has been shown and described in detail herein, along with certain variants thereof, many other varied embodiments that incorporate the teachings of the invention may be easily constructed by those skilled in the art.
- For example, it will be appreciated that any number of substrate preclean steps can occur before the formation of any epitaxial layer. For example, U.S. patent application Ser. No. 10/791,346, which is hereby incorporated in its entirety by reference, discloses several substrate preclean techniques appropriate for cleaning a substrate prior to forming an epitaxial layer.
- In one example, contaminates on the surface of a substrate are subjected to a cleaning process comprising applying a plasma to a surface of the active regions produce a reduction reaction with the contaminates in an upper portion of the surface of the active regions. In an embodiment, the plasma comprises H2. While the plasma is being applied to the upper portion of the exposed active regions, the resultant products or vapor byproducts of the reduction reaction are removed by the normal vacuum process within the chamber. Therefore, contaminates contained in the vapor byproducts and are vented away, leaving the upper portion of the surface of the active regions suitably clean for the ensuing epitaxial process. In one embodiment, the plasma process parameters comprise a gas flow of 450 sccm H2 and 300 sccm argon, at a chamber temperature of 400 degrees Celsius, with a high frequency (HF) power setting of 700 W, and a low frequency (LF) power setting of between approximately 50 to 100 W. Chamber pressure is 1 Torr, and the spacing between the surface of the active region and the faceplate of the tool (not shown) should be 300 mils. In other embodiments, plasma process parameters comprise a gas flow ranging from between 100-800 sccm H2 and from between 100 and 600 sccm argon. Chamber temperatures can range between 300 to 450 degrees Celsius, and HF power settings from between 400-900 W, with LF power settings varying from between 0-150 W. Chamber pressures can range from between 1 mT-5 Torr, with spacing between the surface of the active region and the faceplate of the tool varying from between 200 to 400 mils. Exposure times for the various embodiments utilizing plasma range from between approximately 10 seconds up to approximately 120 seconds.
- Various tool types are suitable for this cleaning, for example, CVD (Chemical Vapor Deposition) equipment, HDP (High Density Plasma) tools, etch chambers, or the like. Differences in chamber design, power settings, and species, e.g., H2 with or H2 without helium or nitrogen, will result in different thickness of the layer after anneal. Typically the layer after anneal will be between 20 and 50 Angstroms thick. This plasma cleaning process also results in passivation of Si—H bonds in the layer after anneal. No wet cleaning dip with hydrofluoric (HF) acid prior to SEG is necessary.
- In addition to no longer requiring an HF dip prior to SEG, the reduced temperature of this H2 plasma cleaning treatment results in a reduction of the SEG process thermal budget of more than 100 degrees Celsius. Typically pre-SEG cleaning processes are conducted at approximately 900 degrees Celsius or greater. In an embodiment of the present disclosure, the cleaning process occurs at less than approximately 800 degrees Celsius. In another embodiment, the cleaning process occurs at less than approximately 500 degrees Celsius or less. In addition, the cleaning processes of the present disclosure could be conducted at less than approximately 700 degrees Celsius or less, or even at less than approximately 600 degrees Celsius or less.
- In another embodiment, location including includes a gate structure and active regions is subjected to a cleaning process utilizing a low-power dry etch to selectively remove an upper atomic layer of material from the active regions. The thickness of the upper atomic layer of material to be removed ranges from between 20 to about 50 Angstroms. In one embodiment, the dry etch process is an anisotropic dry etch utilizing a carbon-free gas as an etchant gas. In another embodiment, the anisotropic dry etch utilizes an oxygen- and carbon-free gas as an etchant gas. The etchant gas can comprise HBr, NF3, SF6, gaseous fluorine-interhalogenics such as ClF3, or any gas containing fluorine, suitable to disassociate F-radicals, which does not contain oxygen and carbon. Prior to undergoing the anisotropic dry etch process, location 200 is subjected to a standard wet etch chemistry process utilizing a dilute HF solution (100:1) at room temperature, e.g., 20 to 26 degrees Celsius, for a time period ranging from 50 to 200 seconds. Following the HF clean, a low-power dry etch utilizing a temperature of approximately 400 degrees Celsius, RF power of approximately 375 W, pressure of approximately 150 mTorr, and a gas flow rate ranging from 50 to 100 sccm, is conducted. In other embodiments, the low-power dry etch utilizes a temperature ranging from between 300-500 degrees Celsius, with RF power ranging from between 200-700 W, a pressure ranging between 0-1 Torr, and a gas flow rate ranging from between 10-300 sccm, for a time ranging between 10 to 60 seconds.
- This low-power dry etch removes carbon and oxygen contamination, and provides a very clean surface for SEG. The low temperature HF clean followed by the low-power dry etch does not require a high temperature bake. This results in a reduction of thermal budget for SEG of more than 100 degrees Celsius.
- In another embodiment, a cleaning process is used that forms an oxidation layer of between 20 to 50 Angstroms on an upper surface of the active regions using a plasma to produce the oxidation layer on doped active regions. In an embodiment, the plasma is an O2 plasma. In another embodiment, the plasma is an O3 plasma.
- An O2 plasma production utilizes O2 gas at a flow rate of 400 sccm, a pressure of 5 Torr, an HF of 300 W, an LF of 100 W, and a temperature of 400 degrees Celsius, with the time ranging from between about 10 to about 120 seconds. The spacing between the surface of the active regions and the faceplate of the vapor deposition apparatus (not shown) should be 400 mils. In other embodiments, the plasma production utilizes O2 gas at a flow rate of between 100 and 1000 sccm, a pressure ranging from between 2-10 Torr, an HF ranging between 200-500 W, an LF ranging between 50-200 W, a temperature ranging between 300-450 degrees Celsius, for a time ranging from between approximately 10 to approximately 120 seconds. In an embodiment, the spacing between the surface of the active regions and the faceplate of the vapor deposition apparatus ranges from between 200 and 600 mils. The tool type used to generate the plasma could be CVD equipment, HDP tools, or etch chambers. In an embodiment where the plasma is O3, plasma production utilizes O3 gas at a flow rate of 300 sccm, a pressure of 5 Torr, an HF of 300 W, an LF of 100 W, and a temperature of 400 degrees Celsius for a time period ranging from between 10 to 120 seconds. The spacing between the surface of the active regions and the face plate of the vapor deposition apparatus (not shown) should be 400 mils. In other embodiments, plasma production utilizes O3 gas at a flow rate of between 50 and 600 sccm, a pressure ranging from between 2-10 Torr, an HF ranging between 200-500 W, an LF ranging between 50-200 W, and a temperature ranging from between 300-450 degrees Celsius for a time period ranging from between about 10 to about 120 seconds. In an embodiment, the spacing between the surface of the active regions and the faceplate of the vapor deposition apparatus ranges from between 200 and 600 mils. As was the case with the O2 plasma, the tool type used to generate the plasma could be HDP tools, CVD equipment, or etch chambers.
- Forming the oxidation layer facilitates trapping or fixing contamination in the oxide layer overlying the upper layer of the doped active regions for subsequent removal using a wet chemistry process. The wet etch chemistry process utilizes a dilute HF acid solution of 100:1 at room temperature, e.g. 20 to 26 degrees Celsius, for a time ranging from 50 to 200 seconds. Differences in chamber design, power settings and species employed, e.g., O2 or O3, results in differing thickness of the oxidation layer, hence the wide range in times for the HF dip. The use of an O2 or O3 plasma to create a contamination-trapping oxidation layer for removal by a room temperature HF dip results in a reduction of the thermal input for location 300.
- Another possible pre-clean, different from the one described above, prior to formation of an SEG that facilitates a reduced temperature H2 bake is performed following formation of any desired spacers, which can comprise one or more nitride or oxide layers and prior to SEG formation. This pre-clean and comprises a first pre-rinse with deionized water, followed by an oxide etch utilizing an aqueous solution of deionized water and hydrofluoric acid (HF or hydrogen fluoride in water) aqueous solution of approximately 30:1 (volumetric ratio) at 21 degrees Celsius, for a time period ranging from between 50-60 seconds. The weight percentage of HF recommended for the HF aqueous solution is 49% in a balance of deionized water (H2O). Bulk HF aqueous solution can be purchased from various chemical suppliers in the HF weight percent range of 10% to 49%. In semiconductor fabrication facilities, this aqueous HF aqueous solution is typically diluted in the range 10:1 to 200:1. A 10:1 HF is 1 part aqueous HF (at 49% weight percent) and 10 parts H2O. It will be appreciated that the etch rate of the HF aqueous solution is substantially linear with respect to both the concentration of the HF aqueous solution and the etch time. Therefore, various combinations of HF concentrations and etch times can be used to accomplish the oxide etch. Additionally, the temperature may vary.
- After the HF etch, an overflow rinse utilizing deionized water is performed for a period ranging from approximately 120 to 600 seconds with a typical rinse being about 400 seconds. The cleaning process of portion 100 results in etching away of the surface contamination/debris located on
substrate 10 resulting from offset spacer formation and/or dopant implantation. The upper semiconductor surface, i.e. silicon surface, ofsubstrate 10 is also slightly etched, for example, from one to several mono layers of silicon, during the HF etch. - It should be noted that the amount of material removed during the HF etch is dependent upon the type of material being removed. For example, when native oxide is present, the HF etch will remove approximately 20 to 30 Angstroms of oxide. If a deposited oxide layer is present in addition to a native oxide, an over-etch of approximately 30% is generally desirable. For example, if removal of 100 Angstroms of a chemical vapor deposition (CVD) oxide is desired, the HF etch could be employed to remove approximately 120 to 130 Angstroms oxide removal. This latter example would be applicable in applications where a liner oxide of approximately 100 Angstroms thickness is employed between a conductive gate 25 and a nitride spacer.
- The next steps in the cleaning process comprise a second pre-rinse with deionized water of approximately 30 seconds duration precedes the performance of a Standard Clean-1 (SC-1), a quick dry rinse (QDR), and a Standard Clean-2 (SC-2). The SC-1 and SC-2 components are followed by a second QDR, and an HF: H2O etch, a third rinse, and an isopropyl alcohol (IPA) dry. The amount of material removed by the SC-1 and SC-2 components are implemented such that they etch from approximately one monolayer of silicon to approximately 10 to 100 Angstroms of silicon.
- In an embodiment, the SC-1 utilizes an aqueous solution of ammonium hydroxide:hydrogen peroxide:deionized water at a ratio of approximately 1:1-4:6-40, at a temperature of approximately 60 degrees Celsius for approximately 72 minutes, to etch approximately 100 Angstroms of silicon. Synonyms for ammonium hydroxide (NH4OH) include ammonia solution (typically contains between 12% and 44% ammonia before dilution), dilute ammonia, or concentrated ammonia. A first quick dry rinse is conducted for approximately 3 minutes. In an embodiment, the SC-2 utilizes a solution of hydrochloric acid:hydrogen peroxide:deionized water at an initial ratio of approximately 1:1:50 at a temperature of approximately 60 degrees for about 5 minutes. A second quick dry rinse is then conducted. Synonyms for hydrochloric acid (HCl) are hydrogen chloride, anhydrous hydrogen chloride, aqueous hydrogen chloride, chlorohydric acid, spirit of salts, and muriatic acid.
- In a particular embodiment, the SC-1 utilizes a solution of ammonium hydroxide:hydrogen peroxide:deionized water at a ratio of approximately 1:4:20 at a temperature ranging of approximately 60 degrees Celsius for approximately 72 minutes. The SC-1 is the step in the clean sequence that etches the silicon. This occurs because the H2O2 (the oxidizer) becomes depleted in the solution with increasing time and increasing temperature. The methods of the present disclosure allow the initial concentration of hydrogen peroxide to be depleted to facilitate etching of the upper-most semiconductor portion. Depletion of the H2O2 is greatly enhanced when the solution temperature rises above 80 degrees Celsius, which can lead to an etch that is difficult to control if not carefully monitored. The temperature range of the SC-1 is expected to be approximately 55 to 85 degrees Celsius, with the etch occurring in a shorter period of time at higher temperatures than at lower temperatures. It is expected that the SC-1 etching will be better controlled at temperatures in the range of 55-80 degrees Celsius and better still at temperatures in the range of 55-75 degrees Celsius. Generally, it is expected that the substrate will be exposed to the SC-1 etch process for longer that 60 minutes. When the oxidizer stops protecting the silicon surface, the ammonium hydroxide (NH4OH) starts to etch the silicon. Thus, a small amount of silicon can be etched in a controlled manner. The SC-1 can be performed in a re-usable bath where the solution is re-circulated and heated to maintain the desired temperature.
- The mechanism of silicon and SiO2 etching by a NH4OH/H2O2 solution occurs when the solution is allowed to be depleted of H2O2. An alkaline solution, such as NH4OH4 in our example, will attack silicon by water molecules, according to the reaction:
-
Si+2H2O+2OH−→Si(OH)2(O−)2+2H2↑ - A passivation layer formed by the H2O2 prevents this attack by the NH4OH. H2O2 decomposes in the course to form O2 and H2O.
-
H2O2−→H2O+½O2 - When the concentration of H2O2 is below 3×10−3M, then silicon will begin to etch, because of the absence of the inhibition layer.
- As indicated in the above equations, heat is given off as the H2O2 is depleted. If a bath is used that is not recharged with fresh solution all H2O2 will be depleted, thereby no longer releasing heat. Therefore, the temperature can be monitored on the low end to indicate when the solution should be refreshed, while the temperature on the high end is monitored to prevent unusually rapid decomposition of the H2O2, which can lead to a process that is difficult to control.
- The first quick dry rinse is conducted for approximately 3 minutes. The subsequent SC-2 utilizes a solution of hydrochloric acid:hydrogen peroxide:deionized water at a ratio of approximately 1:1:50 at a temperature of approximately 60 degrees for about 5 minutes. A quick dry rinse with deionized water, followed by an IPA dry process, is performed following the SC-2.
- The IPA dry process uses a heated IPA vapor at approximately 82 degrees Celsius. The IPA vapor is generated in a separate chamber with 100% N2 bubbled through 100% IPA (heated to 82 degrees Celsius). The IPA condenses on the wafer, and the solution drips off the bottom of the wafer. The IPA vapor concentration is slowly diluted to 100% N2 before the wafers are removed from the rinsing/drying tank.
- Subsequent to the SC-1 and SC-2 processes, the substrate will be further recessed (etched) as a result of the cleaning process. Next, an HF: H2O etch can be conducted at an aqueous solution ratio of 200:1 for about 65 seconds, which typically results in approximately 30 Angstroms of oxide removal. The HF:
H2O etch 8 is followed by a rinse with deionized water for approximately a 10 minute duration. The deionized water rinse is followed by an IPA dry as described in the preceding paragraph. At this time, the source/drain regions of the substrate are ready for ion implantation or selective epitaxial growth. - In a particular embodiment, the SC-1 process comprises a pre-rinse with deionized water of approximately 30 seconds duration. The pre-rinse is followed by a SC-1 solution at a ratio of approximately 1:1-4:6-40, which includes the subranges of 0.25:1:5, 0.5:1:5, 1:1:5, 1:1:6, 1:4:20, and 1:1:40, ammonium hydroxide: hydrogen peroxide: deionized water at a temperature of approximately 60 degrees Celsius for approximately 5 minutes. A quick dump rinse (QDR) is then performed for approximately 3 minutes.
- Following the SC-1 cleaning process, an SC-2 cleaning process is performed. In an embodiment, the SC-2 cleaning process includes utilizing an aqueous solution of hydrochloric acid:hydrogen peroxide:deionized water at a ratio of approximately 1:1:50 at a temperature of approximately 60 degrees Celsius for approximately 5 minutes. A QDR is then performed, and portion 200 is ready for the third cleaning. The weight percent composition of the hydrochloric acid: hydrogen peroxide: deionized water is 29% (weight percent) hydrochloric acid and 30% (weight percent) hydrogen peroxide in a balance of deionized water.
- After the SC-1 and SC-2, a third cleaning process comprising an approximate 30 second pre-rinse, an oxide etch, an overflow rinse and an IP dry is performed. The oxide etch is accomplished utilizing a solution of deionized water and hydrofluoric acid at a ratio of approximately 200:1 for a time period ranging from between 450-650 seconds. Following the HF etch, an overflow rinse is performed for approximately 10 minutes. A final isopropyl alcohol (IPA) dry is then performed. Approximately 120-140 Angstroms of the surface of
substrate 20 is removed in this process. Portion 200 is ready to undergo selective epitaxial growth. - The above-described cleaning process has been found to facilitate formation of an epitaxial layer on a semiconductor surface, specifically silicon. Because various etch processes can etch N- and P-type regions at different rates, it can be useful to amorphize an upper-most surface of the source/drain regions prior to the above-described clean to reduce any preferential etch differences between substrate regions of differing dopant types.
- For example, the above-described clean process can etch the N-type silicon preferentially, as compared to the P-type silicon, resulting in a quality difference of the SEG between the N and P regions after SEG processing. Etch rate differences between N- and P-type regions can allow for contaminates to remain in the lesser-etched region. For example, an etch process that does not etch P-type regions at the same rate as N-type regions can result in P-regions maintaining embedded carbon that is incorporated from previous process steps. Without appropriate etching of silicon in the P-type regions during the clean, the carbon will remain, and the SEG will grow inconsistently. A high bake temperature of 900° C. can be used to overcome this growth issue on P areas, however, as stated previously, high bake temperatures can be detrimental to the device in that it causes diffusion and deactivation of the dopants. Amorphizing the source/drain regions can reduce etch differences associated with the above-described cleaning process as well as other processes that are used to etch doped substrate regions, thereby improving the quality of both the N and P regions.
- It has been observed that the selective etching may be P-type over N-type, or N-type over P-type depending on the solution temperature, flow rate of the aqueous ammonia, concentration of the aqueous ammonia, agitation, or illumination of light. By amorphizing the silicon in this manner to a pre-defined depth, it has been observed that unbiased etching to the depth of the amorphized silicon can be achieved.
- In one embodiment, N- and P-type extensions formed in the source/drain regions are amorphized by being implanted with the Xe, at a dose of 2E14 and energy of 10 keV, to create an amorphous depth of 100 A.
- In accordance with another embodiment, a spacer structure having an undercut can be used to reduce or inhibit facet formation during a selective epitaxial growth process. Such a process can allow for greater lateral uniformity of junction or silicide features during implantation or silicidation processes, and can be accomplished by using a spacer formed with a bi-layer of materials, e.g., a thin liner, such as portion 29 of
FIG. 1 , of one material underlying another layer of material from which the ‘main’ spacer is formed. The thin liner and other material layer are selected such that the two materials are selectively etchable with respect to the other, for example, a thin oxide liner and a nitride layer. By etching the underlying portion of the spacer, an undercut can be formed that reduces facets during epitaxial formation. - In addition, a number of etch chemistries can be used to form nitride spacers. These etch chemistries are known in the art, and include the use of gas mixtures such as NF3/HBr, CF4/HBr, SF6/HBr, or any combination of these gases. In an embodiment, helium or argon can be included in the gas mixture to dilute the etch chemistry.
- To improve the selectivity of the nitride etch over oxide, oxygen (O2) can be added to the gas mixture flowing into the plasma reactor during etch. In an embodiment, the addition of oxygen during the etching process is an amount between 2 percent and 15 percent by volume. The plasma reactor may be of any type which provides ion bombardment, e.g., capacitively-coupled parallel-plate reactor, or inductively coupled plasma with wafer (RF) bias. The wall temperature of the plasma reactor during etching is between 20 degrees C. and 60 degrees C., while the wafer platen (chuck) temperature is between 50 degrees C. and 80 degrees C. The gas mixture has a total gas flow during etching of between 75 sccm and 150 sccm for 200 mm wafers. The total gas flow would require an increase for 300 mm wafers, in order to compensate for the increase in the plasma reactor chamber volume. The chamber pressure is in the range of 50-150 mtorr for 200 mm wafers using capacitively coupled plasma reactor systems. It should be noted that the chamber pressure necessarily depends upon the size of the chamber, as well as the manufacturer of the plasma reactor equipment. The examples presented herein reference Applied Material's MERIE (magnetically enhanced reactive ion etch) systems.
- The amount of oxygen added is dependant upon the particular etch chemistry chosen. An exemplary etch chemistry could be CF4, HBr, and He—O2, with gas flow ratios, by volume, of CF4:HBr:He—O2 of approximately 10:(2-6):(1-6). The ratio of He—O2 used is 70/30 percent by volume, however, other appropriate ratios would work as well. In an embodiment, addition of oxygen during the etching process is an amount between 2% and 15% by volume. The addition of oxygen does not greatly alter the
resultant spacer 16 profile, although small alterations are possible. This could, however, be compensated for by changing (i.e., increasing or decreasing) the thickness of nitride layer. Hence the addition of oxygen during the etching process does not require adjustments of other etch process parameters. The addition of oxygen enhances the etch selectivity of thenitride layer 14 to the liner oxide layer 15. In an embodiment, the etch selectivity for silicon nitride is between 1:2 and 1:3. - Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. Accordingly, the present invention is not intended to be limited to the specific form set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the invention.
Claims (14)
1. A device comprising:
a conductive gate of a transistor overlying a semiconductor substrate;
a sidewall spacer structure abutting the conductive gate, the sidewall spacer structure comprising a first sidewall spacer and a second sidewall spacer between the first sidewall spacer and the conductive gate;
a source/drain extension region underlying the second sidewall spacer;
a deep source/drain region underlying the first sidewall spacer; and
an epitaxial layer abutting the outer surface of the sidewall spacer structure.
2. The device of claim 1 wherein the first sidewall spacer comprises a first offset spacer and a first liner layer, the first liner layer underlying and abutting the first offset spacer, and wherein the second sidewall spacer comprises a second offset spacer between the first liner layer and the conductive gate.
3. The device of claim 2 wherein the first liner layer contains an oxide selectively etchable from the first offset layer.
4. The device of claim 3 wherein the first offset spacer contains nitrogen.
5. The device of claim 3 wherein the first liner layer of the first sidewall spacer contains a silicon oxynitride.
6. The device of claim 5 further comprising an epitaxial layer overlying the conductive gate structure.
7. The device of claim 5 further comprises a silicide at the epitaxial layer.
8. The device of claim 2 , wherein the second sidewall spacer further comprises a second liner layer between the second offset spacer and the conductive gate.
9. The device of claim 1 , wherein the material forming an outer surface of the sidewall spacer contains nitrogen.
10. The device of claim 9 wherein the material forming the outer surface contains a silicon oxynitride.
11. The device of claim 10 further comprising an epitaxial layer overlying the conductive gate structure.
12. The device of claim 10 further comprises a silicide at the epitaxial layer.
13. The device of claim 1 further comprises a silicide at the epitaxial layer.
14. The device of claim 1 further comprising an epitaxial layer overlying the conductive gate structure.
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