US20090057815A1 - Forming channel stop for deep trench isolation prior to deep trench etch - Google Patents

Forming channel stop for deep trench isolation prior to deep trench etch Download PDF

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US20090057815A1
US20090057815A1 US12/263,646 US26364608A US2009057815A1 US 20090057815 A1 US20090057815 A1 US 20090057815A1 US 26364608 A US26364608 A US 26364608A US 2009057815 A1 US2009057815 A1 US 2009057815A1
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deep trench
channel stop
substrate
impurity region
semiconductor structure
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US12/263,646
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Louis D. Lanzerotti
Stephen A. St. Onge
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • FIGS. 1-3 and 5 - 8 show a method of manufacturing a semiconductor structure according to the invention.
  • each deep trench 140 is substantially aligned to an impurity region 122
  • each deep trench 140 is preferably formed such that it has a larger width W 1 than impurity region 122 W 2 .
  • a portion of impurity region 122 i.e., channel stop 172
  • Dielectric 160 can be any now known or later developed material used for deep trench isolations such as boro-phospho-silicate glass (BPSG).
  • BPSG boro-phospho-silicate glass
  • Subsequent processing may include customary polishing and back-end-of-line processing.

Abstract

Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of co-pending U.S. patent application Ser. No. 10/905,627, filed on Jan. 13, 2005.
    • BACKGROUND OF THE INVENTION
  • 1. Technical Field
  • The present invention relates generally to semiconductor device fabrication, and more particularly, to methods of manufacturing a semiconductor structure including a deep trench isolation in which the channel stop is formed prior to deep trench etch.
  • 2. Related Art
  • In semiconductor devices, a number of transistors are generated in very close proximity to one another and isolated from one another by insulating deep trenches. For example, NPN transistor devices are typically formed with a collector that runs laterally through a sub-collector and then up to a contact level. The collectors terminate in an n-type substrate about 2 um deep. In order to isolate the different NPN devices on the wafer, a deep trench isolation in the form of an annulus is formed about the device down into the substrate to isolate the sub-collector of each NPN device from adjacent sub-collectors of other devices.
  • In order for a deep trench to fully isolate a device, it must include a channel stop at a lower end thereof within the substrate. In particular, if a deep trench is formed in, for example, an N+ subcollector, it extends into a P-substrate thereunder. In this situation, a deep trench isolation may invert, i.e., attract electrons, such that current can leak around the bottom of the deep trench isolation, resulting in current flowing between adjacent sub-collectors. To prevent inversion, deep trench isolations are typically formed with a channel stop that includes a dopant type that matches the substrate to prevent the deep trench isolation from inverting. In the above example, the dopant type would be p-type (e.g., boron) to match the substrate.
  • One issue relative to formation of deep trench isolations is when to form them during the fabrication process. Conventionally, deep trench isolations are formed in a substrate and then covered during transistor device fabrication. For example, in conventional processing, the following steps are completed prior to device fabrication: etching of a deep trench, forming a channel stop in the bottom of the deep trench, and finally filling of the deep trench with a dielectric. Formation of a channel stop is completed after the deep trench is etched, for example, by using a p-type (e.g., boron) implant into the bottom of the deep trench. This process is advantageous because as processing proceeds through front-end-of-line (FEOL) fabrication, i.e., device formation and metallization, the implant is exposed to a number of thermal cycles that activate the channel stop. The annealing allows the sharing of collector level between the devices (e.g., SiGE NPNs) because the collectors of adjacent devices are isolated from each other by the deep trench isolation. Without the channel stop, the bottom of the deep trench isolation is inverted and the collectors are electrically tied together.
  • In more advanced processing, however, it has been found advantageous from a cost perspective to generate deep trench isolations at the end of FEOL fabrication, i.e., after device formation and metallization. This latter situation, however, does not provide the thermal cycles required to activate the dopant of the channel stop for the deep trench isolations. Accordingly, a conventional channel stop cannot be used with the low cost deep trench isolation processing. As a result, shared deep trench isolations cannot be used because of inversion shorts. If a conventional channel stop is to be used, it would require device-to-device spacing that is vastly enlarged because a P-well must be inserted between the deep trench isolations of each device to create the isolation. This situation is untenable. In addition, for improved transistor packing density, it remains advantageous to have one large subcollector shape with multiple devices inside a big shape. This structure is only effective if shared deep trench isolations can be used.
  • In view of the foregoing, there is a need in the art for a way to form a deep trench isolation at the end of FEOL processing.
    • SUMMARY OF THE INVENTION
  • The invention includes methods of manufacturing a semiconductor structure including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.
  • A first aspect of the invention is directed to a method of manufacturing a semiconductor structure, the method comprising the steps of: providing a substrate; forming a masking layer having an opening on the substrate; implanting an impurity through the opening to form an impurity region in the substrate; and after the implanting step, forming a deep trench in the substrate substantially aligned to the impurity region, wherein a portion of the impurity region is located adjacent to a bottom surface of the deep trench.
  • A second aspect of the invention relates to a method of forming a deep trench in a semiconductor structure, the method comprising the steps of: forming an embedded impurity region in a substrate, the impurity region including a channel stop dopant appropriate for the substrate; forming a transistor device on the substrate; and after the transistor device forming step, forming a deep trench in the substrate substantially aligned to the impurity region, wherein a portion of the impurity region is located adjacent to a bottom surface of the deep trench so as to form a channel stop for the deep trench.
  • A third aspect of the invention includes a semiconductor structure, comprising: a substrate; and a deep trench isolation including: a dielectric positioned within a deep trench, and a channel stop, wherein at least a portion of an outer edge of the channel stop is spaced inwardly from an outer edge of the deep trench.
  • The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
  • FIGS. 1-3 and 5-8 show a method of manufacturing a semiconductor structure according to the invention.
  • FIGS. 4 and 9 show dopant concentration versus depth graphs for the devices of FIG. 3 and FIG. 8, respectively.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • With reference to the accompanying drawings, FIG. 1 shows a first step of the method of manufacturing a semiconductor structure according to the invention. As shown in FIG. 1, the first step includes providing a substrate 100, which may include one or more shallow trench isolations (STI) 102 formed therein. Substrate 100 may be doped with any conventional dopant to form a p-type or n-type substrate, depending on the devices to be formed.
  • Turning to FIG. 2, a next step includes forming a masking layer 110 having an opening 112 on substrate 100. Masking layer 110 may be any now known or later developed masking material such as a photoresist. Opening 112 is opened in any conventional fashion, e.g., photolithography, patterning and etching.
  • Next, as shown in FIG. 3, an impurity is implanted 120 through opening 112 to form an (embedded) impurity region 122 in substrate 100. The impurity includes a dopant that is commensurate with a substrate dopant to form a channel stop for a deep trench isolation to be formed subsequently. That is, the impurity includes a dopant that will prevent attraction of electrons to a deep trench isolation formed adjacent thereto, and therefore, prevent inversion of the deep trench isolation, as will be described later. FIG. 4 shows a dopant concentration versus depth graph, i.e., a dopant profile, of impurity region 122 as taken along line 4-4 in FIG. 3. As shown in FIG. 4, impurity region 122 has a Gaussian profile into the depth of substrate 100. The implanting step uses an energy sufficient to have impurity region 122 extend beyond a bottom of the deep trench (when formed). The depth of the deep trench depends on the depth of the subcollector. In any event, the minimal energy used should be approximately 100 keV. Using this special masking and implanting steps, the dopant profile for impurity region 122 can be optimized for later formation into a channel stop, as will be described below.
  • In an alternative embodiment, the steps of forming masking layer 110 and opening 112 and implanting 120, may be provided as part of a step of implanting a well region (not shown) using the masking layer. For example, these steps may be carried out with the masking/opening and implanting of a P-well. In this case, the cost of an additional masking layer 110 would be eliminated. However, the ability to tailor the dopant profile would be lost.
  • As shown in FIG. 5, a next step includes conducting typical front-end-of-line (FEOL) processing to form a transistor device 130. FEOL processing may include any now known or later developed processing up to and including metallization of transistor devices 130. For example, FEOL processing may include implanting wells into substrate 100, forming field effect transistors (FETs) 130, building a bipolar transistor, passive elements, and metalizing (forming silicide, etc.) FETs 130. In any event, FEOL processing includes a number of thermal cycles that act to anneal impurity region 122. The annealing may be provided as part of the normal processing, or an additional annealing step may be implemented especially for impurity region 122.
  • Referring to FIGS. 6-8, after the implanting step, a deep trench isolation 140 (FIG. 7) is formed next in substrate 100. This step includes, as shown in FIG. 6, forming a second masking layer 150 having an opening 152 on substrate 100, etching, as shown in FIG. 7, to form deep trench 140, and filling deep trench 140 with a dielectric 160, as shown in FIG. 8. The etching can be any now known or later developed etching process. As shown in FIG. 7, the etching removes a part 162 of impurity region 122, leaving a channel stop 172 for deep trench isolation 170. In addition, while each deep trench 140 is substantially aligned to an impurity region 122, each deep trench 140 is preferably formed such that it has a larger width W1 than impurity region 122 W2. Accordingly, a portion of impurity region 122 (i.e., channel stop 172) is located adjacent to a bottom surface of deep trench 140, but does not extend to the full width of deep trench 140, as is conventional. That is, at least a portion of each edge of channel stop 172 is spaced inwardly from an edge of deep trench 140. Dielectric 160 can be any now known or later developed material used for deep trench isolations such as boro-phospho-silicate glass (BPSG). Subsequent processing (not shown) may include customary polishing and back-end-of-line processing.
  • FIG. 9 illustrates a dopant concentration versus depth graph, i.e., a dopant profile, of deep trench isolation 170, impurity region 122 (channel stop) as taken along line 9-9 in FIG. 8. As shown in FIG. 9, channel stop 172 may have a half-Gaussian profile into the depth of substrate 100 (FIG. 8), depending on the depth of deep trench isolation 170.
  • Returning to FIG. 8, the invention also includes a semiconductor structure 180 including substrate 100, and deep trench isolation 170 including dielectric 160 positioned within deep trench 140, and channel stop 172. As described above, at least a portion of an edge of channel stop 172 is spaced inwardly from an edge of deep trench 140, as shown best in FIG. 7 by widths W1 and W2. As shown in FIG. 9, a dopant concentration of channel stop 172 (FIG. 8) decreases with increasing depth into substrate 100 (FIG. 8).
  • While this invention has been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (4)

1. A semiconductor structure, comprising:
a substrate; and
a deep trench isolation including:
a dielectric positioned within a deep trench, and
a channel stop,
wherein at least a portion of an outer edge of the channel stop is spaced inwardly from an outer edge of the deep trench.
2. Semiconductor structure of claim 1, wherein a dopant concentration of the channel stop decreases with increasing depth into the substrate.
3. The semiconductor structure of claim 1, wherein the channel stop includes a dopant.
4. The semiconductor structure of claim 1, further comprising a transistor device.
US12/263,646 2005-01-13 2008-11-03 Forming channel stop for deep trench isolation prior to deep trench etch Abandoned US20090057815A1 (en)

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US7491614B2 (en) * 2005-01-13 2009-02-17 International Business Machines Corporation Methods for forming channel stop for deep trench isolation prior to deep trench etch
US7550787B2 (en) * 2005-05-31 2009-06-23 International Business Machines Corporation Varied impurity profile region formation for varying breakdown voltage of devices
JP2008192985A (en) 2007-02-07 2008-08-21 Seiko Instruments Inc Semiconductor device and method of manufacturing same
US8236648B2 (en) * 2007-07-27 2012-08-07 Seiko Instruments Inc. Trench MOS transistor and method of manufacturing the same
TWI463644B (en) * 2008-08-12 2014-12-01 United Microelectronics Corp Cmos image sensor, method of making the same, and method of suppressing dark leakage and crosstalk for cmos image sensor
CN115881750B (en) * 2023-02-02 2023-05-23 合肥晶合集成电路股份有限公司 Image sensor and method for manufacturing the same

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