US20090076789A1

US20090076789A1 - Method for pre-verifying software/hardware design of communication system

Info

Publication number: US20090076789A1
Application number: US12/274,615
Authority: US
Inventors: Juinn-Horng Deng; Jeng-Kuang Hwang; Po-Tien Lee; Fu-Chin Shau
Original assignee: National Chung Shan Institute of Science and Technology NCSIST
Current assignee: National Chung Shan Institute of Science and Technology NCSIST
Priority date: 2005-11-09
Filing date: 2008-11-20
Publication date: 2009-03-19
Also published as: US20070104287A1; US7539265B2

Abstract

A pre-verifying method for software/hardware design of a communication system includes simulating a process of sending a data frame from a transmitter to a receiver with a transceiver algorithm meeting a preset specification for obtaining simulation parameters. A transmitter hardware platform sends the data frame via an antenna. A receiver hardware platform receives an echo signal of the data frame and compares each parameter of the echo signal with the simulation parameters. The comparison result of various parameters of the echo signal and the simulation parameters is verified to be in a desired range or not. When the comparison result is not in the desired range, the transceiver algorithm is adjusted. When the comparison result is in the desired range, the transceiver algorithm is converted to a hardware program language format to be written in a programmable module to perform the action of the transmitter and the receiver.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of an application Ser. No. 11/271,414, filed on Nov. 9, 2005, now pending. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of Invention
The present invention relates to a wireless communication equipment and pre-verifying method for software/hardware designing thereof. More particularly, the present invention relates to a MIMO-CDMA wireless communication equipment, and pre-verifying method for software/hardware design of communication system having verification of comparing the system simulation with the hardware realization.
2. Description of Related Art
With the rapid development of the wireless communication techniques, the wireless broadband and high speed data transmission has been a primary requirement of the next generation mobile communication system. For these objects, the space resource will be employed (i.e. multiple antennas are used at the transmitting end and the receiving end to improve the system performance). Therefore, it is very important to discuss the related multi-path, multi-input, multi-output channel and develop the Space-time Processing algorithm. On the other hand, multi-wave orthogonal frequency division multiplexing (OFDM) modulation transmission is an extremely preferable technique for resisting the frequency selective fading resulted form outdoor multiple path effect. But since the OFDM technique means composing all subcarrier data transmissions, the peak-to-average power ratio (PAPR) and the dynamic range are too large, causing the problems of quantization distortion of analog/digital converter, digital/analog converter and radio frequency power amplifier, which influence the performance.

SUMMARY OF THE INVENTION

In view of the above, the present invention is directed to a MIMO-CDMA wireless communication equipment, which has a higher range of dynamic flexible adjustment based on the change of the environment, and provides higher power efficiency and low transmitter complexity.
The present invention is further directed to a pre-verifying method for software/hardware design of communication system, to verify the correctness of the algorithm developed for communication system rapidly.
The present invention provides a MIMO-CDMA wireless communication equipment including a transmitter and a receiver. The transmitter includes an encoder for receiving and encoding a plurality of transmission data, and then sending them to a QPSK unit. The QPSK unit conducts QPSK modulating to an output of the encoder and sends it to a space-time block coding (STBC) unit to conduct space-time coding. Furthermore, a plurality of data frame generating modules generate a data frame respectively based on the output of the STBC unit, a plurality of preamble codes generated by a preamble code spreading unit, a pilot code and a cyclic prefix (CP). The data frames are sent to the receiver via a transmitting antenna respectively.
From another point of view, the present invention further provides a MIMO-CDMA wireless communication equipment including a transmitter and a receiver as the same. The transmitter also includes an encoder for receiving and encoding a plurality of transmission data, and then sending the data to a QPSK unit, except that the QPSK unit conducts QPSK modulating to an output of the encoder and sends it to a space multiplexer to conduct space coding. Then, a plurality of data frame generating modules generate a data frame respectively based on the output of the space multiplexer, a plurality of preamble codes generated by a preamble code spreading unit, a pilot code and a cyclic prefix. The data frames are also sent to the receiver via a transmitting antenna respectively.
In the embodiment of the present invention, the receiver includes a plurality of receiving antennas for receiving the data frames from each corresponding transmitting antenna respectively, and sending them correspondingly to a plurality of radio frequency units respectively, to conduct frequency reducing to the received data frames. Furthermore, a plurality of estimation modules are coupled correspondingly to the radio frequency units respectively, for estimating a time parameter, a frequency parameter and a channel parameter of the frequency reduced data frame, and removing the cyclic prefix. And a decision demodulating module receives the output of each estimation module to conduct data spreading to the data frame passed through the estimation module, so as to conduct space-time block decoding or interference eliminating, and send the data frame to a decoder to revert the original transmission data.
From another point of view, the present invention provides a pre-verifying method for software/hardware design of communication system adapted to verify the communication system having a transmitter and a receiver. The present invention includes simulating the process of sending a data frame from the transmitter to the receiver with a transceiver algorithm meeting a preset specification, so as to obtain plurality of simulation parameters; and then, planning the transmitter hardware platform to send the data frame via an antenna. The transmitter hardware platform has programs meeting the above preset specification. Furthermore, the receiver hardware platform is planned to receive the echo signal of the data frame and compare each parameter of this echo signal to the above simulation parameters. At this time, verifying the result of comparing various parameters of the above echo signal and the simulation parameters is within a desired range or not. When the result of comparing various parameters of the above echo signal and the simulation parameters is not in a desired range, the above transceiver algorithm will be adjusted. Otherwise, if the result of comparing various parameters of the above echo signal and the simulation parameters is in a desired range, the transceiver algorithm will be converted to a hardware program language format to be written in a programmable module to perform the action of the transmitter and the receiver.
Since the wireless communication equipment provided in the present invention employs the MIMO-CDMA technique, and it is a single wave time-space domain spreading technique, the signal dynamic range is not large, and the occupancy to digital/analog converter or digital/analog converter bit number is not large, therefore, a high dynamic flexible adjustment range can be obtained according to the change of the environment. Furthermore, since the single wave is not sensitive to the non-linearity of the radio frequency power amplifier, the present invention has the advantage of higher power efficiency and low transmitter complexity.
Further, the pre-verifying method provided in the present invention can verify the application of the algorithm developed for communication system correctly and rapidly, due to the practical comparison between the results from the system simulation and hardware operation.
In order to the make the aforementioned and other features and advantages of the present invention apparent, the preferred embodiments in accompany with drawings is described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a transmitter having multi-output according to a preferred embodiment of the present invention.

FIG. 2 is a functional block diagram of a data spreader according to a preferred embodiment of the present invention.

FIG. 3 is a schematic view of a data frame format according to a preferred embodiment of the present invention.

FIG. 4 is a functional block diagram of a receiver having multi-input according to a preferred embodiment of the present invention.

FIG. 5 is a circuit block diagram of an estimation module according to a preferred embodiment of the present invention.

FIG. 6 is a circuit block diagram of a decision demodulating module according to a preferred embodiment of the present invention.

FIG. 7 shows a flow chart of a pre-verifying method for software/hardware design of communication system according to a preferred embodiment of the present invention.

FIG. 8 shows a verifying system for software/hardware design of communication system meeting the verifying method of FIG. 7.

DESCRIPTION OF EMBODIMENTS

FIG. 1 is a functional block diagram of a transmitter having multi-output according to a preferred embodiment of the present invention. The transmitter is adapted to a MIMO-CDMA wireless communication equipment. Referring to FIG. 1, the transmitter 100 of the present invention has an encoder 102 with its output coupled to a quadrature phase-shift keying (QPSK) unit 104. The output of the QPSK unit 104 is coupled to a space-time block coding (STBC) unit 106. In the transmitter 100, a plurality of data frame generating modules are further provided, for example, 120, 140, for receiving the outputs of the STBC unit 106 and a preamble code spreading unit 108.
Still referring to FIG. 1, the encoder 102 receives a plurality of transmission data d1, d2, . . . , dn, and encodes the data. Next, the QPSK unit 104 will conduct QPSK modulating to the output of the encoder 102 to generate a plurality of QPSK symbol, and then spread the QPSK symbol with Walsh-Hadamard Orthogonal spreading, thereby obtaining a spread code gain to be output to the STBC unit 106. After the STBC unit 106 receives the output of the QPSK unit 104, it will conduct space-time block coding to the output, which can be represented by the mathematical expression below:
$[d_{2} d_{1}] -> [\begin{matrix} - d_{2}^{*} & d_{1} \\ d_{1}^{*} & d_{2} \end{matrix}]$
where, d1 and d2 are all transmission data. Then, the STBC unit 106 will send the output to the data frame generating module 120 and 140 respectively.
In another alternative embodiments, the STBC unit 106 can be replaced by a space multiplexer. The space multiplexer can conduct space coding to the output of the QPSK unit 104, which can be represented by the mathematical expression below.
$[d_{2} d_{1}] -> [\begin{matrix} d_{1} \\ d_{2} \end{matrix}]$
Still referring to FIG. 1, the data frame generating module 120 can be provided with a data spreader 122 for receiving the output of the STBC unit 106 or the space multiplexer. Furthermore, the output of the data spreader 122 is coupled to one output end of a multiplexer 124, while the other input end of the multiplexer 124 is the output of receiving the preamble code spreading unit 108. Therefore, the multiplexer 124 can send the output of the preamble code spreading unit 108 or the data spreader 124 to a digital/analog converter 126 selectively. The digital/analog converter 126 is coupled to a transmitting antenna 130 by a radio frequency unit 128.
Similarly, the data frame generating module 140 also includes a data spreader 142, a multiplexer 144, a digital/analog converter 146 and a radio frequency unit 148. The output of the radio frequency unit 148 is coupled to the transmitting antenna 150. The connection of the above means is the same as that of the data frame generating module 120. Definitely, the function and operation of each means of the data frame generating module 140 are similar to that of the data frame generating module 120. Therefore, the data frame generating module 120 will be taken as an example for illustration, and those skilled in the art will understand that the data frame generating module 140 can also be used.
For the present embodiment, when the output of the STBC unit 106 is sent to the data frame generating module 120, the data spreader 142 will spread the output of the STBC unit 106. In order to resist the influence of multi-path of the wireless channel, a pilot code is further added after a cyclic prefix (CP) similar to multiple wave orthogonal frequency division multiplexing (OFDM) is added to the output of the STBC unit 106, so as to create a payload data to the multiplexer 124.
FIG. 2 is a functional block diagram of a data spreader according to a preferred embodiment of the present invention. Referring to FIG. 2, in the present invention, the aforementioned data spreader 122 can include, for example, a data spreading unit 211, a cyclic prefix generating unit 213, a pilot codes generating unit 215 and an adder 217.
The data spreading unit 211 is used to spread the output of the STBC unit 106, then output it to the cyclic prefix generating unit 213. The cyclic prefix generating unit 213 will add a cyclic prefix to the output of the data spreading unit 211, then sends it to the adder 217.
Moreover, the pilot code generating unit 215 is used to generate a pilot code, and the output thereof will also coupled to the adder 217. Therefore, the adder 217 will add the output of the cyclic prefix generating unit 213 and the output of the pilot code generating unit 215 to generate a payload data.
Referring back to FIG. 1, after the multiplexer 124 receives, for example, the payload data output from the adder 217 of FIG. 2, it will generate a data frame in accompany with the preamble code spreading unit 108. The preamble codes are used from tracing the offset of the subsequent phase shift.
FIG. 3 is a schematic view of a data frame format according to a preferred embodiment of the present invention. Referring to FIGS. 1 and 3, in the present invention, the multiplexer 124 will firstly select the preamble codes generated by the preamble code spreading unit 108 as the output. As shown in FIG. 3, the preamble codes generated by the preamble code spreading unit 108 can be used for frame detecting, time estimation, frequency estimation, channel estimation and the like. In the present invention, the multiplexer 124 is required to output 8 preamble codes, and then switch to the data spreader 122 to output payload data. It can be seen from FIG. 3, in the payload data, a pilot code will also be added besides the received transmission data for the subsequent phase estimation and time tracing.
Still referring to FIG. 1, after the multiplexer 124 outputs, for example, the data frame shown in FIG. 3 to the digital/analog converter 126, the digital/analog converter 126 will convert the data frame to analog signal, and send it to the radio frequency unit 128. And after the radio frequency unit 128 increases the frequency of the output of the digital/analog converter 126 to the radio frequency, the output will be sent by the transmitting antenna 130.
Although in FIG. 1, the number of the data frame modules and the transmitting antennas is 2, it is known to those skilled in the art that the embodiment of FIG. 1 is only for illustration, and will not limit the present invention. It is similar to the receiver described below.
FIG. 4 is a functional block diagram of a receiver having multi-input according to a preferred embodiment of the present invention, which is also adapted to the MIMO-CDMA wireless communication equipment. Referring to FIG. 4, the receiver of the present invention includes a plurality of receiving antennas correspondingly coupled to a radio frequency unit respectively. For example, in the receiver 400, the receiving antennas 402, 404 are coupled to the radio frequency units 406, 408 respectively. And each of the radio frequency units is coupled to an estimation module, for example, the radio frequency units 406, 408 coupled to the estimation modules 410, 412 respectively. The outputs of all estimation modules will be coupled to a decision demodulating module 414, and the output of the decision demodulating module 414 is sent to a decoder 416.
Still referring to FIG. 4, the receiving antennas 402, 404 are used for receiving, for example, frame data sent by the transmitter 100 of FIG. 1, and each of the receiving antennas corresponds to a transmitting antenna. Taking the receiving antenna 402 as an example, the antenna will reducing the frame data to the base frequency signal through the radio frequency unit 406 after receiving the frame data, and then send it to the estimation module 410 to be processed.
FIG. 5 is a circuit block diagram of an estimation module according to a preferred embodiment of the present invention. Referring to FIG. 5, the estimation units 410, 412 in FIG. 4 can include, as shown in FIG. 5, a analog/digital converter 501, a time/frequency synchronization unit 503, a channel estimation unit 505, a cyclic prefix removing unit 507, and a phase estimation unit 509.
Referring to FIGS. 4 and 5, for example, when the output of the radio frequency unit 406 is sent to the estimation module 410, the analog/digital converter 501 in the estimation module 410 will convert the output to digital signal at first, and then send it to the time/frequency synchronization unit 503, the channel estimation unit 505 and the cyclic prefix removing unit 507. The time/frequency synchronization unit 503 will estimate the time and frequency parameters of the data frame received by the receiving antenna 402 based on the above preamble codes, and then send the output to the cyclic prefix removing unit 507 to remove the cyclic prefix. Furthermore, the channel estimation unit 505 estimates the channel parameter of the data frame based on the preamble codes, and the output A1 thereof is sent to the decision demodulation unit 414.
After the cyclic prefix removing unit 507 removes the cyclic prefix of the data frame, it also sends the output A2 thereof to the decision demodulating module 414. Moreover, the phase estimation unit 509 will estimate the phase of the output of the cyclic prefix removing unit 507 based on the above pilot codes, and the output A3 thereof is also coupled to the decision demodulation unit 414.
Although a estimation module 410 is taken as an example in the above description, it is known to those skilled in the art that the estimation module 412 can also be used.
FIG. 6 is a circuit block diagram of a decision demodulating module according to a preferred embodiment of the present invention, which is adapted to the decision demodulating module 414 of FIG. 4. Referring to FIGS. 4 and 6, the decision demodulating module 414 can include a decision unit 601 and a QPSK demodulation unit 603. When the outputs A1, A2 and A3 of the estimation module are sent to the decision demodulating module 414, the decision unit 601 will spread and compensate the outputs A1, A2 and A3 of the estimation module, and conduct space-time block decoding. Contrarily, in other embodiments, if the STBC unit 106 in the transmitter 100 of FIG. 1 is replaced by the space decoder, the decision unit 601 conducts interference elimination instead of space-time block decoding.
Then, the output of the decision unit 601 will be sent to the QPSK demodulation unit 603, to convert the output of the decision unit 601 back to the QPSK symbol. Then, the output of the QPSK demodulation unit 603 will be sent to the decoder 416 to revert the original transmission data d1, d2, . . . , dn.
In order to verify the correctness of the communication system consisting of the transmitter 100 and the receiver 400 of the FIGS. 1 and 4, the present invention further provides a pre-verifying method for software/hardware design of communication system, as shown in FIG. 7. Referring to FIG. 7, when a communication system having a transmitter and a receiver is to be designed, a transceiver algorithm is firstly designed according to a preset specification. In the present embodiment, the developers can design the transceiver algorithm with MATLAB software.
When the design of the transceiver algorithm is completed, a possible process of sending a data frame from the transmitter to the receiver can be simulated with this transceiver algorithm, and a plurality of simulation parameters can be obtained, as shown in step S701. In the present embodiment, step S701 mainly simulates the following states.
1. Simulating the state of the transmitter: an encoded spreading signal having QPSK modulation is generated with MATLAB Comm. Tool Box, and after the simulated base frequency signal is sampled and pulse shaped, the transmission signal of band-pass radio frequency is simulated under the equivalent base frequency I/Q model.
2. Simulating the channel environment: in order to simulate the possible situation in real environment, the transmission signal is added with channel effect including Additive White Gaussian Noise channel (AWGN Channel) effect and Rayleigh Fading channel effect. Moreover, in order to simulate the real transceiver, the effect of frequency offset between the oscillators of the transmitter and the receiver and the simulation of the signal propagation delay between the transmitter and the receiver are also added in the present invention.
3. Simulating the state of the receiver: simulate the echo signal influenced by the channel, and process the synchronization estimation and compensation with the de-spread technique of the above preamble codes and the pilot code, thereby decoding to revert original signal.
After the step S701 is completed, the present invention proceeds to step S703, that is, planning the transmitter hardware platform, to actually send out the data frame via an antenna. Then, as described in step S705, plan the receiver hardware platform to receive the echo signal of the data frame sent by the transmitter, and compare each of the parameters of the echo signal and the above simulation parameters, so as to verify whether the result of comparing each of the parameters of the echo signal and the above simulation parameters is within a desired range or not, as described in step S709.
When the result of comparing each of the parameters of the echo signal and the above simulation parameters does not fall within the desired range (“NO” indicated in step S709), the content of the above transceiver algorithm needs to be adjusted such that it can meet the desired better effect, as described in step S711.
Contrarily, When the result of comparing each of the parameters of the echo signal and the above simulation parameters fall in the desired range (“YES” indicated in step S709), the transceiver algorithm is converted to a hardware language, e.g. Verilog or VHDL and the like as described in step S713, such that it can be written into a programmable module to perform the action of the transmitter and the receiver as described in step S715.
FIG. 8 shows a verifying system for software/hardware design of communication system meeting the verifying method of FIG. 7. Referring to FIGS. 7 and 8, in FIG. 8, a system simulation part 810 and a hardware part 820 are included. The system simulation part 810 described in step S701 includes a transmitter algorithm 812 for simulating transmitter state, a channel model 814 for simulating real channel state, and a receiver algorithm 816 for simulating receiver state. And the simulation manner of these systems has been described above, and will not be described herein again.
In the hardware part 820, a transmitter hardware platform 830 and a receiver hardware platform 850 are included. The transmitter hardware platform 830 includes a charge coupled device (CCD) camera 832 for capturing image information. Furthermore, a read only memory (ROM) 834 can also be included in the transmitter hardware platform 830, to store the transmission signal meeting the preset specification.
After the transceiver hardware platform is activated, the transmitter hardware platform 830 will send the transmission signal stored in the ROM 834 in form of data frame to the receiver hardware platform 850 via a real channel environment.
After the receiver hardware platform 850 receives the echo signal of the data frame, a logic analyzer (LA) 852 will capture the digital signal, and various parameters of the digital signal are then analyzed under the MATLAB environment. Then these parameters are compared with the various parameters generated by the system simulation part 810 to be the reference of the adjustment by the developers.
When the result of comparing the various parameters of the echo signal and the simulation parameters generated by the system simulation part 810 is within a desired range, the transmitter algorithm 812 and the receiver algorithm 816 in the system simulation part 810 are converted to hardware language form, and are written into a field programmable gate array (FPGA) 838 of the transmitter hardware platform 830 and a FPGA 858 of the receiver hardware platform 850 respectively, thereby replacing the function of the ROM 834 and logic analyzer 852 by the FPGAs 838, 858.
In view of the above, the present invention can capture real-time dynamic image with a CCD camera 832, and then send the image information in form of data frame through a USB 836 via a real channel environment to the receiver to be processed. The image information is displayed on the display 856 through a USB 854 to realize a verifying scheme using comparison between the software and hardware, such that the communication system developed by the developers can be verified rapidly and correctly.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A pre-verifying method for software/hardware design of a communication system having a transmitter and a receiver, the pre-verifying method comprising:

simulating a process of sending a data frame from the transmitter to the receiver with a transceiver algorithm meeting a preset specification, and obtaining a plurality of simulation parameters;

planning a transmitter hardware platform to send out a data frame via an antenna, the transmitter hardware platform having a transmission signal meeting the preset specification;

planning a receiver hardware platform to receive an echo signal of the data frame, and comparing various parameters of the echo signal with the simulation parameters;

verifying whether the result of comparing the various parameters of the echo signal and the simulation parameters is within a desired range;

adjusting the transceiver algorithm if the result of comparing the various parameters of the echo signal and the simulation parameters is not within the desired range; and

converting the transceiver algorithm to a hardware program language format to be written into a programmable module to perform an action of the transmitter and the receiver if the result of comparing the various parameters of the echo signal and the simulation parameters is in the desired range.

2. The pre-verifying method for software/hardware design of the communication system as claimed in claim 1, wherein the simulating step using the receiver algorithm comprises:

simulating the state of the transmitter, including generating an encoded spreading signal having QPSK modulation by the MATLAB program language, and sampling and pulse shaping the encoded spreading signal;

simulating the channel environment, to simulate the possible situation of the data frame transmitted by the transmitter in real environment, and adding a plurality of channel effects to the data frame, the channel effects including Additive White Gaussian Noise (AWGN) channel effect and Reyleigh Fading channel effect; and

simulating the state of the receiver, to simulate the situation of the receiver receiving the echo signal of the data frame.

3. The pre-verifying method for software/hardware design of the communication system as claimed in claim 2, wherein the step of simulating the channel environment further comprises simulating the oscillating frequency offset effect between the transmitter and the receiver, and simulating the signal propagation delay between the transmitter and the receiver.

4. The pre-verifying method for software/hardware design of the communication system as claimed in claim 1, wherein the step of planning the transmitter hardware platform comprises:

sending the data frame to the receiver via a transmitter radio frequency unit and the antenna, based on the transmission signal stored in a read-only memory (ROM).

5. The pre-verifying method for software/hardware design of the communication system as claimed in claim 1, wherein the step of planning the receiver hardware platform comprises:

analyzing the echo signal of the data frame with a logic analyzer and MATLAB, to compare it with the simulation parameters; and

displaying the image information on a display through a second universal serial bus (USB).

6. The pre-verifying mryhof for software/hardware design of the communication system as claimed in claim 1, wherein the programmable module is a field programmable gate array (FPGA).