US20090101513A1 - Method of manufacturing a film printed circuit board - Google Patents

Method of manufacturing a film printed circuit board Download PDF

Info

Publication number
US20090101513A1
US20090101513A1 US12/326,601 US32660108A US2009101513A1 US 20090101513 A1 US20090101513 A1 US 20090101513A1 US 32660108 A US32660108 A US 32660108A US 2009101513 A1 US2009101513 A1 US 2009101513A1
Authority
US
United States
Prior art keywords
copper
layer
printed circuit
circuit board
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/326,601
Inventor
Chia-Hui Wu
Pai-Sheng Cheng
Hung-Yi Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US12/326,601 priority Critical patent/US20090101513A1/en
Publication of US20090101513A1 publication Critical patent/US20090101513A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography
    • H05K2203/0542Continuous temporary metal layer over metal pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1476Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Definitions

  • Taiwan Application Serial Number 94114561 filed May 5, 2005, the disclosure of which is hereby incorporated by reference herein in its entirety.
  • the present invention relates to a method of manufacturing a film printed circuit board, which is used in a chip on flex or chip on film process. More particularly, the present invention relates to a method of manufacturing a copper structure on a film printed circuit board, which is used in a chip on flex or chip on film process.
  • IC packaging technology has evolved from a tape automatic bonding (TAB) process into a chip on flex or chip on film (COF) process.
  • TAB tape automatic bonding
  • COF chip on film
  • the COF process makes a flip chip bond on a flexible or film printed circuit board. That is, to achieve the objective of being smaller, a driving IC and the electrical components are mounted on a film without the use of a traditional printed circuit. Thus, the COF process is usually employed to package a driving IC on a display panel.
  • a substrate of the film printed circuit board is made of polyimide (PI).
  • An alloy layer is positioned on the substrate, and a copper metal layer is positioned on the alloy layer wherein the alloy layer is made of Ni—Cr alloy.
  • a patterned photo resistant layer is formed on the copper metal layer by a lithography process, and then the copper metal layer, which is exposed, and the alloy layer under thereof are etched by a wet etching process.
  • the wet etching process may employ a solution containing copper chloride, ferric amine etc, as an etchant.
  • FIG. 1 is a sectional view of a conductive copper line formed by a traditional process.
  • the copper metal layer on the PI substrate 100 is etched by the wet etching process to form a conductive copper line 104 .
  • a side effect of the wet etching process is that undercuts occur under the photo resistant layer 106 , which makes the conductive copper line 104 to have a narrower top and a wider bottom.
  • the thickness of the conductive copper line 104 is preferably between 6-12 ⁇ m, and the top width of the conductive copper line 104 should be more than half of the bottom width of the conductive copper line 104 .
  • top width of the copper line is too narrow, following processes, such as inner lead Au bump packaging and outer lead anisotropic conductive film (ACF) packaging processes, will be hard to perform.
  • a way to increase the top width of the conductive copper line is to reduce the thickness of the conductive copper line, but if the thickness of the conductive copper line is too thin, the conductive copper line will be broken when the film printed circuit board is bent.
  • FIG. 2A and FIG. 2B are schematic views of a traditional process for preventing the top width of the copper line from being too narrow.
  • an alloy layer 202 and a copper metal layer 204 are positioned on a PI substrate 200 in order.
  • a patterned photo resistant layer 206 is formed on the copper metal layer 204 , and the patterned photo resistant layer 206 has openings 207 .
  • Another copper metal layer 208 is formed in the openings 207 by an electroplating process, and then, as illustrated in FIG. 2B , the patterned photo resistant layer 206 is removed, and thus the copper metal layer 208 protrudes from the copper metal layer 204 .
  • the copper metal layer 208 , copper metal layer 204 and alloy layer 202 are etched by a wet etching process until the PI substrate 200 is exposed. Parts of the copper metal layer 204 , which are positioned in the opening 211 (illustrated in FIG. 2B ), are completely removed and the other parts of the copper metal layer 204 which are positioned under the copper metal layer 208 partially remain.
  • the side-walls of the conductive copper lines 210 have a recess caused by the wet etching process with the top width of the copper metal lines 210 maintained, a characteristic of isotropic etching.
  • the alloy layer 202 usually exists and is positioned under the copper metal layer 204 , and the alloy layer 202 is typically made of Ni—Cr alloy. It is more difficult to etch Ni—Cr than copper when forming conductive copper lines 210 by the wet etching process.
  • the alloy layer 202 which is positioned between the conductive copper lines 210 , will not be removed completely such that a micro-short problem will occur between the conductive copper lines 210 ; if the time of the wet etching process is increased to assure that the alloy layer 202 , which is positioned between the conductive copper lines 210 , can be removed completely, undercuts due to the over-etching the alloy layer 202 will occur under the conductive copper lines 210 , such that the base of the conductive copper lines 210 will be weak. That is, although the solution mentioned above is able to improve the top width of the conductive lines, undercuts may still occur. Obviously, this solution cannot solve all problems related to manufacturing film printed circuit boards effectively.
  • the shape of the conductive copper lines on the film substrate influences the following COF process. If the top widths of the conductive lines are too narrow, it will be difficult to fasten the conductive lines on the substrate; if the thickness of the conductive lines is too thick, the conductive copper line will be broken when the film printed circuit board is bent.
  • the top widths and thicknesses of the conductive lines with the required shape are sufficient and prevent micro-short problems from occurring between the conductive lines.
  • a method of manufacturing a film printed circuit board is provided.
  • a film substrate consisting of a polyimide substrate, an alloy layer and a first metal layer are provided.
  • a first lithographic and etching process is performed to pattern the first metal layer and the alloy layer, and a plurality of first conductive line structures is formed on the polyimide substrate.
  • a second metal layer is formed over the polyimide substrate and the first conductive line structures.
  • a second lithographic and etching process is performed to pattern the second metal layer.
  • the first metal layer and the second metal layer may be made of copper.
  • a film printed circuit board includes a film substrate and a conductive line positioned on the film substrate.
  • the conductive line has a first metal conductive line structure and a second metal conductive line structure.
  • the first metal conductive line structure is positioned on the film substrate, and the second metal conductive line structure is positioned on the first metal conductive line structure.
  • the conductive line is has concave side-walls.
  • the first metal conductive line structure may comprise copper and Ni—Cr alloy, and the second metal conductive line structure may comprise copper.
  • the film printed circuit board according to the present invention may be used to support a chip.
  • the method of manufacturing a film printed circuit board according to the present invention employs the first lithographic and etching process to define the width of the conductive lines; employs a copper electroplating process to form a copper metal layer for determining the thickness of the conductive lines; and finally employs the second lithographic and etching process to determine the top width of the conductive lines.
  • a film substrate is provided first, and an alloy layer and a first copper layer is positioned on the film substrate in order.
  • the alloy layer may be made of Ni—Cr alloy.
  • a first patterned photo resistant layer is formed on the first copper layer, and then the first wet etching process is performed to remove the first copper layer, which is exposed, and the alloy layer, which is positioned under the copper layer.
  • conductive line structures which are electrically insulated from each other are formed under the first patterned photo resistant layer.
  • a second copper layer is formed over the film substrate.
  • An electroplating process or a chemical plating process may be employed to form the second copper layer on a copper crystal seed layer positioned on the surface of the film substrate.
  • the copper crystal seed layer may be formed by a physical vapor deposition process (PVD), eg. sputtering.
  • PVD physical vapor deposition process
  • a second patterned photo resistant layer is formed on the second copper layer.
  • the pattern of the second patterned photo resistant layer is the same as the pattern of the first patterned photo resistant layer.
  • a second wet etching process is performed to pattern the second copper layer, and thus conductive lines, which are electrically insulated from each other, are formed under the second patterned photo resistant layer.
  • the second patterned photo resistant layer is removed.
  • the patterned photo resistant layer may be formed by spin coating a photo resistant layer on the second copper layer or adhering a dry film photo resistant layer on the second copper layer first and then performing a lithography process for patterning the photo resistant layer.
  • the alloy layer which is positioned between the two adjacent conductive lines, can be removed completely by the first lithography and etching process, which defines the width of the conductive lines.
  • the second copper layer is able to compensate the first copper layer, which is removed by the first lithography and etching process, the problem of the top width of the conductive lines not being wide enough because of over etching the copper layer is no longer a concern in this step.
  • the second copper layer is formed by the copper electroplating process to determine the thickness of the conductive lines and to compensate the top width of the first copper layer; finally, the top width of the conductive lines are defined by the second lithography and etching process.
  • the method of manufacturing a film printed circuit board according to the present invention solves the problem of narrow conductive line top widths experienced by contemporary manufacturing methods and maintains the thickness of the conductive lines. Furthermore, the method of manufacturing a film printed circuit board according the present invention does not only satisfy the design requirement of the conductive lines, but prevents the micro-short problem from occurring between the conductive lines because the alloy layer, positioned between two adjacent conductive lines, is removed completely.
  • FIG. 1 is a sectional view of a conductive copper line formed by a traditional process
  • FIGS. 2A-2C are schematic views of a traditional process for preventing the top width of the copper line from being too narrow.
  • FIGS. 3A-3E are sectional views illustrating the method of manufacturing a film printed circuit board according to one preferred embodiment of the present invention.
  • FIGS. 3A-3E are sectional views illustrating the method of manufacturing a film printed circuit board according to one preferred embodiment of the invention.
  • An alloy layer 302 and a copper layer 304 are formed on a PI substrate 300 in order.
  • the alloy layer 302 may be made of Ni—Cr alloy.
  • a copper crystal seed layer (not shown) may be formed between the copper layer 304 and the alloy layer 302 .
  • a patterned photo resistant layer 306 is formed on the copper layer 304 , and the patterned photo resistant layer 306 has openings 307 .
  • the copper layer 304 which is exposed by the openings 307 , and the alloy layer 302 , which is positioned under the openings 307 , are etched by a wet etching process which employs the patterned photo resistant layer 306 as a mask.
  • the wet etching process may also employ a solution containing copper chloride and ferric amine etc as an etchant.
  • the patterned photo resistant layer 306 may be formed by spin coating a photo resistant layer on the copper layer 304 or adhering a dry film photo resistant layer on the copper layer 304 first and then performing a lithography process for patterning the photo resistant layer. After the wet etching process is performed, conductive line structures 305 consisting of the copper layer 304 a and the alloy layer 302 a as shown in FIG. 3B can be obtained.
  • another copper layer 308 is formed on the conductive line structures.
  • the PI substrate 300 and the conductive line structures 305 may be covered with a copper crystal seed layer by a physical vapor deposition process (PVD), ex. sputtering. Then an electroplating process or an electroless plating process may be used to form the copper layer 308 .
  • PVD physical vapor deposition process
  • a patterned photo resistant layer 309 is formed on the copper layer 308 .
  • the patterned photo resistant layer 309 has openings 311 .
  • the openings 311 expose a region between two adjacent conductive line structures 305 .
  • a wet etching process is performed.
  • the wet etching process may also employ a solution containing copper chloride and ferric amine etc as an etchant.
  • Detailed steps for forming the patterned photo resistant layer 309 are the same as the detailed steps for forming the patterned photo resistant layer 306 which has been described above.
  • the copper layer 308 which is not covered by the patterned photo resistant layer 309 , is etched until the PI substrate 300 is exposed by the wet etching process, after which conductive copper line structures 310 that are covered with the patterned photo resistant layer 309 are formed.
  • the conductive copper line structures 310 consists of a copper layer 304 a and a copper layer 308 (as shown in FIG. 3C ) which have been etched.
  • the conductive copper line structures 310 are shaped with a narrower middle and wider top and bottom because the wet etching process isotropic etching characteristics, and the copper layer 308 is covered with the patterned photo resistant layer 309 (shown in FIG. 3C ).
  • the conductive copper line structures 310 have concave side-walls.
  • conductive lines 312 consisting of the conductive copper line structures 310 and the alloy layer 302 a under thereof are provided.
  • the side-walls of the conductive lines 312 have a concave shape because the wet etching process isotropic etching characteristics.
  • the top width of the conductive lines 312 can be maintained because the pattern of the photo resistant layer 309 (shown in FIG. 3D ).
  • the conductive lines 312 have the characteristics of concave side-walls with a sufficiently thickness and top width.
  • the method of manufacturing a film printed circuit board according to the present invention can remove the alloy layer 302 , which is exposed, completely by over etching when forming the conductive line structures. Thus, a micro-short problem can be prevented from occurring between the conductive lines and the top width of the conductive lines need not be considered in this step.
  • the copper layer 308 which is formed by the electroplating process shown in FIG. 3C is able to compensate the lost top width and thickness of conductive line structures 305 .
  • the lost top width and thickness of conductive line structures 305 are due to over etch the conductive line structures 305 .
  • Materials which are etched by the wet etching process to form the conductive lines 312 are copper, and the alloy layer need not to be over etched in this step.
  • the dual problems of narrow conductive line top widths and undercutting experienced by contemporary manufacturing methods are solved.
  • the widths of the conductive lines are defined by the first lithography and etching process; the thickness of the conductive lines are determined by the copper layer formed by the electroplating process; finally, the top widths of the conductive lines are defined by the second lithography and etching process.
  • the method of manufacturing a film printed circuit board disclosed in this invention is able to manufacture the conductive lines with the required shape, that is, that top widths and thicknesses of the conductive lines are sufficient. Furthermore, the method of manufacturing a film printed circuit board according to the present invention does not only satisfy the design requirement of the conductive lines, but prevents the micro-short problem from occurring between the conductive lines because the alloy layer, positioned between two adjacent conductive lines, is removed completely.

Abstract

A method of manufacturing a film printed circuit board is provided. A film substrate consisting of a polyimide substrate, an alloy layer and a first copper layer is provided. A first lithographic and etching process is performed to pattern the copper layer and the alloy layer and a plurality of conductive line structures is formed on the polyimide substrate. A second copper layer is formed over the polyimide substrate and the conductive line structures. A second lithographic and etching process is performed to pattern the second copper layer.

Description

    RELATED APPLICATIONS
  • The present application is based on, and claims priority from, Taiwan Application Serial Number 94114561, filed May 5, 2005, the disclosure of which is hereby incorporated by reference herein in its entirety.
  • BACKGROUND
  • 1. Field of Invention
  • The present invention relates to a method of manufacturing a film printed circuit board, which is used in a chip on flex or chip on film process. More particularly, the present invention relates to a method of manufacturing a copper structure on a film printed circuit board, which is used in a chip on flex or chip on film process.
  • 2. Description of Related Art
  • Driving integrated circuit (IC) packaging technology has evolved from a tape automatic bonding (TAB) process into a chip on flex or chip on film (COF) process. The driving force behind the evolution is the demand for increasingly smaller displays with higher dpi resolutions, while the sizes of the machines for which the displays are adapted are always decreasing.
  • The COF process makes a flip chip bond on a flexible or film printed circuit board. That is, to achieve the objective of being smaller, a driving IC and the electrical components are mounted on a film without the use of a traditional printed circuit. Thus, the COF process is usually employed to package a driving IC on a display panel.
  • Typically, a substrate of the film printed circuit board is made of polyimide (PI). An alloy layer is positioned on the substrate, and a copper metal layer is positioned on the alloy layer wherein the alloy layer is made of Ni—Cr alloy. A patterned photo resistant layer is formed on the copper metal layer by a lithography process, and then the copper metal layer, which is exposed, and the alloy layer under thereof are etched by a wet etching process. The wet etching process may employ a solution containing copper chloride, ferric amine etc, as an etchant.
  • FIG. 1 is a sectional view of a conductive copper line formed by a traditional process. After the patterned photo resistant layer 106 is formed, the copper metal layer on the PI substrate 100 is etched by the wet etching process to form a conductive copper line 104. A side effect of the wet etching process is that undercuts occur under the photo resistant layer 106, which makes the conductive copper line 104 to have a narrower top and a wider bottom. Generally, the thickness of the conductive copper line 104 is preferably between 6-12 μm, and the top width of the conductive copper line 104 should be more than half of the bottom width of the conductive copper line 104. If the top width of the copper line is too narrow, following processes, such as inner lead Au bump packaging and outer lead anisotropic conductive film (ACF) packaging processes, will be hard to perform. A way to increase the top width of the conductive copper line is to reduce the thickness of the conductive copper line, but if the thickness of the conductive copper line is too thin, the conductive copper line will be broken when the film printed circuit board is bent.
  • A solution to the problem mentioned above has been developed. FIG. 2A and FIG. 2B are schematic views of a traditional process for preventing the top width of the copper line from being too narrow. As illustrated in FIG. 2A, an alloy layer 202 and a copper metal layer 204 are positioned on a PI substrate 200 in order. A patterned photo resistant layer 206 is formed on the copper metal layer 204, and the patterned photo resistant layer 206 has openings 207. Another copper metal layer 208 is formed in the openings 207 by an electroplating process, and then, as illustrated in FIG. 2B, the patterned photo resistant layer 206 is removed, and thus the copper metal layer 208 protrudes from the copper metal layer 204.
  • As illustrated in FIG. 2C, the copper metal layer 208, copper metal layer 204 and alloy layer 202 are etched by a wet etching process until the PI substrate 200 is exposed. Parts of the copper metal layer 204, which are positioned in the opening 211 (illustrated in FIG. 2B), are completely removed and the other parts of the copper metal layer 204 which are positioned under the copper metal layer 208 partially remain. The side-walls of the conductive copper lines 210 have a recess caused by the wet etching process with the top width of the copper metal lines 210 maintained, a characteristic of isotropic etching.
  • The solution mentioned above seems effective but still has serious problems. As illustrated in FIG. 2A, the alloy layer 202 usually exists and is positioned under the copper metal layer 204, and the alloy layer 202 is typically made of Ni—Cr alloy. It is more difficult to etch Ni—Cr than copper when forming conductive copper lines 210 by the wet etching process. Thus, if the time of the wet etching process is not enough, the alloy layer 202, which is positioned between the conductive copper lines 210, will not be removed completely such that a micro-short problem will occur between the conductive copper lines 210; if the time of the wet etching process is increased to assure that the alloy layer 202, which is positioned between the conductive copper lines 210, can be removed completely, undercuts due to the over-etching the alloy layer 202 will occur under the conductive copper lines 210, such that the base of the conductive copper lines 210 will be weak. That is, although the solution mentioned above is able to improve the top width of the conductive lines, undercuts may still occur. Obviously, this solution cannot solve all problems related to manufacturing film printed circuit boards effectively.
  • SUMMARY
  • The shape of the conductive copper lines on the film substrate influences the following COF process. If the top widths of the conductive lines are too narrow, it will be difficult to fasten the conductive lines on the substrate; if the thickness of the conductive lines is too thick, the conductive copper line will be broken when the film printed circuit board is bent.
  • It is therefore an aspect of the present invention to provide a method of manufacturing a film printed circuit board, which is able to manufacture conductive lines with a required shape. The top widths and thicknesses of the conductive lines with the required shape are sufficient and prevent micro-short problems from occurring between the conductive lines.
  • In accordance with the foregoing and other aspects of the present invention, a method of manufacturing a film printed circuit board is provided. A film substrate consisting of a polyimide substrate, an alloy layer and a first metal layer are provided. A first lithographic and etching process is performed to pattern the first metal layer and the alloy layer, and a plurality of first conductive line structures is formed on the polyimide substrate. A second metal layer is formed over the polyimide substrate and the first conductive line structures. A second lithographic and etching process is performed to pattern the second metal layer. The first metal layer and the second metal layer may be made of copper.
  • In accordance with the foregoing and other aspects of the present invention, a film printed circuit board is provided. The film printed circuit board includes a film substrate and a conductive line positioned on the film substrate.
  • The conductive line has a first metal conductive line structure and a second metal conductive line structure. The first metal conductive line structure is positioned on the film substrate, and the second metal conductive line structure is positioned on the first metal conductive line structure. The conductive line is has concave side-walls. The first metal conductive line structure may comprise copper and Ni—Cr alloy, and the second metal conductive line structure may comprise copper. The film printed circuit board according to the present invention may be used to support a chip.
  • The method of manufacturing a film printed circuit board according to the present invention employs the first lithographic and etching process to define the width of the conductive lines; employs a copper electroplating process to form a copper metal layer for determining the thickness of the conductive lines; and finally employs the second lithographic and etching process to determine the top width of the conductive lines.
  • To perform the method of manufacturing a film printed circuit board according to the present invention, a film substrate is provided first, and an alloy layer and a first copper layer is positioned on the film substrate in order. The alloy layer may be made of Ni—Cr alloy. A first patterned photo resistant layer is formed on the first copper layer, and then the first wet etching process is performed to remove the first copper layer, which is exposed, and the alloy layer, which is positioned under the copper layer. Thus, conductive line structures, which are electrically insulated from each other are formed under the first patterned photo resistant layer.
  • Then, a second copper layer is formed over the film substrate. An electroplating process or a chemical plating process may be employed to form the second copper layer on a copper crystal seed layer positioned on the surface of the film substrate. The copper crystal seed layer may be formed by a physical vapor deposition process (PVD), eg. sputtering. After the second copper layer is formed, a second patterned photo resistant layer is formed on the second copper layer. The pattern of the second patterned photo resistant layer is the same as the pattern of the first patterned photo resistant layer. A second wet etching process is performed to pattern the second copper layer, and thus conductive lines, which are electrically insulated from each other, are formed under the second patterned photo resistant layer. Finally, the second patterned photo resistant layer is removed.
  • The patterned photo resistant layer may be formed by spin coating a photo resistant layer on the second copper layer or adhering a dry film photo resistant layer on the second copper layer first and then performing a lithography process for patterning the photo resistant layer.
  • According to one preferred embodiment of the present invention, the alloy layer, which is positioned between the two adjacent conductive lines, can be removed completely by the first lithography and etching process, which defines the width of the conductive lines. Because the second copper layer is able to compensate the first copper layer, which is removed by the first lithography and etching process, the problem of the top width of the conductive lines not being wide enough because of over etching the copper layer is no longer a concern in this step. The second copper layer is formed by the copper electroplating process to determine the thickness of the conductive lines and to compensate the top width of the first copper layer; finally, the top width of the conductive lines are defined by the second lithography and etching process.
  • The method of manufacturing a film printed circuit board according to the present invention solves the problem of narrow conductive line top widths experienced by contemporary manufacturing methods and maintains the thickness of the conductive lines. Furthermore, the method of manufacturing a film printed circuit board according the present invention does not only satisfy the design requirement of the conductive lines, but prevents the micro-short problem from occurring between the conductive lines because the alloy layer, positioned between two adjacent conductive lines, is removed completely.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention can be more fully understood by reading the following detailed description of the preferred embodiment, with reference made to the accompanying drawings as follows:
  • FIG. 1 is a sectional view of a conductive copper line formed by a traditional process; and
  • FIGS. 2A-2C are schematic views of a traditional process for preventing the top width of the copper line from being too narrow; and
  • FIGS. 3A-3E are sectional views illustrating the method of manufacturing a film printed circuit board according to one preferred embodiment of the present invention.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Reference will now be made in detail to the method of manufacturing a film printed circuit board according to the present invention. How to form conductive copper lines, which have a proper top width, on a film printed circuit board will be illustrated in the present embodiment of the invention.
  • FIGS. 3A-3E are sectional views illustrating the method of manufacturing a film printed circuit board according to one preferred embodiment of the invention. Reference is made to FIG. 3A. An alloy layer 302 and a copper layer 304 are formed on a PI substrate 300 in order. The alloy layer 302 may be made of Ni—Cr alloy. A copper crystal seed layer (not shown) may be formed between the copper layer 304 and the alloy layer 302. A patterned photo resistant layer 306 is formed on the copper layer 304, and the patterned photo resistant layer 306 has openings 307. The copper layer 304, which is exposed by the openings 307, and the alloy layer 302, which is positioned under the openings 307, are etched by a wet etching process which employs the patterned photo resistant layer 306 as a mask. The wet etching process may also employ a solution containing copper chloride and ferric amine etc as an etchant. The patterned photo resistant layer 306 may be formed by spin coating a photo resistant layer on the copper layer 304 or adhering a dry film photo resistant layer on the copper layer 304 first and then performing a lithography process for patterning the photo resistant layer. After the wet etching process is performed, conductive line structures 305 consisting of the copper layer 304 a and the alloy layer 302 a as shown in FIG. 3B can be obtained.
  • As shown in FIG. 3C, another copper layer 308 is formed on the conductive line structures. The PI substrate 300 and the conductive line structures 305 may be covered with a copper crystal seed layer by a physical vapor deposition process (PVD), ex. sputtering. Then an electroplating process or an electroless plating process may be used to form the copper layer 308.
  • Reference is made to FIG. 3C, again. A patterned photo resistant layer 309 is formed on the copper layer 308. The patterned photo resistant layer 309 has openings 311. The openings 311 expose a region between two adjacent conductive line structures 305. Then, a wet etching process is performed. The wet etching process may also employ a solution containing copper chloride and ferric amine etc as an etchant. Detailed steps for forming the patterned photo resistant layer 309 are the same as the detailed steps for forming the patterned photo resistant layer 306 which has been described above.
  • As shown in FIG. 3D, the copper layer 308, which is not covered by the patterned photo resistant layer 309, is etched until the PI substrate 300 is exposed by the wet etching process, after which conductive copper line structures 310 that are covered with the patterned photo resistant layer 309 are formed. The conductive copper line structures 310 consists of a copper layer 304 a and a copper layer 308 (as shown in FIG. 3C) which have been etched. The conductive copper line structures 310 are shaped with a narrower middle and wider top and bottom because the wet etching process isotropic etching characteristics, and the copper layer 308 is covered with the patterned photo resistant layer 309 (shown in FIG. 3C). Basically, the conductive copper line structures 310 have concave side-walls.
  • As shown in FIG. 3E, after the patterned photo resistant layer 309 is removed, conductive lines 312 consisting of the conductive copper line structures 310 and the alloy layer 302 a under thereof are provided. The side-walls of the conductive lines 312 have a concave shape because the wet etching process isotropic etching characteristics. The top width of the conductive lines 312 can be maintained because the pattern of the photo resistant layer 309 (shown in FIG. 3D). The conductive lines 312 have the characteristics of concave side-walls with a sufficiently thickness and top width.
  • The method of manufacturing a film printed circuit board according to the present invention can remove the alloy layer 302, which is exposed, completely by over etching when forming the conductive line structures. Thus, a micro-short problem can be prevented from occurring between the conductive lines and the top width of the conductive lines need not be considered in this step.
  • Then, the copper layer 308 which is formed by the electroplating process shown in FIG. 3C is able to compensate the lost top width and thickness of conductive line structures 305. The lost top width and thickness of conductive line structures 305 are due to over etch the conductive line structures 305.
  • Materials which are etched by the wet etching process to form the conductive lines 312 (shown in FIG. 3E) are copper, and the alloy layer need not to be over etched in this step. Thus, the dual problems of narrow conductive line top widths and undercutting experienced by contemporary manufacturing methods are solved.
  • According to one preferred embodiment of the present invention, the widths of the conductive lines are defined by the first lithography and etching process; the thickness of the conductive lines are determined by the copper layer formed by the electroplating process; finally, the top widths of the conductive lines are defined by the second lithography and etching process. The method of manufacturing a film printed circuit board disclosed in this invention is able to manufacture the conductive lines with the required shape, that is, that top widths and thicknesses of the conductive lines are sufficient. Furthermore, the method of manufacturing a film printed circuit board according to the present invention does not only satisfy the design requirement of the conductive lines, but prevents the micro-short problem from occurring between the conductive lines because the alloy layer, positioned between two adjacent conductive lines, is removed completely.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (11)

1. A method of manufacturing a film printed circuit board, comprising the steps of:
providing a film substrate having a first metal layer;
performing a first etching process to pattern the first metal layer, and a plurality of first conductive line structures are formed on the film substrate;
forming a second metal layer over the film substrate and the first conductive line structures; and
performing a second etching process to pattern the second metal layer.
2. The method of manufacturing a film printed circuit board as claimed in claim 1, wherein the first metal layer comprises Ni—Cr alloy.
3. The method of manufacturing a film printed circuit board as claimed in claim 1, wherein the first etching process comprises:
forming a photo resistant layer on the first metal layer;
patterning the photo resistant layer for exposing parts of the first metal layer;
etching the first metal layer, which is exposed, by a wet etching process until the film substrate is exposed; and
removing the photo resistant layer.
4. The method of manufacturing a film printed circuit board as claimed in claim 3, wherein the first metal layer comprises copper.
5. The method of manufacturing a film printed circuit board as claimed in claim 1, further comprising covering the film substrate and the first conductive lines with a copper crystal seed layer.
6. The method of manufacturing a film printed circuit board as claimed in claim 5, wherein the step of covering the film substrate and the first conductive lines with the copper crystal seed layer comprises a sputtering process.
7. The method of manufacturing a film printed circuit board as claimed in claim 1, wherein the step of forming the second metal layer comprises an electroplating process.
8. The method of manufacturing a film printed circuit board as claimed in claim 1, wherein the step of forming the second metal layer comprises a chemical plating process.
9. The method of manufacturing a film printed circuit board as claimed in claim 1, wherein the second etching process comprises:
forming a photo resistant layer on the second metal layer;
patterning the photo resistant layer, the patterned photo resistant layer are positioned over the first conductive line structures;
etching the second metal layer, which is exposed, by a wet etching process until the film substrate is exposed; and removing the photo resistant layer.
10. The method of manufacturing a film printed circuit board as claimed in claim 1, wherein the second metal layer comprises copper.
11-15. (canceled)
US12/326,601 2005-05-05 2008-12-02 Method of manufacturing a film printed circuit board Abandoned US20090101513A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/326,601 US20090101513A1 (en) 2005-05-05 2008-12-02 Method of manufacturing a film printed circuit board

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW094114561A TWI333808B (en) 2005-05-05 2005-05-05 A method of manufacturing a film printed circuit board
TW94114561 2005-05-05
US11/379,744 US7473459B2 (en) 2005-05-05 2006-04-21 Method of manufacturing a film printed circuit board
US12/326,601 US20090101513A1 (en) 2005-05-05 2008-12-02 Method of manufacturing a film printed circuit board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/379,744 Division US7473459B2 (en) 2005-05-05 2006-04-21 Method of manufacturing a film printed circuit board

Publications (1)

Publication Number Publication Date
US20090101513A1 true US20090101513A1 (en) 2009-04-23

Family

ID=37394356

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/379,744 Expired - Fee Related US7473459B2 (en) 2005-05-05 2006-04-21 Method of manufacturing a film printed circuit board
US12/326,601 Abandoned US20090101513A1 (en) 2005-05-05 2008-12-02 Method of manufacturing a film printed circuit board

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/379,744 Expired - Fee Related US7473459B2 (en) 2005-05-05 2006-04-21 Method of manufacturing a film printed circuit board

Country Status (2)

Country Link
US (2) US7473459B2 (en)
TW (1) TWI333808B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200455170Y1 (en) * 2009-07-15 2011-08-23 히타치 덴센 가부시키가이샤 TBI tape for semiconductor device and manufacturing method thereof
US20120138968A1 (en) * 2010-12-07 2012-06-07 Na-Rae Shin Semiconductor package and display panel assembly having the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI606771B (en) 2015-04-01 2017-11-21 群創光電股份有限公司 Display panel
EP3322267A1 (en) 2016-11-10 2018-05-16 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with adhesion promoting shape of wiring structure
CN108575056A (en) * 2017-03-07 2018-09-25 宏启胜精密电子(秦皇岛)有限公司 flexible circuit board manufacturing method
CN111465220B (en) * 2020-04-23 2022-11-08 胜宏科技(惠州)股份有限公司 Compensation method for gold finger etching

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4786576A (en) * 1984-09-27 1988-11-22 Olin Hunt Specialty Products, Inc. Method of high resolution of electrostatic transfer of a high density image to a nonporous and nonabsorbent conductive substrate
US4948462A (en) * 1989-10-20 1990-08-14 Applied Materials, Inc. Tungsten etch process with high selectivity to photoresist
US5458763A (en) * 1992-11-12 1995-10-17 Hitachi, Ltd. Method for forming wiring pattern
US5569960A (en) * 1994-05-16 1996-10-29 Hitachi, Ltd. Electronic component, electronic component assembly and electronic component unit
US5701055A (en) * 1994-03-13 1997-12-23 Pioneer Electronic Corporation Organic electoluminescent display panel and method for manufacturing the same
US5779926A (en) * 1994-09-16 1998-07-14 Applied Materials, Inc. Plasma process for etching multicomponent alloys
US6605519B2 (en) * 2001-05-02 2003-08-12 Unaxis Usa, Inc. Method for thin film lift-off processes using lateral extended etching masks and device
US6617234B2 (en) * 2001-04-06 2003-09-09 United Microelectronics Corp. Method of forming metal fuse and bonding pad
US6652073B2 (en) * 2001-12-31 2003-11-25 Nanodynamics Inc. Structure of a flexible printed circuit for inkjet printheads and the manufacturing process therefor
US6878901B2 (en) * 2001-02-12 2005-04-12 Morgan Miller Technologies Llc Laser micromachining and electrical structures formed thereby
US6897568B2 (en) * 2000-03-31 2005-05-24 Infineon Technologies Ag Electronic component with flexible contacting pads and method for producing the electronic component

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19911150C1 (en) 1999-03-12 2000-04-20 Siemens Ag Microelectronic structure, especially semiconductor memory, production comprising physically etching a conductive layer from a substrate such that removed material is transferred onto a layer structure side wall
TW200406829A (en) 2002-09-17 2004-05-01 Adv Lcd Tech Dev Ct Co Ltd Interconnect, interconnect forming method, thin film transistor, and display device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4786576A (en) * 1984-09-27 1988-11-22 Olin Hunt Specialty Products, Inc. Method of high resolution of electrostatic transfer of a high density image to a nonporous and nonabsorbent conductive substrate
US4948462A (en) * 1989-10-20 1990-08-14 Applied Materials, Inc. Tungsten etch process with high selectivity to photoresist
US5458763A (en) * 1992-11-12 1995-10-17 Hitachi, Ltd. Method for forming wiring pattern
US5701055A (en) * 1994-03-13 1997-12-23 Pioneer Electronic Corporation Organic electoluminescent display panel and method for manufacturing the same
US5569960A (en) * 1994-05-16 1996-10-29 Hitachi, Ltd. Electronic component, electronic component assembly and electronic component unit
US5779926A (en) * 1994-09-16 1998-07-14 Applied Materials, Inc. Plasma process for etching multicomponent alloys
US6897568B2 (en) * 2000-03-31 2005-05-24 Infineon Technologies Ag Electronic component with flexible contacting pads and method for producing the electronic component
US6878901B2 (en) * 2001-02-12 2005-04-12 Morgan Miller Technologies Llc Laser micromachining and electrical structures formed thereby
US6617234B2 (en) * 2001-04-06 2003-09-09 United Microelectronics Corp. Method of forming metal fuse and bonding pad
US6605519B2 (en) * 2001-05-02 2003-08-12 Unaxis Usa, Inc. Method for thin film lift-off processes using lateral extended etching masks and device
US6652073B2 (en) * 2001-12-31 2003-11-25 Nanodynamics Inc. Structure of a flexible printed circuit for inkjet printheads and the manufacturing process therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200455170Y1 (en) * 2009-07-15 2011-08-23 히타치 덴센 가부시키가이샤 TBI tape for semiconductor device and manufacturing method thereof
US20120138968A1 (en) * 2010-12-07 2012-06-07 Na-Rae Shin Semiconductor package and display panel assembly having the same

Also Published As

Publication number Publication date
US7473459B2 (en) 2009-01-06
US20060251873A1 (en) 2006-11-09
TW200640311A (en) 2006-11-16
TWI333808B (en) 2010-11-21

Similar Documents

Publication Publication Date Title
TWI413461B (en) Method of manufacturing wiring board
JP4162583B2 (en) Printed wiring board and semiconductor device
US20060220242A1 (en) Method for producing flexible printed wiring board, and flexible printed wiring board
US20090101513A1 (en) Method of manufacturing a film printed circuit board
WO2009038950A2 (en) Flexible circuit board, manufacturing method thereof, and electronic device using the same
US20130313004A1 (en) Package substrate
US7005241B2 (en) Process for making circuit board or lead frame
JP3760731B2 (en) Bumped wiring circuit board and manufacturing method thereof
CN108811301B (en) Circuit board structure and manufacturing method thereof
US20070023877A1 (en) Chip on flex tape with dimension retention pattern
JP2005303172A (en) Wiring circuit substrate
JP2003282651A (en) Method of manufacturing flexible circuit substrate
US6800816B2 (en) Wiring circuit board having bumps and method of producing same
JP2004158725A (en) Film-carrier tape for mounting electronic component
JP2004095983A (en) Manufacturing method of printed wiring board
JP2008263026A (en) Cof wiring substrate and its manufacturing method
JP2002164390A (en) Tape carrier and its manufacturing method
WO2005027221A1 (en) Chip on flex tape with dimension retention pattern
JP4386827B2 (en) Method for manufacturing printed circuit board
JP3997629B2 (en) TAB film carrier tape with reinforcing sheet
JP2004087862A (en) Tape carrier for semiconductor device
US7413670B2 (en) Method for forming wiring on a substrate
JP4770884B2 (en) COF substrate and manufacturing method thereof
JP2009071066A (en) Chip on film (cof) wiring substrate and manufacturing method of the same
KR100447495B1 (en) circuit pattern of tape carrier type semiconductor package and the method of manufacturing the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION