US20090115047A1 - Robust multi-layer wiring elements and assemblies with embedded microelectronic elements - Google Patents
Robust multi-layer wiring elements and assemblies with embedded microelectronic elements Download PDFInfo
- Publication number
- US20090115047A1 US20090115047A1 US12/287,380 US28738008A US2009115047A1 US 20090115047 A1 US20090115047 A1 US 20090115047A1 US 28738008 A US28738008 A US 28738008A US 2009115047 A1 US2009115047 A1 US 2009115047A1
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- metal layer
- metal
- conductive protrusions
- dielectric layer
- conductive
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- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0361—Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0382—Continuously deformed conductors
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Abstract
Description
- This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/998,564, filed Oct. 10, 2007, entitled, “Robust Multi-Layer Wiring Elements And Assemblies With Embedded Microelectronic Elements,” the disclosure of which is hereby incorporated herein by reference.
- The subject matter of the present application relates to multi-layer wiring elements and their fabrication, such as used in the packaging of, or in the connection to micro-electronic elements, particularly semiconductor integrated circuits.
- The packaging of microelectronic elements, e.g., semiconductor integrated circuits continually poses new challenges. Processor chips pose particular challenges, due to the large area over which they typically extend, the great number of external contacts which typically are present as pinout at the external signal interface of the chip, and large fluctuations in temperature to which they are subject, because of high operating temperatures of processor chips. Moreover, the pitch and the size of the contacts of the chip are each becoming smaller as the number of external contacts of the chip increases.
- Surface mount technology including flip-chip interconnect technology, has been frequently used to interconnect such chips. Flip-chip interconnects can be formed quickly and reliably by holding a semiconductor chip with solder bumps thereon in contact with corresponding lands of a chip carrier and then heating the chip with the chip carrier to a point at which the solder bumps melt and form joints with the lands of the chip carrier. Often, solder bumps are used which contain a high-lead content solder. Among advantages of the high-lead solder is that it tends to yield to thermal and mechanical stresses within the package. Recently however, industry is trending away from use of high-lead content solder, or rather, towards increased use of lead-free solder. Currently, the future use of lead-containing solder is in question.
- Apart from the trend towards lead-free solders, the packaging of microelectronic chips poses significant challenges, particularly the reduction in pitch and size of contacts, high power density, and large area of certain chips such as processor chips.
- An interconnect element can include a dielectric layer having a top face and a bottom face remote from the top face. A first metal layer may define a plane extending along the bottom face and a second metal layer can extend along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces. A plurality of conductive protrusions can extend upwardly from the plane defined by the first metal layer through the dielectric layer. The conductive protrusions can have top surfaces at a first height above the first metal layer. The first height can be greater than 50% of a height of the dielectric layer above the first metal layer, for example. A plurality of conductive vias can extend from the top surfaces through openings in the dielectric layer to conductively connect the conductive protrusions with the second metal layer. At least one of the conductive vias can have a first width in contact with the top surface of the conductive protrusion. The first width can be less than a width of the top surface.
- An interconnect element can include a dielectric layer having a top face and a bottom face remote from the top face. A first metal layer can define a plane extending along the bottom face and a second metal layer can extend along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces. A plurality of conductive protrusions can extend upwardly from the plane defined by the first metal layer through the dielectric layer, and a plurality of plated features can extend through openings in the dielectric layer to conductively connect the conductive protrusions with the second metal layer.
- A packaged microelectronic element can include a dielectric layer having a top face and a bottom face remote from the top face. A first metal layer can define a plane extending along the bottom face and a second metal layer can extend along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces. A plurality of conductive protrusions can extend upwardly from the plane defined by the first metal layer through the dielectric layer and a microelectronic element disposed between the first and second wiring layers. The microelectronic element can have a contact-bearing face separated from the second metal layer by the dielectric layer. A plurality of plated features, can extend through openings in the dielectric layer to conductively connect the conductive protrusions and contacts of the microelectronic element with the second metal layer.
- A multiple wiring layer interconnect element having at least one of an active or passive component incorporated therein can include a dielectric layer having a top face and a bottom face remote from the top face. A first metal layer can define a plane extending along the bottom face and a second metal layer can extend along the top face. At least one of the first and second metal layers can include a plurality of conductive traces. A plurality of conductive protrusions can extend from the plane upwardly through the dielectric layer. The at least one of an active or passive component can be disposed between the first and second metal layers. The component can have a plurality of terminals confronting the second metal layer and separated from the second metal layer by the dielectric layer. A plurality of plated features can extend through openings in the dielectric layer to conductively connect the conductive protrusions and the terminals of the component with the second metal layer.
- A method of fabricating an interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer can include laminating a dielectric layer and a first metal layer atop the dielectric layer onto a base element. The base element can include, for example, a second metal layer having at least portions defining a plane and a plurality of conductive protrusions extending upwardly from the plane. Portions of the dielectric layer may separate adjacent ones of the conductive protrusions. The method can include forming openings in the dielectric layer which expose at least top surfaces of the conductive protrusions. A metal can be plated onto the exposed surfaces of the conductive protrusions within the openings to form plated features connecting the conductive protrusions with the first metal layer.
- A method of packaging a microelectronic element between wiring layers of an interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer can include laminating a dielectric layer and a first metal layer atop the dielectric layer onto a first element. The first element can include, for example, a second metal layer having at least portions defining a plane, a plurality of conductive protrusions extending upwardly from the plane and a microelectronic element having a first face adjacent to the plane. The step of laminating can be performed such that portions of the dielectric layer separate adjacent ones of the conductive protrusions and separate the microelectronic element from the conductive protrusions. The method can include forming openings in the dielectric layer which expose contacts at a second face of the microelectronic element and at least top surfaces of the conductive protrusions. The method can also include plating a metal onto the exposed contacts and exposed surfaces of the conductive protrusions within the openings to form plated features connecting the contacts and the conductive protrusions with the first metal layer.
- A method is provided in accordance with an embodiment for forming an interconnect element including at least one of an active or passive component between respective wiring layers of the interconnect element, wherein a plurality of wiring layers are separated from each other by at least one dielectric layer. A dielectric layer and a first metal layer atop the dielectric layer can be laminated onto a first element. The first element can include a second metal layer having at least portions defining a plane, a plurality of conductive protrusions extending upwardly from the plane and at least one of an active or passive component having a surface overlying the plane. The step of laminating can be performed such that portions of the dielectric layer separate adjacent ones of the conductive protrusions and the component from each other. Openings may be formed in the dielectric layer which can expose contacts of the component and at least top surfaces of the conductive protrusions. A metal may be plated onto the exposed contacts and exposed surfaces of the conductive protrusions within the openings to form plated features connecting the contacts and the conductive protrusions with the second metal layer.
- Further, in an embodiment of the present invention, the method as set forth herein can include after forming the plated features, patterning the first and second metal layers to form wiring patterns. Moreover, the third metal layer can fill the recesses to form solid conductive protrusions. Additionally, the third metal layer can coat the inner walls of the recesses to form hollow conductive protrusions. The conductive protrusions can include solid conductive protrusions. The hollow conductive protrusions can have continuous metal surfaces extending away from the plane.
- In an embodiment of the present invention, the first metal layer can include the planar portions and the hollow conductive protrusions can extend continuously away from the planar portions. The hollow conductive protrusions can have a frustoconical shape. The method as set forth herein can also include, after forming the plated features, patterning a fourth metal layer to form wiring patterns and after forming the second plated features, patterning the first and fourth metal layers to form wiring patterns.
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FIGS. 1( a) through 1(g) are sectional views illustrating stages in a method of fabricating a multi-layer wiring element such as a circuit panel having multiple layers of wiring patterns, in accordance with an embodiment of the invention. -
FIG. 2 is a plan view illustrating wiring patterns exposed at a face of a multi-layer wiring element fabricated in accordance with the method illustrated inFIGS. 1( a) through 1(f). -
FIG. 3( a) is a sectional view illustrating a particular example of a multi-layer wiring element fabricated in accordance with the embodiment illustrated inFIGS. 1( a) through 1(g). -
FIG. 3( b) is a plan view of a face of the multi-layer wiring element shown inFIG. 3( a). -
FIGS. 4( a) through 4(g) are sectional views illustrating stages in a method of fabricating a multi-layer wiring element in accordance with a variation of the embodiment illustrated inFIGS. 1( a)-(g). -
FIGS. 4( f)′ and 4(g)′ are sectional views illustrating stages in a variation of the method of fabricating a multi-layer wiring element illustrated inFIGS. 4( a)-(g). -
FIGS. 5( a) through 5(f) are sectional views illustrating stages in a method of fabricating a multi-layer wiring element in accordance with a variation of the embodiment illustrated inFIGS. 4( a)-(g). -
FIGS. 6( a) through 6(f) are sectional views illustrating stages in a method of fabricating a multi-layer wiring element in accordance with a variation of the embodiment illustrated inFIGS. 1( a)-(g). -
FIG. 7 is a sectional view illustrating a microelectronic assembly including a multi-layer wiring element having microelectronic elements and components incorporated therein in accordance with an embodiment of the invention. -
FIG. 8 is a sectional view illustrating a microelectronic assembly including a multi-layer wiring element having a microelectronic element and at least one of an active or passive component incorporated therein and a thermal conductor, in accordance with an embodiment of the invention. -
FIGS. 9( a) through 9(h) are sectional views illustrating stages in a method of fabricating a microelectronic assembly such as shown inFIG. 7 in accordance with an embodiment of the invention. -
FIG. 10 is a sectional view illustrating a microelectronic assembly having embedded components and a microelectronic device mounted thereto in accordance with an embodiment of the invention. -
FIG. 11 is a sectional view illustrating a microelectronic assembly having an embedded microelectronic element and components mounted thereto in accordance with an embodiment of the invention. -
FIG. 12 is a sectional view illustrating a microelectronic assembly having an embedded microelectronic element and embedded components in accordance with an embodiment of the invention. -
FIG. 13 is a sectional view illustrating a stacked arrangement including a plurality of microelectronic assemblies such as shown inFIG. 10 . -
FIG. 14 is a sectional view illustrating a stacked arrangement including a plurality of microelectronic assemblies such as shown inFIG. 12 . - As used in this disclosure, a feature such as a terminal, contact or pad which is “exposed at” a surface of a dielectric element may be flush with such surface; recessed relative to such surface; or protruding from such surface, so long as the feature is accessible for contact by a theoretical point moving towards the surface in a direction perpendicular to the surface.
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FIG. 1( a) throughFIG. 1( g) illustrate stages in a method of fabricating an interconnect element such as a multi-layer wiring element in accordance with an embodiment of the invention. As illustrated inFIG. 1( a), alayered metal structure 110 includes a relativelythin metal layer 102 having a thickness between about three and 25 micrometers (μm or “microns”) and athicker metal layer 104 having a thickness between about 30 microns and 200 microns. Typically, each of the metal layers 102, 104 has an exposedsurface thin metal layer 102 has a thickness of less than about 10 microns and thethicker metal layer 104 has a thickness between about 25 microns and 50 microns. In one embodiment, themetal layer 102 has an exposedsurface 102 a which defines a continuous plane. - An
intermediate layer 106 having a different composition from the twolayers metal layers intermediate layer 106 can be of such composition that it is not attacked by an etchant or etchants which attack either one or both of the metal layers 102, 104. In one embodiment, each of the twometal layers intermediate layer 106 includes or consists essentially of nickel. In such way, when an etchant which attacks copper is applied to one of the exposed faces 102 a, 104 a of the metal layers 102, 104, theintermediate layer 106 functions as an etch stop layer to prevent the etchant from penetrating beyond theintermediate layer 106 and possibly attacking the other one of the metal layers 102, 104 that is remote from the exposed face. - As illustrated in
FIG. 1( b), themetal layer 104 is patterned by lithography to form solid metal posts extending upwardly above themetal layer 102. Typically, the solid metal posts have aheight 115 which is about equal to the original thickness of themetal layer 104 above theintermediate layer 106. Each of the solid metal posts typically has aheight 115 which is at least about half adiameter 117 or width of each post, such that the height to width aspect ratio is about ½ or greater. However, in a particular embodiment, there is no requirement that the posts have a minimum aspect ratio. In a particular embodiment, the metal posts have frusto-conical or pyramidal shape. In another embodiment, the metal posts can have cylindrical shape. - In an example of forming the metal posts, a photoresist layer (not shown) can be deposited and developed to form mask
patterns overlying layer 104. The layeredmetal structure 110 can then be etched selectively with respect to theintermediate layer 106 to form theconductive posts 112. Such processing tends to form metal posts which have frusto-conical shape, whereinwalls 127 of the posts are sloped away from thetop surface 126. Subsequently, the intermediate layer can be removed where exposed between the conductive posts using a different etch process performed selectively with respect to the posts andmetal layer 102. Themetal layer 102 and the conductive posts extending upwardly therefrom form abase element 114 to which additional processing is applied in subsequent steps. - As illustrated in
FIG. 1( c), adielectric layer 116 and another relativelythin metal layer 118 atop the dielectric layer are now laminated to thebase element 114. Themetal layer 118 can be such as or similar to themetal layer 102 described above and can have an exposedsurface 118 a which defines a continuous plane. There are many different types of dielectric materials and processes which can be used to form the laminated structure. Lamination processes can also vary. For example, thedielectric layer 116 and themetal layer 118 can be laminated in one simultaneous step with the base element to form a laminated structure 120 (FIG. 1( d)) by applying heat and pressure with themetal layer 118,dielectric layer 116 andbase element 114 sandwiched between pressure-bearing plates of a press. In another example, thedielectric layer 116 can be first laminated to the base element, after which themetal layer 118 is laminated to an exposed surface of thedielectric layer 116 to form thestructure 120. In one particular embodiment, the material and characteristics of the dielectric layer and the type of lamination process can be selected such that lamination can be performed at a relatively low temperature of less than about 200° C. and with a relatively low pressure, such as less than 20 kilograms of force per square centimeter. - In such embodiment, in a particular example, the dielectric layer can include an uncured dielectric element such as commonly referred to as a “pre-preg”, such element containing a curable dielectric such as an epoxy among others, and an embedded glass cloth, for example. Curing of such dielectric element can occur as a result of the heat and pressure applied during a simultaneous lamination process when the dielectric layer is joined with the
base element 114 and theoverlying metal layer 118 or during subsequent treating. Such uncured dielectric layer can be selected for additional properties such as relatively low coefficient of thermal expansion (“CTE”), and relative rigidity, i.e., having a Young's modulus (modulus of elasticity) which is not very low. Desirably, peel strength of the dielectric layer should not be too low. - In embodiments where the
metal layer 118 is laminated sequentially after thedielectric layer 116 is laminated to the base element, thedielectric layer 116 may have a rough surface or smooth surface prior to lamination of themetal layer 118 thereto. The surface roughness of particular dielectric materials can vary widely. Certain dielectric materials such as particular pre-preg type layers can have a surface roughness ranging between about 500 nm and 700 nm prior to laminating the metal layer thereto. In a particular example of a sequential lamination process, adielectric layer 116 having a thickness of about 50 microns and characteristics such as described below can be laminated to the base element at a temperature of about 100° C. for 30 seconds with pressure of 7 kg/cm2 applied, then at 100° C. for 60 seconds with a pressure of 5.5 kg/cm2 applied thereto. A post lamination treatment known as “PET”, which may include chemical, laser or plasma treatment, may be applied to an exposedsurface 116 a of the dielectric layer at this time to help cure the dielectric layer or alter surface characteristics of the dielectric layer. A desmear process may be performed to remove smear from an exposedsurface 116 a of thedielectric layer 116 and to improve adhesion strength. Subsequently, themetal layer 118 having characteristics such as described above can be laminated to the structure including the base element and thedielectric layer 116 at a temperature held at about 120° C. for moderate time intervals, such as 30 to 60 seconds, with pressure of 7 kg/cm2 applied, and can be further treated by applying a temperature of about 120° C. to the dielectric layer for 90 seconds with a pressure of 5.5 kg/cm2 applied thereto. -
FIG. 1( d) illustrates the resultingstructure 120 after lamination of thedielectric layer 116 and themetal layer 118. At the temperature and pressure applied during lamination, portions 122 of thedielectric layer 116 may separate themetal posts 112 from themetal layer 118. The top surfaces 126 of themetal posts 112 can be separated from themetal layer 118 by distances up to a few tens of microns. In a particular example, where thethickness 119 of the dielectric layer is about 50 microns, the separation distance can range up to a value of somewhat less than 25 microns, such that the height 115 (FIG. 1( b)) of the metal posts 112 is greater than 50% of thethickness 119 of thedielectric layer 116. More typically, the separation distance between thetop surfaces 126 of themetal posts 112 and themetal layer 118 in such example is less than 20 microns, and can be significantly less than 15 microns. - Subsequently, as illustrated in
FIG. 1( e)-(f), processing is performed which connects themetal posts 112 with themetal layer 118. In one example, a laser ablation process such as laser drilling can be performed (FIG. 1( e)) to formholes 124 which extend through themetal layer 118 and the intervening portions of the dielectric layer to exposetop surfaces 126 of the metal posts. As examples, a focused beam from a YAG laser or CO2 laser is used to form the holes. In another example, theholes 124 can be formed by lithography in accordance with openings in a contact mask or photoresist mask (not shown) overlying themetal layer 118. Subsequently, as illustrated inFIG. 1( f),conductive connectors 128 are formed in theholes 124 which extend between at least thetop surfaces 126 of themetal posts 112 and themetal layer 118. Theconductive connectors 128 can also be referred to as micro-vias. In one example, theconductive connectors 128 are formed by plating a metal within the openings which then forms conductors which bridge the separation between theposts 112 and themetal layer 118. For example, the process can be performed by plating copper into the openings in contact withtop surfaces 126 of themetal posts 112 andmetal layer 118. During such process, themetal layer 102 andposts 112 or themetal layer 118 or all can serve as a plating electrode. The process may be performed via electroplating directly onto the exposedtop surfaces 126 of the metal posts or, alternatively, via electrolessly plating a seed layer, followed by electroplating. - Alternatively, the
conductive connectors 128 can be formed by other methods, such as, for example, screening or stenciling of a conductive matrix material, e.g., a conductive paste such as a metal-filled epoxy, solder paste, among many others, which is then cured by post-treatment. In another example, theconductive connectors 128 can be formed by vapor deposition, e.g., physical vapor deposition (sputtering), which may or may not be followed by subsequent plating. In yet another example, theconductive connectors 128 can be formed by introducing a fusible metal such as a solder, tin or eutectic composition into theholes 124 so as to wettop surfaces 126 of the metal posts 112. - As illustrated in
FIG. 1( f), thewidth 150 of each micro-via typically is less than theentire width 152 of themetal posts 112 at thetop surface 126. The area of the micro-via in contact with the top surface may actually be less than an area of thetop surface 126. In a particular embodiment, the maximum area of the hole in the dielectric layer in which the micro-via is formed can be smaller than the maximum area occupied by thepost 112 at theheight 115 of thepost 112 above the metal layer. - Processing or structural advantages may be realized when the
width 150 of the micro-via is less than thewidth 152 of thetop surface 126 of themetal post 112, or particularly, when the maximum area of thehole 124 in the dielectric layer is smaller than the area of themetal post 112 at the top surface. For example, if plating is used to form the micro-vias, less time may be needed to do so under such condition. Alternatively, if solder or a conductive matrix is included in the micro-via, better control may be attained over the amount of material needed to bridge the separation distance between the top surface of themetal post 112 and themetal layer 118. - Subsequently, the metal layers 102, 118 of the structure shown in
FIG. 1( f) can be patterned lithographically to form individual wiring patterns. A completedinterconnect element 130, illustrated inFIG. 1( d), includesconductive traces bottom surface 116 a and atop surface 116 b of thedielectric layer 116. Some of theconductive traces 132 exposed at thebottom surface 116 a conductively connect with some of the metal posts 112. Some of the metal posts, in turn, are conductively connected to some of thewiring patterns 134, e.g., conductive traces exposed at thetop surface 116 b through theconnectors 128. - As further illustrated in plan view (
FIG. 2 ), thewiring patterns 134 may form connections between a plurality of the metal posts through theconductive connectors 128. The wiring patterns may also include conductive mountingpads 136 available for attachment of other elements, e.g., active or passive devices or microelectronic elements thereto. The wiring patterns may also include ground or power transmission planes, various conductors or transmission line elements for maintaining ground or a power supply voltage or transmitting signals. In a particular embodiment, particular conductors of thewiring patterns FIG. 1( d)) of the dielectric layer. - While the diameter and height of each metal post can be the same as in the above-described embodiment, in a particular embodiment, the heights H1, H2 (
FIG. 3( a)) of the metal posts above a wiring layer can vary at different locations of the structure. As illustrated inFIG. 3( a), the height H1 ofpost 222 is significantly greater, e.g., several microns to tens of microns greater, than the height H2 ofpost 224. Moreover, the widths W1, W2 of the metal posts can also vary to significant degrees. The plated or otherwise-formedconductive connectors FIG. 3( a) overcome the differences in the heights and widths of themetal posts corresponding wiring patterns FIG. 3( b), a metal post can have an oblong or rectangular shape, having a length L1 greater than the width W1. - Several possible advantages can be realized in accordance with the embodiment of the invention described above. The amount of time required to fabricate a multi-layer wiring element as shown in
FIG. 1( g) can be reduced in comparison to the time required to fabricate other similar multi-layer wiring elements which do not have the above-describedconductive connectors 128. Costs of materials, manufacture or both may also be reduced. The method also permits wiring elements to be fabricated in which the sizes (horizontal dimensions and height) of metal posts therein can vary substantially. The wiring element can, in some cases, accommodate metal posts having different (small or large) pitches, as well. In addition, because the metal posts are solid, capacitance and inductance can be reduced in some cases in comparison to wiring elements having hollow or cylindrical plated metal features such as plated through holes for connecting the first and second metal layers. In addition, when solid metal posts are used, power consumption, current density and hence, electromigration can also be reduced, increasing the durability of the wiring element. - Several possible variations of the above process of forming a multi-layer wiring element are worth noting at this time. In one variation,
metal layer 102 can be patterned to form wiring patterns before themetal layer 104 is patterned to form the metal posts 112 (FIG. 1( b)). For example, themetal layer 102 can be patterned by lithography performed via selectively etchingmetal layer 102 with respect to theintermediate layer 106 used as an etch stop layer. Then, prior to etching the metal posts, the 110 structure with the wiring patterns defined therein can be attached temporarily to a carrier, which will remain in place until after theconductive connectors 128 are formed. During the lamination process, thedielectric layer 116 may fill spaces between adjacent wiring patterns such that the wiring patterns may become more similar to damascene (inlaid) wiring patterns having exposed surfaces which are flush with the exposed surface of the dielectric layer between adjacent wiring patterns. - In another variation of the above, the
metal layer 118 can have through holes pre-formed, e.g., pre-punched, pre-drilled, or pre-etched therein. During the lamination process (FIG. 1( c)), the pre-formed through holes of themetal layer 118 are aligned with theunderlying posts 112 such that upon forming the structure 120 (FIG. 1( d)), the portions 122 of the dielectric layer overlying theposts 112 are exposed within such holes. In a particular embodiment, prior to the lamination step illustrated inFIG. 1( c), themetal layer 118 may already be patterned into wiring patterns similar to thepatterns 134 illustrated inFIG. 1( g) and already be joined with thedielectric layer 116 when the lamination process (FIG. 1( c)) is performed. - In a further variation, the
dielectric layer 116 may also have holes pre-formed therein at the time the dielectric layer is laminated to thebase element 114. In a case where thedielectric layer 116 and theoverlying metal layer 118 both have holes pre-formed therein, a subsequent step of forming holes 124 (FIG. 1( e)) can be omitted. - In another variation, instead of forming the
posts 112 and wiring patterns by etching a layered metal structure 110 (FIG. 1( a)) selectively with respect to anintermediate layer 106, the metal posts are formed by etching from a top surface of a single, relatively thick, e.g., 25 to 50 microns thick metal layer via a timed etch in accordance with pre-defined mask patterns thereon. Subsequently, the wiring patterns are formed by a timed process of etching from a bottom surface of the same relatively thick metal layer. - In yet another variation, the
posts 112 can include or consist essentially of a conductive matrix material, e.g., a conductive paste, among others. In such case, theposts 112 can be formed, for example, by screening or stenciling onto themetal layer 102. In one embodiment, theposts 112 can be formed by screening or stenciling into openings in a sacrificial layer or mandrel, followed by removal of such sacrificial layer or mandrel to expose the posts. - Referring to
FIGS. 4( a) to 4(g), a method is provided for fabricating an interconnect element in accordance with another embodiment of the invention similar to that described above (FIGS. 1( a)-(g)).FIGS. 4( a)-(b) illustrate stages in processing which are the same as those shown and described above with respect toFIGS. 1( a)-(b) above or the above-described variations thereof. As illustrated inFIG. 1( c), a secondlayered metal structure 310 includes afirst metal layer 302, asecond metal layer 304 and anintermediate layer 306 between them. optionally, thesecond metal layer 304 can be thicker than thefirst metal layer 302. In one embodiment, the layeredmetal structure 310 has dimensions and properties similar to those of the above-described layered metal structure 110 (FIG. 1( a)). However, prior to the lamination step,metal layer 302 of thelayered structure 310 is patterned to formholes 308, such as by a masked etch performed selectively with respect to anintermediate layer 306 of the layered structure. In addition to having holes, themetal layer 302 may already be patterned to formindividual wiring patterns 334. - The second
layered metal structure 310 is positioned atop adielectric layer 316 which has properties similar to dielectric layer 116 (FIG. 1( c)) described above, and thestructure 310 then is laminated with thedielectric element 316 and thebase element 314 havingposts 312 protruding therefrom to form thestructure 320 illustrated inFIG. 4( d). - Subsequently, as illustrated in
FIG. 4( e), themetal layer 304 is patterned lithographically to formsecond metal posts 322 which protrude above thewiring patterns 334 overlying atop surface 316 a of thedielectric layer 316. After forming thesecond metal posts 322, the intermediate layer 306 (FIG. 4( c)) can be removed such that thewiring layer 302 is exposed above thetop surface 316 a of the dielectric layer. Referring toFIGS. 4( f) and 4(g), processing is then performed in a manner such as described above with respect toFIGS. 1( f) and 1(g) above, resulting in the structure havingsecond posts 322 protruding above thewiring patterns 334, as illustrated inFIG. 4( g). However, themetal layer 334 may not need to undergo patterning at this time, if individual wiring patterns have already been defined previously in accordance with the processing described above with respect toFIG. 4( c). - In a variation of the above embodiment shown in
FIGS. 4( f)′ and 4(g)′, the structure illustrated in 4(f) can have twoadditional metal layers 306′ and 304′ underlying thebottom surface 302 a of themetal wiring layer 302. These layers can remain from an initial layered structure (FIG. 4( a)) which contains five layers rather than the three shown therein. Thelayer 306′ is an intermediate layer andlayer 304′ is a relatively thick layer of a metal different from that of whichlayer 306′ essentially consists. Like layer 306 (FIG. 4( c)),layer 306′ functions as an etch stop layer when selectively etchinglayer 304′ in accordance with mask patterns (not shown) to formthird metal posts 342 which protrude downwardly from thebottom surface 302 a of themetal wiring patterns 332. After forming the third metal posts, exposed portions oflayer 306′ are removed and ametal layer 302′ (FIG. 4( f)′) is patterned by lithography to form the wiring patterns 332 (FIG. 4( g)′). - Alternatively to the processing illustrated in
FIGS. 4( f)′ and 4(g)′, third metal posts similar to the third metal posts 342 (FIG. 4( g)′) can be formed by plating a metal layer (not shown) within openings in a sacrificial mask layer such as a photoresist layer overlying themetal layer 302. The plated metal layer can be such as to fill the openings therein to form third metal posts which are solid, similar to themetal posts 342 illustrated inFIG. 4( g)′. -
FIGS. 5( a)-(f) illustrate a variation of the embodiment described above which results in formation of amulti-layer wiring element 450 having three wiringlayers metal posts conductive connectors FIG. 5( a)) havingsecond metal posts 422 exposed above asecond metal layer 418 has a structure such as that shown and described above with respect toFIG. 4( f). As illustrated inFIG. 5( b), asecond dielectric layer 426 and athird metal layer 440 are laminated to thebase element 414, such as by the process described above with reference toFIGS. 1( c) and 1(d). The third metal layer of the resulting laminated structure 420 (FIG. 5( c)) then is patterned to formholes 424 exposingtop surfaces 425 of the second metal posts 422. Subsequently, secondconductive connectors 438 are formed which connect thesecond metal posts 422 to the third wiring layer 440 (FIG. 5( e)), by processing such as described above (FIG. 1( f)) and the first and third wiring layers then can be patterned to formindividual wiring patterns -
FIGS. 6( a) through 6(f) illustrate a method of fabricating an interconnect element in accordance with yet another variation of the embodiment described above with reference toFIGS. 1( a) through 1(f). In this embodiment, thebase element 514 varies from the base element 114 (FIG. 1( c)) in that it includes ametal layer 502 havingplanar portions 504 which define a plane and a plurality ofhollow metal protrusions 512 which protrude upwardly from theplanar portions 504. The hollow metal protrusions may be provided as a metal layer which is integral with the metal layer of which theplanar portions 504 are formed, and may be formed, for example, by stamping or by plating a metal layer onto surfaces of a mandrel followed by removing the mandrel. Alternatively, thebase element 514 can include a plurality of metal layers, and the metal layers can each have the same thickness as other such metal layers or can have different thicknesses. - During processing such as illustrated in
FIGS. 6( a)-6(b) thebase element 514 may be attached to a temporary element such as a carrier for support or to protect the base element from corrosion or chemical attack, for example. In one embodiment, the base element consists essentially of copper. In another embodiment, the base element can include a plurality of layers of metal and themetal protrusions 512 can be of a different layer or layers of metal than the planar portions. Subsequently, in the steps illustrated with respect toFIGS. 6( b) through 6(f) processing such as that described above (FIGS. 1( c) through 1(g)) is performed to produce themulti-layer wiring element 550 as shown inFIG. 6( f). - In a variation of the embodiment illustrated in
FIGS. 6( a) through 6(f), theprotrusions 512 of themetal layer 502 can be filled with a conductive material, e.g., a plated metal layer, conductive paste, solder or other metallic material such that the final structure has filled conductive protrusions rather than hollow ones as illustrated inFIG. 6( f). -
FIG. 7 is a sectional view illustrating a packagedmicroelectronic assembly 700 in accordance with an embodiment of the invention. As illustrated therein, individualmicroelectronic elements microelectronic elements - The microelectronic elements are encapsulated within
dielectric layers assembly 700 also includesdielectric layers electric devices respective wiring layers other wiring layers FIG. 7 ,metal posts 712 andconductive connectors 728 extending upwardly therefrom provide conductive interconnection between adjacent wiring levels, such as, for example, betweenwiring layers other metal posts 722 and theconductive connectors 738 in contact therewith conductivelyinterconnect wiring layer 706 withwiring layer 708. - As illustrated in
FIG. 7 , it is not necessary that alldielectric layers thickness 714 ofdielectric layer 716 is less than thethickness 724 ofdielectric layer 726. The thicknesses may be different in order to accommodate devices or microelectronic elements which have different thicknesses. Although themicroelectronic elements 710 can be thinned prior to incorporation into theassembly 700, it may not be desirable to reduce the thickness of each microelectronic element to less than a few tens of microns, e.g., 50 microns, because of increased fragility. As further illustrated inFIG. 7 , themetal posts FIGS. 1( a) through 1(b) and 4(d) through 4(e). In such case,conductive connectors 738 within the thickerdielectric layer 724 may need to have greater height than theconductive connectors 728 within the thinnerdielectric layer 714.Conductive connectors 728′, having a construction and fabrication such as theconnectors 128 described above with reference toFIG. 1( f), conductively interconnect contacts of the electric devices with patterns of thewiring layer 706. Similarlyconnectors 738′ having such construction and fabricationconductively interconnect contacts 739 at a face of the microelectronic element to patterns of thewiring layer 702. In a particular embodiment, theconnectors 738′ have a height of between about 5 and 20 microns between an exposed surface of acontact 739 on the microelectronic element and the patterns of thewiring layer 702 to which they are connected. - A plurality of
external metal posts 762 protrude upwardly above atop surface 771 of theassembly 700. The metal posts 762 can be arranged in peripheral rows or in a grid pattern. Typically, theexternal metal posts 762 are arranged at a pitch which is more relaxed, i.e., having a greater value in microns than the pitch ofcontacts 739 exposed at the face of themicroelectronic element 720. Conductive interconnection can be provided to external elements, e.g., to a circuit panel or motherboard through the external metal posts 762. The top surfaces of theexternal metal posts 762 can be co-planar, the metal posts typically havinguniform height 766 from thetop surface 702 a of adielectric layer 756. Theexternal metal posts 762 may also haveuniform width 776 or may have varying widths. In one embodiment, theexternal metal posts 762 havegreater height 766 than aheight 768 ofmetal posts 722 within an interior of the assembly. Thewidth 776 of theexternal metal posts 762 may also be greater than awidth 778 of internal metal posts 722. In addition, the height to width aspect ratio of theexternal posts 762 may be different from such measure of the internal metal posts 722. - As further shown in
FIG. 7 , theexternal posts 762 may also include a wettableconductive layer 763 exposed at a surface thereof. For example, theexternal metal posts 762 may consist essentially of copper and have external wettable layers of nickel and gold (collectively shown as 763) joined thereto, such as by plating, sputtering, or other method.Top surfaces 765 of the metal posts are co-planar, in order to facilitate external interconnection to other elements (not shown). A cap layer or coating (not shown) of a fusible metal such as a solder, tin or a eutectic coating may further overlie an exposed surface of themetal post 762 or surface of suchwettable layer 763 when present. Conductive wettable pads may be exposed at one or more of the top and bottom surfaces or “faces” 770, 771 of the assembly. As illustrated,conductive pads 764, which can be wettable by a fusible metal such as solder, tin or a eutectic composition, are exposed at thebottom face 770 of the assembly. Conductive interconnection of theassembly 700 to one or more external elements such as a circuit panel, motherboard, discrete electric device or other element may be achieved through solder joints extending from theconductive pads 764 to corresponding contacts of such element. Alternatively, theconductive pads 764 can be conductively joined to other conductive elements through diffusion bonds, conductive adhesive, conductive paste or any other suitable method. Solder mask layers 772 and 773 may also overlie wiring layers 708, 701, respectively, with the caveat that themetal posts 762 andpads 764 remain uncovered by the solder mask layers. -
FIG. 8 illustrates a variation of the above embodiment (FIG. 7 ), wherein athermal conductor 880, e.g., a solid layer of metal such as copper or aluminum, underlies amicroelectronic element 810. Themicroelectronic element 810 may be attached to the thermal conductor through a thermallyconductive adhesive 814. Alternatively, the microelectronic element can be attached to the thermal conductor via a fusible metal such as a solder, eutectic composition or tin, such as when the thermal conductor includes a solid layer of copper. Copper has greater thermal conductivity than aluminum, making copper a suitable choice when high amounts of heat need to be conducted away from a chip having a high power density such as a processor chip, for example. -
FIGS. 9( a) through 9(h) are simplified views illustrating a method of fabricating amicroelectronic assembly 700 such as illustrated inFIG. 7 .FIG. 9( a) illustrates a stage in fabrication similar to that described above with reference toFIGS. 1( a)-(b) in which aconductive post 912 is formed overlying ametal layer 902. Thereafter, as illustrated inFIG. 9( b), an active orpassive component 946 or, alternatively, a microelectronic element such as element 720 (FIG. 7) is mounted to thewiring layer 902 through a die attach adhesive or other adhesive connecting a face, e.g., an inactive face, of such device to thewiring layer 902. - Thereafter, as illustrated in
FIG. 9( c), adielectric layer 916 and ametal layer 918 are laminated thereto such as through a process as described above with reference toFIG. 1( c). The metal layer then is patterned lithographically by an etching process which can be performed selectively with respect to the material exposed at asurface 916 a of thedielectric layer 916. In the resulting structure, shown inFIG. 1( d),second metal posts 922 protrude upwardly from the exposedsurface 916 a of thedielectric layer 916. - Next, as illustrated in
FIG. 9( e), holes 915 are patterned in thedielectric layer 916 in alignment with top surfaces ofposts 912 and withcontacts 914 of theelectric device 946. Various processes, such as described above with respect toFIG. 1( e) can be used to form theholes 915. - As further illustrated in
FIG. 9( f), a metal layer is formed by electroplating which at least coatsinner walls 927 of the holes and forms a continuous metal layer overlying atop surface 916 a of thedielectric layer 916 and themetal post 922. In one embodiment, the metal layer can consist essentially of copper. - Subsequently, as illustrated in
FIG. 9( g), the metal layer 902 (FIG. 9( a)) and metal layer 926 (FIG. 1( g)) are patterned lithographically to form wiring layers 902′, 926′ including individual conductive patterns, e.g., conductive traces, pads, other elements or combinations thereof. - As further shown in
FIG. 9( h), solder mask layers 972, 973 then are formed which partially cover the wiring layers 902′, 926′, leaving aconductive pad 964 andconductive post 922 exposed. The exposed metal features may then be subjected to additional processing such as steps for plating wettableconductive layers 963, such as nickel and gold in succession onto thepad 964 and theconductive post 922. - Various unit-level assemblies and higher-level assemblies can be realized in accordance with principles in accordance with the embodiments of the invention. For example, as illustrated in the sectional view of
FIG. 10 , amulti-layer wiring assembly 1000 can have a plurality ofpassive devices 1046 incorporated therein, similar to theelectric devices 746 shown and described above (FIG. 7 ). Amicroelectronic element 1020 can be externally connected, e.g., via wire-bonding or flip-chip mounting to contacts (not shown) exposed at an exposedface 1071 of theassembly 1000. Conductive interconnection to a circuit panel, e.g.,wiring board 1080 can be established throughexternal metal posts 1062 andsolder masses 1066 joined thereto. - In another variation, the microelectronic element 1120 (
FIG. 11 ) can be incorporated within themulti-layer wiring assembly 1100, and the electric devices, e.g.,passive devices 1146 be mounted to contacts at aface 1171 of the assembly. - In yet another variation, both the
microelectronic element 1220 andelectric devices 1246 are incorporated within themulti-layer wiring assembly 1200. In the particular embodiment shown, theelectric devices 1246 are positioned between themicroelectronic element 1220 and an external conductive interface provided byexternal metal posts 1262. Alternatively, themicroelectronic element 1220 can be disposed between theexternal metal posts 1262 and theelectric devices 1246. In another alternative, the electric devices can be disposed adjacent to anedge 1224 of the microelectronic element. -
FIG. 13 illustrates a higher level assembly in which a plurality ofmulti-layer wiring assemblies FIG. 10 ), withmicroelectronic elements 1320 joined to exterior surfaces thereof, are connected together in a stacked arrangement. In such arrangement, the externalconductive posts microelectronic elements conductive posts solder masses 1366 to conductive pads (not shown) exposed atfaces 1370 of theadjacent assembly -
FIG. 14 illustrates a different arrangement which includes a plurality of conductively connected stackedmulti-layer wiring assemblies 1400, 1400 a and 1400 b, each having microelectronic elements and electric devices incorporated therein, similar toassembly 1200 shown inFIG. 12 . In this case, theexternal metal posts 1462 can be arranged in an area grid array for connection throughsolder masses 1466 to corresponding conductive pads (not shown) exposed at aface 1470 of eachassembly 1400. - Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention.
Claims (42)
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US15/282,255 US10032646B2 (en) | 2007-10-10 | 2016-09-30 | Robust multi-layer wiring elements and assemblies with embedded microelectronic elements |
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US12/287,380 US20090115047A1 (en) | 2007-10-10 | 2008-10-08 | Robust multi-layer wiring elements and assemblies with embedded microelectronic elements |
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KR20100086472A (en) | 2010-07-30 |
JP2011501410A (en) | 2011-01-06 |
WO2009048604A2 (en) | 2009-04-16 |
EP2213148A2 (en) | 2010-08-04 |
WO2009048604A3 (en) | 2009-09-24 |
US10032646B2 (en) | 2018-07-24 |
KR101572600B1 (en) | 2015-11-27 |
EP2213148A4 (en) | 2011-09-07 |
US20170018440A1 (en) | 2017-01-19 |
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