US20090153377A1

US20090153377A1 - Time to digital converter with error protection

Info

Publication number: US20090153377A1
Application number: US12/372,841
Authority: US
Inventors: Hsiang-Hui Chang
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2007-10-16
Filing date: 2009-02-18
Publication date: 2009-06-18
Also published as: US7728686B2; CN102739244A; TWI380594B; US20090096537A1; TW200919972A; TWI363499B; US8429487B2; TW200919976A; TW200919974A; US20090096535A1; CN102611443A; US20110099450A1; CN102739244B; US8228128B2; US20090096538A1; US8395453B2; US8031007B2; CN102651648B; TW200922150A; US7791428B2

Abstract

Time to digital converters (TDCs) with high resolution are disclosed. The TDC includes a first time to digital converting module, a selection and time amplifying module, a second time to digital converting module and a decoder, and is applied in estimating a time difference between a first signal and a second signal. As the delay time of the delay units of the time to digital converting modules is the unit of the time difference measurement, the first and second time to digital converting modules are responsible for the integral portion and the fractional portion of the estimated time difference, respectively. Moreover, by introducing the normalization process, the linearity of the converting characteristic of the TDC can be improved; by adding an error detection circuit to the TDC, the possible metastable problem can be prevented.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. utility application Ser. No. 12/235,624, filed on Sep. 23, 2008, entitled “Error Protection Method, TDC module, CTDC Module, All-Digital Phase-Locked Loop, and Calibration Method thereof” and claiming the priority of U.S. Provisional Applications No. 60/980,172 filed on Oct. 16, 2007 and 60/980,461 filed on Oct. 17, 2007, the entirety of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to time to digital converters (TDCs), and in particular relates to high resolution TDCs.
2. Description of the Related Art
FIG. 1A illustrates a conventional time to digital converter (TDC), which estimates the time difference between a first signal A and a second signal B. The conventional TDC comprises a time to digital converting module 102 and a decoder 104. The time to digital converting module 102 comprises a plurality of delay units DU₁˜DU₄and a D-Flip-Flops array 106. The first signal A is sequentially delayed by the delay units DU₁˜DU₄, and a plurality of delayed first signals A₁˜A₄are generated and sent to the D-Flip-Flops array 106. The D-Flip-Flops array 106 is triggered by the second signal B to read out the states of the delayed first signals A₁˜A₄(i.e. to read out whether the delayed first signals A₁˜A₄are at the high voltage levels or low voltage levels). Digital data data_D[0:3], showing the states of A₁˜A₄, are sent to the decoder 104 to be decoded. The output 108 of the decoder 104 is the estimated time difference between the first and second signals A and B.
FIG. 1B uses waveforms to show the functions of the TDC of FIG. 1A. Each delay unit (DU₁, DU₂. . . or DU₄) delays the input signal by a unit delay time T. When the second signal B rises from low to high, the D-Flip-Flops array 106 is triggered to read out the states of the delayed first signals A₁˜A₄. In this case, the digital data data_D[0:3] are [1, 0, 0, 0]. The decoder 104 decodes the digital data [1, 0, 0, 0] as 1, which means that the estimated time difference between the signals A and B is greater than one unit delay time T and smaller than two unit delay time 2T. This structure of FIG. 1A limits the estimation resolution to the unit delay time T and is incapable of estimating the fraction part. The output of the decoder 104 is an integer multiple of unit delay time T.
Since the value of the unit delay time T is mainly dependent on the manufacturing process of the delay units DU₁˜DU₄, it is difficult to improve the estimation resolution of the conventional TDCs. Thus, novel TDC architectures with higher resolution are called for.

BRIEF SUMMARY OF THE INVENTION

The invention discloses time to digital converters. According to one embodiment, the time to digital converter comprises a first time to digital converting module, a selection and time-amplifying module, a second time to digital converting module and a decoder. The first time to digital converting module delays a first signal to generate a plurality of delayed first signals, and reads out the states of the delayed first signals according to a second signal. The read-out states form first digital data. The selection and time-amplifying module determines the first zero bit of the first digital data and then selects and stretches the corresponding delayed first signal. The stretched result is outputted by the selection and time-amplifying module as a first reference signal. In additional to outputting the first reference signal, the selection and time-amplifying module further stretches the second signal along the time axis and outputs the stretched second signal. The second time to digital converting module delays the stretched second signal to generate a plurality of delayed and stretched second signals, and reads out the states of the delayed and stretched second signals according to the first reference signal to generate second digital data. The first and second digital data are sent to the decoder to be decoded for estimating a time difference between the first and second signals.
A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1A illustrates a conventional TDC;

FIG. 1B shows waveforms to explain the functions of the TDC of FIG. 1A;

FIG. 2A illustrates a TDC of the invention;

FIG. 2B-2D show waveforms to explain the functions of the TDC of FIG. 2A;

FIG. 3A illustrates another embodiment of the TDC of the invention;

FIG. 3B shows waveforms to explain the functions of the TDC of FIG. 3A;

FIG. 4 shows waveforms to explain the effect of a metastable problem; and

FIG. 5 illustrates another embodiment of the TDC of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description shows the embodiments of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 2A illustrates an embodiment of the time to digital converter of the invention, which estimates a time difference between a first signal A and a second signal B. The time to digital converter comprises a first time to digital converting module 202, a selection and time-amplifying module 204, a second time to digital converting module 206 and a decoder 208. In this embodiment, the first time to digital converting module 202 comprises a plurality of delay units DU₁˜DU₄and a D-Flip-Flops array 210. The delay units DU₁˜DU₄are coupled in series to delay the first signal A to generate a plurality of delayed first signals A₁˜A₄. The D-Flip-Flops array 210 is triggered by the second signal B to read out the states of the delayed first signals A₁˜A₄(e.g. to read out whether the delayed first signals A₁˜A₄are at the high voltage levels or low voltage levels when the D-Flip-Flops array 210 is triggered), wherein the read-out states are shown by first digital data data_D[0:3]. In this embodiment, the selection and time-amplifying module 204 comprises a plurality of time amplifiers TA₁˜TA₅and a selection circuit 212. The time amplifiers TA₁˜TA₅stretches (or enlarges the width of) the delayed first signals A₁˜A₄and the second signal B along the time axis, respectively, to generate stretched and delayed first signals SA₁˜SA₄and a stretched second signal SB. FIG. 2B depicts the waveforms of the first signal A, the delayed first signals A₁˜A₄and the stretched and delayed first signals SA₁˜SA₄. The first signal A is sequentially delayed by a time delay T to generates the delayed first signals A₁˜A₄. The delayed first signals A₁˜A₄are stretched by M times as shown in FIG. 2B. FIG. 2C depicts the waveforms of the second signal B and the stretched second signals SB. As shown in FIG. 2C, after being stretched by the time amplifier TA₅the second signal B is stretched to the stretched second signal SB and time width t_ris amplified by M times, M t_r. The selection circuit 212 receives the first digital data data_D[0:3], finds out the first logic ‘0’ thereof to determine it as a first zero bit, and selects the corresponding stretched and delayed first signal (selected from the delayed and stretched first signals SA₁, SA₂. . . or SA₄according to the first zero bit) as a first reference signal 214. In the second time to digital converting module 206, the stretched second signal SB is delayed and a plurality of delayed and stretched second signals SB₁˜SB₄are generated. The first reference signal 214 is sent to the second time to digital converting module 206 to trigger the D-Flip-Flops array 216 to read out the states of the delayed and stretched second signals SB₁˜SB₄. The second digital data data_F[0:3] representing the read-out states are generated. The decoder 208 decodes the first and second digital data data_D[0:3] and data_F[0:3] to get decoded values D and F. With proper calculations, the decoder 208 outputs an output digital signal 218 representing the estimated time difference between the first and second signals A and B.
Please note that the number of the delay units DU in the first and second time to digital converting modules 202 and 206 and the number of the time amplifiers TA in the selection and time-amplifying module 204 shown in this embodiment are for illustrative purpose only. The numbers and configurations of the delay units DU and the time amplifiers TA can be modified according to circuit requirements.
Using the delay time T of the delay units adopted in the time to digital converting modules 202 and 206 as a unit of estimating the time difference between the first and the second signals A and B, the decoded values D and F relate to the integral and fractional portions of the estimated time difference, respectively. When the time amplifiers TA₁˜TA₅stretch their input signals along the time axis by M times, the decoder 208 executes a calculation of DT+(1−F/M)T to estimate the time difference between the first and second signals A and B.
For further explain the operation of the TDC shown in FIG. 2A, the first and second signals A and B of FIG. 1B are taken as an example. The first time to digital converting module 202 works similar to the time to digital converting module 102 and outputs [1,0,0,0] as the first digital data data_D[0:3]. The selection circuit 212 identifies that the first logic ‘0’ in data_D[0:3] is located at the second bit, and then determines that the second bit is the first zero bit of data_D[0:3]. In other words, the transition of the second signal B occurs between the transition of the delayed first signal A₁and the transition of the delayed first signal A₂. Based on the identifying result, the selection circuit 212 selects the stretched and delayed first signal SA₂as the first reference signal 214. FIG. 2D shows the waveforms of the stretched second signal SB, the delayed and stretched second signals SB₁˜SB₄, and the first reference signal 214 (SA₂). The first reference signal 214 (SA₂) triggers the D-Flip-Flops array 216 to read out the states of the delayed and stretched second signals SB₁˜SB₄to get the second digital data data_F[0:3]. In the case shown in the FIG. 2D, data_F[0:3]=[1,0,0,0].
The decoder 208 decodes the first digital data data_D[0:3] (=[1,0,0,0]) and the second digital data data_F[0:3] (=[1,0,0,0]) as 1 (D=1) and 1 (F=1), respectively, and then performs a calculation of DT+(1−F/M)T. The calculated result is 1 T+(1−½)T=1.5 T. Compared with the conventional TDC shown in FIG. 1A, the TDC shown in FIG. 2A not only estimates the integral portion of the time difference between the first and second signals A and B, further estimates the fractional portion thereof. The invention provides TDCs with higher resolution.
FIG. 3A illustrates another embodiment of the invention. Compared with the embodiment of FIG. 2A, the selection and time-amplifying module and the second time to digital converting module are replaced by modules 312 and 314, respectively. In the selection and time-amplifying module 312, the selection circuit 302 further selects another signal from the stretched and delayed first signals (SA₁-SA₄) to output as a second reference signal 304. Generally, the second reference signal 304 follows the first reference signal 214 and leads the other stretched and delayed first signals that lags the first reference signal 214. In addition to the first reference signal 214, the D-Flip-Flops array 306 is further trigger by the second reference signal 304 to read out the states of the stretched and delayed second signals SB₁˜SB₄. The read-out states are the third digital data data_N[0:3]. Compared to the decoder 208, the decoder 308 further decodes the third digital data data_N[0:3] to get a decoded value N. The difference between the decoded values N and F is (N−F) and is used in normalizing the decoded value F. With proper calculations, the decoder 308 outputs the estimated time difference between the first and second signals A and B by the output signal 310.
Using the delay time T of the delay units adopted in the time to digital converting modules 202 and 314 as a unit of estimating the time difference between the first and the second signals A and B, the decoded value D relates to the integral portion of the estimated time difference, and the decoded values F and N relate to the fractional portion of the estimated time difference. To estimate the time difference between the first and second signals A and B, the decoder 308 executes a calculation of DT+(1−F/(N−F))T, or DT+(1−F/Avg(N−F))T. Avg(.) represents an average operation, which accumulates the calculated (N−F) and averages them.
Referring to the aforementioned case, the stretched and delayed first signal that follows the first reference signal (SA₂) is SA₃. The selection circuit 302 therefore selects SA₃as the second reference signal 304. Compared to FIG. 2B, FIG. 3B further shows the waveform of SA₃. The second reference signal (SA₃) triggers the D-Flip-Flops array 306 to read out the states of the delayed and stretched second signals SB₁˜SB₄to get the third digital data data_N[0:3]. As shown in the figure, data_N[0:3]=[1,1,1,0].
In addition to getting the decoded values D=1 and F=1, the decoder 308 further decodes the third digital data data_N[0:3] as 3 (N=3), and then performs a calculation of DT+(1−F/(N−F))T. The calculated result is 1 T+(1−1/(3−1))T=1.5 T. Compared with the conventional TDC shown in FIG. 1A, the TDC shown in FIG. 3A not only estimates the integral portion of the time difference between the first and second signals A and B, further estimates the fractional portion thereof. This exemplary embodiment provides TDCs with higher resolution.
In some cases, because of metastable, the D-Flip-Flops array 210 may not correctly identify the states of the delayed first signals A₁-A₄and output incorrect first digital data data_D[0:3]. In the case that the first and second signals A and B are those shown in FIG. 1B, resulting in close waveforms of the second signal B and the delay first signal A₁, the metastable may cause the D-FlipFlops array 210 to output incorrect digital data [0,0,0,0] instead of the correct digital data [1,0,0,0]. The incorrect digital data causes the selection circuit 302 to output incorrect reference signals 214 and 304 to trigger the D-Flip-Flops array 306 of the second time to the digital converting module 314. In the case that the incorrect first digital data data_D[0:3] are [0,0,0,0], the selection circuit 302 wrongly selects SA₁and SA₂as the first and second reference signals 214 and 304. FIG. 4 shows the waveforms of the stretched second signal SB, the stretched and delayed second signals SB₁-SB₄, and the wrongly selected reference signals SA₁and SA₂. As shown in the figure, the second digital data data_F[0:3]=[0,0,0,0] and the third digital data data_N[0:3]=[1,0,0,0]. The decoder 308 decodes the digital data data_D[0:3], data_F[0:3] and data_N[0:3] and gets the decoded values D=0, F=0 and N=1, respectively, and then executes the calculation, DT+(1−F/(N−F))T, or DT+(1−F/Avg(N−F))T, to calculate the time difference between first and second signal A and B. The calculated result is 1 T. Compared with the aforementioned normal result, 1.5 T, the operation of the TDC is affected by the metastable problem.
As such, to overcome the metastable problem, the invention further discloses TDCs with error protection. FIG. 5 shows an embodiment of the TDC with error protection. Compared with FIG. 3A, the TDC of FIG. 5 further comprises an error detector 502, which detects the phases of the first reference signal 214 and the stretched second signal SB. As shown in FIG. 4, when the metastable occurs, the incorrect first reference signal (SA₁) leads the stretched second signal SB, which results in zero F[0:3]. Note that in a normal operation without metastable, the first reference signal 214 must lag the stretched second signal SB. The error detection 502 outputs an error protection enable signal 504 to the decoder 506 when detecting that the first reference signal 214 leads the stretched second signal SB. When receiving the error protection enable signal 504, the decoder 506 executes a calculation of DT+(1−N/avg_pre)T+1 T to replace the original calculation DT+(1−F/(N−F))T or DT+(1−F/Avg(N−F))T. avg_pre represents the previous value of Avg(N−F). The current value of (N−F) is abandoned.
Referring to the case shown in FIG. 4, the error detector 502 detects that the first reference signal (SA₁) is leading the stretched second signal SB and then outputs the error protection enable signal 504 to enable the decoder 506 to perform a calculation of DT+(1−N/avg_pre)T+1 T. In the case that avg_pre is 2, the calculated result is 0 T+(1−½)T+1 T=1.5 T since the decoded values D=0 and N=1. Thus, solving the matastable problem.
The decoders of the invention may realize the aforementioned calculations by software or hardware.
The structures of the selection and time-amplifying modules 204 and 312 are not used to limit the scope of the invention, and may be replaced by other circuits capable of outputting the reference signals (such as the signal 214 or signals 214 and 304) and the stretched second signal SB. In some embodiments, the selection circuit may be placed prior to the timing amplifiers TA₁˜TA₄to first select from the delayed first signals A₁˜A₄, and then stretch the selected signal along the time axis.
The structures of the time to digital converting modules 202 is not used to limit the scope of the invention, and other circuits capable of producing a plurality of delayed first signals and outputting a first digital data representing the time difference between the first and second signals, can be applied to replace the module 202. Furthermore, the second time to digital converting modules 206 and 314 can be replaced by any circuit with the same functions.
To conclude, the first time to digital converting module 202 may be regarded as a coarse converter, while the second time to digital converting module 206 (or 314) may be regarded as a fine converter. For example, the first time to digital converting module 202 compares at least a first signal A and a second signal B to generate first digital data data_D[0:3] representing a first portion (e.g. the integer part) of the phase/time difference between the first and second signals; the selection and time-amplifying module 204 (or 312) stretches (or magnifies) a second portion (e.g. the fractional part) of the phase/time difference between the first and second signals A and B to a degree that the second time to digital converting module 206 (or 314) can process; and the second time to digital converting module 206 (or 314) then compares the stretched second portion 214 with at least one stretched signal (SB₁˜SB₄in above embodiment) corresponding to at least one of the first signal A and the second signal B to generate second digital data data_F[0:3] representing the second portion of the difference between the first and second signals. In this way, the resolution of the TDC can be improved. Moreover, by introducing the normalization process, the linearity of the converting characteristic of the TDC can be improved; by adding the error detection circuit 502, the possible metastable problem can be prevented.
Moreover, when the time to digital converters of above embodiments are implemented in a phase lock loop (PLL) circuit, the high resolution property of the time to digital converter can benefit the PLL to have small phase noise.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A time to digital converter, comprising:

a first time to digital converting module, for delaying a first signal to generate a plurality of delayed first signals and reading out states of the delayed first signals according to a second signal to generate first digital data;

a selection and time-amplifying module, for selecting a first specific delayed first signal from the plurality of delayed first signals, stretching the first specific delayed first signal along the time axis to generate a first reference signal, and stretching the second signal along the time axis;

a second time to digital converting module, for delaying the stretched second signal to generate a plurality of delayed and stretched second signals, and reading out states of the delayed and stretched second signals according to the first reference signal to generate second digital data; and

a decoder, for decoding at least the first and second digital data to generate an estimation of a time difference between the first and second signals.

2. The time to digital converter as claimed in claim 1, wherein the selection and time-amplifying module further finds out a first zero bit in the first digital data, and selects the first specific delayed first signal according to the first zero bit.

3. The time to digital converter as claimed in claim 1, wherein the selection and time-amplifying module further selects and stretches a second specific delayed first signal from the plurality of delayed first signals to generate a second reference signal, and the second specific delayed first signal lags the first specific delayed signal by a delay time.

4. The time to digital converter as claimed in claim 3, wherein the second time to digital converting module further reads out states of the delayed and stretched second signals according to the second reference signal to generate third digital data.

5. The time to digital converter as claimed in claim 4, wherein the decoder further decodes the third digital data and generates the estimation of the time difference between the first and second signals by performing a first calculation on the decoded first, second and third digital data.

6. The time to digital converter as claimed in claim 5, further comprising an error detector, for detecting phases of the first reference signal and the stretched second signal and outputting an error protection enable signal to the decoder when the stretched second signal lags the first reference signal.

7. The time to digital converter as claimed in claim 6, wherein the decoder is switched to perform a second calculation to generate the estimation when receiving the error protection enable signal.

8. The time to digital converter as claimed in claim 7, wherein the second calculation utilizes previous decoded second digital data and previous decoded third data rather than the decoded second digital data and decoded third data to generate the estimation.

9. A time to digital converter, comprising:

a first time to digital converting module, for delaying a first signal to generate a plurality of delayed first signals, and reading out states of the delayed first signals according to a second signal to generate first digital data;

a selection and time-amplifying module, for stretching the delayed first signals and the second signal along a time axis to generate a plurality of stretched and delayed first signals and a stretched second signal, and selecting one stretched and delayed first signal from the plurality of stretched and delayed first signals as a first reference signal according to the first digital data;

10. The time to digital converter as claimed in claim 9, wherein the first reference signal lags the stretched second signal and leads the other stretched and delayed first signals that lags the stretched second signal.

11. The time to digital converter as claimed in claim 9, wherein the selection and time-amplifying module further selects another stretched and delayed first signal from the plurality of stretched and delayed first signals as a second reference signal, wherein the second reference signal lags the first reference signal and leads the other stretched and delayed first signals that lags the first reference signal.

12. The time to digital converter as claimed in claim 11, wherein the second time to digital converting module further reads out states of the delayed and stretched second signals according to the second reference signal to generate third digital data.

13. The time to digital converter as claimed in claim 12, wherein the decoder further decodes the third digital data, and calculates the difference between the decoded second and third digital data to normalize the decoded second digital data.

14. A time to digital converter, comprising:

a first time to digital converting module, for comparing at least a first signal and a second signal to generate first digital data representing a first portion of a difference between the first and second signals;

a time-amplifying module, for stretching a second portion of the difference between the first and second signals to generate a stretched second portion;

a second time to digital converting module, for comparing the stretched second portion with at least one stretched signal corresponding to at least one of the first signal and the second signal to generate second digital data representing the second portion of the difference between the first and second signals; and

15. The time to digital converter as claimed in claim 14, wherein the first portion corresponds to integer part of the difference, and the second portion corresponds to fractional part of the difference.

16. The time to digital converter as claimed in claim 14, further comprising an error detector, for detecting error of the time-amplifying module and outputting an error protection enable signal to the decoder when the error is detected.

17. The time to digital converter as claimed in claim 16, wherein the decoder decodes the first and second digital data by performing a first calculation scheme when the error protection enable signal is not received, and is switched to perform a second calculation scheme different from the first calculation scheme when receiving the error protection enable signal.

18. The time to digital converter as claimed in claim 14, wherein the decoder further normalizes the second digital data before generating the estimation of the time difference between the first and second signals.