US20090165706A1 - Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer - Google Patents

Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer Download PDF

Info

Publication number
US20090165706A1
US20090165706A1 US12/397,169 US39716909A US2009165706A1 US 20090165706 A1 US20090165706 A1 US 20090165706A1 US 39716909 A US39716909 A US 39716909A US 2009165706 A1 US2009165706 A1 US 2009165706A1
Authority
US
United States
Prior art keywords
insulating layer
metal
forming
metal lines
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/397,169
Inventor
June Woo Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Priority to US12/397,169 priority Critical patent/US20090165706A1/en
Assigned to DONGBU ELECTRONICS CO., LTD. reassignment DONGBU ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, JUNE WOO
Publication of US20090165706A1 publication Critical patent/US20090165706A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Definitions

  • the present invention generally relates to a metallization method of a semiconductor device, and particularly to a method for forming a plurality of metal lines on a semiconductor substrate using a dual insulating layer.
  • metal interconnecting lines need to be designed to have a low electric resistivity.
  • the electric resistivity is proportional to the width and height of the metal line, and inversely proportional to length thereof.
  • the height of the metal line, as well as the width thereof, should be reduced to a minimum.
  • the height and width have a critical value in view of limitations of the metal line formation process. Therefore, an aspect ratio (i.e., a ratio of height-to-diameter) of the gaps between the metal lines, which may be filled with an insulating material, is increased according to the miniaturization of the devices.
  • low resistivity metals such as aluminum, copper and their alloys have been widely used as fine metal lines in semiconductor manufacturing.
  • aluminum alloyed with copper of about 1 ⁇ 4 wt % is used for the fine metal line, which is resistant to electromigration.
  • the aluminum metal line is generally formed by a physical vapor deposition (PVD) process, also known as a sputtering process, which involves the steps of: depositing a metal thin film on a substrate; etching the metal thin film to form metal lines; and filling gaps between the metal lines with an insulating material.
  • PVD physical vapor deposition
  • One approach is to utilize a damascene method, but it may incur increase of electric resistivity of the metal line owing to the diffusion of chemical impurities.
  • Another approach is to employ an aluminum gap-fill process using chemical vapor deposition (CVD), but this may lead to reliability problems including electromigration.
  • CVD chemical vapor deposition
  • Korean Patent Publication No. 10-2003-005600 discloses a multilayered metallization structure with a barrier metal layer.
  • the barrier metal layer is formed on an upper surface and sidewall of an insulating layer and a contact plug is formed to interconnect with an underlying metal line in a bottom portion of the insulating layer.
  • This metallization structure can reduce the electric resistivity of metal lines, because the insulating layer is disposed between metal lines. Yet, it is difficult for metal to fill a high aspect ratio of the gaps present in the insulating layer.
  • an object of the present invention to provide a method for forming a plurality of metal lines in a semiconductor device using a dual insulating layer.
  • the metal deposition can be easily performed without gap-fill problems, even by a PVD sputtering process generally known as having inferior step coverage.
  • an embodiment of a method for forming a plurality of metal lines in a semiconductor device includes: (a) forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced to each other; (b) depositing a metal layer on and between the first insulating layer patterns; (c) planarizing the metal layer; (d) patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and (e) forming a second insulating layer on and between the metal lines.
  • FIGS. 1A to 1H are cross-sectional views of a semiconductor substrate, illustrating an embodiment of a method for forming metal lines in a semiconductor device, according to the present invention.
  • the present invention utilizes a couple of insulating layers to reduce an aspect ratio of gaps into which metal lines may be deposited. It should be understood that the techniques and resulting structures are not limited to using any specific substrates and dielectric or insulating overlays. Moreover, the present invention is not restricted to any particular metal or metal alloys. Hereinafter, an exemplary embodiment of the present invention will be described in detail, with reference to FIGS. 1A to 1H .
  • a first insulating layer 110 is formed on a semiconductor substrate 100 .
  • a thickness or height of the first insulating layer 110 is from about 1 ⁇ 3 to about 2 ⁇ 3 of that of a resulting metal line (see a metal line 130 in FIG. 1E ) that may be formed in the subsequent steps.
  • the first insulating layer 110 is patterned to form insulating layer patterns 110 a by a photolithography and etch processes, as shown in FIG. 1B .
  • metal material 120 such as aluminum is deposited over the entire substrate, filling gaps between the insulating layer patterns 110 a , as shown in FIG. 1C .
  • the deposition of the metal material 120 preferably aluminum, is performed by a PVD sputtering process.
  • the metal material 120 is deposited thicker than the resulting metal line 130 , sufficiently covering the insulating layer patterns 110 a . Since the insulating layer patterns 110 a are formed to be much lower than the resulting metal line 130 , the gaps between the insulating layer patterns 110 a may have a relatively low aspect ratio. As a result, a PVD-Al layer 120 can fill the gaps without gap-fill issues such as voids.
  • the metal layer 120 is continuously planarized via chemical-mechanical polishing (CMP) or an etch-back process until it has a desired thickness or height.
  • CMP chemical-mechanical polishing
  • the planarized metal layer 120 is patterned to form metal lines 130 by a photolithography and etching processes using a photo mask.
  • the photo mask defines openings over regions in which the insulating layer patterns 110 a are formed. Namely, portions of the metal layer 120 over the insulating layer patterns 110 a may be removed. In this case, the etching process is controlled to expose upper surfaces of each of insulating layer patterns 110 a.
  • a second insulating layer 140 is formed over the entire substrate 100 , thus covering the metal lines 130 and filling gaps between the metal lines 130 .
  • the gaps between the metal lines 130 in which the first insulating layer patterns 110 a remains, may have a relatively low aspect ratio.
  • the gap filling with the second insulating material is performed by high-density plasma CVD.
  • a capping layer 150 may be selectively formed on the second insulating layer 140 , as shown in FIG. 1G , and the substrate is then planarized by a CMP process, as shown in FIG. 1H .

Abstract

A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.

Description

  • This application claims the benefit of Korean Application No. 10-2004-0115538, filed on Dec. 29, 2004, which is incorporated by reference herein in its entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a metallization method of a semiconductor device, and particularly to a method for forming a plurality of metal lines on a semiconductor substrate using a dual insulating layer.
  • 2. Description of the Related Art
  • As the integration and miniaturization of semiconductor devices are increased, the dimension of a metal line for interconnecting circuits is decreased more and more. For a higher operational speed of devices, metal interconnecting lines need to be designed to have a low electric resistivity. In general, the electric resistivity is proportional to the width and height of the metal line, and inversely proportional to length thereof. The height of the metal line, as well as the width thereof, should be reduced to a minimum. However, the height and width have a critical value in view of limitations of the metal line formation process. Therefore, an aspect ratio (i.e., a ratio of height-to-diameter) of the gaps between the metal lines, which may be filled with an insulating material, is increased according to the miniaturization of the devices.
  • Conventionally, low resistivity metals such as aluminum, copper and their alloys have been widely used as fine metal lines in semiconductor manufacturing. As a typical example, aluminum alloyed with copper of about 1˜4 wt % is used for the fine metal line, which is resistant to electromigration. The aluminum metal line is generally formed by a physical vapor deposition (PVD) process, also known as a sputtering process, which involves the steps of: depositing a metal thin film on a substrate; etching the metal thin film to form metal lines; and filling gaps between the metal lines with an insulating material.
  • However, today's emphasis on scaling down line width dimension of the metal lines has led to gap-fill problems due to a high aspect ratio of the gaps. A variety of alternative approaches have been explored for forming fine metal lines in a semiconductor substrate.
  • One approach is to utilize a damascene method, but it may incur increase of electric resistivity of the metal line owing to the diffusion of chemical impurities. Another approach is to employ an aluminum gap-fill process using chemical vapor deposition (CVD), but this may lead to reliability problems including electromigration.
  • In order to solve these problems, Korean Patent Publication No. 10-2003-005600 discloses a multilayered metallization structure with a barrier metal layer. The barrier metal layer is formed on an upper surface and sidewall of an insulating layer and a contact plug is formed to interconnect with an underlying metal line in a bottom portion of the insulating layer. This metallization structure can reduce the electric resistivity of metal lines, because the insulating layer is disposed between metal lines. Yet, it is difficult for metal to fill a high aspect ratio of the gaps present in the insulating layer.
    • SUMMARY OF THE INVENTION
  • It is, therefore, an object of the present invention to provide a method for forming a plurality of metal lines in a semiconductor device using a dual insulating layer. The metal deposition can be easily performed without gap-fill problems, even by a PVD sputtering process generally known as having inferior step coverage.
  • To achieve the above objects, an embodiment of a method for forming a plurality of metal lines in a semiconductor device, according to the present invention includes: (a) forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced to each other; (b) depositing a metal layer on and between the first insulating layer patterns; (c) planarizing the metal layer; (d) patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and (e) forming a second insulating layer on and between the metal lines.
  • It is to be understood that both the foregoing general description of the invention and the following detailed description are exemplary, but are not restrictive of the invention.
    • BRIEF DESCRIPTION OF DRAWINGS
  • These and other aspects of the present invention will become evident by reference to the following description of the invention, often referring to the accompanying drawings.
  • FIGS. 1A to 1H are cross-sectional views of a semiconductor substrate, illustrating an embodiment of a method for forming metal lines in a semiconductor device, according to the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The present invention utilizes a couple of insulating layers to reduce an aspect ratio of gaps into which metal lines may be deposited. It should be understood that the techniques and resulting structures are not limited to using any specific substrates and dielectric or insulating overlays. Moreover, the present invention is not restricted to any particular metal or metal alloys. Hereinafter, an exemplary embodiment of the present invention will be described in detail, with reference to FIGS. 1A to 1H.
  • Referring to FIG. 1A, a first insulating layer 110 is formed on a semiconductor substrate 100. Preferably, a thickness or height of the first insulating layer 110 is from about ⅓ to about ⅔ of that of a resulting metal line (see a metal line 130 in FIG. 1E) that may be formed in the subsequent steps.
  • Next, the first insulating layer 110 is patterned to form insulating layer patterns 110 a by a photolithography and etch processes, as shown in FIG. 1B.
  • Subsequent to the formation of the insulating layer patterns 110 a, metal material 120 such as aluminum is deposited over the entire substrate, filling gaps between the insulating layer patterns 110 a, as shown in FIG. 1C. The deposition of the metal material 120, preferably aluminum, is performed by a PVD sputtering process. In this case, the metal material 120 is deposited thicker than the resulting metal line 130, sufficiently covering the insulating layer patterns 110 a. Since the insulating layer patterns 110 a are formed to be much lower than the resulting metal line 130, the gaps between the insulating layer patterns 110 a may have a relatively low aspect ratio. As a result, a PVD-Al layer 120 can fill the gaps without gap-fill issues such as voids.
  • As shown in FIG. 1D, the metal layer 120 is continuously planarized via chemical-mechanical polishing (CMP) or an etch-back process until it has a desired thickness or height.
  • Referring to FIG. 1E, the planarized metal layer 120 is patterned to form metal lines 130 by a photolithography and etching processes using a photo mask. The photo mask defines openings over regions in which the insulating layer patterns 110 a are formed. Namely, portions of the metal layer 120 over the insulating layer patterns 110 a may be removed. In this case, the etching process is controlled to expose upper surfaces of each of insulating layer patterns 110 a.
  • Next, as shown in FIG. 1F, a second insulating layer 140 is formed over the entire substrate 100, thus covering the metal lines 130 and filling gaps between the metal lines 130. The gaps between the metal lines 130, in which the first insulating layer patterns 110 a remains, may have a relatively low aspect ratio. Preferably, the gap filling with the second insulating material is performed by high-density plasma CVD.
  • A capping layer 150 may be selectively formed on the second insulating layer 140, as shown in FIG. 1G, and the substrate is then planarized by a CMP process, as shown in FIG. 1H.
  • While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1-7. (canceled)
8. An apparatus for forming a plurality of metal lines in a semiconductor device, comprising:
means for forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other;
means for depositing a metal layer on and between the first insulating layer patterns;
means for planarizing the metal layer;
means for patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns;
means for forming a second insulating layer on and between the metal lines.
9. The apparatus of claim 8, wherein the means for forming first insulating layer patterns includes means for forming first insulating layer patterns lower than the metal lines.
10. The apparatus of claim 9, wherein the means for forming first insulating layer patterns includes means for forming first insulating layer patterns with a height of ⅓ to ⅔ of that of the metal lines.
11. The apparatus of claim 9, further comprising means for planarizing the second insulating layer.
12. The apparatus of claim 9, wherein means for depositing a metal layer includes means for depositing a metal layer comprising aluminum.
13. The apparatus of claim 9, wherein means for depositing a metal layer includes a sputtering apparatus.
14. The apparatus of claim 9, wherein means for forming a second insulating layer includes a high-density plasma CVD apparatus.
US12/397,169 2004-12-29 2009-03-03 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer Abandoned US20090165706A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/397,169 US20090165706A1 (en) 2004-12-29 2009-03-03 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020040115538A KR100661220B1 (en) 2004-12-29 2004-12-29 Method for forming metal interconnect with dual dielectric layer
KR10-2004-0115538 2004-12-29
US11/320,408 US7517799B2 (en) 2004-12-29 2005-12-29 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer
US12/397,169 US20090165706A1 (en) 2004-12-29 2009-03-03 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/320,408 Division US7517799B2 (en) 2004-12-29 2005-12-29 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer

Publications (1)

Publication Number Publication Date
US20090165706A1 true US20090165706A1 (en) 2009-07-02

Family

ID=36971587

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/320,408 Active 2026-09-13 US7517799B2 (en) 2004-12-29 2005-12-29 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer
US12/397,169 Abandoned US20090165706A1 (en) 2004-12-29 2009-03-03 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/320,408 Active 2026-09-13 US7517799B2 (en) 2004-12-29 2005-12-29 Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer

Country Status (2)

Country Link
US (2) US7517799B2 (en)
KR (1) KR100661220B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8030215B1 (en) * 2008-02-19 2011-10-04 Marvell International Ltd. Method for creating ultra-high-density holes and metallization

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4702792A (en) * 1985-10-28 1987-10-27 International Business Machines Corporation Method of forming fine conductive lines, patterns and connectors
US5242861A (en) * 1991-06-06 1993-09-07 Nec Corporation Method for manufacturing semiconductor device having a multilayer wiring structure
US5905298A (en) * 1996-10-03 1999-05-18 Fujitsu Limited Semiconductor device having an insulation film of low permittivity and a fabrication process thereof
US6079354A (en) * 1996-05-08 2000-06-27 Applied Materials, Inc. Thermal post-deposition treatment of halogen-doped films to improve film stability and reduce halogen migration to interconnect layers
US6284591B1 (en) * 1995-11-02 2001-09-04 Samsung Electromics Co., Ltd. Formation method of interconnection in semiconductor device
US20020093078A1 (en) * 2001-01-15 2002-07-18 Paek Jong Sik Optical device packages having improved conductor efficiency, optical coupling and thermal transfer
US20050051904A1 (en) * 2003-09-09 2005-03-10 Kim Sarah E. Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0156124B1 (en) * 1994-10-20 1998-12-01 문정환 Formation method of metal wiring in semiconductor device
JPH1131692A (en) * 1997-07-10 1999-02-02 Oki Electric Ind Co Ltd Manufacture of wiring semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4702792A (en) * 1985-10-28 1987-10-27 International Business Machines Corporation Method of forming fine conductive lines, patterns and connectors
US5242861A (en) * 1991-06-06 1993-09-07 Nec Corporation Method for manufacturing semiconductor device having a multilayer wiring structure
US6284591B1 (en) * 1995-11-02 2001-09-04 Samsung Electromics Co., Ltd. Formation method of interconnection in semiconductor device
US6079354A (en) * 1996-05-08 2000-06-27 Applied Materials, Inc. Thermal post-deposition treatment of halogen-doped films to improve film stability and reduce halogen migration to interconnect layers
US5905298A (en) * 1996-10-03 1999-05-18 Fujitsu Limited Semiconductor device having an insulation film of low permittivity and a fabrication process thereof
US20020093078A1 (en) * 2001-01-15 2002-07-18 Paek Jong Sik Optical device packages having improved conductor efficiency, optical coupling and thermal transfer
US20050051904A1 (en) * 2003-09-09 2005-03-10 Kim Sarah E. Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow

Also Published As

Publication number Publication date
US7517799B2 (en) 2009-04-14
KR20060076913A (en) 2006-07-05
KR100661220B1 (en) 2006-12-22
US20060205212A1 (en) 2006-09-14

Similar Documents

Publication Publication Date Title
US6548905B2 (en) Semiconductor device having multi-layer copper line and method of forming the same
US7563710B2 (en) Method of fabrication of interconnect structures
US7915162B2 (en) Method of forming damascene filament wires
US5801095A (en) Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
US7867895B2 (en) Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric
US6169024B1 (en) Process to manufacture continuous metal interconnects
JP2002319625A (en) Semiconductor device and manufacturing method therefor
US7452801B2 (en) Metal interconnection structure of a semiconductor device having low resistance and method of fabricating the same
US6429119B1 (en) Dual damascene process to reduce etch barrier thickness
US6133142A (en) Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias
US6258709B1 (en) Formation of electrical interconnect lines by selective metal etch
JPH08298285A (en) Semiconductor element and its manufacture
US6204096B1 (en) Method for reducing critical dimension of dual damascene process using spin-on-glass process
US7485574B2 (en) Methods of forming a metal line in a semiconductor device
US7517799B2 (en) Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer
JP2001053151A (en) Semiconductor integrated circuit device and manufacturing method of the same
JP2006114724A (en) Semiconductor device and manufacturing method thereof
JPH10125785A (en) Method of forming wiring of semiconductor integrated circuit
US7514793B2 (en) Metal interconnection lines of semiconductor devices and methods of forming the same
US20030119301A1 (en) Method of fabricating an IMD layer to improve global planarization in subsequent CMP
US7186641B2 (en) Methods of forming metal interconnection lines in semiconductor devices
US6576555B2 (en) Method of making upper conductive line in dual damascene having lower copper lines
US9773735B1 (en) Geometry control in advanced interconnect structures
KR100440475B1 (en) Method for fabricating semiconductor device
KR100186515B1 (en) Method for forming layer of semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, JUNE WOO;REEL/FRAME:022339/0098

Effective date: 20051226

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION