US20090166884A1 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- US20090166884A1 US20090166884A1 US12/407,280 US40728009A US2009166884A1 US 20090166884 A1 US20090166884 A1 US 20090166884A1 US 40728009 A US40728009 A US 40728009A US 2009166884 A1 US2009166884 A1 US 2009166884A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the same.
- FIGS. 1 to 3 are sectional views representing a method for forming a metal interconnection of a semiconductor device according to the related art.
- a hole 40 is formed by partially etching the interlayer dielectric layer 30 .
- a diffusion barrier layer 50 and a seed layer 60 including copper are sequentially stacked in the hole 40 and on the surface of the interlayer dielectric layer 30 .
- the seed layer 60 and the diffusion barrier layer 50 are formed through a PVD (Plasma Vapor Deposition) process.
- PVD Physical Vapor Deposition
- a reduction of the via size and an increase of the step difference may cause a poor step coverage, so that overhang A or a deposition discontinuous point B may occur.
- a copper interconnection layer 70 is deposited on the seed layer 60 through electroplating so as to fill the hole 40 .
- a void C is formed in the hole 40 due to the overhang A and the deposition discontinuous point B.
- the overhang, the deposition discontinuous point and voids cause the increase of the contact resistance so that the reliability of the semiconductor device is reduced.
- Embodiments of the present invention can solve the above problems occurring in the prior art.
- An embodiment of the present invention can provide a semiconductor device and a method for manufacturing the same, capable of preventing an overhang or a void from being generated due to a step difference in the process of forming a diffusion barrier layer and a seed layer.
- Another embodiment of the present invention is to provide a semiconductor device and a method for manufacturing the same, capable of preventing the performance degradation of the semiconductor device caused by an overhang or a void, thereby preventing the reliability of the semiconductor device from being degraded.
- embodiments of the present invention provide a semiconductor device comprising: a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate and provided with a hole having a tapered angle on the upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.
- Another aspect of the present invention provides a method comprising: forming an interlayer dielectric layer on the semiconductor substrate having a conductive layer; forming a first photoresist layer having a predetermined thickness on the interlayer dielectric layer; exposing an entire surface of the first photoresist layer; forming a shielding layer on the exposed first photoresist layer; forming and patterning a second photoresist layer on the shielding layer; etching the shielding layer exposed by the patterned second photoresist layer; developing and removing a predetermined portion of the first photoresist layer which is exposed by the etched shielding layer; and forming a hole by etching the interlayer dielectric layer exposed by the removal of the predetermined portion of the first photoresist layer.
- FIGS. 1 to 3 are sectional views illustrating a method for forming a metal interconnection of a semiconductor device according to the related art.
- FIGS. 4 to 12 are sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.
- the expression “formed on each layer” may include the meaning of both “formed directly on each layer” and “formed indirectly on each layer”.
- FIGS. 4 to 12 illustrate a method for forming a metal interconnection of a semiconductor device in accordance with an exemplary embodiment of the present invention.
- the first photoresist layer 130 can have a thickness within a range of about 50 nm to about 200 nm. That is, when the thickness of the first photoresist layer 130 is less than 50 nm, an undercut hardly occurs, and when the thickness of the first photoresist layer 130 exceeds 200 nm, the undercut excessively occurs so that a taper angle of the interlayer dielectric layer 120 is excessively increased.
- an undercut having a proper size may be obtained by forming the first photoresist layer 130 with a thickness of about 100 nm.
- a blank exposure process can be performed to expose the entire surface of the first photoresist layer 130 ) to light without using a photo mask.
- a shielding layer 140 can be formed on the first photoresist layer 130 .
- the shielding layer 140 functions to protect the first photoresist layer 130 except for the regions of the first photoresist layer 130 exposed in a subsequent process from making contact with a developer.
- a middle metal layer formed by depositing a metal can be used as the shielding layer 140 .
- the present invention is not limited thereto. That is, in other embodiments, an insulating layer such as an oxide layer or a nitride layer can be used as the shielding layer 140 .
- the middle metal layer 140 can be deposited through PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition).
- the middle metal layer 140 can be aluminum deposited on the first photoresist layer 130 through CVD.
- the middle metal layer 140 can Support a second photoresist layer 150 , described below, and serves as a mask when removing the first photoresist layer 130 .
- a second photoresist layer 150 can be formed on the middle metal layer 140 and patterned for forming a trench.
- the second photoresist layer 150 can be exposed to light through a predetermined photo mask so that the second photoresist layer 150 is patterned on the middle metal layer 140 . Accordingly, a predetermined portion of the middle metal layer 140 is exposed.
- the exposed middle metal layer 140 can be etched so that a predetermined portion of the first photoresist layer 130 is exposed.
- a wet etching process or a dry etching process can be used as a method for etching the middle metal layer 140 .
- the exposed middle metal layer 140 can be etched through RIE (Reactive Ion Etch).
- a predetermined portion of the first photoresist layer 130 positioned under the middle metal layer 140 is exposed as the predetermined portion of the middle metal layer 140 is removed.
- the exposed first photoresist layer 130 can be developed.
- the undercut which is sunk in at a predetermined angle and removed, may occur as the exposed portion of the first photoresist layer 130 is developed.
- overhang can be prevented from being generated in the following process of forming the diffusion barrier layer 170 and the seed layer 180 .
- a predetermined portion of the interlayer dielectric layer 120 can be exposed.
- the exposed portion of the interlayer dielectric layer 120 can be etched so as to form a hole 160 for the interconnection between layers. Accordingly, a predetermined portion of the conductive layer 110 is exposed.
- the hole 160 can be formed as a trench a via hole or a contact hole depending on the desired application.
- a wet etching process or a dry etching process can be used for etching the interlayer dielectric layer 120 .
- the interlayer dielectric layer 120 can be etched such that the hole 160 is formed therein, and the upper portion thereof is sunk at a predetermined angle.
- the upper portion of the hole 160 has a width wider than the width of the lower portion of the hole 160 .
- the lower portion of the hole 160 can have a width identical to a width of a middle portion of the hole 160 , and the upper portion of the hole can have a width wider than the width of the lower portion of the hole.
- the etching rate may increase at the upper portion of the interlayer dielectric layer 120 . Accordingly, after the etching process has been performed, the hole 160 is formed in the interlayer dielectric layer 120 and the upper portion of the interlayer dielectric layer 120 is sunk at a predetermined angle.
- the first photoresist layer 130 , the middle metal layer 140 and the second photoresist layer 150 can be removed leaving a hole 160 in the interlayer dielectric layer 120 having a tapered angle at the upper portion of the hole 160 .
- a diffusion barrier layer 170 and a seed layer 180 can be sequentially stacked on the interlayer dielectric layer 120 .
- the diffusion barrier layer 170 prevents a metal interconnection layer to be filled in the hole in the following process from diffusing into the interlayer dielectric layer 120 , and the seed layer 180 accelerates the growth of the metal interconnection layer.
- the diffusion barrier layer 170 can be formed on the interlayer dielectric layer 120 and the exposed portion of the conductive layer 110 , and the seed layer 180 can be formed on the diffusion barrier layer 170 .
- the diffusion barrier layer 170 may be formed of a single TaN layer, a single Ta layer, or a dual TaN/Ta layer.
- the diffusion barrier layer 170 may include a dual layer of TaN/Ta 171 and 172 .
- the diffusion barrier layer 170 and the seed layer formed on the interlayer dielectric layer 120 are also chamfered at a predetermined angle.
- the overhang does not occur in the process of forming the diffusion barrier layer 170 and the seed layer 180 so a void which may generate in the metal interconnection layer to be filled in the hole 160 can be prevented.
- a process of forming the metal interconnection layer can be performed to interconnect the layers.
- Embodiments of the present invention can be applied to both single damascene process and dual damascene process, and can be applied to the process for forming the contact hole and the via hole.
- the semiconductor device and the method for manufacturing the same according to the exemplary embodiment of the present invention can prevent an overhang from being generated due to a step difference of a hole in the process of forming a diffusion barrier layer and a seed layer.
- the performance degradation of the semiconductor device caused by an overhang or a void can be prevented, so that the reliability of the semiconductor device can be improved.
Abstract
A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole's upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.
Description
- This application is a divisional of U.S. application Ser. No. 11/610,899, filed Dec. 14, 2006, which claims the benefit of Korean Patent Application No. 10-2005-0129865, filed Dec. 26, 2005, which are incorporated herein by reference in their entirety.
- The present invention relates to a semiconductor device and a method for manufacturing the same.
- In general, there has been a rapid change toward high performance in next generation semiconductor devices. As a result, a via hole size has become reduced and the aspect ratio thereof has become increased. Thus, superior step coverage, via filling capability and high speed operation of a device has become necessary. To this end, a method for forming a metal interconnection on a damascene pattern using copper has been suggested as a useful method. As an example of conventional methods for forming copper interconnection, there is a method including the steps of forming a diffusion barrier layer and a seed layer for forming copper through physical vapor deposition, forming a copper interconnection layer on the seed layer through electroplating to fill a via with the copper interconnection, and performing chemical mechanical polishing.
FIGS. 1 to 3 are sectional views representing a method for forming a metal interconnection of a semiconductor device according to the related art. - First, referring to
FIG. 1 , after an interlayerdielectric layer 30 is formed on asemiconductor substrate 10 having aconductive layer 20 thereon, ahole 40 is formed by partially etching the interlayerdielectric layer 30. - Then, referring to
FIG. 2 , adiffusion barrier layer 50 and aseed layer 60 including copper are sequentially stacked in thehole 40 and on the surface of the interlayerdielectric layer 30. - In detail, the
seed layer 60 and thediffusion barrier layer 50 are formed through a PVD (Plasma Vapor Deposition) process. However, a reduction of the via size and an increase of the step difference may cause a poor step coverage, so that overhang A or a deposition discontinuous point B may occur. - Referring to
FIG. 3 , acopper interconnection layer 70 is deposited on theseed layer 60 through electroplating so as to fill thehole 40. - However, a void C is formed in the
hole 40 due to the overhang A and the deposition discontinuous point B. As described above, according to the related art, the overhang, the deposition discontinuous point and voids cause the increase of the contact resistance so that the reliability of the semiconductor device is reduced. - Further, according to the related art, such overhang, deposition discontinuous point and voids may become serious problems because the aspect ratio of the hole may increase as the degree of integration of the semiconductor device increases.
- Embodiments of the present invention can solve the above problems occurring in the prior art. An embodiment of the present invention can provide a semiconductor device and a method for manufacturing the same, capable of preventing an overhang or a void from being generated due to a step difference in the process of forming a diffusion barrier layer and a seed layer.
- Another embodiment of the present invention is to provide a semiconductor device and a method for manufacturing the same, capable of preventing the performance degradation of the semiconductor device caused by an overhang or a void, thereby preventing the reliability of the semiconductor device from being degraded.
- To achieve the above, embodiments of the present invention provide a semiconductor device comprising: a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate and provided with a hole having a tapered angle on the upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.
- Another aspect of the present invention provides a method comprising: forming an interlayer dielectric layer on the semiconductor substrate having a conductive layer; forming a first photoresist layer having a predetermined thickness on the interlayer dielectric layer; exposing an entire surface of the first photoresist layer; forming a shielding layer on the exposed first photoresist layer; forming and patterning a second photoresist layer on the shielding layer; etching the shielding layer exposed by the patterned second photoresist layer; developing and removing a predetermined portion of the first photoresist layer which is exposed by the etched shielding layer; and forming a hole by etching the interlayer dielectric layer exposed by the removal of the predetermined portion of the first photoresist layer.
-
FIGS. 1 to 3 are sectional views illustrating a method for forming a metal interconnection of a semiconductor device according to the related art; and -
FIGS. 4 to 12 are sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. - Hereinafter a semiconductor device and a method for manufacturing the same according to an exemplary embodiment of the present invention will be explained in detail with reference to accompanying drawings.
- In the following description the expression “formed on each layer” may include the meaning of both “formed directly on each layer” and “formed indirectly on each layer”.
-
FIGS. 4 to 12 illustrate a method for forming a metal interconnection of a semiconductor device in accordance with an exemplary embodiment of the present invention. - Referring to
FIG. 4 an interlayerdielectric layer 120 is formed on asemiconductor substrate 100 where aconductive layer 110 is formed. - Then referring to
FIG. 5 , a photoresist is coated on the interlayerdielectric layer 120 to a predetermined thickness so as to form a firstphotoresist layer 130. The firstphotoresist layer 130 can have a thickness such that the width of the undercut portion can be controlled. - In a specific embodiment, the first
photoresist layer 130 can have a thickness within a range of about 50 nm to about 200 nm. That is, when the thickness of the firstphotoresist layer 130 is less than 50 nm, an undercut hardly occurs, and when the thickness of the firstphotoresist layer 130 exceeds 200 nm, the undercut excessively occurs so that a taper angle of the interlayerdielectric layer 120 is excessively increased. - For instance, according to an embodiment of the present embodiment, an undercut having a proper size may be obtained by forming the first
photoresist layer 130 with a thickness of about 100 nm. - Subsequently, a blank exposure process can be performed to expose the entire surface of the first photoresist layer 130) to light without using a photo mask.
- Then, referring to
FIG. 6 , ashielding layer 140 can be formed on the firstphotoresist layer 130. - The
shielding layer 140 functions to protect the firstphotoresist layer 130 except for the regions of the firstphotoresist layer 130 exposed in a subsequent process from making contact with a developer. - In one embodiment a middle metal layer formed by depositing a metal can be used as the
shielding layer 140. However, the present invention is not limited thereto. That is, in other embodiments, an insulating layer such as an oxide layer or a nitride layer can be used as theshielding layer 140. - The
middle metal layer 140 can be deposited through PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). - In a specific embodiment, the
middle metal layer 140 can be aluminum deposited on the firstphotoresist layer 130 through CVD. - The
middle metal layer 140 can Support a secondphotoresist layer 150, described below, and serves as a mask when removing the firstphotoresist layer 130. - Referring to
FIG. 7 , a secondphotoresist layer 150 can be formed on themiddle metal layer 140 and patterned for forming a trench. - For example, the second
photoresist layer 150 can be exposed to light through a predetermined photo mask so that the secondphotoresist layer 150 is patterned on themiddle metal layer 140. Accordingly, a predetermined portion of themiddle metal layer 140 is exposed. - Then, referring to
FIG. 8 , the exposedmiddle metal layer 140 can be etched so that a predetermined portion of the firstphotoresist layer 130 is exposed. - In this case, a wet etching process or a dry etching process can be used as a method for etching the
middle metal layer 140. - In one embodiment, the exposed
middle metal layer 140 can be etched through RIE (Reactive Ion Etch). - A predetermined portion of the first
photoresist layer 130 positioned under themiddle metal layer 140 is exposed as the predetermined portion of themiddle metal layer 140 is removed. - Then, referring to
FIG. 9 , the exposed firstphotoresist layer 130 can be developed. - Since the first
photoresist layer 130 is blank-exposed in the previous process, the undercut, which is sunk in at a predetermined angle and removed, may occur as the exposed portion of the firstphotoresist layer 130 is developed. - As the first
photoresist layer 130 has been partially undercut, overhang can be prevented from being generated in the following process of forming thediffusion barrier layer 170 and theseed layer 180. - Referring to
FIG. 10 , as the exposed portion of thefirst photoresist layer 130 is removed, a predetermined portion of the interlayerdielectric layer 120 can be exposed. The exposed portion of the interlayerdielectric layer 120 can be etched so as to form ahole 160 for the interconnection between layers. Accordingly, a predetermined portion of theconductive layer 110 is exposed. - The
hole 160 can be formed as a trench a via hole or a contact hole depending on the desired application. - In an embodiment, a wet etching process or a dry etching process can be used for etching the interlayer
dielectric layer 120. The interlayerdielectric layer 120 can be etched such that thehole 160 is formed therein, and the upper portion thereof is sunk at a predetermined angle. - In this case, the upper portion of the
hole 160 has a width wider than the width of the lower portion of thehole 160. - If the interlayer
dielectric layer 120 is etched through the dry etching process, the lower portion of thehole 160 can have a width identical to a width of a middle portion of thehole 160, and the upper portion of the hole can have a width wider than the width of the lower portion of the hole. - That is, according to the exemplary embodiment of the present invention, since the lower portion of the
first photoresist layer 130 formed on theinterlayer dielectric layer 120 is undercut to be sunk at a predetermined angle, the etching rate may increase at the upper portion of theinterlayer dielectric layer 120. Accordingly, after the etching process has been performed, thehole 160 is formed in theinterlayer dielectric layer 120 and the upper portion of theinterlayer dielectric layer 120 is sunk at a predetermined angle. - The upper portion of the
interlayer dielectric layer 120 and the lower portion of thefirst photoresist layer 130, being sunk in at predetermined angles, form sinkparts 161. - Referring to
FIG. 11 , thefirst photoresist layer 130, themiddle metal layer 140 and thesecond photoresist layer 150 can be removed leaving ahole 160 in theinterlayer dielectric layer 120 having a tapered angle at the upper portion of thehole 160. - Referring to
FIG. 12 , adiffusion barrier layer 170 and aseed layer 180 can be sequentially stacked on theinterlayer dielectric layer 120. - The
diffusion barrier layer 170 prevents a metal interconnection layer to be filled in the hole in the following process from diffusing into theinterlayer dielectric layer 120, and theseed layer 180 accelerates the growth of the metal interconnection layer. - In detail, the
diffusion barrier layer 170 can be formed on theinterlayer dielectric layer 120 and the exposed portion of theconductive layer 110, and theseed layer 180 can be formed on thediffusion barrier layer 170. - The
diffusion barrier layer 170 may be formed of a single TaN layer, a single Ta layer, or a dual TaN/Ta layer. - Referring to
FIG. 12 , thediffusion barrier layer 170 may include a dual layer of TaN/Ta - Since the upper portion of the
interlayer dielectric layer 120 is chamfered at a predetermined angle, thediffusion barrier layer 170 and the seed layer formed on theinterlayer dielectric layer 120 are also chamfered at a predetermined angle. - Accordingly, the overhang does not occur in the process of forming the
diffusion barrier layer 170 and theseed layer 180 so a void which may generate in the metal interconnection layer to be filled in thehole 160 can be prevented. After forming thediffusion barrier layer 170 and theseed layer 180, a process of forming the metal interconnection layer can be performed to interconnect the layers. - Embodiments of the present invention can be applied to both single damascene process and dual damascene process, and can be applied to the process for forming the contact hole and the via hole.
- The semiconductor device and the method for manufacturing the same according to the exemplary embodiment of the present invention can prevent an overhang from being generated due to a step difference of a hole in the process of forming a diffusion barrier layer and a seed layer.
- Further, according to embodiments of the present invention, the performance degradation of the semiconductor device caused by an overhang or a void can be prevented, so that the reliability of the semiconductor device can be improved.
- The embodiments and the accompanying, drawings illustrated and described herein are intended to not limit the present invention, and it will be obvious to those skilled in the art that various changes, variations and modifications can be made to the present invention without departing from the technical spirit of the invention.
Claims (8)
1. A semiconductor device comprising:
a semiconductor substrate having a conductive layer;
an interlayer dielectric layer formed on the semiconductor substrate, wherein the interlayer dielectric layer has a hole above the conductive layer, wherein an upper portion of the hole has a tapered angle;
a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and
a seed layer formed on the di fusion barrier layer.
2. The semiconductor device of claim 1 , wherein a lower portion of the hole has a width identical to a width of a middle portion of the hole, and a width of the upper portion of the hole is wider than the width of the lower portion of the hole.
3. The semiconductor device of claim 1 , wherein the diffusion barrier layer comprises a single TaN layer.
4. The semiconductor device of claim 1 , wherein the diffusion barrier layer comprises a single Ta layer.
5. The semiconductor device of claim , wherein the diffusion barrier layer comprises a dual TaN/Ta layer.
6. The semiconductor device of claim 1 , wherein the upper portion of the hole is sunk at a predetermined angle.
7. The semiconductor device of claim 1 , wherein the upper portion of the hole has a width wider than the width of the lower portion of the hole.
8. The semiconductor device of claim 1 , wherein the lower portion of the hole has a width identical to a width of a middle portion of the hole.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US12/407,280 US20090166884A1 (en) | 2005-12-26 | 2009-03-19 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR10-2005-0129865 | 2005-12-26 | ||
KR1020050129865A KR100698741B1 (en) | 2005-12-26 | 2005-12-26 | Method for forming metal wiring layer of semiconductor device |
US11/610,899 US7524760B2 (en) | 2005-12-26 | 2006-12-14 | Semiconductor device and method for manufacturing the same |
US12/407,280 US20090166884A1 (en) | 2005-12-26 | 2009-03-19 | Semiconductor device and method for manufacturing the same |
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Application Number | Title | Priority Date | Filing Date |
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US11/610,899 Division US7524760B2 (en) | 2005-12-26 | 2006-12-14 | Semiconductor device and method for manufacturing the same |
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US20090166884A1 true US20090166884A1 (en) | 2009-07-02 |
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US11/610,899 Expired - Fee Related US7524760B2 (en) | 2005-12-26 | 2006-12-14 | Semiconductor device and method for manufacturing the same |
US12/407,280 Abandoned US20090166884A1 (en) | 2005-12-26 | 2009-03-19 | Semiconductor device and method for manufacturing the same |
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US11/610,899 Expired - Fee Related US7524760B2 (en) | 2005-12-26 | 2006-12-14 | Semiconductor device and method for manufacturing the same |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103390638A (en) * | 2012-05-11 | 2013-11-13 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
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CA2346878A1 (en) | 1998-10-16 | 2000-04-27 | Xubai Zhang | Voltage tunable laminated dielectric materials for microwave applications |
JP2002353195A (en) * | 2001-05-23 | 2002-12-06 | Sony Corp | Method of manufacturing semiconductor device |
KR100870659B1 (en) * | 2001-12-31 | 2008-11-26 | 엘지디스플레이 주식회사 | A method of liquid crystal display device |
-
2005
- 2005-12-26 KR KR1020050129865A patent/KR100698741B1/en not_active IP Right Cessation
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2006
- 2006-12-14 US US11/610,899 patent/US7524760B2/en not_active Expired - Fee Related
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2009
- 2009-03-19 US US12/407,280 patent/US20090166884A1/en not_active Abandoned
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US5057186A (en) * | 1989-07-28 | 1991-10-15 | At&T Bell Laboratories | Method of taper-etching with photoresist adhesion layer |
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CN103390638A (en) * | 2012-05-11 | 2013-11-13 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
US9721952B2 (en) | 2012-05-11 | 2017-08-01 | Samsung Electronics Co., Ltd. | Semiconductor devices having gate patterns in trenches with widened openings |
Also Published As
Publication number | Publication date |
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US20070145593A1 (en) | 2007-06-28 |
US7524760B2 (en) | 2009-04-28 |
KR100698741B1 (en) | 2007-03-23 |
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