US20090269919A1 - Split gate type non-volatile memory device - Google Patents
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- US20090269919A1 US20090269919A1 US12/497,845 US49784509A US2009269919A1 US 20090269919 A1 US20090269919 A1 US 20090269919A1 US 49784509 A US49784509 A US 49784509A US 2009269919 A1 US2009269919 A1 US 2009269919A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- a non-volatile memory device may be able to electrically erase and store data, and may be able to store data even when power is not supplied. Because of this ability, applications of non-volatile memory may be important in various fields.
- the non-volatile memory device may be divided into a NAND-type non-volatile memory device and a NOR-type non-volatile memory device.
- the NAND-type non-volatile memory device may be used for storing data.
- the NOR-type non-volatile memory device may be used for booting up various systems.
- NOR-type non-volatile memory device a plurality of memory cells, which may constitute a single transistor, may be connected to one bit line in parallel.
- One memory cell transistor may be connected between a drain connected to a bit line and a source region connected to a common source line.
- a current of a memory cell may be high, the memory cell may operate at high speed, and a contact of the bit line and the common source line may occupy a large area. Accordingly, it may be difficult for a NOR-type non-volatile memory device to be highly integrated.
- the memory cells may be connected to the bit line in parallel. Accordingly, if the threshold voltage of the memory cell transistor is lower than a voltage (commonly 0V) applied to the word line of a non-selected memory cell, current may flow between a source and a drain regardless of whether a selected memory cell is turned on or off. In this instance, all memory cells may be read to be turned on.
- a non-volatile memory device referred to as a split-gate type may be used.
- a non-volatile memory device may be divided into a flash memory device, which may have a laminated gate of a FLOTOX structure, and a SONOS device, which may have a structure similar to that of a MOS transistor and may include a multi-layer gate insulating layer.
- the gate insulating layer of the SONOS device may be a multi-layer charge storage insulating layer and may have a structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer may be sequentially laminated (oxide-nitride-oxide (ONO) layer). Since charges may be stored in a deep level trap that a nitride layer has, the SONOS device may have a higher reliability than the flash memory device.
- SONOS devices may be capable of performing writing and erasing operations at a low voltage.
- FIGS. 1A to 1C illustrate an example method of manufacturing a related art split gate-type non-volatile memory device.
- a device isolation layer (not shown) may be formed in the direction of a bit line in parallel on semiconductor substrate 50 , and may limit active region 51 .
- Multi-layer charge storage layer 54 , first conductive layer 56 , and capping layers 58 and 60 may be formed to be parallel to a word line with a prescribed width on semiconductor substrate 50 .
- the ONO layer may be used as the charge storage layer.
- capping layers may be formed by laminating silicon oxide layer 58 , which may function as a buffer, and silicon nitride layer 60 used as a hard mask. Then, to form first conductive layer 56 , to cure damaged sidewalls, an oxide process may be performed on the sidewalls of first conductive layer 56 to form sidewall insulating layers 62 .
- the multi-layer charge storage layer exposed on active region 51 may be removed, excluding portions of multi-layer charge storage layer 54 under first conductive layer 56 .
- Gate insulating layer 64 may be formed on the exposed active region of the substrate.
- second conductive layer 66 may be formed on gate insulating layer 64 and first conductive layer 56 (including silicon oxide layer 58 and silicon nitride layer 60 ).
- Photoresist pattern 68 which may have opening 67 , may be formed on second conductive layer 66 .
- Photoresist pattern 68 may be formed so that opening 67 may limit tops of first conductive layer 56 and active region 51 .
- Part of second conductive layer 66 may be exposed by opening 67 .
- second conductive layer 66 may be etched using photoresist pattern 68 as an etching mask and the various layers (capping layers 58 , 60 , first conductive layer 56 , and ONO layer 54 ) under second conductive layer 66 may be simultaneously etched. Therefore, a pair of split gates, including ONO layer 54 , first conductive layer patterns 56 a, capping layer patterns 58 a and 60 a, and second conductive layer patterns 66 a, may be formed in active region 51 of the substrate.
- the split gates may extend from a top of capping layer pattern 60 a to gate insulating layer 64 , covering sidewalls of first conductive layer patterns 56 a (including sidewall insulating layers 62 ), and may be formed in active region 51 of the substrate.
- the pair of split gates may constitute the word line and may be perpendicular to the bit line.
- first conductive layer 56 and second conductive layer 66 may be formed, and may be etched in a single etching process.
- a step difference between the objects may be very high.
- a top of second conductive layer 66 which may be the uppermost layer, may therefore be damaged. That is, if photoresist 68 formed on second conductive layer 66 is not thick enough, photoresist 68 may be substantially or completely consumed during the etching process.
- a top of second conductive layer 66 may therefore be revealed.
- second conductive layer 66 may not be able to withstand the high etching rate, and may be damaged.
- FIG. 2 illustrates the potential damage to tops of conductive layer patterns 66 a in the region A.
- Embodiments relate to a semiconductor device and a method of manufacturing the same. Embodiments relate to a split gate type non-volatile memory device and a method of manufacturing the same.
- Embodiments relate to a split gate-type non-volatile memory device in which second conductive layer patterns that constitute a word line may be formed on the sidewalls of first conductive layer patterns in the form of spacers so that it may be possible to prevent the top of a second conductive layer from being damaged when a first conductive layer is patterned.
- a split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region.
- the pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.
- sidewall insulating layers may be formed on the sidewalls of the pair of first conductive layer patterns.
- the second conductive layer patterns may be electrically connected to the first conductive layer patterns by the sidewall insulating layers.
- capping insulating layers may be formed on the first conductive layer patterns. The second conductive layer patterns may be electrically insulated from the first conductive layer by the capping insulating layers.
- a method of manufacturing a non-volatile memory device may include limiting an active region on a semiconductor substrate, forming a charge storage layer and a first conductive layer having a prescribed width on the active region, forming a second conductive layer on the first conductive layer and the active region positioned on the right and left of the first conductive layer to be conformal, forming a pair of second conductive layer patterns on both sidewalls of the first conductive layer by etching back the second conductive layer, forming a photoresist pattern with an opening that crosses the active region on the first conductive layer, and forming a pair of conductive layer patterns by etching the first conductive layer using the photoresist pattern as an etching mask.
- the pair of second conductive layer patters may be formed on the right and left sidewalls of the first conductive layer in the form of spacers.
- sidewall insulating layers may be formed on the right and left sidewalls of the first conductive layer.
- a gate insulating layer may be formed on the active region position on the right and left sides of the first conductive layer.
- a capping insulating layer may be formed on the first conductive layer.
- FIGS. 1A to 1C are example of diagrams illustrating a method of manufacturing a related art split gate-type non-volatile memory device
- FIG. 2 is an example image showing damage to a top of a selected gate that may occur from an etching process when a split gate is formed by the method illustrated in FIGS. 1A to 1C ;
- FIGS. 3A to 3C are example diagrams illustrating a split gate-type non-volatile memory device and a method of manufacturing a split gate-type non-volatile memory device according to embodiments.
- first conductive layer patterns 56 a may be formed to be adjacent to each other in an active region of a semiconductor substrate. Inside sidewalls of first conductive layer patterns 56 a may face each other. Second conductive layer patterns 66 a may be formed on the active region adjacent to outside portions of sidewalls of first conductive layer patterns 56 a. Multi-layer charge storage layer 54 may be interposed between first conductive layer patterns 56 a and a surface of substrate 50 in the active region. Gate insulating layer 64 may be interposed between second conductive layer patterns 66 a and a surface of substrate 50 in the active region.
- Multi-layer charge storage layer 54 may be formed of an ONO layer formed of a silicon oxide layer-silicon nitride layer-silicon oxide layer, according to embodiments.
- multi-layer charge storage layer 54 may be patterned to form multi-layer charge storage layer patterns 54 a below first conductive layer patterns 56 a, and an oxide layer 52 may be provided on substrate 50 between the pair of first conductive layer patterns 56 a.
- Capping insulating layer patterns 58 a and 60 a may be formed on first conductive layer patterns 56 a.
- Sidewall insulating layers 62 may be interposed between the sidewalls adjacent to second conductive layer patterns 66 a and may electrically insulate first conductive layer patterns 56 a from second conductive layer patterns 66 a.
- Second conductive layer patterns 66 a may cross a top of the active region to be parallel to the word line.
- second conductive layer patterns 66 a may be formed as spacers on sidewalls adjacent to first conductive layer patterns 56 a.
- second conductive layer patterns 66 a may be formed on outer sides of capping insulating layer pattern 60 a but may not be formed on a top surface of capping insulating layer pattern 60 a.
- FIGS. 3A to 3C a method of forming the split gate according to embodiments will be described.
- charge storage layer 54 , first conductive layer 56 , and capping insulating layers 58 and 60 may be sequentially laminated on silicon substrate 50 .
- Charge storage layer 54 , first conductive layer 56 , and capping insulating layers 58 and 60 may be formed by sequentially forming the layers on a surface of the substrate and by patterning the layers to have a prescribed with.
- Sidewall insulating layers 62 and gate insulating layer 64 may be formed on left and right sidewalls of first conductive layer 56 and the active region of the substrate, respectively.
- Sidewall insulating layers 62 and gate insulating layer 64 may be formed, for example by oxidizing a polysilicon layer and silicon substrate 50 by a thermal oxidation process.
- second conductive layer 66 may be formed on the substrate and capping insulating layer 60 and may be be conformal.
- second conductive layer 66 may be etched, for example through an etch back process. This may form second conductive layer patterns 66 a that may be left on the sidewalls of first conductive layer 56 , and may also be on sidewalls of capping insulating layers 50 and 60 . Second conductive layer patterns 66 a may be formed over gate insulating layer 64 . In embodiments, sidewall insulating layer 62 may be interposed between first conductive layer 56 and second conductive layer 66 . Hence, after performing the etch-back process, as illustrated in FIG. 3B , second conductive layer 66 may be formed to second conductive patterns 66 a in the form of spacers. In embodiments, second conductive layer patterns 66 a may be formed on outer sides of capping insulating layer 50 and 60 but may be etched off of a top surface of capping insulating layer 60 .
- a photoresist pattern (not shown), that may have an opening that may limit a part of first conductive layer 56 , may be formed.
- the photoresist pattern may have an opening parallel to the word line, and accordingly the opening may cross a plurality of active regions.
- Capping insulating layers 58 and 60 , first conductive layer 56 , and ONO layer 54 may be sequentially etched using the photoresist pattern as an etching mask. Capping layer patterns 58 a and 60 a, first conductive layer patterns 56 a, and ONO layer patterns 54 a, as illustrated in FIG. 3C , may thus be formed.
- Photoresist pattern may then be stripped.
- Sidewall insulating layers 57 and oxide layer 52 may be formed on the exposed one sidewalls of first conductive layer patterns 56 a and on the exposed region of substrate 50 .
- a multi-layer structure including first conductive layer 56
- first conductive layer 56 may be etched. Since second conductive layer 66 may not be included in the multi-layer structure, a step difference may relatively small. For example, the step difference may be much less than that of the related art. Also, since second conductive layer patterns 66 a may be formed only on the sidewalls of first conductive layer patterns 56 a, second conductive layer patterns 66 a may be sufficiently protected by the photoresist pattern in the etching process of patterning first conductive layer 56 . Therefore, second conductive layer patterns 66 a may not be damaged. Accordingly, it may be possible to form a reliable split gate.
- second conductive layer patterns 66 a that constitute the word line, may be formed on sidewalls of first conductive layer patterns 56 a in the form of spacers. Therefore, it may not be necessary to pattern the first conductive layer and the second conductive layer through one etching process. Hence, it may be possible to prevent a top of the second conductive layer from being damaged by an excessive etching rate.
Abstract
Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.
Description
- The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0131476 (filed on Dec. 28, 2005), which is hereby incorporated by reference in its entirety.
- A non-volatile memory device may be able to electrically erase and store data, and may be able to store data even when power is not supplied. Because of this ability, applications of non-volatile memory may be important in various fields. The non-volatile memory device may be divided into a NAND-type non-volatile memory device and a NOR-type non-volatile memory device. The NAND-type non-volatile memory device may be used for storing data. The NOR-type non-volatile memory device may be used for booting up various systems.
- In a NOR-type non-volatile memory device, a plurality of memory cells, which may constitute a single transistor, may be connected to one bit line in parallel. One memory cell transistor may be connected between a drain connected to a bit line and a source region connected to a common source line. In the NOR-type non-volatile memory device, a current of a memory cell may be high, the memory cell may operate at high speed, and a contact of the bit line and the common source line may occupy a large area. Accordingly, it may be difficult for a NOR-type non-volatile memory device to be highly integrated.
- In the NOR type non-volatile memory device, the memory cells may be connected to the bit line in parallel. Accordingly, if the threshold voltage of the memory cell transistor is lower than a voltage (commonly 0V) applied to the word line of a non-selected memory cell, current may flow between a source and a drain regardless of whether a selected memory cell is turned on or off. In this instance, all memory cells may be read to be turned on. To solve such a problem, a non-volatile memory device referred to as a split-gate type may be used.
- A non-volatile memory device may be divided into a flash memory device, which may have a laminated gate of a FLOTOX structure, and a SONOS device, which may have a structure similar to that of a MOS transistor and may include a multi-layer gate insulating layer. The gate insulating layer of the SONOS device may be a multi-layer charge storage insulating layer and may have a structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer may be sequentially laminated (oxide-nitride-oxide (ONO) layer). Since charges may be stored in a deep level trap that a nitride layer has, the SONOS device may have a higher reliability than the flash memory device. Moreover, SONOS devices may be capable of performing writing and erasing operations at a low voltage.
-
FIGS. 1A to 1C illustrate an example method of manufacturing a related art split gate-type non-volatile memory device. - Referring to
FIG. 1A , a device isolation layer (not shown) may be formed in the direction of a bit line in parallel onsemiconductor substrate 50, and may limitactive region 51. Multi-layercharge storage layer 54, firstconductive layer 56, andcapping layers semiconductor substrate 50. In embodiments, the ONO layer may be used as the charge storage layer. In embodiments, capping layers may be formed by laminatingsilicon oxide layer 58, which may function as a buffer, andsilicon nitride layer 60 used as a hard mask. Then, to form firstconductive layer 56, to cure damaged sidewalls, an oxide process may be performed on the sidewalls of firstconductive layer 56 to formsidewall insulating layers 62. - The multi-layer charge storage layer exposed on
active region 51 may be removed, excluding portions of multi-layercharge storage layer 54 under firstconductive layer 56.Gate insulating layer 64 may be formed on the exposed active region of the substrate. - Referring to
FIG. 1B , secondconductive layer 66 may be formed ongate insulating layer 64 and first conductive layer 56 (includingsilicon oxide layer 58 and silicon nitride layer 60).Photoresist pattern 68, which may have opening 67, may be formed on secondconductive layer 66.Photoresist pattern 68 may be formed so that opening 67 may limit tops of firstconductive layer 56 andactive region 51. Part of secondconductive layer 66 may be exposed by opening 67. - Referring to
FIG. 1C , secondconductive layer 66 may be etched usingphotoresist pattern 68 as an etching mask and the various layers (capping layers conductive layer 56, and ONO layer 54) under secondconductive layer 66 may be simultaneously etched. Therefore, a pair of split gates, includingONO layer 54, firstconductive layer patterns 56 a,capping layer patterns conductive layer patterns 66 a, may be formed inactive region 51 of the substrate. The split gates may extend from a top ofcapping layer pattern 60 a togate insulating layer 64, covering sidewalls of firstconductive layer patterns 56 a (including sidewall insulating layers 62), and may be formed inactive region 51 of the substrate. The pair of split gates may constitute the word line and may be perpendicular to the bit line. - In the related art method, first
conductive layer 56 and secondconductive layer 66 may be formed, and may be etched in a single etching process. However, when the various layers are laminated, a step difference between the objects may be very high. Hence, it may be necessary to use etching equipment having high etching rate. A top of secondconductive layer 66, which may be the uppermost layer, may therefore be damaged. That is, ifphotoresist 68 formed on secondconductive layer 66 is not thick enough, photoresist 68 may be substantially or completely consumed during the etching process. A top of secondconductive layer 66 may therefore be revealed. Hence, secondconductive layer 66 may not be able to withstand the high etching rate, and may be damaged.FIG. 2 illustrates the potential damage to tops ofconductive layer patterns 66 a in the region A. - Embodiments relate to a semiconductor device and a method of manufacturing the same. Embodiments relate to a split gate type non-volatile memory device and a method of manufacturing the same.
- Embodiments relate to a split gate-type non-volatile memory device in which second conductive layer patterns that constitute a word line may be formed on the sidewalls of first conductive layer patterns in the form of spacers so that it may be possible to prevent the top of a second conductive layer from being damaged when a first conductive layer is patterned.
- According to embodiments, a split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.
- In embodiments, sidewall insulating layers may be formed on the sidewalls of the pair of first conductive layer patterns. In embodiments, the second conductive layer patterns may be electrically connected to the first conductive layer patterns by the sidewall insulating layers. In embodiments, capping insulating layers may be formed on the first conductive layer patterns. The second conductive layer patterns may be electrically insulated from the first conductive layer by the capping insulating layers.
- According to embodiments, a method of manufacturing a non-volatile memory device may include limiting an active region on a semiconductor substrate, forming a charge storage layer and a first conductive layer having a prescribed width on the active region, forming a second conductive layer on the first conductive layer and the active region positioned on the right and left of the first conductive layer to be conformal, forming a pair of second conductive layer patterns on both sidewalls of the first conductive layer by etching back the second conductive layer, forming a photoresist pattern with an opening that crosses the active region on the first conductive layer, and forming a pair of conductive layer patterns by etching the first conductive layer using the photoresist pattern as an etching mask. In embodiments, the pair of second conductive layer patters may be formed on the right and left sidewalls of the first conductive layer in the form of spacers.
- In embodiments, before forming the second conductive layer, sidewall insulating layers may be formed on the right and left sidewalls of the first conductive layer. In embodiments, a gate insulating layer may be formed on the active region position on the right and left sides of the first conductive layer. Also, a capping insulating layer may be formed on the first conductive layer.
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FIGS. 1A to 1C are example of diagrams illustrating a method of manufacturing a related art split gate-type non-volatile memory device; -
FIG. 2 is an example image showing damage to a top of a selected gate that may occur from an etching process when a split gate is formed by the method illustrated inFIGS. 1A to 1C ; and -
FIGS. 3A to 3C are example diagrams illustrating a split gate-type non-volatile memory device and a method of manufacturing a split gate-type non-volatile memory device according to embodiments. - Referring to
FIG. 3C , a pair of firstconductive layer patterns 56 a may be formed to be adjacent to each other in an active region of a semiconductor substrate. Inside sidewalls of firstconductive layer patterns 56 a may face each other. Secondconductive layer patterns 66 a may be formed on the active region adjacent to outside portions of sidewalls of firstconductive layer patterns 56 a. Multi-layercharge storage layer 54 may be interposed between firstconductive layer patterns 56 a and a surface ofsubstrate 50 in the active region.Gate insulating layer 64 may be interposed between secondconductive layer patterns 66 a and a surface ofsubstrate 50 in the active region. Multi-layercharge storage layer 54 may be formed of an ONO layer formed of a silicon oxide layer-silicon nitride layer-silicon oxide layer, according to embodiments. In embodiments, multi-layercharge storage layer 54 may be patterned to form multi-layer chargestorage layer patterns 54 a below firstconductive layer patterns 56 a, and anoxide layer 52 may be provided onsubstrate 50 between the pair of firstconductive layer patterns 56 a. - Capping insulating
layer patterns conductive layer patterns 56 a.Sidewall insulating layers 62 may be interposed between the sidewalls adjacent to secondconductive layer patterns 66 a and may electrically insulate firstconductive layer patterns 56 a from secondconductive layer patterns 66 a. -
Sidewall insulating layers 57 may be formed on inside portions of opposing sidewalls of firstconductive layer patterns 56 a that are not adjacent to secondconductive layer patterns 66 a.Sidewall insulating layers 57 may face each other. Secondconductive layer patterns 66 a may cross a top of the active region to be parallel to the word line. In embodiments, secondconductive layer patterns 66 a may be formed as spacers on sidewalls adjacent to firstconductive layer patterns 56 a. In embodiments, secondconductive layer patterns 66 a may be formed on outer sides of capping insulatinglayer pattern 60 a but may not be formed on a top surface of capping insulatinglayer pattern 60 a. - Referring to
FIGS. 3A to 3C , a method of forming the split gate according to embodiments will be described. - Referring to
FIG. 3A ,charge storage layer 54, firstconductive layer 56, and capping insulatinglayers silicon substrate 50.Charge storage layer 54, firstconductive layer 56, and capping insulatinglayers Sidewall insulating layers 62 andgate insulating layer 64 may be formed on left and right sidewalls of firstconductive layer 56 and the active region of the substrate, respectively.Sidewall insulating layers 62 andgate insulating layer 64 may be formed, for example by oxidizing a polysilicon layer andsilicon substrate 50 by a thermal oxidation process. After formingsidewall insulating layers 62 andgate insulating layer 64, secondconductive layer 66 may be formed on the substrate and capping insulatinglayer 60 and may be be conformal. - Referring to
FIG. 3B , portions of secondconductive layer 66 may be etched, for example through an etch back process. This may form secondconductive layer patterns 66 a that may be left on the sidewalls of firstconductive layer 56, and may also be on sidewalls of capping insulatinglayers conductive layer patterns 66 a may be formed overgate insulating layer 64. In embodiments,sidewall insulating layer 62 may be interposed between firstconductive layer 56 and secondconductive layer 66. Hence, after performing the etch-back process, as illustrated inFIG. 3B , secondconductive layer 66 may be formed to secondconductive patterns 66 a in the form of spacers. In embodiments, secondconductive layer patterns 66 a may be formed on outer sides of capping insulatinglayer layer 60. - After forming second
conductive layer patterns 66 a, a photoresist pattern (not shown), that may have an opening that may limit a part of firstconductive layer 56, may be formed. The photoresist pattern may have an opening parallel to the word line, and accordingly the opening may cross a plurality of active regions. Capping insulatinglayers conductive layer 56, andONO layer 54 may be sequentially etched using the photoresist pattern as an etching mask. Cappinglayer patterns conductive layer patterns 56 a, andONO layer patterns 54 a, as illustrated inFIG. 3C , may thus be formed. Photoresist pattern may then be stripped.Sidewall insulating layers 57 andoxide layer 52 may be formed on the exposed one sidewalls of firstconductive layer patterns 56 a and on the exposed region ofsubstrate 50. - In the etching process illustrated in
FIG. 3C , a multi-layer structure, including firstconductive layer 56, may be etched. Since secondconductive layer 66 may not be included in the multi-layer structure, a step difference may relatively small. For example, the step difference may be much less than that of the related art. Also, since secondconductive layer patterns 66 a may be formed only on the sidewalls of firstconductive layer patterns 56 a, secondconductive layer patterns 66 a may be sufficiently protected by the photoresist pattern in the etching process of patterning firstconductive layer 56. Therefore, secondconductive layer patterns 66 a may not be damaged. Accordingly, it may be possible to form a reliable split gate. - According to embodiments, second
conductive layer patterns 66 a, that constitute the word line, may be formed on sidewalls of firstconductive layer patterns 56 a in the form of spacers. Therefore, it may not be necessary to pattern the first conductive layer and the second conductive layer through one etching process. Hence, it may be possible to prevent a top of the second conductive layer from being damaged by an excessive etching rate. - It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments. Thus, it is intended that embodiments cover modifications and variations thereof within the scope of the appended claims. It is also understood that when a layer is referred to as being “on” or “over” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.
Claims (6)
1-20. (canceled)
21. A method, comprising:
sequentially forming a charge storage layer, a first conductive layer and a capping insulating layer_having a prescribed width over a semiconductor substrate;
forming first insulating layers on outer sidewalls of the first conductive layer and gate insulating layers on the active region of the substrate;
forming a second conductive layer over the first conductive layer and the gate insulating layer;
forming second conductive layer patterns directly contacting the outer sidewall of the first insulating layers and the capping insulating layer_by performing a first etching process etching back the second conductive layer to thereby remove the second conductive layer from the entire uppermost surface of the capping insulating layer;
forming capping layer pattern and_a pair of first conductive layer patterns after forming the second conductive layer patterns by performing a second etching process etching the capping insulating layer and_a center portion of the first conductive layer to expose a portion of the uppermost surface of the semiconductor substrate and inner sidewalls of the first conductive layer; and then
forming second sidewall insulating layers on an inner sidewall of the first conductive layer patterns and an oxide layer on the exposed portion of the substrate.
22. The method of claim 21 , wherein the second conductive layer formed over the capping insulating layer and the semiconductor substrate is formed to be conformal.
23. The method of claim 21 , wherein the pair of second conductive layer patterns are formed on the right and left sidewalls of the first conductive layer and the capping insulating layer in the form of spacers such that the capping layer directly contacts the right and left sidewalls of the second conductive layer patterns.
24. The method of claim 21 , further comprising forming a photoresist pattern having an opening that crosses an active region on the first conductive layer to form the pair of first conductive layer patterns by etching
25. The method of claim 21 , wherein the gate insulating layers on the active region of the substrate is formed by performing a first thermal oxidation process;
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US12/497,845 US20090269919A1 (en) | 2005-12-28 | 2009-07-06 | Split gate type non-volatile memory device |
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KR1020050131476A KR100660283B1 (en) | 2005-12-28 | 2005-12-28 | Split gate type non-volatile memory device and method of fabricating the same |
US11/616,816 US7572702B2 (en) | 2005-12-28 | 2006-12-27 | Split gate type non-volatile memory device |
US12/497,845 US20090269919A1 (en) | 2005-12-28 | 2009-07-06 | Split gate type non-volatile memory device |
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US11/616,816 Continuation US7572702B2 (en) | 2005-12-28 | 2006-12-27 | Split gate type non-volatile memory device |
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US12/497,845 Abandoned US20090269919A1 (en) | 2005-12-28 | 2009-07-06 | Split gate type non-volatile memory device |
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KR100859490B1 (en) * | 2007-06-12 | 2008-09-23 | 주식회사 동부하이텍 | Method for fabricating semi-conductor transistor |
KR100844939B1 (en) * | 2007-06-14 | 2008-07-09 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device with gate line of fine line width |
KR20100080243A (en) * | 2008-12-31 | 2010-07-08 | 주식회사 동부하이텍 | Semiconductor device and fabricating method thereof |
CN101807581B (en) * | 2010-02-05 | 2013-09-04 | 上海宏力半导体制造有限公司 | Contactless split-gate flash memory of shared word line and manufacture method thereof |
US8575683B1 (en) * | 2012-05-16 | 2013-11-05 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
US9570457B2 (en) * | 2014-08-26 | 2017-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates |
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US20070145469A1 (en) | 2007-06-28 |
US7572702B2 (en) | 2009-08-11 |
KR100660283B1 (en) | 2006-12-20 |
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