US20090271750A1 - Timing constraint merging in hierarchical soc designs - Google Patents
Timing constraint merging in hierarchical soc designs Download PDFInfo
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- US20090271750A1 US20090271750A1 US12/095,164 US9516406A US2009271750A1 US 20090271750 A1 US20090271750 A1 US 20090271750A1 US 9516406 A US9516406 A US 9516406A US 2009271750 A1 US2009271750 A1 US 2009271750A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Definitions
- IP Blocks form predesigned functional blocks that can be used in a larger design.
- IP Blocks are provided to the design integrator they have several different types of information.
- One of these different types of information is a set of timing constraints.
- EDA Electronic Design Automation
- the present invention disclosed and claimed herein in one aspect thereof comprises a method for propagation of timing constraints from lower level design blocks to higher level design blocks.
- a circuit containing a plurality of design blocks is designed such that each of the plurality of design blocks has a set of timing constraints associated therewith.
- a composite set of timing constraints are created for the circuit from each of the set of timing constraints associated with each of the plurality of design blocks according to an established propagation rule set.
- FIG. 1 is a block diagram of a Design Manipulation System
- FIG. 2 illustrates the implementation of a Type I Timing Constraint
- FIG. 3 illustrates the implementation of a Type II Timing Constraint
- FIG. 4 is a flow diagram illustrating the propagation of a Type III Timing Constraint
- FIG. 5 is a flow diagram illustrating resolution of conflicts of Type III Timing Constraints.
- FIG. 1 there is illustrated the present system implemented within a Design Manipulation System.
- the present disclosure has been implemented in a computer program called a Design Manipulation System (DMS) 102 .
- the DMS system 102 enables the design of a system using various combinations of existing IP Blocks.
- the generated design will operate according to various established timing constraints 104 , the DMS System 102 also makes use of other design functions 106 .
- Timing Constraints 108 are dependent on the instantiation of the block for which they are defined.
- Type I Timing Constraints include, but are not limited to, constraints such as set_input_delay, set_load or set_driving_cell. They are usually, though not always, defined in terms of ports of the IP Block. If the IP Block is instantiated in a hierarchy, these timing constraints should be inferred from the context, except when they map directly to the boundary of higher level.
- Type II Timing Constraints 110 are independent of the instantiation context. These Constraints include, but are not limited to, set_case_analysis, set_false_path, and set_multicycle_path. These timing constraints may be defined in terms of ports of the IP Block, instance pins of lower level IP Blocks or leaf cells, nets or clocks. These timing constraints can not be inferred from the context, and must be propagated to the higher level of the design.
- Type III Timing Constraints 112 cannot be inferred but may conflict with constraints from the context, such as create_clock or create_generated_clock.
- an IP Block has a clock constraint defined from an input pin with a period that corresponds to the maximum frequency at which the IP Block is intended to run. In a system, this input pin may be connected to a clock that is defined with a different frequency.
- Type IV Timing Constraints do not have a hierarchical source point. Examples of these constraints include, but are not limited to, set_wire_load_model or set_operating_conditions.
- Timing Constraints have a specific source point (or points) specified in terms of a block port, instance pin, or net.
- the fourth type of Constraint does not have a specific source point.
- a “connected cloud” is defined.
- a connected cloud includes the nets, pins and ports that connect directly to the source point of a timing constraint.
- a connected cloud is bounded by leaf cell (library or black box) instance pins or top level ports.
- the connected cloud is not bounded by intermediate hierarchy levels.
- Port C 202 of Block Low 204 is the source of the Type I timing constraint.
- the connected cloud includes port A 206 of the Top level 208 , port B 210 of Mid level 212 , and port E 214 of Mid level 212 .
- the connected cloud does not include port D 216 of Mid level 212 because the connected cloud stops at the input to the buffer 218 .
- the procedure for handling Type I timing constraints defined for Block Low 204 and creating timing constraints for Block Mid 212 based upon these lower level timing constraints may be described as follows. If any part of the connected cloud is present at the boundary of the target level, the timing constraint is propagated.
- the timing constraint is discarded and not passed to the upper level. For example, if the Mid level 212 is the target level and a set_input delay constraint (Type I) is defined for port C 202 of Block Low 204 , the set input delay constraint is propagated to the next level for port B 210 of Block Mid 212 . If a set_output_delay constraint (Type I) is defined for pin Q of instance I 2 220 , this constraint is discarded because the connected cloud stops at buffer 222 and does not reach the boundary.
- Type II timing constraint there is illustrated the implementation of a Type II timing constraint.
- Type II timing constraints are all propagated. Hierarchy level(s) are added (or removed) as required.
- a Type II timing constraint defined on a port of lower level Block may become a constraint on an instance pin for the target level. False paths and multi-cycle paths must be traced through the netlist to identify where they enter or leave the target level. This tracing does not stop at combinatorial logic. The tracing continues until it reaches either a clocked element, a port of the top level, or another part of the same false path. Examples of the process for propagating Type II constraints are more fully illustrated in FIG. 3 .
- a false path 306 defined from instance pin I 1 /A to I 2 /D, inside Mid level 302 will become a false path from I 3 /I 1 /A to pin I 3 /I 2 /D at the higher level.
- a false path 308 defined from instance pin I 1 /B to port C of Mid level 302 becomes a false path from I 3 /I 1 /B to pin I 3 /C.
- a false path 306 defined from instance pin I 3 /I 1 /A to pin I 3 /I 2 /D becomes a false path from instance pin I 1 /A to I 2 /D.
- a false path defined from instance pin I 3 /I 1 /B to pin I 4 /E becomes a false path 308 from instance pin I 1 /B to port C.
- FIG. 4 there is illustrated a flow diagram illustrating the propagation of a Type III constraint.
- a Type III clock constraint is determined at inquiry step 400 .
- the network is traced back at step 402 from the original source through any buffers or inverters (i.e. non-branching combinatorial logic) until a driving source point is found at inquiry step 404 .
- the network is traced forward at step 406 from this new source point, through any combinatorial logic, to all the clocked instances it controls. This forward tracing is modified at step 408 by the presence of any constant values that are applied to the combinatorial logic.
- the combinatorial element is a multiplexer and there are constant values on the select lines, the selection is obeyed.
- These constant values could be either from the netlist (e.g. a constant zero from 1'b0 in Verilog), or from other constraints (e.g. set_case_analysis).
- each visited net is marked as being a clock or a constant value at the step 410 .
- inquiry step 400 determines a constant constraint is defined, this constraint is not traced back to a source. The constraint is only traced forward through the combinatorial logic at step 406 .
- each IP Block may have its own clock definition, but these are all driven by the same source.
- the defined source of each clock is significant in resolving such conflicts as illustrated in FIG. 5 .
- a clock definition is read at step 502 , its defined source is compared with previously traced clocks at step 504 . If the defined source corresponds to a traced source at step 506 , this newly read clock is taken as the dominant one at step 508 , replacing other clocks that traced back to this source.
- An example of this would be when there is a clock generation block, and the clock defined as coming from this is taken as overriding any clocks defined in other IP Blocks that are driven by this clock.
- this clock is discarded at step 510 . So the sequence in which the constraints are read is significant. This would be the case where two or more IP Blocks each have their own definitions of what is in fact the same clock.
- Type IV Timing Constraints do not need to be modified to apply to a higher level. If there are multiple different values for the same constraint type, such as different operating conditions, the most restrictive constraint is propagated. Virtual clocks, i.e. clocks that have been defined with no specific source, are always propagated.
- Some design tools require ports to have certain constraints specified, such as non-clock inputs, relative to a clock. If the port does not have such a constraint, found by propagating from the defined constraints, one is generated. This is done by tracing (backward from outputs, forward from inputs) to clocked elements. The highest frequency clock of these elements is used, and a delay constraint is created as a percentage of this period.
- the clocks for a design may be generated externally and brought on chip through pads, or they may be generated internally, e.g. with PLLs. Any timing constraints provided for either of these clock generation sources must override clock constraints traced from other IP Blocks. This is because the constraints supplied with an IP Block may be for a scenario that does not apply to the current design instantiation. For example a memory controller may be capable of running at 250 MHz, but the design only requires 225 MHz. This situation is covered in the procedure for Type III timing constraints, which takes account of the defined source of the clock when resolving conflicts.
- This method can be used in any hierarchical design where timing constraints are provided for individual IP Blocks, and constraints are needed for top level or chiplet level.
- Such designs include platform-based designs such as Nexperia Home or Nexperia Mobile designs.
Abstract
Description
- Many designs, especially platform-based logic designs, have a large percentage of reusable Intellectual Property (IP) Blocks. These IP Blocks form predesigned functional blocks that can be used in a larger design. When these IP Blocks are provided to the design integrator they have several different types of information. One of these different types of information is a set of timing constraints.
- Electronic Design Automation (EDA) tools require timing constraints for the entities on which they are operating. This may be for the whole design, or it may be an intermediate level hierarchical block (a chiplet) incorporated within the design. These entities do not usually correspond to a single IP Block. Examples of EDA tools that need timing constraints are physical synthesis, placement and routing, and timing analysis. These all operate either at chiplet or full chip level, so that is the level for which they need constraints. Often constraints do not exist for the entire design, but they do exist for the separate IP Blocks within the design. An efficient way is needed to merge these separate constraints to make ones for higher levels.
- Existing tools can manipulate constraints for an entire design, for example by timing budgeting, to create constraints for the chiplets, or lower levels of the design hierarchy. But existing tools cannot derive a set of timing constraints for a higher level of a design from lower level timing constraints. Currently this must be done manually. This is not a simple concatenation process, since only some of the timing constraints need to be propagated to a higher level. It is a time consuming, error prone process, often requiring several man weeks to complete and verify. The process is repeated, with somewhat different inputs, whenever the design changes.
- The present invention disclosed and claimed herein, in one aspect thereof comprises a method for propagation of timing constraints from lower level design blocks to higher level design blocks. A circuit containing a plurality of design blocks is designed such that each of the plurality of design blocks has a set of timing constraints associated therewith. A composite set of timing constraints are created for the circuit from each of the set of timing constraints associated with each of the plurality of design blocks according to an established propagation rule set.
- A more complete understanding of the method and apparatus of the present invention may be obtained by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:
-
FIG. 1 is a block diagram of a Design Manipulation System; -
FIG. 2 illustrates the implementation of a Type I Timing Constraint; -
FIG. 3 illustrates the implementation of a Type II Timing Constraint; -
FIG. 4 is a flow diagram illustrating the propagation of a Type III Timing Constraint; and -
FIG. 5 is a flow diagram illustrating resolution of conflicts of Type III Timing Constraints. - Referring now to the drawings, and more particularly to
FIG. 1 , there is illustrated the present system implemented within a Design Manipulation System. The present disclosure has been implemented in a computer program called a Design Manipulation System (DMS) 102. TheDMS system 102 enables the design of a system using various combinations of existing IP Blocks. The generated design will operate according to various establishedtiming constraints 104, the DMS System 102 also makes use ofother design functions 106. - The timing constraints are described herein in terms of their implementation in SDC (Synopsis Design Constraint) format. There are four categories of timing constraints. Type I
Timing Constraints 108 are dependent on the instantiation of the block for which they are defined. Type I Timing Constraints include, but are not limited to, constraints such as set_input_delay, set_load or set_driving_cell. They are usually, though not always, defined in terms of ports of the IP Block. If the IP Block is instantiated in a hierarchy, these timing constraints should be inferred from the context, except when they map directly to the boundary of higher level. - Type II
Timing Constraints 110 are independent of the instantiation context. These Constraints include, but are not limited to, set_case_analysis, set_false_path, and set_multicycle_path. These timing constraints may be defined in terms of ports of the IP Block, instance pins of lower level IP Blocks or leaf cells, nets or clocks. These timing constraints can not be inferred from the context, and must be propagated to the higher level of the design. - Type III
Timing Constraints 112 cannot be inferred but may conflict with constraints from the context, such as create_clock or create_generated_clock. Typically an IP Block has a clock constraint defined from an input pin with a period that corresponds to the maximum frequency at which the IP Block is intended to run. In a system, this input pin may be connected to a clock that is defined with a different frequency. Finally, Type IV Timing Constraints do not have a hierarchical source point. Examples of these constraints include, but are not limited to, set_wire_load_model or set_operating_conditions. - The first three types of Timing Constraints have a specific source point (or points) specified in terms of a block port, instance pin, or net. The fourth type of Constraint does not have a specific source point. To determine whether a timing constraint applies to the boundary of a target level, a “connected cloud” is defined. A connected cloud includes the nets, pins and ports that connect directly to the source point of a timing constraint. A connected cloud is bounded by leaf cell (library or black box) instance pins or top level ports. The connected cloud is not bounded by intermediate hierarchy levels.
- Referring now to
FIG. 2 , there illustrated the implementation of a Type I timing constraint. Port C 202 of Block Low 204 is the source of the Type I timing constraint. The connected cloud includes port A 206 of theTop level 208,port B 210 of Midlevel 212, andport E 214 of Midlevel 212. The connected cloud does not includeport D 216 of Midlevel 212 because the connected cloud stops at the input to thebuffer 218. The procedure for handling Type I timing constraints defined for Block Low 204 and creating timing constraints for Block Mid 212 based upon these lower level timing constraints may be described as follows. If any part of the connected cloud is present at the boundary of the target level, the timing constraint is propagated. If the connected cloud does not reach the boundary, the timing constraint is discarded and not passed to the upper level. For example, if theMid level 212 is the target level and a set_input delay constraint (Type I) is defined forport C 202 of Block Low 204, the set input delay constraint is propagated to the next level forport B 210 of Block Mid 212. If a set_output_delay constraint (Type I) is defined for pin Q ofinstance I2 220, this constraint is discarded because the connected cloud stops atbuffer 222 and does not reach the boundary. - Referring now to
FIG. 3 , there is illustrated the implementation of a Type II timing constraint. Type II timing constraints are all propagated. Hierarchy level(s) are added (or removed) as required. A Type II timing constraint defined on a port of lower level Block may become a constraint on an instance pin for the target level. False paths and multi-cycle paths must be traced through the netlist to identify where they enter or leave the target level. This tracing does not stop at combinatorial logic. The tracing continues until it reaches either a clocked element, a port of the top level, or another part of the same false path. Examples of the process for propagating Type II constraints are more fully illustrated inFIG. 3 . For example, if the constraints were defined for theMid level 302, andTop level 304 is the target level, afalse path 306 defined from instance pin I1/A to I2/D, insideMid level 302, will become a false path from I3/I1/A to pin I3/I2/D at the higher level. Afalse path 308 defined from instance pin I1/B to port C ofMid level 302, becomes a false path from I3/I1/B to pin I3/C. If the Type II constraints are defined for theTop level 304, and theMid level 302 is the target level, afalse path 306 defined from instance pin I3/I1/A to pin I3/I2/D becomes a false path from instance pin I1/A to I2/D. A false path defined from instance pin I3/I1/B to pin I4/E becomes afalse path 308 from instance pin I1/B to port C. - Referring now to
FIG. 4 , there is illustrated a flow diagram illustrating the propagation of a Type III constraint. When a Type III clock constraint is determined atinquiry step 400, the network is traced back atstep 402 from the original source through any buffers or inverters (i.e. non-branching combinatorial logic) until a driving source point is found atinquiry step 404. This could be a top-level port, a clocked leaf instance or a combinatorial instance. The network is traced forward atstep 406 from this new source point, through any combinatorial logic, to all the clocked instances it controls. This forward tracing is modified atstep 408 by the presence of any constant values that are applied to the combinatorial logic. For example, if the combinatorial element is a multiplexer and there are constant values on the select lines, the selection is obeyed. These constant values could be either from the netlist (e.g. a constant zero from 1'b0 in Verilog), or from other constraints (e.g. set_case_analysis). As the network is traced, each visited net is marked as being a clock or a constant value at thestep 410. Wheninquiry step 400 determines a constant constraint is defined, this constraint is not traced back to a source. The constraint is only traced forward through the combinatorial logic atstep 406. - When the constraints from more than one IP Block are being propagated, there may be conflicts. For example, each IP Block may have its own clock definition, but these are all driven by the same source. The defined source of each clock is significant in resolving such conflicts as illustrated in
FIG. 5 . When a clock definition is read atstep 502, its defined source is compared with previously traced clocks atstep 504. If the defined source corresponds to a traced source atstep 506, this newly read clock is taken as the dominant one atstep 508, replacing other clocks that traced back to this source. An example of this would be when there is a clock generation block, and the clock defined as coming from this is taken as overriding any clocks defined in other IP Blocks that are driven by this clock. If the defined source is not a previously traced source, but a previous clock has been traced through this source, this clock is discarded atstep 510. So the sequence in which the constraints are read is significant. This would be the case where two or more IP Blocks each have their own definitions of what is in fact the same clock. - Type IV Timing Constraints do not need to be modified to apply to a higher level. If there are multiple different values for the same constraint type, such as different operating conditions, the most restrictive constraint is propagated. Virtual clocks, i.e. clocks that have been defined with no specific source, are always propagated.
- Some design tools require ports to have certain constraints specified, such as non-clock inputs, relative to a clock. If the port does not have such a constraint, found by propagating from the defined constraints, one is generated. This is done by tracing (backward from outputs, forward from inputs) to clocked elements. The highest frequency clock of these elements is used, and a delay constraint is created as a percentage of this period.
- The clocks for a design may be generated externally and brought on chip through pads, or they may be generated internally, e.g. with PLLs. Any timing constraints provided for either of these clock generation sources must override clock constraints traced from other IP Blocks. This is because the constraints supplied with an IP Block may be for a scenario that does not apply to the current design instantiation. For example a memory controller may be capable of running at 250 MHz, but the design only requires 225 MHz. This situation is covered in the procedure for Type III timing constraints, which takes account of the defined source of the clock when resolving conflicts.
- This method can be used in any hierarchical design where timing constraints are provided for individual IP Blocks, and constraints are needed for top level or chiplet level. Such designs include platform-based designs such as Nexperia Home or Nexperia Mobile designs.
- Many variations and embodiments of the above-described invention and method are possible. Although only certain embodiments of the invention and method have been illustrated in the accompanying drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of additional rearrangements, modifications and substitutions without departing from the invention as set forth and defined by the following claims. Accordingly, it should be understood that the scope of the present invention encompasses all such arrangements and is solely limited by the claims as follows.
Claims (16)
Applications Claiming Priority (3)
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7926011B1 (en) * | 2007-01-10 | 2011-04-12 | Cadence Design Systems, Inc. | System and method of generating hierarchical block-level timing constraints from chip-level timing constraints |
US8504978B1 (en) | 2009-03-30 | 2013-08-06 | Cadence Design Systems, Inc. | User interface for timing budget analysis of integrated circuit designs |
US8539402B1 (en) * | 2007-01-10 | 2013-09-17 | Cadence Design Systems, Inc. | Systems for single pass parallel hierarchical timing closure of integrated circuit designs |
US8549454B1 (en) * | 2012-07-20 | 2013-10-01 | Xilinx, Inc. | System and method for automated configuration of design constraints |
US8589835B2 (en) | 2012-01-17 | 2013-11-19 | Atrenta, Inc. | System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency |
US8640066B1 (en) * | 2007-01-10 | 2014-01-28 | Cadence Design Systems, Inc. | Multi-phase models for timing closure of integrated circuit designs |
US8656335B2 (en) | 2012-04-27 | 2014-02-18 | Atrenta, Inc. | System and methods for inferring higher level descriptions from RTL topology based on connectivity propagation |
US8683399B2 (en) * | 2010-06-22 | 2014-03-25 | Fujitsu Limited | Timing constraint generating support apparatus and method of supporting generation of timing constraint |
US8782587B2 (en) | 2012-07-30 | 2014-07-15 | Atrenta, Inc. | Systems and methods for generating a higher level description of a circuit design based on connectivity strengths |
US8977995B1 (en) * | 2007-01-10 | 2015-03-10 | Cadence Design Systems, Inc. | Timing budgeting of nested partitions for hierarchical integrated circuit designs |
US9053270B1 (en) | 2012-12-18 | 2015-06-09 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs |
US9542524B2 (en) | 2015-01-27 | 2017-01-10 | International Business Machines Corporation | Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction |
US10394983B2 (en) * | 2017-06-14 | 2019-08-27 | Excellicon Corporation | Method to automatically generate and promote timing constraints in a Synopsys Design Constraint format |
US10594422B2 (en) * | 2016-01-19 | 2020-03-17 | Huawei Technologies Co., Ltd. | Method and apparatus for transmitting clock packet |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5396435A (en) * | 1993-02-10 | 1995-03-07 | Vlsi Technology, Inc. | Automated circuit design system and method for reducing critical path delay times |
US5956257A (en) * | 1993-03-31 | 1999-09-21 | Vlsi Technology, Inc. | Automated optimization of hierarchical netlists |
US6173435B1 (en) * | 1998-02-20 | 2001-01-09 | Lsi Logic Corporation | Internal clock handling in synthesis script |
US20030177463A1 (en) * | 2002-03-18 | 2003-09-18 | Daga Ajay Janami | Automated approach to constraint generation in IC design |
US20040003360A1 (en) * | 2002-06-26 | 2004-01-01 | Batchelor Dennis B. | Systems and methods for time-budgeting a complex hierarchical integrated circuit |
US6857110B1 (en) * | 2001-01-30 | 2005-02-15 | Stretch, Inc. | Design methodology for merging programmable logic into a custom IC |
US7194400B2 (en) * | 2002-04-04 | 2007-03-20 | International Business Machines Corporation | Method and system for reducing storage and transmission requirements for simulation results |
US7240303B1 (en) * | 1999-11-30 | 2007-07-03 | Synplicity, Inc. | Hardware/software co-debugging in a hardware description language |
US7308666B1 (en) * | 2004-12-16 | 2007-12-11 | Cadence Design Systems, Inc. | Method and an apparatus to improve hierarchical design implementation |
US20070294655A1 (en) * | 2006-05-24 | 2007-12-20 | Jorge Campos | Automatically generating an input sequence for a circuit design using mutant-based verification |
US20080028347A1 (en) * | 2006-07-28 | 2008-01-31 | Synopsys, Inc. | Transformation of IC designs for formal verification |
US7653884B2 (en) * | 2005-06-29 | 2010-01-26 | Geoffrey Mark Furnish | Methods and systems for placement |
US7694249B2 (en) * | 2005-10-07 | 2010-04-06 | Sonics, Inc. | Various methods and apparatuses for estimating characteristics of an electronic system's design |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5644498A (en) * | 1995-01-25 | 1997-07-01 | Lsi Logic Corporation | Timing shell generation through netlist reduction |
-
2006
- 2006-11-30 EP EP06832015A patent/EP1958103A1/en not_active Withdrawn
- 2006-11-30 JP JP2008542922A patent/JP2009517764A/en active Pending
- 2006-11-30 US US12/095,164 patent/US20090271750A1/en not_active Abandoned
- 2006-11-30 CN CNA200680044499XA patent/CN101317179A/en active Pending
- 2006-11-30 WO PCT/IB2006/054520 patent/WO2007063513A1/en active Application Filing
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5396435A (en) * | 1993-02-10 | 1995-03-07 | Vlsi Technology, Inc. | Automated circuit design system and method for reducing critical path delay times |
US5956257A (en) * | 1993-03-31 | 1999-09-21 | Vlsi Technology, Inc. | Automated optimization of hierarchical netlists |
US6173435B1 (en) * | 1998-02-20 | 2001-01-09 | Lsi Logic Corporation | Internal clock handling in synthesis script |
US7240303B1 (en) * | 1999-11-30 | 2007-07-03 | Synplicity, Inc. | Hardware/software co-debugging in a hardware description language |
US6857110B1 (en) * | 2001-01-30 | 2005-02-15 | Stretch, Inc. | Design methodology for merging programmable logic into a custom IC |
US6877139B2 (en) * | 2002-03-18 | 2005-04-05 | Fishtail Design Automation Inc. | Automated approach to constraint generation in IC design |
US20030177463A1 (en) * | 2002-03-18 | 2003-09-18 | Daga Ajay Janami | Automated approach to constraint generation in IC design |
US7194400B2 (en) * | 2002-04-04 | 2007-03-20 | International Business Machines Corporation | Method and system for reducing storage and transmission requirements for simulation results |
US20040003360A1 (en) * | 2002-06-26 | 2004-01-01 | Batchelor Dennis B. | Systems and methods for time-budgeting a complex hierarchical integrated circuit |
US7308666B1 (en) * | 2004-12-16 | 2007-12-11 | Cadence Design Systems, Inc. | Method and an apparatus to improve hierarchical design implementation |
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JP2009517764A (en) | 2009-04-30 |
EP1958103A1 (en) | 2008-08-20 |
WO2007063513A1 (en) | 2007-06-07 |
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