US20090286453A1

US20090286453A1 - Method and apparatus for chemical-mechanical polishing

Info

Publication number: US20090286453A1
Application number: US12/385,704
Authority: US
Inventors: Il-young Yoon; Tae-Hoon Lee; Jae-ouk Choo
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2008-05-14
Filing date: 2009-04-16
Publication date: 2009-11-19
Also published as: KR20090118751A

Abstract

In accordance with at least one example embodiment, a method of chemical-mechanical polishing includes re-polishing a polished layer on a wafer based on a measured thickness of the polished layer. In accordance with at least one example embodiment, an apparatus for chemical-mechanical polishing may include a thickness measuring unit configured to measure a thickness of a polished surface on a wafer and to determine a re-polishing time based on the measured thickness. In accordance with example embodiments, a thickness deviation between different lots, wafers, or chips inside a wafer is reduced regardless of the durability of a polishing pad, a polishing head, or a disk used in a polishing apparatus.

Description

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2008-0044726, filed on May 14, 2008, in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.

BACKGROUND

1. Field
Example embodiments relate to a method and apparatus for chemical-mechanical polishing, and more particularly, to a method and apparatus for chemical-mechanical polishing an insulation layer formed on a wafer, a metal layer formed on a wafer, and/or a surface of a wafer.
2. Description of the Related Art
During the fabrication of semiconductor devices, stepped layers may be formed which require planarization in order to adequately form semiconductor patterns. An example of such a planarization process is chemical-mechanical polishing (CMP), which involves planarizing a material layer by performing both a chemical and a mechanical polishing operation.
A conventional CMP device includes an elastic polishing pad, a rotatable polishing head, a pad conditioner, and a device for supplying a slurry, e.g., a polishing solution. According to conventional CMP processes, the polishing head may apply pressure to a wafer during the polishing process. The polishing head may also be configured to rotate while applying pressure to the wafer.
According to conventional CMP processes, the slurry may include minute polishing particles in a chemical solution. The slurry is provided between the wafer and the polishing pad, and the surface of the wafer is polished by pressurizing and rotating the polishing head on the wafer. In conventional CMP processes, a platen, in which the polishing pad is attached, is rotated in a fixed direction. The platen rotates in one direction at a uniform speed in order to uniformly polish the surface of the wafer.
According to a conventional CMP method, when a target thickness of a wafer is about 3500 Å, the total thicknesses of a plurality of wafers included in one lot (the plurality of wafers are vertically aligned for convenient transportation) are between about 3200 to 3800 Å, and a difference between the thicknesses of the wafers may be approximately 600 Å. Also, the thickness of one wafer may be about 2900˜4100 Å, and a difference of the thickness between the center and edge of the wafer may be about 1200 Å. Moreover, the thickness of one chip included in a wafer may be about 2850˜4150 Å, and a difference of the thickness of the chip may be about 1500 Å, according to the density of the chip.
When a wafer is polished and a contact is etched for a predetermined or given time, the contact may be un-etched or punched through due to the above-described differences, and thus a problem, such as a leak between the contact and a polysilicon, may occur.

SUMMARY

Example embodiments relates to apparatus for chemical-mechanical polishing and a method of chemical-mechanical polishing a material, e.g., a wafer, a metal layer, and/or an insulation layer.
In accordance with at least one example embodiment, a method of chemical-mechanical polishing includes re-polishing a polished layer on a wafer based on a measured thickness of the polished layer.
In accordance with at least one example embodiment, an apparatus for chemical-mechanical polishing may include a thickness measuring unit configured to measure a thickness of a polished surface on a wafer and to determine a re-polishing time based on the measured thickness.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-6 represent non-limiting, example embodiments as described herein.

FIG. 1 is a block diagram of an apparatus for chemical-mechanical polishing according to an embodiment of the present invention;

FIG. 2 is a flowchart of a method of chemical-mechanical polishing, according to an embodiment of the present invention;

FIG. 3 is a flowchart of a method of chemical-mechanical polishing, according to an embodiment of the present invention;

FIG. 4 is a graph showing change of a polishing amount according to durability of a polishing pad, when conventional chemical-mechanical polishing is performed;

FIG. 5 is a graph showing change of a polishing amount according to a durability of a polishing pad, when chemical-mechanical polishing according to an embodiment of the present invention is performed; and

FIG. 6 is a graph showing change of a thickness of an inter layer dielectric layer on the surface of a wafer, when a method of chemical-mechanical polishing according to an embodiment of the present invention is performed.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings. However, example embodiments are not limited to the embodiments illustrated hereinafter, and the embodiments herein are introduced to provide easy and complete understanding of the scope and spirit of example embodiments. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.
It will be understood that when an element, such as a layer, a region, or a substrate, is referred to as being “on,” “connected to” or “coupled to” another element, it may be directly on, connected, or coupled to the other element or intervening elements that may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
Spatially relative terms, such as “above,” “upper,” “beneath,” “below,” “lower,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “above” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes may not be intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
FIG. 1 is a block diagram of an apparatus configured to chemically and/or mechanically polish a material in accordance with an embodiment of the present invention. Referring to FIG. 1, the apparatus may include a polishing unit 11, and a cleaning unit 12. The polishing unit 11 may include a first platen 111, a second platen 112, a thickness measuring unit 113, and a third platen 114. Although only three platens are illustrated in FIG. 1, the polishing unit 11 may include more or less platens.
The polishing unit 11 may chemically and/or mechanically polish a material layer formed on a wafer, e.g., an insulation layer or a metal layer. The polishing unit 11 may also chemically and/or mechanically polish a surface of a wafer, for example, a back surface of a wafer. Hereinafter, for convenience of description, the material layer formed on the wafer and/or the surface of the wafer undergoing the polishing process are referred to generally as the surface of the wafer.
A first polishing pad may be attached to the top of the first platen 111, and a wafer may be disposed on the surface of the first polishing pad. The polishing unit 11 may reduce the thickness of the surface of the wafer by a first removal amount. The thickness may be reduced by supplying slurry while the wafer contacts the surface of the first polishing pad so as to chemically react the surface of the wafer with the slurry while operating the first platen 111 to mechanically polish the wafer. The wafer may be transferred while attached to a polishing head. During this polishing operation the wafer may be pressed against the first polishing pad and/or the first platen 111 to contact the first polishing pad and/or first platen 111. During this operation, the first polishing time may be fixed.
A second polishing pad may be attached to the top of the second platen 112, and the wafer having been polished by the first platen 111 may be disposed on the surface of the second polishing pad. The polishing unit 11 may reduce the thickness of the surface of the wafer over a second polishing time by removing a second removal amount. The thickness may be reduced by supplying slurry to chemically react with the surface of the wafer while the wafer contacts the surface of the second polishing pad and operating the second platen 112 in conjunction with the polishing head to mechanically polish the material. During this polishing operation, the wafer may contact the second polishing pad and may be pressed against the second polishing pad and/or the second platen 112. During this operation, the second polishing time may be fixed.
In accordance with at least one example embodiment, the amount of material removed by the first and second platens 111 and 112 may be about 50˜90% of the total removal amount.
The cleaning unit 12 may clean the wafer polished by the second platen 112 and may supply the cleaned wafer to the thickness measuring unit 113. In accordance with at least one example embodiment, the measuring unit 113 may be included in the polishing unit 11. In accordance with an example embodiment, the cleaning unit 12 may also clean the wafer polished by the third platen 114 and may supply the cleaned wafer again to the thickness measuring unit 113.
The thickness measuring unit 113 may determine a third polishing time for the wafer on the third platen 114. The third polishing time may be based on the measured thickness of the surface of the cleaned wafer. For example, when the thickness of the surface of the wafer is thicker than a target value, the thickness measuring unit 113 may increase the third polishing time, and when the thickness of the surface of the wafer is thinner than the target value, the thickness measuring unit 113 may decrease the third polishing time. In an example embodiment, when the method is performed on an inter layer dielectric (ILD) layer formed on the wafer, the thickness measuring unit 113 may determine the third polishing time by measuring the thickness of the ILD layer.
In accordance with an example embodiment, a time polish method, which may adjust a polishing time, may be used so that the polishing is performed up to a targeted thickness. The time polish method may be performed to reach a polishing target by performing the polishing for a predetermined or given time. In accordance with this example embodiment, the method may consider a polishing ratio (the number of polishing particles applied over a unit area of the polished surface) for polishing the wafer. In this embodiment, the wafer is re-polished by directly measuring the thickness of the wafer.
A third polishing pad may be attached to the top of the third platen 114, and the cleaned wafer may be disposed on a surface of third polishing pad. The polishing unit 11 may reduce the thickness of the surface of the wafer over a third polishing time by removing a third removal amount. The material may be removed by supplying a slurry to chemically react with the surface of the wafer while the wafer contacts the third polishing pad, and mechanically polishing the surface of the wafer by operating the third platen 114 in conjunction with the polishing head. Here, the sum of the first through third removal amounts may correspond to the targeted polishing amount of the wafer. The wafer polished by the third platen 114 may again be supplied to the cleaning unit 12. Here, the third polishing time may vary according to the result of the thickness measuring unit 113.
After cleaning the polished wafer, the cleaning unit 12 may supply the wafer again to the thickness measuring unit 113. Then, the thickness measuring unit 113 may measure the thickness of the surface of the wafer, and may determine whether the measured thickness is within a standard range. For example, when the measured thickness is within the standard range, i.e., when the measured thickness is close to the target thickness, the thickness measuring unit 113 may determine to output the wafer. Alternatively, when the measured thickness exceeds the standard range, i.e., when the measured thickness is thicker than the target thickness, the thickness measuring unit 113 may determine to output the wafer to the third platen 114 to remove more material. Alternatively, when the measured thickness is under the standard range, i.e., when the measured thickness is thinner than the target thickness, the thickness measuring unit 113 may determine to re-deposit a corresponding material layer on the surface of the wafer.
According to another example embodiment, the cleaning unit 12 may directly output the wafer instead of supplying the wafer to the thickness measuring unit 113, after cleaning the wafer.
FIG. 2 is a flowchart of a method for chemical-mechanical polishing, according to an example embodiment. The method performed on an ILD layer formed on a surface of the wafer, according to example embodiments, will now be described in time series with reference to FIGS. 1 and 2. However as described above, the method may also be applied on an insulation layer or a metal layer formed on the surface of the wafer, or the back surface of the wafer.
In operation 20, the ILD layer formed on the surface of the wafer is polished on a first platen P1 for a given or predetermined time.
In operation 21, the ILD layer polished on the first platen P1 is polished on a second platen P2 for a given or predetermined time.
In operation 22, the cleaning unit 12 cleans the polished wafer.
In operation 23, a re-polishing time is determined by measuring the thickness (Tox) of the ILD layer on the cleaned wafer. The re-polishing time may be determined in several ways. For example, the Tox may be used in conjunction with a look-up table, wherein the look-up table stores empirically determined re-polishing times based on the measured Tox. In the alternative, the re-polishing time may be determined by an equation, such as a polynomial, wherein the coefficients of the polynomial are determined empirically, the measured Tox is the input variable of the equation and the re-polishing time is the output of the equation.
In operation 24, the third platen P3 re-polishes the wafer for the re-polishing time.
In operation 25, the cleaning unit 12 may clean the re-polished wafer.
In operation 26, the Tox of the ILD layer on the cleaned wafer may be measured. In accordance with an example embodiment, operation 26 determines whether or not to remove more material from the substrate. For example, if the Tox of the ILD layer exceeds a standard range, operation 24 is performed; otherwise, if the Tox of the ILD layer is under the standard range (if the ILD layer has been overpolished), operation 27 is performed. Also, when the Tox is within the standard range, the method ends by outputting the wafer.
In operation 27, the ILD layer having a predetermined or given thickness may be re-deposited on the surface of the wafer.
FIG. 3 is a flow chart illustrating another method for chemical-mechanical polishing according to another example embodiment. The method illustrated in FIG. 3 is similar to the method of illustrated in FIG. 2. For example, steps 30, 31, 32, 33, 34, 35, 36, and 37 correspond to steps 20, 21, 22, 23, 24, 25, 26, and 27 illustrated in FIG. 2. In the example embodiment illustrated in FIG. 3, a first re-polishing time for a first re-polishing operation is determined by measuring the Tox of the ILD layer after the layer is polished in operations 30 and 31 and cleaned in operation 32. However, in the example embodiment illustrated in FIG. 3, the re-polishing time for subsequent re-polishing operations is re-determined based on the Tox of the ILD layer after the layer is re-polished. In other words, after the ILD layer has been re-polished for a first re-polishing time, the re-polished layer may be re-polished in subsequent re-polishing operations for re-determined re-polishing times based on the Tox of the ILD layer after the ILD layer has been re-polished.
The operation 33 determines and/or re-determines a re-polishing time by measuring the Tox of the ILD layer on a polished and/or re-polished wafer. The re-polishing time determined and/or re-determined in operation 33 may be determined and/or re-determined in several ways. For example, the Tox of the polished and/or re-polished ILD layer may be used in conjunction with a look-up table, wherein the look-up table stores empirically determined re-polishing times based on the measured Tox. In the alternative, the re-polishing time may be determined by an equation, such as a polynomial, wherein the coefficients of the polynomial are determined empirically, the measured Tox is the input variable of the equation and the re-polishing time is the output of the equation. As explained above, an initial re-polishing time may be based on the Tox of the ILD layer after the ILD layer has been polished and cleaned in operations 30, 31, and 32. Subsequent re-polishing times, for example, a second re-polishing time, are determined based on the Tox of the ILD after the ILD has been re-polished in steps 34 and 35.
The methods performed on the ILD layers formed on the wafer is illustrated in time series in FIGS. 2 and 3, however, the method may also be performed on a shallow trench isolation (STI) layer formed on the wafer. STI denotes forming a trench for electrical isolation of a semiconductor device. The method performed on the STI layer will now be described in brief. First, a silicon nitride is deposited on a wafer, and a trench may be formed in the wafer using an optical lithography process and/or a dry etching process. The external wall of the trench is oxidized via a high-temperature heating process, and the internal trench is filled with oxide using a quick depositing method. An oxide layer is removed via a CMP process, and the remaining nitride layer may be removed using a plasma etching method. Accordingly, a trench filled only with an insulating material is formed, thereby electrically separating a semiconductor device.
Also as described above, the method may be applied to a metal layer formed on the wafer, for example, the method may be applied to a damascene process. Here, the damascene process may be used while manufacturing metal wiring in a semiconductor. The damascene process may use metals such as aluminum, tungsten, copper, etc.
When the metal wiring process uses aluminum, the aluminum may be deposited on a surface of the wafer, and an aluminum wiring pattern may be formed using an optical lithography process and/or a dry etching process. An oxide layer may be coated around the metal wiring for insulation, and performing the polishing method flattens the required areas.
When the metal wiring process uses copper, an insulation oxide layer may be formed on a surface of the wafer, and a patterning on a photosensitive layer may be performed via an optical lithography process. A wiring line may be formed inside the insulation oxide layer via a dry etching process. The copper may be coated by using an electroplating method, and materials, except for the copper, may be removed from inside the wiring line by polishing the materials using an electroplating method. The metal wiring process using copper may be completed by re-depositing the insulation oxide layer on the metal wiring.
FIG. 4 is a graph illustrating the amount of material removed (polishing amount) from a material, for example, a wafer, as a function of the condition or age of the polishing pad (durability) over a given or predetermined length of time when using a conventional chemical-mechanical polishing system.
Referring to FIG. 4, the abscissa denotes the condition or age of a polishing pad (durability) in seconds and the vertical axis denotes the amount of material removed (polishing amount) in Å units. In particular, the left side of the abscissa represents the condition of a new pad and the right side of the abscissa represents the condition of an old pad. The polishing amount per second of the polishing pad used in an apparatus for chemical-mechanical polishing decreases as the polishing pad is used for a relatively long time. For example, when a new polishing pad is used, the polishing amount per second may be about 35.7 Å/s, and when an old polishing pad is used, the polishing amount per sec. may be about 25.3 Å/s. In accordance with this example, when a target polishing amount is, for example, 2200 Å, the actual polishing amount may be between about 1900˜2500 Å according to the condition or age of the polishing pad, and thus approximately 600 Å of variation may exist in the material removed using the conventional chemical-mechanical polishing system.
FIG. 4 illustrates the variation of the polishing amount according to the durability of the polishing pad, but FIG. 4 is only an exemplary embodiment, and the variation of the polishing amount according to the durability of the polishing head and a disk may show similar results.
According to the conventional chemical-mechanical polishing, the surface thickness of a wafer input to a polishing unit, i.e., an unpolished wafer, may be measured, and then a third polishing time for performing polishing on a third platen may be determined. In this case, a difference between the thickness of the inputted wafer and a target thickness may be quite large, and thus the extra material to be removed may also be quite large. Accordingly, the required amount of material to be removed may be large. Also, the variation of the removal amount may increase according to the durability of polishing pad, durability of the disk, and/or the variation of the polishing head.
FIG. 5 is a graph showing change of a polishing amount according to a durability of a polishing pad, when chemical-mechanical polishing according to example embodiments is performed. Referring to FIG. 5, the horizontal axis denotes the durability of a polishing pad or a disk, and the vertical axis denotes a polishing amount in Å units. For example, when a target polishing amount is 440 Å, the actual polishing amount is 380˜535 Å according to the durability of the polishing pad or disk, and thus variation of approximately 155 Å exists.
According to example embodiments, the surface thickness of a wafer input to a polishing unit is not measured, rather the surface thickness of a wafer that is polished for a predetermined or given time after being input to the polishing unit, for example, a wafer that is polished on first and second platens, is measured. Accordingly, a removal amount that is substantially polished by a third platen reduces, and thus, variation of the removal amount also reduces. Consequently, a difference between thicknesses of surfaces of wafers that is chemically and/or mechanically polished, or chips inside a wafer is not large.
FIG. 6 is a graph showing change of a thickness of an ILD layer on the surface of a wafer, when a method of chemical-mechanical polishing according to example embodiments is performed. Referring to FIG. 6, when a target thickness (Tox) of the ILD layer is 3500 Å, a variation of about 500 Å may occur according to a conventional method. However, according to at least one example embodiment, when the target thickness is about 3100 Å, a variation of approximately 140 Å may occur. Accordingly, by using the method of chemical-mechanical polishing of example embodiments, a difference in thicknesses between lots, wafers, or ILD layers between chips inside a wafer can be reduced.
According to at least one example embodiment, a method of chemical-mechanical polishing may include polishing an insulation layer formed on a wafer for a first polishing time, measuring the thickness of the polished insulation layer, determining a second polishing time for the insulation layer based on the measured thickness, and re-polishing the insulation layer for the second polishing time. Accordingly, thickness deviation between different lots, wafers, or chips inside a wafer is remarkably reduced regardless of the durability of a polishing pad, a polishing head, or a disk used in a polishing apparatus.
At least one example embodiment may also be embodied as computer readable codes on a computer readable recording medium. The computer readable recording medium may be any data storage device that may store data, which may be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, optical data storage devices, and carrier waves (such as data transmission through the Internet). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code may be stored and executed in a distributed fashion. Here, a program stored in a recording medium may be expressed in a series of instructions used directly or indirectly within a device with a data processing capability, for example, computers. Thus, a term “computer” may involve all devices with data processing capability in which a particular function may be performed according to a program using a memory, input/output devices, and arithmetic logics.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages of example embodiments. Accordingly, all such modifications are intended to be included within the scope of the claims. Therefore, it is to be understood that the foregoing is illustrative of example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. Example embodiments are defined by the following claims, with equivalents of the claims to be included therein.

Claims

1. A method of chemical-mechanical polishing, the method comprising:

first re-polishing of a polished layer on a wafer based on a measured thickness of the polished layer.

2. The method of claim 1, further comprising:

polishing a layer on the wafer to form the polished layer;

measuring a thickness of the polished layer;

first determining a re-polishing time based on the measured thickness; and wherein

the first re-polishing step re-polishes the polished layer for the determined re-polishing time.

3. The method of claim 2, wherein the polishing step comprises:

polishing the layer for a first fixed time on a first platen; and

polishing the layer for a second fixed time on a second platen.

4. The method of claim 2, wherein the first re-polishing step re-polishes the polished layer on a third platen for the determined re-polishing time.

5. The method of claim 2, further comprising:

first cleaning the wafer after the polishing step and before the first re-polishing step.

6. The method of claim 5, wherein the measuring step measures the thickness of the polished layer after the first cleaning step.

7. The method of claim 2, further comprising:

measuring the thickness of the re-polished layer;

second determining whether to re-polish the re-polished layer based on the measured thickness of the re-polished layer; and

second re-polishing the re-polished layer if the second determining step determines to re-polish the re-polished layer.

8. The method of claim 7, further comprising:

second cleaning the wafer after the second re-polishing step.

9. The method of claim 8, wherein the measuring the thickness of the re-polished layer step measures the thickness of the re-polished layer after the second cleaning step.

10. The method of claim 7, wherein the second re-polishing step re-polishes the re-polished layer on the third platen for the re-polishing time.

11. The method of claim 7, further comprising:

determining a second re-polishing time if the second determining step determines to re-polish the re-polished layer.

12. The method of claim 11, wherein the second re-polishing time is based on a measured thickness of the re-polished layer.

13. The method of claim 11, wherein the second re-polishing step re-polishes the re-polished layer on the third platen for the second re-polishing time.

14. The method of claim 2, wherein the polishing step removes 50˜90% of a total amount of the layer removed by the method.

15. The method of claim 1, wherein the layer is an insulation layer.

16. The method of claim 15, wherein the layer is at least one of an inter-layer dielectric layer and a shallow trench isolation layer.

17. The method of claim 1, wherein the layer is a metal layer.

18. The method of claim 17, wherein the metal layer includes any one of tungsten (W), aluminum (Al), and copper (Cu) layers.

19. The method of claim 7, wherein the second determining step determines whether the layer has been overpolished based on the measured thickness of the re-polished layer.

20. The method of claim 19, further comprising:

redepositing a layer on a surface of the wafer if the second determining step determines the layer has been overpolished.

21-25. (canceled)