US20090289372A1 - Power Supply Network - Google Patents
Power Supply Network Download PDFInfo
- Publication number
- US20090289372A1 US20090289372A1 US12/306,898 US30689807A US2009289372A1 US 20090289372 A1 US20090289372 A1 US 20090289372A1 US 30689807 A US30689807 A US 30689807A US 2009289372 A1 US2009289372 A1 US 2009289372A1
- Authority
- US
- United States
- Prior art keywords
- power supply
- current
- grid
- supply
- supply network
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
- The invention relates to an integrated circuit, and in particular relates to an improved power supply network for an integrated circuit.
- In an integrated circuit or a system-on-chip (SoC), a power supply network is provided to supply the components in the circuit with power from an external power supply. A conventional power supply network consists of a power network and a ground network.
- A power supply network is characterized by its structure or topology, i.e. metal layers used, grid structure versus tree structures or combinations of these, distances between wires and/or grid meshes, and the width of the wires. Supply pads and a peripheral supply ring surrounding the internal grid structure are also considered to be part of the power supply network.
- Power integrity is a key parameter in characterising and controlling integrated circuit and SoC functionality and performance. The decreasing component sizes in deep sub-micron technologies allows packing densities to be increased with more functional blocks in an integrated circuit, with the supply and threshold voltages in the circuit being reduced accordingly. On the other hand, the switching current and switching speed increase. A consequence of decreasing the supply voltage is that the acceptable level of voltage drop in the power supply network also decreases. However, the actual voltage drop increases due to increased resistance in the power supply network from thinner wires, and increased supply current levels. A similar effect to voltage drop in the power network occurs in the ground network, and is called voltage rise. Voltage drop in the power supply network comprises both voltage drop in the power network and voltage rise in the ground network.
- One conventional way of reducing the voltage drop (otherwise known as the IR-drop, from V=IR) across the power supply network for an integrated circuit is to widen all of the wires of the power supply network. This results in the resistance of these wires being reduced. However, this also uses routing resources which could otherwise be used for signal and clock wires.
- In reducing the IR-drop to specified limits, the area occupied by the supply grid in an SoC is increased to such proportions that it seriously impacts the available routing resources for data and clock signals. In many designs, the supply grid requires an extra metal layer, which increases production costs. The area required by the supply grid can be reduced if the supply grid is made with narrower wires and if a larger width (and hence lower-resistance) peripheral supply ring is applied around the supply grid. However, the penalty is SoC area. Instead of an area-consuming peripheral supply ring, an increased amount of supply pads can be applied if there is space in the input/output ring. However, the SoC package costs will be increased. If there is no space in the input/output ring, adding supply pads will also increase SoC area.
- U.S. Pat. No. 5,767,011 describes a fabrication method for integrated circuits and a resulting structure. The method includes adding power lines and/or increasing the width of power lines and/or adding a power bus near regions of high current flow.
- It is an object of the invention to provide a power supply network for an integrated circuit having a low IR-drop in the power network and a low voltage-rise in the ground network, which minimises the required chip area and/or routing resources for the power supply network.
- It has been recognised that the connection between the supply pads and the supply grid is quite small, which means that current spreading into the supply grid is very poor. In accordance with the invention, a more efficient solution (in terms of resource cost and space required) is to improve the conducting fields in the supply grid adjacent to the supply pads. This is achieved using current spreaders which are formed to have a lower electrical resistance than the wires in the supply grid and which connect a number of wires in the internal grid to the supply pads, thereby minimising the routing resources and/or additional silicon area required.
- In accordance with a first aspect of the invention, there is provided a power supply network for an integrated circuit, the power supply network comprising a supply grid; a plurality of supply pads, each supply pad being in electrical contact with an edge of the supply grid; a current spreader for at least one of the plurality of supply pads, each current spreader being in electrical contact with a respective supply pad and the supply grid; each current spreader being sized so that it overlaps with a respective portion of the supply grid; and each current spreader having a lower electrical resistance than the supply grid.
- The current spreaders in accordance with invention provide an advantage that the IR-drop in the power network and/or voltage-rise in the ground network can be reduced, whilst minimising the required chip area and/or routing resources for the power supply network.
- Preferably, each current spreader comprises a metal plate, as this is simple to implement in a power supply network.
- Furthermore, it is preferred if the metal plate is slotted, as this reduces the mechanical stress in the power supply network.
- In a preferred embodiment of the invention, the supply grid comprises first and second sets of wires, the first set of wires being oriented perpendicularly to the second set of wires.
- Preferably, each current spreader comprises metallic strips which are wider than and overlap with the wires in the respective portion of the supply grid. This further reduces the area that the current spreaders occupy in the power supply network.
- Preferably, each of the current spreaders is sized such that it extends along the respective edge of the supply grid by a distance that is greater than the distance the current spreader extends into the supply grid from the respective edge, as this minimises the impact of the current spreader on interconnect routing in the integrated circuit.
- In one embodiment, the current spreaders are substantially rectangular in shape, as this is very economical and is simple to design.
- Alternatively, the current spreaders are substantially semi-circular in shape, as this implementation is very area efficient.
- Preferably, there is a current spreader for each of the plurality of supply pads, as this allows the improvement in the IR-drop to be maximised.
- Preferably, the power supply network is for supplying power and ground to the integrated circuit.
- Preferably, each of the supply pads are for connection to a respective one of a power supply or a ground.
- Preferably, in a region in which a current spreader for the power and a current spreader for the ground overlap, the current spreaders are interleaved using a comb structure.
- In particular embodiments, the supply grid is formed in one or more metallization layers.
- In one embodiment, the current spreaders are formed in the same metallization layer or layers as the supply grid, which means that the resources required for the current spreader are reduced.
- Alternatively, the current spreaders are formed in a different metallization layer or layers to the supply grid.
- In preferred embodiments, the current spreaders are formed in a post-passivation layer, which provides a very cheap way of decreasing the IR-drop.
- In accordance with a second aspect of the invention, there is provided an integrated circuit that comprises a power supply network as described above.
- The invention will now be described, by way of example only, with reference to the following drawings, in which:
-
FIG. 1 shows a power supply network in accordance with a first embodiment of the invention; -
FIG. 2 shows a power supply network in accordance with a second embodiment of the invention; -
FIG. 3 is a cross-section of an integrated circuit that includes a current spreader in accordance with the invention; -
FIG. 4 is a cross-section of an integrated circuit in which the current spreader is patterned in a post passivation layer; -
FIG. 5 shows part of a power supply network in accordance with a third embodiment of the invention; and -
FIG. 6 shows a power supply network in accordance with a fourth embodiment of the invention; -
FIG. 7 shows a power supply network in accordance with a fifth embodiment of the invention; -
FIG. 8 is a top view of two overlapping current spreaders in accordance with a sixth embodiment of the invention; and -
FIG. 9 is a graph showing the difference in IR-drop for five different power supply network configurations. - As described above, in an integrated circuit or a system-on-chip (SoC), a power supply network is provided to supply the components in the circuit with power from an external power supply. The power supply network comprises a power network and a ground network. In the following, the term “power supply network” is intended to cover either or both of the power network and the ground network. Thus any reference in this specification to IR-drop or an improvement or reduction in IR-drop in a power network is equally applicable to voltage rise or an improvement or reduction in voltage rise in a ground network.
- In a conventional power supply network design, the connection between the supply pads and the supply grid is quite small, which means that current spreading in the supply grid is very poor. It is known that reducing the resistance in the supply grid is effective in reducing the IR-drop in the power supply network. However, it has now been recognised that it is only necessary to reduce the resistance of the supply grid near to the supply pads in order to provide an effective improvement in the IR-drop. Therefore, in accordance with the invention, a more efficient solution (in terms of resource cost and space required) is to improve the conducting fields in the supply grid adjacent to the supply pads.
-
FIG. 1 shows apower supply network 2 in accordance with the invention. Thenetwork 2 comprises asupply grid 4, a plurality ofsupply pads 6 located around thesupply grid 4, each in electrical contact with an edge of thesupply grid 4, and acurrent spreader 8 for each of the plurality ofsupply pads 6, eachcurrent spreader 8 being in electrical contact with arespective supply pad 6 and thesupply grid 4. The dash-dot lines in the FIGS. indicate a break in the drawing. It will be appreciated that the drawings of the power supply network are not to scale. - Although in the following description of the invention each
supply pad 6 in thepower supply network 2 is illustrated as having an associatedcurrent spreader 8, it will be appreciated that in alternative embodiments of the invention, a respectivecurrent spreader 8 may be provided only for some of thesupply pads 6 in thepower supply network 2. - The
supply grid 4 comprises a plurality of conducting stripes or wires. Although thesupply grid 4 is shown as being substantially square in shape, it will be appreciated that thesupply grid 4 can be any required shape. - In this illustrated embodiment, although the
supply grid 4 has anouter ring 10 in electrical contact with the other wires in thegrid 4, thisring 10 is considerably narrower than a conventional peripheral power ring. For example, in the illustrated embodiment, theouter ring 10 has a width that is comparable or equal to the width of the other wires in thegrid 4, whereas a conventional peripheral power ring would be of the order of 50 times the width of the other wires in the grid. As a result of this significant reduction in width, theouter ring 10 should not be considered to be a peripheral power ring. - In an alternative embodiment of the invention, the
outer ring 10 may be omitted from thepower supply network 2 entirely. - As illustrated, there are four
supply pads 6 in this embodiment of the invention, with onesupply pad 6 being located towards the middle of each edge of thesupply grid 4. In an alternative embodiment of the invention, more than onesupply pad 6 per edge of thegrid 4 may be provided. In a further alternative embodiment of the invention, thesupply pads 6 may be arranged around thesupply grid 4 so that one or more edges of thegrid 4 does not have asupply pad 6 attached. - As described, a
current spreader 8 is provided for eachsupply pad 6 and is in electrical contact with thesupply pad 6 and thesupply grid 4. The function of eachcurrent spreader 8 is to improve the electrical contact between thesupply pads 6 and thesupply grid 4, and they are formed so that they have a lower electrical resistance than the wires in thesupply grid 4. When viewing thepower supply network 2 from above, thecurrent spreaders 8 extend into thesupply grid 4 from theirrespective supply pad 6 and thus overlap with a respective portion of thesupply grid 4. - As described above, this
grid 4 can be either power or ground, or, if multiple power domains are required, one or more of power1, power2, etc. - The
current spreaders 8 may be formed in the same metallization layer as thesupply grid 4, in which case thecurrent spreaders 8 are integrally formed with the wires in thesupply grid 4. In alternative embodiments, thecurrent spreaders 8 may be formed in a different metallization layer to thesupply grid 4, in which case thecurrent spreaders 8 are a separate structure to the wires in thesupply grid 4. In further alternative embodiments which are discussed later in more detail, thesupply grid 4 may be formed in two or more metallization layers, which means that respective parts of thecurrent spreaders 8 can also be formed in each of those layers. - In the illustrated embodiment, the
current spreader 8 is a full metal plate, sized so that it effectively overlaps a portion of thesupply grid 4. The full metal plate covers thesupply pad 6 completely and extends towards the core area of the integrated circuit. Alternatively, as illustrated inFIG. 2 , the full metal plate may have small holes in it to relieve mechanical stress. As a further alternative, thecurrent spreaders 8 can be formed as a grid which may be denser than thesupply grid 4. The highest metal density yields the most efficient implementation. - The
current spreaders 8 can be patterned in any metallization layer in the integrated circuit process, although it is preferable to use the higher and thicker layers. In one embodiment, thecurrent spreader 8 can be patterned in a post passivation layer which is an extra metal layer that is usually patterned in, but not limited to, point-to-point connections on top of a finished integrated circuit for relocation of the input, output and/orsupply pads 6. The post passivation layer may be an aluminium layer. The passivation layer is used to protect the underlying integrated circuit from damage by mobile ions, moisture, transition metals, and contamination. One type of post passivation layer is known as an ALUCAP layer or RDL (redistribution layer). - The
current spreader 8 is connected to thesupply grid 4 that is associated with thesupply pad 6 with vias through the passivation layer. Locatingcurrent spreaders 8 in this layer provides a very cheap way of decreasing the IR-drop. - As described above, the
current spreaders 8 may be located in the same layer as thesupply grid 4 or in other layers within the integrated circuit. -
FIG. 3 is a cross-section of anintegrated circuit 50 that includes a current spreader in accordance with the invention. In the FIG., which is not to scale, there is a silicon (or other suitable material)substrate 52 in and on whichelectronic devices 54, for example MOST, bipolar transistors, etc. are formed. In afirst dielectric layer 56 above theseelectronic devices 54 are viacontacts 58, which connect theelectronic devices 54 to a set ofthin metal layers 60 above thedielectric layer 56. In the FIG., viacontacts 58 are represented by solid rectangles. Thesevias 58 form an electrical contact between theelectronic devices 54 in thesubstrate 52 and the set of thin metal layers 60.Interconnect wires 62 are patterned in two of the thin metal layers in theset 60. In a dielectric layer above one of the thin metal layers are viacontacts 58 to the next metal layer. Thesevias 58 form an electrical contact between thewires 62 in one metal layer to thewires 62 in the next metal layer. The set ofthin metal layers 60 comprise a number of thin metal and dielectric layers stacked on top of each other. - In general,
wires 62 in successive metal layers alternate in the horizontal and vertical directions, which is represented inFIG. 3 with narrow rectangles forwires 62 that run perpendicularly to the surface of the page, and wide rectangles forwires 62 that run parallel to the surface of the page. - On top of the set of thin metal layers 60 is a set of thick metal layers 64.
Interconnects interconnects 62 in the set of thin metal layers 60. - In this illustrated embodiment of the invention, the current spreaders are patterned in one or more of the thick metal layers in the
set 64. In the FIG., the current spreader is made in the two top metal layers frominterconnects power 66 a are in sets of three, which are drawn as running perpendicularly to the surface of the page. The ground wires, labelled 66 b, and illustrated with a dashed outline, are located between the set of threepower wires 66 a. Thecurrent spreader wire 68 for power runs parallel to the surface of the page, and is located in the topmost metal layer of theset 64. Apassivation layer 70 is located on top of the set of thick metal layers 64. -
FIG. 4 shows an integrated circuit in which the current spreader is patterned in a post passivation layer. InFIG. 4 , elements of theintegrated circuit 50 that are common to the integrated circuit inFIG. 3 have been given the same reference numeral. - In this illustrated embodiment, there are vias 58 through the
passivation layer 70 which extend to apost-passivation metal layer 72. The current spreader can be formed in thispost-passivation metal layer 72. The current spreader can be formed in combination with current spreaders in the set of thin orthick metal layers post-passivation layer 72 which connects to a power grid formed in the set of thin orthick metal layers further passivation layer 74 is located above thepost-passivation layer 72. - Ideally, the
current spreaders 8 should be as large as possible. However if the layer or layers in which thecurrent spreaders 8 are patterned is used for other interconnects, thecurrent spreaders 8 must be shaped so that they achieve the most efficient improvement in the IR-drop whilst minimising the impact on the other connections that use that layer. Eachcurrent spreader 8 will extend into thesupply grid 4 from itsrespective supply pad 6. It will be appreciated that any shape ofcurrent spreader 8 may be used in accordance with the invention, although it is preferable that thecurrent spreaders 8 are wider than they are deep. In other words, it is preferable that thecurrent spreader 8 extends a distance along the edge of thesupply grid 4 that is greater than the distance thecurrent spreader 8 extends in towards the centre of thesupply grid 4. - For example, in the embodiments of the invention illustrated in
FIGS. 1 and 2 , thecurrent spreaders 8 have a rectangular shape, with therespective supply pad 6 being located in line with the centre of a long edge of thecurrent spreader 8. A rectangularcurrent spreader 8 is very economical and is simple to design. -
FIG. 5 shows apower supply network 2 in accordance with a third embodiment of the invention. Thepower supply network 2 is as described above with reference toFIGS. 1 and 2 withcurrent spreaders 8 having a rectangular shape. However, thecurrent spreaders 8 are oriented so that they extend into thesupply grid 4 further than they extend along the edge of thesupply grid 4. In other words, thecurrent spreaders 8 are deeper than they are wide. -
FIG. 6 shows apower supply network 2 in accordance with a fourth embodiment of the invention. Thepower supply network 2 is as described above with reference toFIG. 1 . However, in this embodiment, thecurrent spreaders 8 have a semi-circular profile, with the centre of the circle being located in line with therespective supply pad 6. This implementation of thecurrent spreaders 8 is very area efficient. -
FIG. 7 shows a part of apower supply network 2 in accordance with a fifth embodiment of the invention. In this embodiment, there is apower supply grid 82 and aground supply grid 84. Thepower supply grid 82 comprises interconnectedhorizontal wires 86 andvertical wires 88, and theground supply grid 84 comprises interconnectedhorizontal wires 90 andvertical wires 92. - The
supply grids horizontal wires vertical wires horizontal wires FIG. 7 with lines that are filled with dots whilst thevertical wires FIG. 7 with lines that are clear. Thewires power supply grid 82 are illustrated with a solid outline, whilst thewires ground supply grid 84 are illustrated with a dashed outline. Thepower supply grid 82 andground supply grid 84 are formed by interconnecting the appropriate wires in the two metallization layers withvias 93. - In this illustrated embodiment, a
current spreader 8 is provided for thepower supply grid 82 which is in electrical contact with arespective supply pad 6 and thepower supply grid 82. Thecurrent spreader 8 comprises horizontal metallic strips 94 (which are dotted like thehorizontal wires vertical wires 88, 92) that are formed integrally with respective wires in thepower supply grid 82. The horizontal and verticalmetallic strips vertical wires power supply grid 82, so they therefore have a lower resistance. - Thus, as the
power supply grid 82 is formed in two metallization layers, thecurrent spreader 8 is also formed in two layers, with one part of the current spreader 8 (the horizontal metallic strips 94) being formed integrally with thehorizontal wires 86 in the first metallization layer and a second part (the vertical metallic strips 96) being formed integrally with thevertical wires 88 in the second metallization layer. The two parts of thecurrent spreader 8 can be interconnected withvias 93 as illustrated, and/or they may both be in separate electrical contact with therespective supply pad 6. The two parts of thecurrent spreader 8 may have the same or a different overall shape, which may depend on the local layer requirements in the integrated circuit. - Each horizontal and vertical
metallic strip vertical wires FIG. 7 , or may comprise a number of parallel strips perwire power supply grid 82 that are interconnected to form a composite strip that is much wider than arespective wire - The illustrated
current spreader 8 is rectangular in shape, which extends a distance r into thepower supply grid 82, and has a width of 2r. -
FIG. 8 shows a top view of a pair of current spreaders for a power supply grid and a ground supply grid respectively in accordance with a sixth embodiment of the invention. In this embodiment, apower supply pad 98 for a power supply grid is located close to aground supply pad 100 for a ground supply grid and the preferred areas for thecurrent spreaders current spreaders comb structure 106 is used in the overlapping area. Thecurrent spreaders - It will be appreciated that when the
current spreaders FIG. 7 (i.e. they are both formed in two layers of the integrated circuit), aseparate comb structure 106 is used in the overlapping area of each layer. - The
comb structure 106 is preferably sized so that thecurrent spreaders - As an example of the effectiveness of the current spreaders in accordance with the invention, consider an integrated circuit as illustrated in
FIG. 2 . For ease of explanation, the ground grid is not illustrated inFIG. 2 , and thesupply grid 4 shown inFIG. 2 is considered to be a power supply grid. - The core of electronic circuits and active cells is of size 8.8×8.8 mm2. The power grid and a ground grid have been designed in two metal layers of equal thickness and resistivity. The lower metal layer comprises 175 power wires and 175 ground wires in the horizontal direction and the upper metal layer comprises 175 power wires and 175 ground wires in the vertical direction. The pitch between the power wires is 50 μm, and the pitch between ground wires is also 50 μm. The power and ground lines are interleaved, so that the pitch between each subsequent power and ground wire is 25 μm. The width of each power wire and each ground wire in the grid is 5 μm, so that the metal coverage of the power grid is 10% in each layer and the metal coverage of the ground grid is also 10% in each layer.
- A
power supply pad 6 is provided in the middle of each side of thegrid 4. The ground supply pads are not shown. In the following, only the IR-drop of the power grid will be discussed, although similar results are obtained for the voltage rise in the ground supply network. - At each
power supply pad 6, a rectangularcurrent spreader 8 has been provided, although thecurrent spreaders 8 are not drawn to scale. In the following example, thecurrent spreaders 8 are removed if a peripheral power ring is applied. Furthermore different shapes ofcurrent spreaders 8 are considered with thecurrent spreader 8 being in both layers as in the embodiment described with reference toFIG. 7 or in either one of the two layers. - Five different configurations are considered in this example. The first configuration is a conventional power grid without any current spreaders or a peripheral power ring. This configuration would correspond to that shown in any of
FIGS. 1 , 2, 5 or 6 with thecurrent spreaders 8 removed. - The second configuration comprises a conventional power grid having a power ring with an electrical width of 165 μm, which is 33 times the width of a power wire. Due to technological constraints, the geometrical width is 200 μm. In the following, the peripheral ring is designed around the supply grid, which increases the size to 9.2×9.2 mm2. It should be noted that in practice it might be possible for the power ring to be internal to the core, so no increase in area occurs.
- The third configuration is a power supply network as shown in
FIG. 2 . Eachsupply pad 6 is connected to a rectangularcurrent spreader 8. The layout of thecurrent spreader 8 is substantially as depicted inFIG. 7 . The size of eachcurrent spreader 8 is 1.1×0.55 mm2. The metal coverage in each metal layer is 80% for the power grid. The metal coverage in each layer for the ground grid is 10%. - The fourth configuration is similar to the third configuration, but the
current spreaders 8 are rotated by 90°, so that they are oriented as shown inFIG. 5 . - The fifth configuration is again similar the third configuration, but the
current spreaders 8 correspond in shape to those shown inFIG. 6 . The area of each semi-circularcurrent spreader 8 is equal to that of each of thecurrent spreaders 8 in the third and fourth configurations. -
FIG. 9 is a graphical illustration of the effectiveness of the various configurations in reducing the IR-drop in a power supply network. The different configurations are shown across the horizontal axis of the graph, with the IR-drop shown on the vertical axis. The IR-drop has been normalised so that the IR-drop experienced in the first configuration, which corresponds to a conventional power supply network with no current spreaders or a peripheral power ring, is 1. - It can be seen that there is around a 62% improvement in the IR-drop in the second configuration, which corresponds to a conventional power supply network with a peripheral power ring.
- Each of the third, fourth and fifth configurations have been analysed with three different arrangements for the
current spreaders 8. The first arrangement corresponds to the structure shown inFIG. 7 in which there are both horizontal and verticalmetallic stripes FIG. 9 . - The second arrangement, whose IR-drop is represented graphically by a cross in
FIG. 9 , corresponds to a current spreader structure as shown inFIG. 7 with the horizontalmetallic strips 94 removed. - The third arrangement, whose IR-drop is represented graphically by a hollow dot in
FIG. 9 , corresponds to a current spreader structure as shown inFIG. 7 with the verticalmetallic strips 96 removed. - It can be seen that a peripheral power ring as in the second configuration reduces the IR-drop by around 62%. It can also be seen that the current spreaders in the third, fourth and fifth configurations reduce the IR-drop by an equivalent amount to the peripheral power ring when the current spreaders are in accordance with the first arrangement.
- However, the area required by the peripheral power ring is 4×0.2×8.8 mm2=7 mm2, whilst the area required by the current spreaders is only 4×0.605 mm2=2.4 mm2. Thus, the current spreaders provide the same IR-drop as the peripheral power ring whilst using almost 3 times less area.
- It can also be seen that current spreaders in accordance with the second and third arrangements reduce the IR-drop by around 50% and 25% respectively with respect to the first configuration. Thus, a current spreader with widened wires directed towards the centre of the supply grid is more effective in reducing the IR-drop than a current spreader with widened wires running parallel to the edge of the supply grid.
- It will be noted that this difference is more pronounced for the fourth configuration, but this configuration has the disadvantage that the current spreader extends further towards the centre of the supply grid than the third or fifth configurations, which means that it is more likely to obstruct interconnect routing in the integrated circuit.
- However, it will be appreciated that the current spreaders are more effective in reducing the IR-drop when they are in accordance with the first arrangement.
- It has also been noted that the full plate current spreaders have properties that are similar to the two layer current spreaders that comprise horizontal and vertical wires.
- There is therefore provided a power supply network for an integrated circuit or system-on-chip having a low IR-drop, in which the required chip area and routing resources are minimised. In particular, when there is little routing at the periphery of the integrated circuit, the
current spreaders 8 may occupy all of the available metal in the higher metal layers in which thesupply grid 4 is patterned, which means that the use ofcurrent spreaders 8 will not increase the silicon area required for the integrated circuit. When there are signal interconnects at the periphery of the integrated circuit, thecurrent spreaders 8 may require some additional silicon area, which at most may be equal to the total area of thecurrent spreaders 8. - While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustrations and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.
- Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.
Claims (21)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06116377 | 2006-06-30 | ||
EP06116377.0 | 2006-06-30 | ||
EP06116377 | 2006-06-30 | ||
PCT/IB2007/052354 WO2008004151A2 (en) | 2006-06-30 | 2007-06-19 | Power supply network |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090289372A1 true US20090289372A1 (en) | 2009-11-26 |
US7928567B2 US7928567B2 (en) | 2011-04-19 |
Family
ID=38723869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/306,898 Active 2028-03-12 US7928567B2 (en) | 2006-06-30 | 2007-06-19 | Power supply network |
Country Status (6)
Country | Link |
---|---|
US (1) | US7928567B2 (en) |
EP (1) | EP2038927A2 (en) |
JP (1) | JP2009543325A (en) |
CN (1) | CN101479848B (en) |
TW (1) | TW200824086A (en) |
WO (1) | WO2008004151A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8594604B2 (en) * | 2009-12-18 | 2013-11-26 | Nxp, B.V. | Fringe capacitor circuit |
US8581343B1 (en) * | 2010-07-06 | 2013-11-12 | International Rectifier Corporation | Electrical connectivity for circuit applications |
CN111443652B (en) * | 2020-03-24 | 2021-06-18 | 深圳市紫光同创电子有限公司 | Power supply structure of CPLD (complex programmable logic device) logic unit array |
US11749670B2 (en) * | 2020-05-18 | 2023-09-05 | Taiwan Semiconductor Manufacturing Company Limited | Power switch for backside power distribution |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5767011A (en) * | 1993-12-14 | 1998-06-16 | Oki Semiconductor, An Operating Group Of Oki America, Inc. Or Oki America, Inc. | Fabrication method for integrated circuits |
US6649509B1 (en) * | 2000-10-18 | 2003-11-18 | Megic Corporation | Post passivation metal scheme for high-performance integrated circuit devices |
US6809419B2 (en) * | 2002-09-20 | 2004-10-26 | Hitachi, Ltd. | Semiconductor device |
US7135759B2 (en) * | 2000-10-27 | 2006-11-14 | Texas Instruments Incorporated | Individualized low parasitic power distribution lines deposited over active integrated circuits |
US7230340B2 (en) * | 2000-10-18 | 2007-06-12 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US7335992B2 (en) * | 2004-03-29 | 2008-02-26 | Nec Electronics Corporation | Semiconductor apparatus with improved yield |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3727220B2 (en) | 2000-04-03 | 2005-12-14 | Necエレクトロニクス株式会社 | Semiconductor device |
WO2004077556A1 (en) * | 2003-02-26 | 2004-09-10 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit device and its power supply wiring method |
JP2005150556A (en) * | 2003-11-18 | 2005-06-09 | Sharp Corp | Layout design-support system of semiconductor integrated circuit, slit-creating method of interconnection, and automatic slit-creating device |
-
2007
- 2007-06-19 CN CN2007800245755A patent/CN101479848B/en active Active
- 2007-06-19 WO PCT/IB2007/052354 patent/WO2008004151A2/en active Application Filing
- 2007-06-19 US US12/306,898 patent/US7928567B2/en active Active
- 2007-06-19 EP EP07789732A patent/EP2038927A2/en not_active Withdrawn
- 2007-06-19 JP JP2009517517A patent/JP2009543325A/en active Pending
- 2007-06-27 TW TW096123231A patent/TW200824086A/en unknown
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5767011A (en) * | 1993-12-14 | 1998-06-16 | Oki Semiconductor, An Operating Group Of Oki America, Inc. Or Oki America, Inc. | Fabrication method for integrated circuits |
US6649509B1 (en) * | 2000-10-18 | 2003-11-18 | Megic Corporation | Post passivation metal scheme for high-performance integrated circuit devices |
US7230340B2 (en) * | 2000-10-18 | 2007-06-12 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US7135759B2 (en) * | 2000-10-27 | 2006-11-14 | Texas Instruments Incorporated | Individualized low parasitic power distribution lines deposited over active integrated circuits |
US6809419B2 (en) * | 2002-09-20 | 2004-10-26 | Hitachi, Ltd. | Semiconductor device |
US7335992B2 (en) * | 2004-03-29 | 2008-02-26 | Nec Electronics Corporation | Semiconductor apparatus with improved yield |
Also Published As
Publication number | Publication date |
---|---|
JP2009543325A (en) | 2009-12-03 |
WO2008004151A3 (en) | 2008-03-06 |
CN101479848B (en) | 2011-06-29 |
CN101479848A (en) | 2009-07-08 |
US7928567B2 (en) | 2011-04-19 |
WO2008004151A2 (en) | 2008-01-10 |
TW200824086A (en) | 2008-06-01 |
EP2038927A2 (en) | 2009-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7413329B2 (en) | semiconductor equipment | |
US7038280B2 (en) | Integrated circuit bond pad structures and methods of making | |
CN101038912B (en) | Semiconductor device having function of improved electrostatic discharge protection | |
US7057296B2 (en) | Bonding pad structure | |
JP2012134198A (en) | Semiconductor device and manufacturing method of the same | |
US10181508B2 (en) | Semiconductor device and manufacturing method thereof | |
US7928567B2 (en) | Power supply network | |
JP4820542B2 (en) | Semiconductor integrated circuit | |
JP2009177139A (en) | Semiconductor integrated circuit | |
KR20150020313A (en) | Semiconductor device | |
JP5589342B2 (en) | Semiconductor device | |
US7335992B2 (en) | Semiconductor apparatus with improved yield | |
CN105448875A (en) | Electronic component | |
US7554133B1 (en) | Pad current splitting | |
EP3065171A2 (en) | Electronic device and electronic package thereof | |
JP4165460B2 (en) | Semiconductor device | |
US6346721B1 (en) | Integrated circuit having radially varying power bus grid architecture | |
TW202137403A (en) | Integrated circuit apparatus | |
US20170125357A1 (en) | Integrated circuit and method of making an integrated circuit | |
US6794691B2 (en) | Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features | |
US20120168934A1 (en) | Flip chip device having simplified routing | |
JPH11340425A (en) | Electrostatic-protection transistor for semiconductor chip and manufacture thereof, and semiconductor chip using transistor thereof | |
JP2016219655A (en) | Semiconductor device | |
CN112185931A (en) | Semiconductor device with a plurality of transistors | |
JP2022516866A (en) | Interconnect for electronic devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NXP, B.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VAN DE WIEL, PETRUS J. A. M.;APPLEBY, ANDREW T.;REEL/FRAME:022035/0845;SIGNING DATES FROM 20070719 TO 20070815 Owner name: NXP, B.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VAN DE WIEL, PETRUS J. A. M.;APPLEBY, ANDREW T.;SIGNING DATES FROM 20070719 TO 20070815;REEL/FRAME:022035/0845 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:039361/0212 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042762/0145 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042985/0001 Effective date: 20160218 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050745/0001 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051030/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |