US20090319844A1 - Apparatus selectively adopting different determining criteria in erasure marking procedure when performing decoding process, and method thereof - Google Patents

Apparatus selectively adopting different determining criteria in erasure marking procedure when performing decoding process, and method thereof Download PDF

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US20090319844A1
US20090319844A1 US12/550,423 US55042309A US2009319844A1 US 20090319844 A1 US20090319844 A1 US 20090319844A1 US 55042309 A US55042309 A US 55042309A US 2009319844 A1 US2009319844 A1 US 2009319844A1
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signal
decoder
generate
indication signal
reliability
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Rong-Liang Chiou
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Xueshan Technologies Inc
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MediaTek Inc
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • H04L1/0054Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0059Convolutional codes
    • H04L1/006Trellis-coded modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0064Concatenated codes
    • H04L1/0065Serial concatenated codes

Definitions

  • the present invention relates to an apparatus for performing a decoding process, and more particularly, to an apparatus that selectively adopts different determining criteria in an erasure marking procedure when performing a decoding process, and a method thereof.
  • Error-correcting coding is a technique that can be adopted in digital communication systems to help transceivers resist the above-mentioned factors, reduce the probability of errors, and enhance the reliability of the outputted data.
  • Concatenated coding is a kind of error-correcting coding technique that implements multiple levels of coding.
  • inner and outer codes are commonly applied to provide two levels of coding.
  • convolutional codes or Trellis-Coded-Modulation (TCM) codes could be used as the inner codes, which help to overcome scattered random errors.
  • Reed-Solomon (RS) codes or BCH codes could be used as the outer codes, which help to overcome burst errors.
  • FIG. 1 shows a schematic diagram of a receiver for decoding concatenated codes.
  • the receiver 100 shown in FIG. 1 comprises a demodulator 110 , an inner decoder 120 , a deinterleaver 130 , and an outer decoder 140 .
  • the demodulator 110 may comprise analog-to-digital converters for converting analog signals into digital signals, a mixer for transferring frequency from a radio frequency (RF) into an intermediate frequency (IF) or baseband, filters for anti-aliasing, a synchronization means for timing or frequency recovery, and an equalizer for compensating fading or impairment channel effects.
  • RF radio frequency
  • IF intermediate frequency
  • the demodulator 110 After some or all of the above-mentioned operations are performed, the demodulator 110 then generates a demodulated signal.
  • a Viterbi decoder or a TCM decoder could implement the inner decoder 120 , which decodes the demodulated signal to generate an inner-code decoded signal. Then, the deinterleaver 130 deinterleaves the inner-code decoded signal to generate a deinterleaved signal.
  • the deinterleaver 130 plays an important role in scattering some kinds of burst noise in order to share the error-correction burden.
  • the outer decoder 140 could be implemented by an RS decoder or a BCH decoder.
  • an RS error decoder can be used as the outer decoder 140 .
  • the RS error decoder 140 can correct a maximum of t errors for an (n, k, 2t) RS code.
  • the RS error decoder 140 has an error correction capability of t errors per codeword.
  • complex multi-path channels would induce severe fading or interference that the equalizer of the demodulator 110 cannot compensate entirely.
  • burst noise may causes errors of the inner decoder 120 to propagate to the outer decoder 140 and even the deinterleaver 130 cannot scatter them efficiently.
  • the outer decoder 140 with only t-error correction capability may not be sufficient.
  • the outer decoder 140 can be upgraded to an RS error-erasure decoder.
  • an RS error-erasure decoder can correct x errors and y erasures for an (n, k, 2t) RS code, only if 2x+y ⁇ 2t. That is, if an RS error-erasure decoder implements the outer decoder 140 , a correction capability of t errors or 2t erasures per codeword can be achieved. In other words, the RS error-erasure decoder 140 has the opportunity to correct codewords with an actual error number that is larger than t if it is informed with some error locations marked as erasures.
  • the additionally provided reliability-determining unit determines the reliability information corresponding to the inner-code decoded signal according to a changeless criterion.
  • the changeless criterion works fine for only certain situations. For other situations, the changeless criterion might lead to erroneous erasure marking.
  • the reliability-determining unit erroneously generates erasure marks
  • the error correction capability of the error-erasure decoder 140 will be taken up by the erroneously generated erasure marks. Even worse, the erroneously generated erasure marks received by the error-erasure decoder 140 might cause the error-erasure decoder 140 to generate incorrect symbol(s) in its output signal.
  • an apparatus for decoding an input signal to generate an output signal comprises a noise detector, an inner decoder, a reliability-determining unit, and an outer decoder.
  • the noise detector determines burst noise locations corresponding to the input signal and generates a first indication signal accordingly.
  • the inner decoder decodes the input signal to generate an inner-code decoded signal.
  • the reliability-determining unit is coupled to the noise detector and selectively adopts one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly.
  • the outer decoder is coupled to the inner decoder and the reliability-determining unit and decodes the inner-code decoded signal with reference to the second indication signal to generate the output signal.
  • a method for decoding an input signal to generate an output signal comprises determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly, and decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.
  • FIG. 1 shows a schematic diagram of a receiver for decoding concatenated codes according to a related art.
  • FIG. 2 shows a schematic diagram of an apparatus according to an embodiment of the present invention.
  • FIG. 3 shows an exemplary 4-state Trellis diagram of a Viterbi algorithm adopted by a Viterbi decoder.
  • FIG. 4 shows a schematic diagram illustrating how path metrics are determined in the Viterbi algorithm.
  • FIG. 5 shows a schematic diagram illustrating how the states of the second indication signal are determined in a trace back procedure.
  • FIG. 2 shows a schematic diagram of an apparatus according to an embodiment of the present invention for decoding an input signal to generate an output signal.
  • the apparatus 200 shown in FIG. 2 comprises a noise detector 210 , an inner decoder 220 , a reliability-determining unit 230 , and an outer decoder 240 .
  • the noise detector 210 determines burst noise locations corresponding to the input signal and generates a first indication signal accordingly. When burse noise, which might be induced by severe fading or interference, is detected, the noise detector 210 may assert the first indication signal. When burse noise is not detected, the noise detector 210 may de-assert the first indication signal.
  • the apparatus 200 may be set inside a receiver comprising a demodulator for demodulating a preliminary signal to generate the input signal shown in FIG. 2 .
  • the noise detector 210 may function with reference to operations performed by the demodulator. There are several ways for the noise detector 210 to perform the burst noise detection function.
  • the noise detector 210 may determine burst noise locations corresponding to the input signal through a signal-to-noise ratio (SNR) measurement process.
  • the noise detector 210 may also determine burst noise locations corresponding to the input signal by distribution of hard decision errors or by using a threshold detection of soft decision errors.
  • SNR signal-to-noise ratio
  • a Viterbi decoder or a TCM decoder may implement the inner decoder 220 , which decodes the input signal to generate an inner-code decoded signal.
  • the reliability-determining unit 230 in this embodiment is set in the inner decoder 220 and selectively adopts one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly. More specifically, in this embodiment, when the noise detector 210 asserts the first indication signal, the reliability-determining unit 230 will adopt a first determining criterion.
  • the reliability-determining unit 230 When the noise detector 210 does not assert the first indication signal, the reliability-determining unit 230 will adopt a second determining criterion. In other words, the reliability-determining unit 230 of this embodiment determines the reliability of information corresponding to the inner-code decoded signal through an adaptive manner.
  • FIG. 3 shows an exemplary 4-state Trellis diagram of a Viterbi algorithm adopted by the Viterbi decoder 220 .
  • S 0 , S 1 , S 2 , S 3 There are four possible branches that might lead the state; the two possible branches include an upper branch and a lower branch.
  • the Viterbi algorithm is a minimum-distance decoding algorithm for convolutional codes, a path metric for each state and a branch metric for each branch are determined in the Viterbi algorithm.
  • FIG. 4 shows a schematic diagram illustrating how path metrics are determined in the Viterbi algorithm.
  • states x and y at time t ⁇ 1 are two possible states that might lead to state z at time t.
  • the path metrics of the states x and y at time t ⁇ 1 are PM(x, t ⁇ 1) and PM(y, t ⁇ 1), respectively.
  • the branch metrics of the upper and lower branches lead to the state z at time t are BM(x, t) and BM(y, t), respectively.
  • a first candidate path metric is Upper_PM, which equals to PM(x, t ⁇ 1)+BM(x, t); and a second candidate path metric is Lower_PM, which equals to PM(y, t ⁇ 1)+BM(y, t).
  • a minimum value of the two candidate path metrics will be determined to be the path metric PM(z, t) of the state z at time t.
  • the reliability-determining unit 230 determines whether each state in a Trellis diagram of the Viterbi algorithm is reliable or unreliable through comparing a threshold with a difference between two candidate path metrics, such as the Upper_PM and Lower_PM shown in FIG. 4 , of the state in the Viterbi algorithm.
  • the threshold utilized by the reliability-determining unit 230 is adaptively adjusted according to the first indication signal generated by the noise detector 210 . For example, when the first indication signal is asserted, the reliability-determining unit 230 will adopt a first determining criterion.
  • the reliability-determining unit 230 compares a first threshold Th_ 1 with the difference Diff between the two candidate path metrics Upper_PM and Lower_PM of the state. If the first threshold Th_ 1 is smaller than the difference Diff, the state will be marked by the reliability-determining unit 230 and be stored into memory. Otherwise, the reliability-determining unit 230 will not mark the state. When the first indication signal is not asserted, the reliability-determining unit 230 will adopt a second determining criterion. Under this situation the reliability-determining unit 230 compares a second threshold Th_ 2 with the difference Diff between the two candidate path metrics Upper_PM and Lower_PM of the state.
  • the first threshold Th_ 1 and the second threshold Th_ 2 are two different values that can be determined through experimental statistics.
  • the first threshold Th_ 1 is smaller than the second threshold Th_ 2 so that the first determining criterion adopted when the first indication is asserted is stricter than the second determining criterion adopted when the first indication is not asserted.
  • a trace back procedure is performed by the Viterbi decoder 220 to find a survivor path, which is also called a trace back path.
  • the reliability-determining unit 230 asserts the second indication signal in a specific location corresponding to the symbol.
  • the reliability-determining unit 230 de-asserts the second indication signal in a specific location corresponding to the symbol.
  • FIG. 5 shows a schematic diagram illustrating how the states of the second indication signal are determined in a trace back procedure.
  • the upper part of FIG. 5 illustrates the signal states of the first indication signal and the how different determining criteria does the reliability-determining unit 230 adopt according to the signal states of the first indication signal.
  • the reliability-determining unit 230 adopts a first determining criterion.
  • the reliability-determining unit 230 adopts a second determining criterion.
  • the middle part of FIG. 5 is a Trellis diagram of the Viterbi algorithm performed by the Viterbi decoder 220 .
  • the inner-code decoded signal is generated according to the determined survivor path.
  • the Viterbi decoder 220 according to the survivor path in the Trellis diagram determines the inner-code decoded signal.
  • the lower part of FIG. 5 illustrates how the signal states of the second indication signal are determined according to marks on the survivor path on the Trellis diagram.
  • the reliability-determining unit 230 asserts the second indication signal in a specific location corresponding to the marked state.
  • the reliability-determining unit 230 de-asserts the second indication signal in a specific location corresponding to the unmarked state.
  • an error-erasure decoder implements the outer decoder 240 .
  • the error-erasure decoder 240 decodes the inner-code decoded signal with reference to the second indication signal to generate the output signal. More specifically, the error-erasure decoder 240 decodes the inner-code decoded signal by regarding unreliable locations specified by the second indication signal as erasure locations corresponding to the inner-code decoded signal.
  • the reliability-determining unit 230 of the embodiment adaptively adopt different determining criterion according to the first indication signal to determine the reliability information corresponding to the inner-code decoded signal, even under different circumstances the second indication signal can still be accurately generated. With the accurately generated second indication signal, the error correction capability of the error-erasure decoder 240 is utilized more efficiently.
  • a deinterleaver can further be set in front of the input ends of the outer decoder 240 to deinterleave the inner-code decoded signal and the second indication signal before they are inputted into the outer decoder 240 .

Abstract

A method and a related apparatus that decode an input signal to generate an output signal. The method includes determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly, and decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.

Description

    BACKGROUND
  • The present invention relates to an apparatus for performing a decoding process, and more particularly, to an apparatus that selectively adopts different determining criteria in an erasure marking procedure when performing a decoding process, and a method thereof.
  • Various types of noise, distortion, and interference are commonly seen factors that deteriorate signal communication quality and cause an output of a communication channel to be different from its input. Error-correcting coding is a technique that can be adopted in digital communication systems to help transceivers resist the above-mentioned factors, reduce the probability of errors, and enhance the reliability of the outputted data.
  • Concatenated coding is a kind of error-correcting coding technique that implements multiple levels of coding. Generally speaking, inner and outer codes are commonly applied to provide two levels of coding. For example, convolutional codes or Trellis-Coded-Modulation (TCM) codes could be used as the inner codes, which help to overcome scattered random errors. Reed-Solomon (RS) codes or BCH codes could be used as the outer codes, which help to overcome burst errors.
  • Please refer to FIG. 1, which shows a schematic diagram of a receiver for decoding concatenated codes. The receiver 100 shown in FIG. 1 comprises a demodulator 110, an inner decoder 120, a deinterleaver 130, and an outer decoder 140. The demodulator 110 may comprise analog-to-digital converters for converting analog signals into digital signals, a mixer for transferring frequency from a radio frequency (RF) into an intermediate frequency (IF) or baseband, filters for anti-aliasing, a synchronization means for timing or frequency recovery, and an equalizer for compensating fading or impairment channel effects. After some or all of the above-mentioned operations are performed, the demodulator 110 then generates a demodulated signal.
  • Depending on which kind of inner code is utilized, a Viterbi decoder or a TCM decoder could implement the inner decoder 120, which decodes the demodulated signal to generate an inner-code decoded signal. Then, the deinterleaver 130 deinterleaves the inner-code decoded signal to generate a deinterleaved signal. The deinterleaver 130 plays an important role in scattering some kinds of burst noise in order to share the error-correction burden.
  • Depending on which kind of outer code is utilized, the outer decoder 140 could be implemented by an RS decoder or a BCH decoder. For example, when RS codes are utilized as the outer codes, an RS error decoder can be used as the outer decoder 140. The RS error decoder 140 can correct a maximum of t errors for an (n, k, 2t) RS code. In other words, the RS error decoder 140 has an error correction capability of t errors per codeword. However, in some communication systems, especially in terrestrial broadcasting systems, complex multi-path channels would induce severe fading or interference that the equalizer of the demodulator 110 cannot compensate entirely. In such circumstances, burst noise may causes errors of the inner decoder 120 to propagate to the outer decoder 140 and even the deinterleaver 130 cannot scatter them efficiently. The outer decoder 140 with only t-error correction capability may not be sufficient.
  • If the receiver 100 is further provided with a reliability-determining unit (not shown in FIG. 1) that determines unreliable locations corresponding to the inner-code decoded signal and generates an indication signal to indicate the unreliable locations, the outer decoder 140 can be upgraded to an RS error-erasure decoder. Different from the above-mentioned RS error decoder, an RS error-erasure decoder can correct x errors and y erasures for an (n, k, 2t) RS code, only if 2x+y≦2t. That is, if an RS error-erasure decoder implements the outer decoder 140, a correction capability of t errors or 2t erasures per codeword can be achieved. In other words, the RS error-erasure decoder 140 has the opportunity to correct codewords with an actual error number that is larger than t if it is informed with some error locations marked as erasures.
  • In the related art, the additionally provided reliability-determining unit determines the reliability information corresponding to the inner-code decoded signal according to a changeless criterion. The changeless criterion works fine for only certain situations. For other situations, the changeless criterion might lead to erroneous erasure marking. When the reliability-determining unit erroneously generates erasure marks, the error correction capability of the error-erasure decoder 140 will be taken up by the erroneously generated erasure marks. Even worse, the erroneously generated erasure marks received by the error-erasure decoder 140 might cause the error-erasure decoder 140 to generate incorrect symbol(s) in its output signal.
  • Heading
  • SUMMARY
  • According to the claimed invention, an apparatus for decoding an input signal to generate an output signal is disclosed. The apparatus comprises a noise detector, an inner decoder, a reliability-determining unit, and an outer decoder. The noise detector determines burst noise locations corresponding to the input signal and generates a first indication signal accordingly. The inner decoder decodes the input signal to generate an inner-code decoded signal. The reliability-determining unit is coupled to the noise detector and selectively adopts one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly. The outer decoder is coupled to the inner decoder and the reliability-determining unit and decodes the inner-code decoded signal with reference to the second indication signal to generate the output signal.
  • According to the claimed invention, a method for decoding an input signal to generate an output signal is disclosed. The method comprises determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly, and decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
  • Heading
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a schematic diagram of a receiver for decoding concatenated codes according to a related art.
  • FIG. 2 shows a schematic diagram of an apparatus according to an embodiment of the present invention.
  • FIG. 3 shows an exemplary 4-state Trellis diagram of a Viterbi algorithm adopted by a Viterbi decoder.
  • FIG. 4 shows a schematic diagram illustrating how path metrics are determined in the Viterbi algorithm.
  • FIG. 5 shows a schematic diagram illustrating how the states of the second indication signal are determined in a trace back procedure.
  • DETAILED DESCRIPTION
  • FIG. 2 shows a schematic diagram of an apparatus according to an embodiment of the present invention for decoding an input signal to generate an output signal. The apparatus 200 shown in FIG. 2 comprises a noise detector 210, an inner decoder 220, a reliability-determining unit 230, and an outer decoder 240.
  • The noise detector 210 determines burst noise locations corresponding to the input signal and generates a first indication signal accordingly. When burse noise, which might be induced by severe fading or interference, is detected, the noise detector 210 may assert the first indication signal. When burse noise is not detected, the noise detector 210 may de-assert the first indication signal. The apparatus 200 may be set inside a receiver comprising a demodulator for demodulating a preliminary signal to generate the input signal shown in FIG. 2. The noise detector 210 may function with reference to operations performed by the demodulator. There are several ways for the noise detector 210 to perform the burst noise detection function. For example, the noise detector 210 may determine burst noise locations corresponding to the input signal through a signal-to-noise ratio (SNR) measurement process. The noise detector 210 may also determine burst noise locations corresponding to the input signal by distribution of hard decision errors or by using a threshold detection of soft decision errors.
  • Depending on which kind of inner code is utilized in the input signal, a Viterbi decoder or a TCM decoder may implement the inner decoder 220, which decodes the input signal to generate an inner-code decoded signal. The reliability-determining unit 230 in this embodiment is set in the inner decoder 220 and selectively adopts one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly. More specifically, in this embodiment, when the noise detector 210 asserts the first indication signal, the reliability-determining unit 230 will adopt a first determining criterion. When the noise detector 210 does not assert the first indication signal, the reliability-determining unit 230 will adopt a second determining criterion. In other words, the reliability-determining unit 230 of this embodiment determines the reliability of information corresponding to the inner-code decoded signal through an adaptive manner.
  • As mentioned, a Viterbi decoder may implement the inner decoder 220. FIG. 3 shows an exemplary 4-state Trellis diagram of a Viterbi algorithm adopted by the Viterbi decoder 220. There are four possible states (S0, S1, S2, S3) in each time point. For each state, there are two possible branches that might lead the state; the two possible branches include an upper branch and a lower branch. Since the Viterbi algorithm is a minimum-distance decoding algorithm for convolutional codes, a path metric for each state and a branch metric for each branch are determined in the Viterbi algorithm. FIG. 4 shows a schematic diagram illustrating how path metrics are determined in the Viterbi algorithm. In FIG. 4, states x and y at time t−1 are two possible states that might lead to state z at time t. The path metrics of the states x and y at time t−1 are PM(x, t−1) and PM(y, t−1), respectively. The branch metrics of the upper and lower branches lead to the state z at time t are BM(x, t) and BM(y, t), respectively. There are two possible candidate path metrics that might be determined to be the path metric PM(z, t) of the state z at time t. A first candidate path metric is Upper_PM, which equals to PM(x, t−1)+BM(x, t); and a second candidate path metric is Lower_PM, which equals to PM(y, t−1)+BM(y, t). As mentioned, since the Viterbi algorithm is a minimum-distance decoding algorithm, a minimum value of the two candidate path metrics will be determined to be the path metric PM(z, t) of the state z at time t.
  • With reference to the Viterbi algorithm adopted by the Viterbi decoder 220, in this embodiment the reliability-determining unit 230 determines whether each state in a Trellis diagram of the Viterbi algorithm is reliable or unreliable through comparing a threshold with a difference between two candidate path metrics, such as the Upper_PM and Lower_PM shown in FIG. 4, of the state in the Viterbi algorithm. The threshold utilized by the reliability-determining unit 230 is adaptively adjusted according to the first indication signal generated by the noise detector 210. For example, when the first indication signal is asserted, the reliability-determining unit 230 will adopt a first determining criterion. Under this situation the reliability-determining unit 230 compares a first threshold Th_1 with the difference Diff between the two candidate path metrics Upper_PM and Lower_PM of the state. If the first threshold Th_1 is smaller than the difference Diff, the state will be marked by the reliability-determining unit 230 and be stored into memory. Otherwise, the reliability-determining unit 230 will not mark the state. When the first indication signal is not asserted, the reliability-determining unit 230 will adopt a second determining criterion. Under this situation the reliability-determining unit 230 compares a second threshold Th_2 with the difference Diff between the two candidate path metrics Upper_PM and Lower_PM of the state. If the second threshold Th_2 is smaller than the difference Diff, the state will be marked by the reliability-determining unit 230 and be stored in memory. Otherwise, the reliability-determining unit 230 will not mark the state. The first threshold Th_1 and the second threshold Th_2 are two different values that can be determined through experimental statistics. Preferably, the first threshold Th_1 is smaller than the second threshold Th_2 so that the first determining criterion adopted when the first indication is asserted is stricter than the second determining criterion adopted when the first indication is not asserted.
  • After the path metrics of the states in a Trellis diagram of the Viterbi algorithm are determined, a trace back procedure is performed by the Viterbi decoder 220 to find a survivor path, which is also called a trace back path. For a symbol in the inner-code decoded signal that corresponds to a marked state on the survivor path, the reliability-determining unit 230 asserts the second indication signal in a specific location corresponding to the symbol. For a symbol in the inner-code decoded signal that corresponds to a state on the survivor path without a mark, the reliability-determining unit 230 de-asserts the second indication signal in a specific location corresponding to the symbol.
  • FIG. 5 shows a schematic diagram illustrating how the states of the second indication signal are determined in a trace back procedure. The upper part of FIG. 5 illustrates the signal states of the first indication signal and the how different determining criteria does the reliability-determining unit 230 adopt according to the signal states of the first indication signal. As mentioned, when the noise detector 210 asserts the first indication signal, the reliability-determining unit 230 adopts a first determining criterion. When the noise detector 210 does not assert the first indication signal, the reliability-determining unit 230 adopts a second determining criterion.
  • The middle part of FIG. 5 is a Trellis diagram of the Viterbi algorithm performed by the Viterbi decoder 220. The inner-code decoded signal is generated according to the determined survivor path. The Viterbi decoder 220 according to the survivor path in the Trellis diagram determines the inner-code decoded signal. The lower part of FIG. 5 illustrates how the signal states of the second indication signal are determined according to marks on the survivor path on the Trellis diagram. As mentioned, for a marked state on the survivor path, the reliability-determining unit 230 asserts the second indication signal in a specific location corresponding to the marked state. For a state on the survivor path without a mark, the reliability-determining unit 230 de-asserts the second indication signal in a specific location corresponding to the unmarked state.
  • In this embodiment, an error-erasure decoder implements the outer decoder 240. The error-erasure decoder 240 decodes the inner-code decoded signal with reference to the second indication signal to generate the output signal. More specifically, the error-erasure decoder 240 decodes the inner-code decoded signal by regarding unreliable locations specified by the second indication signal as erasure locations corresponding to the inner-code decoded signal.
  • Since the reliability-determining unit 230 of the embodiment adaptively adopt different determining criterion according to the first indication signal to determine the reliability information corresponding to the inner-code decoded signal, even under different circumstances the second indication signal can still be accurately generated. With the accurately generated second indication signal, the error correction capability of the error-erasure decoder 240 is utilized more efficiently.
  • Please note that the diagram shown in FIG. 2 is only a schematic diagram drawn according to the embodiment of the present invention. If it is required, a deinterleaver can further be set in front of the input ends of the outer decoder 240 to deinterleave the inner-code decoded signal and the second indication signal before they are inputted into the outer decoder 240.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (2)

1. An apparatus for decoding an input signal to generate an output signal, the apparatus comprising:
a noise detector for determining a burst noise location corresponding to the input signal and generating a first indication signal for indicating the burst noise location;
an inner decoder for decoding the input signal to generate an inner-code decoded signal;
a reliability-determining unit coupled to the noise detector, for selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal; and
an outer decoder coupled to the inner decoder and the reliability-determining unit, the outer decoder decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.
2. A method for decoding an input signal to generate an output signal, the method comprising:
determining a burst noise location corresponding to the input signal and generating a first indication signal indicating the burst noise location;
decoding the input signal to generate an inner-code decoded signal;
selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal; and
decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.
US12/550,423 2005-07-19 2009-08-31 Apparatus selectively adopting different determining criteria in erasure marking procedure when performing decoding process, and method thereof Abandoned US20090319844A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090276670A1 (en) * 2008-04-30 2009-11-05 Sony Corporation Reception apparatus, reception method, and program
US10917833B2 (en) * 2017-02-02 2021-02-09 Telefontakiebolaget Lm Ericsson (Publ) Implicit system information (SI) content variation enabling soft combining

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8190964B2 (en) * 2002-04-05 2012-05-29 Sentel Corporation Decoding method
US8407563B2 (en) * 2008-12-31 2013-03-26 Stmicroelectronics, Inc. Low-complexity soft-decision decoding of error-correction codes
US20110090773A1 (en) * 2009-10-16 2011-04-21 Chih-Ching Yu Apparatus for generating viterbi-processed data using an input signal obtained from reading an optical disc
US20110090779A1 (en) * 2009-10-16 2011-04-21 Mediatek Inc. Apparatus for generating viterbi-processed data
US20110167323A1 (en) * 2010-01-07 2011-07-07 Mediatek Inc. Error-Correcting Apparatus and Method Thereof
US8433975B2 (en) * 2010-08-13 2013-04-30 Nxp B.V. Bitwise reliability indicators from survivor bits in Viterbi decoders
US8432780B1 (en) 2012-05-10 2013-04-30 Mediatek Inc. Viterbi decoding apparatus using level information generator supporting different hardware configurations to generate level information to Viterbi decoder and related method thereof
US9942003B2 (en) * 2015-09-04 2018-04-10 Futurewei Technologies, Inc. Adaptive forward error correction (FEC) in passive optical networks (PONs)
US9660845B2 (en) * 2015-10-06 2017-05-23 Huawei Technologies Co., Ltd. System and method for state reduction in trellis equalizers using bounded state enumeration

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653052A (en) * 1984-06-29 1987-03-24 Hitachi, Ltd. Method for decoding double-encoding codes and apparatus using the same
US5434886A (en) * 1992-01-24 1995-07-18 Hitachi, Ltd. Digital communication system
US5715262A (en) * 1995-07-12 1998-02-03 Lsi Logic Corporation Errors and erasures correcting reed-solomon decoder
US5812603A (en) * 1996-08-22 1998-09-22 Lsi Logic Corporation Digital receiver using a concatenated decoder with error and erasure correction
US5875199A (en) * 1996-08-22 1999-02-23 Lsi Logic Corporation Video device with reed-solomon erasure decoder and method thereof
US5968198A (en) * 1996-08-16 1999-10-19 Ericsson, Inc. Decoder utilizing soft information output to minimize error rates
US5996103A (en) * 1996-07-31 1999-11-30 Samsung Information Systems America Apparatus and method for correcting errors in a communication system
US6011817A (en) * 1996-07-04 2000-01-04 U.S. Philips Corporation Transmission system and receiver with improved detection, and improved detection method
US6044485A (en) * 1997-01-03 2000-03-28 Ericsson Inc. Transmitter method and transmission system using adaptive coding based on channel characteristics
US6108811A (en) * 1996-10-18 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Error-correcting decoder continuously adding flag signals to locations preceding a first location at which a difference between path metrics is lower than the threshold
US6209112B1 (en) * 1998-07-31 2001-03-27 Lucent Technologies Inc. Apparatus and method for reducing power consumption of an error-correcting decoder
US20030026028A1 (en) * 2001-06-11 2003-02-06 Fujitsu Limited Information recording and reproducing apparatus and method and signal decoding circuit
US6580930B1 (en) * 1999-04-15 2003-06-17 Ericsson, Inc. Signal detector selector and method for selecting a detector
US20030192001A1 (en) * 2002-04-05 2003-10-09 Iit Research Institute Decoding method and apparatus
US20040030984A1 (en) * 2000-11-27 2004-02-12 Christine Renaud Method for decoding a block of symbols and device therefor
US20040061964A1 (en) * 2002-10-01 2004-04-01 Kabushiki Kaisha Toshiba Method and apparatus for turbo coding and decoding in a disk drive
US20050078640A1 (en) * 2003-10-14 2005-04-14 Samsung Electronics Co., Ltd. Apparatus and method for receiving control message on packet data control channel in a mobile communication system supporting packet data service
US20050120286A1 (en) * 2003-11-28 2005-06-02 Kabushiki Kaisha Toshiba Method and apparatus for data reproducing using iterative decoding in a disk drive
US7047474B2 (en) * 2002-12-23 2006-05-16 Do-Jun Rhee Decoding concatenated codes via parity bit recycling
US7236536B2 (en) * 2001-07-26 2007-06-26 Lucent Technologies Inc. Method and apparatus for detection and decoding of signals received from a linear propagation channel
US7237173B2 (en) * 2001-06-11 2007-06-26 Fujitsu Limited Recording and reproducing apparatus, signal decoding circuit, error correction method and iterative decoder
US7478306B2 (en) * 2004-03-31 2009-01-13 Sanyo Electric Co., L:Td. Method of detecting error location, and error detection circuit, error correction circuit, and reproducing apparatus using the method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708665A (en) 1996-08-22 1998-01-13 Lsi Logic Corporation Digital receiver using equalization and block decoding with erasure and error correction
WO2001048927A1 (en) * 1999-12-24 2001-07-05 Ensemble Communications, Inc. Method and apparatus for concatenated channel coding
US20060184839A1 (en) * 2002-11-25 2006-08-17 Matsushita Electric Industrial Co., Ltd. Erasure determination procedure for fec decoding
EP1618669A1 (en) * 2003-04-30 2006-01-25 Marconi Communications GmbH Forward error correction coding

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653052A (en) * 1984-06-29 1987-03-24 Hitachi, Ltd. Method for decoding double-encoding codes and apparatus using the same
US5434886A (en) * 1992-01-24 1995-07-18 Hitachi, Ltd. Digital communication system
US5715262A (en) * 1995-07-12 1998-02-03 Lsi Logic Corporation Errors and erasures correcting reed-solomon decoder
US6011817A (en) * 1996-07-04 2000-01-04 U.S. Philips Corporation Transmission system and receiver with improved detection, and improved detection method
US5996103A (en) * 1996-07-31 1999-11-30 Samsung Information Systems America Apparatus and method for correcting errors in a communication system
US5968198A (en) * 1996-08-16 1999-10-19 Ericsson, Inc. Decoder utilizing soft information output to minimize error rates
US5812603A (en) * 1996-08-22 1998-09-22 Lsi Logic Corporation Digital receiver using a concatenated decoder with error and erasure correction
US5875199A (en) * 1996-08-22 1999-02-23 Lsi Logic Corporation Video device with reed-solomon erasure decoder and method thereof
US6108811A (en) * 1996-10-18 2000-08-22 Mitsubishi Denki Kabushiki Kaisha Error-correcting decoder continuously adding flag signals to locations preceding a first location at which a difference between path metrics is lower than the threshold
US6044485A (en) * 1997-01-03 2000-03-28 Ericsson Inc. Transmitter method and transmission system using adaptive coding based on channel characteristics
US6209112B1 (en) * 1998-07-31 2001-03-27 Lucent Technologies Inc. Apparatus and method for reducing power consumption of an error-correcting decoder
US6580930B1 (en) * 1999-04-15 2003-06-17 Ericsson, Inc. Signal detector selector and method for selecting a detector
US20040030984A1 (en) * 2000-11-27 2004-02-12 Christine Renaud Method for decoding a block of symbols and device therefor
US20030026028A1 (en) * 2001-06-11 2003-02-06 Fujitsu Limited Information recording and reproducing apparatus and method and signal decoding circuit
US7237173B2 (en) * 2001-06-11 2007-06-26 Fujitsu Limited Recording and reproducing apparatus, signal decoding circuit, error correction method and iterative decoder
US7236536B2 (en) * 2001-07-26 2007-06-26 Lucent Technologies Inc. Method and apparatus for detection and decoding of signals received from a linear propagation channel
US20030192001A1 (en) * 2002-04-05 2003-10-09 Iit Research Institute Decoding method and apparatus
US20040061964A1 (en) * 2002-10-01 2004-04-01 Kabushiki Kaisha Toshiba Method and apparatus for turbo coding and decoding in a disk drive
US7047474B2 (en) * 2002-12-23 2006-05-16 Do-Jun Rhee Decoding concatenated codes via parity bit recycling
US20050078640A1 (en) * 2003-10-14 2005-04-14 Samsung Electronics Co., Ltd. Apparatus and method for receiving control message on packet data control channel in a mobile communication system supporting packet data service
US20050120286A1 (en) * 2003-11-28 2005-06-02 Kabushiki Kaisha Toshiba Method and apparatus for data reproducing using iterative decoding in a disk drive
US7478306B2 (en) * 2004-03-31 2009-01-13 Sanyo Electric Co., L:Td. Method of detecting error location, and error detection circuit, error correction circuit, and reproducing apparatus using the method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090276670A1 (en) * 2008-04-30 2009-11-05 Sony Corporation Reception apparatus, reception method, and program
US8381054B2 (en) * 2008-04-30 2013-02-19 Sony Corporation Reception apparatus, reception method, and program
US10917833B2 (en) * 2017-02-02 2021-02-09 Telefontakiebolaget Lm Ericsson (Publ) Implicit system information (SI) content variation enabling soft combining
US20210127322A1 (en) * 2017-02-02 2021-04-29 Telefonaktiebolaget Lm Ericsson (Publ) Implicit system information (si) content variation enabling soft combining
US11743807B2 (en) * 2017-02-02 2023-08-29 Telefonaktiebolaget Lm Ericsson (Publ) Implicit system information (SI) content variation enabling soft combining

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