US20100062693A1

US20100062693A1 - Two step method and apparatus for polishing metal and other films in semiconductor manufacturing

Info

Publication number: US20100062693A1
Application number: US12/205,266
Authority: US
Inventors: Chen-Hua Yu; Wen-Chih Chiou; Weng-Jin Wu; Ku-Feng Yang; Jung-Chih Hu
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2008-09-05
Filing date: 2008-09-05
Publication date: 2010-03-11
Also published as: TWI376743B; TW201011824A; CN101667526A; CN101667526B

Abstract

A method and apparatus for removing a metal or conductive film from over a surface of a semiconductor wafer provides a two step process carried out within a single wafer processing apparatus. A first step is a wet chemical or mechanical removal process that removes an upper portion of the film at a high removal rate and is followed by a second step of a lower removal rate, the second step being CMP, chemical mechanical polishing.

Description

FIELD OF THE INVENTION

The present invention relates, most generally, to semiconductor manufacturing. More particularly, the present invention is related to an apparatus and polishing method for removing metal and other films.

BACKGROUND

In the rapidly advancing semiconductor manufacturing industry, conventional methods for polishing to remove metal or other conductive films from over the surface of a semiconductor substrate, are well known. Chemical mechanical polishing, CMP, is a favored polishing operation although various other polishing operations are available in the semiconductor manufacturing industry. CMP is conventionally used in damascene processing operations which include forming a metal or other conductive layer over a dielectric or other surface and filling openings such as contacts, vias and trenches formed in the surface. CMP removes the metal or other conductive materials from over the surface, leaving the metal or other conductive material filling the openings to form conductive interconnect structures such as contacts, vias and conductive leads, the tops of these interconnect structures being coplanar with the dielectric surface.
Advanced technologies such as 3D-IC using wafer stacking and through-Si-via (TSV) technologies require narrow, deeper vias or other openings with high aspect ratios. As a consequence, conductive films with greater thicknesses are now used in order to ensure that these narrow, deeper vias or other openings with high aspect ratios, are completely filled with the conductive material. One shortcoming associated with conventional chemical mechanical polishing operations is a relatively slow removal rate that is typically less than about 0.4 or 0.5 microns per minute. Therefore, as advancing technologies require the metal or other conductive film thicknesses to become greater to fill narrower, deeper openings with higher aspect ratios, the time associated with removing a metal or other conductive film from over the surface of the semiconductor substrate increases and limits production throughput. Another shortcoming associated with conventional CMP is the very high cost of the polishing slurry used, this shortcoming being magnified when CMP is used for lengthy operations required for removing increasingly thicker films.
It would therefore be advantageous to provide an apparatus and cost-efficient process that more quickly removes a bulk metal or other conductive film from over a surface of a semiconductor wafer and produces a high-quality polished surface such as may be produced by chemical mechanical polishing.

SUMMARY OF THE INVENTION

To address these and other needs, and in view of its purposes, one aspect of the present invention provides a wafer processing apparatus. The apparatus comprises a first processing chamber comprising at least one of (a) a wet chemical etching apparatus and (b) a mechanical polishing apparatus that removes material from a wafer seated on a chuck therein by relative motion between the chuck and a cutting member. The wafer processing apparatus also includes a second processing chamber comprising a chemical mechanical polishing, CMP, apparatus and a wafer transfer apparatus that transfers the semiconductor substrate from the first processing chamber to the second processing chamber within the wafer processing apparatus.
According to another aspect, the present invention provides a method for processing a semiconductor wafer within a single apparatus, the method comprising: forming a semiconductor wafer with a bulk metal layer formed over a surface thereof; removing an upper portion of the bulk metal layer from the semiconductor wafer using wet chemical etching or mechanical cutting in a first processing chamber of the apparatus; and thereafter, polishing in a second processing chamber of the apparatus, thereby removing a remaining portion of the bulk metal layer and exposing the surface. The polishing comprises chemical mechanical polishing, CMP.

BRIEF DESCRIPTION OF THE DRAWING

The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.

FIG. 1 is a schematic view of an exemplary apparatus according to the invention;

FIG. 2 is a schematic view of another exemplary apparatus according to the invention; and

FIGS. 3A-3C are cross sectional views illustrating an exemplary process sequence according to the invention and as may be carried out using an exemplary apparatus according to the invention.

DETAILED DESCRIPTION

Damascene processing is commonly used in the semiconductor manufacturing industry and includes forming a dielectric layer then forming openings or voids in a surface of the dielectric layer. The openings or voids, hereinafter referred to as openings, extend down from an upper surface of the dielectric layer. The openings which may be contact openings, vias, trenches or other grooves, are then filled with a conductive material, typically a metal such as aluminum or copper. Various deposition methods may be used to form a film of the conductive material over the top surface of the dielectric and also filling the openings. A polishing operation is then used to planarize by removing the bulk conductive film from over the surface, leaving the conductive material to fill the openings. The conductive material in the openings form conductive structures such as contacts, vias, or interconnect leads. Chemical mechanical polishing, CMP, is conventionally known and used for this purpose.
As technologies advance, the vias and other openings formed in the dielectric layers become increasingly deeper and narrower and have increasingly higher aspect ratios. In order to completely fill such a deep via or other opening with high aspect ratio, various deposition techniques such as ECP (electrochemical plating) may be used to form a conductive material such as metal over the dielectric surface and within the opening, but these deposition processes require the formation of an increasingly thicker bulk film over the dielectric surface in order ensure that the vias or other openings are completely filled. Typical CMP polishing operations remove bulk metal films such as copper at a relatively slow rate such as about 0.4 μm/min. With the thickness of the bulk metal films increasing to accommodate the deeper openings with higher aspect ratios, the use of CMP to completely remove an entire bulk metal layer and to finally polish the film to produce the interconnect structure using damascene technology, is a time consuming process that limits throughput.
The present invention provides a multi-step processing operation that removes a bulk metal or other conductive or semiconductive film from over a surface and is carried out in a single, multi-chamber processing apparatus. The multi-step processing operation features a first, bulk film removal operation followed by CMP which polishes and planarizes the surface to form damascene structures such as contacts, openings and interconnect leads from conductive material formed in the openings formed within the dielectric layer.
FIG. 1 is a schematic view showing an exemplary wafer processing apparatus to according to the invention. Within common housing 4 are first processing chamber 6, wafer transfer mechanism 8, CMP apparatus 10 and optional post-processing cleaning station 12. Load/unload station 14 is illustrated as being outside common housing 4 in the illustrated embodiment but may alternatively be disposed within common housing 4 in other exemplary embodiments. First processing chamber 6 may be a wet chemical etching apparatus or a mechanical polishing apparatus. Wafer transfer mechanism 8 may be any suitable wafer transfer mechanism such as various robots that are capable of transferring wafers, either individually or as a lot of wafers, to and from each of the load/unload station 14, first process chamber 6, CMP apparatus 10 and post processing cleaning station 12. According to an exemplary processing sequence, a wafer or lot of wafers is loaded at load/unload station 14 and wafer transfer mechanism 8 delivers the wafer or lot of wafers first to first process chamber 6. After processing is complete in first process chamber 6, wafer transfer mechanism 8 transfers the wafers to CMP apparatus 10, either individually or as an entire lot of wafers. After processing at CMP apparatus 10, wafer transfer mechanism 8 transfers the wafer or lot of wafers to post process cleaning station 12 then to load/unload station 14. CMP apparatus 10 may be any of various suitable commercially available CMP apparatuses as known in the art. Post process cleaning station 12 may be any suitable, conventionally known station for cleaning wafers after they have gone through a chemical mechanical polishing operation.
FIG. 2 shows another exemplary embodiment of a wafer processing apparatus 22. Wafer processing apparatus 22 includes common housing 4 and within common housing 4 are CMP apparatus 10, wafer transfer mechanism 8, post process cleaning station 12 and both wet chemical etching apparatus 16 and mechanical polishing apparatus 18.
According to the exemplary wafer processing apparatus shown in FIG. 2, wafer transfer mechanism 8 is adapted to transfer wafers, either individually or as a lot of wafers, to and from each of wet chemical etching apparatus 16 and mechanical polishing station 18. As such, one exemplary process sequence may be first processing in wet chemical etch apparatus 16 then processing in CMP apparatus 10; another exemplary processing sequence may be first processing in mechanical polishing apparatus 18 then processing in CMP apparatus 10; and another exemplary processing operation may be first processing in one of wet chemical etching apparatus 16 and mechanical polishing apparatus 18 then polishing in the other of wet chemical etching apparatus 16 and mechanical polishing station 18 and thereafter processing in CMP apparatus 10.
Wet chemical etching apparatus 16 may be any of various suitable and conventionally known wet chemical etching apparatuses, such as a stagnant or cascading bath or an apparatus that includes a chuck upon which a wafer is seated and including one or more nozzles directing wet chemical etching solutions to a surface of the wafer seated on the chuck. According to various exemplary embodiments, the chuck may provide rotation to the wafer and various conventional methods such as laser interferometry may be used to detect an amount of film thickness being removed and to provide feedback to a controller to terminate the operation when a desired thickness has been removed. In one exemplary embodiment, chemical etching apparatus 16 may be used to remove a copper film from over a substrate and the wet chemical solution may be DI:H₃PO₄:H₂O₂in a 20:1:1 ratio but other suitable wet chemical etching solutions may be used for etching copper and various suitable wet chemical etching solutions may be used for removing other conductive films such as aluminum, or other semiconductive films, in other exemplary embodiments.
Mechanical polishing station 18 may be any of various mechanical polishing stations that remove a film from the surface of a substrate using conventional abrading or cutting methods. Mechanical polishing station 18 may use any of various conventional techniques for terminating the removal operation when a desired film thickness has been removed. In one exemplary embodiment, mechanical polishing station 18 may include a diamond grit for planar cutting and according to another exemplary embodiment, various teeth or blades may be used to remove a film from a surface of a substrate by mechanical force by providing motion between the cutting member and the chuck upon which a wafer is seated.
Each of wet chemical etching apparatus 16 and mechanical polishing station 18 may have their particular components adapted to remove a conductive metal film such as aluminum, copper, or alloys thereof or various semiconductor materials such as polysilicon, from over a subjacent surface such as a dielectric or other material. For example, the cutting tool or surface and rotational speed in mechanical polishing station 18 may be chosen in conjunction with the material to be removed and the chemical solution, temperatures and other parameters in wet chemical etching apparatus 16 may be chosen in conjunction with the material to be removed.
FIG. 3A is a cross sectional view showing substrate 30 with film 32 formed thereover. Substrate 30 may be any of various conventionally used substrates, i.e. wafers, used in semiconductor manufacturing. According to an advantageous embodiment, film 32 may be a dielectric material. Film 32 contains openings 34 that extend downward from top surface 40. Openings 34 may be contacts, vias or various other trenches or grooves formed within film 32. Openings 34 are defined by height or depth 38 and width 36. The ratio of height or depth 38 to width 36 is known as the aspect ratio. According to various exemplary embodiments, openings 34 may have a depth 38 as great as 80 microns, a width as narrow as 5-10 microns and an aspect ratio as great as about 10:1. Various methods known in the art such as dry etching or laser drilling, may be used to form openings 34 to a considerable depth. Conductive film 42 is formed over top surface 40 and filling openings 34 using various deposition methods including but not limited to ECP, electrochemical plating. According to one exemplary embodiment, conductive film 42 may be copper and according to another exemplary embodiment copper film 42 may be aluminum but various other alloys and conductive or semiconductive material may be used for conductive film 42 in other exemplary embodiments. Although not illustrated, at least one barrier or other film such as Ta and/or TaN may be first formed lining openings 34 prior to the formation of conductive film 42. Conductive film 42 includes a thickness 44 over top surface 40 of film 32 that may be any thickness ranging from about 1 micron to 10 microns, thickness 44 being determined at least in part by the depth, width and aspect ratio of openings 34 which are required to be completely filled. For rather deep openings 34 with high aspect ratios, thickness 44 may be along the lines of about 8 to 10 microns or more.
Although openings 34 are illustrated as terminating within film 32, it should be understood that in other exemplary embodiments openings 34 may extend through film 32 and extend into an underlying layer and in still other exemplary embodiments openings 34 may be formed directly within a substrate material.
The structure in FIG. 3A undergoes a first removal process such as may be carried out using wet chemical etching such as may performed in wet chemical etching apparatus 16 shown in FIG. 2 or the first removal process may be carried out by a mechanical cutting operation such as may be carried out in mechanical polishing station 18 shown in FIG. 2. Alternatively stated, the first removal operation that removes removed portion 46 of original thickness 44 is carried out in a first processing chamber. The first removal operation terminates at surface 48 to produce remaining portion 50 of conductive film 42 which includes thickness 52. According to various exemplary embodiments, thickness 44 may range from 1 to 10 microns and removed thickness 46 may range from 1 to 10 microns. Thickness 46 may be about 10 to 90 percent of thickness 44. According to one exemplary embodiment, thickness 44 may be about 9 microns and removed thickness 46 may be about 7 microns thereby producing remaining portion 50 having a thickness 52 of about 2 microns. This is intended to be exemplary only and in other exemplary embodiments, different portions of the original thickness may be removed in the first processing chamber.
The removal operation in the first processing chamber advantageously includes a faster removal rate than that which will be obtained in the subsequent chemical mechanical processing operation that may be carried out in CMP apparatus 10 of FIGS. 1 or 2. In one exemplary embodiment, the removal rate in the first processing chamber may be 2-10 times the removal rate obtained in the subsequent CMP operation. According to an exemplary embodiment in which conductive film 42 is copper, a diamond grit planar cutting operation may be used in exemplary mechanical polishing station 18 to provide a removal rate of about 2 microns/minute to 4 microns/minute and according to an exemplary embodiment in which conductive film 42 is copper and wet chemical etching apparatus 16 is used and employs a chemical solution of DI/H₃PO₄/H₂O₂in a 20:1:1 ratio, the removal rate may be about 1-3 microns/minute but other removal rates may be used in other exemplary embodiments.
A chemical mechanical polishing operation is carried out on the structure illustrated in FIG. 3B to produce the structure shown in FIG. 3C, in which all of conductive film 42 that was formed over top surface 40 has been removed by CMP. According to an exemplary embodiment in which conductive film 42 is copper, the CMP operation may produce a removal rate of about 0.4 microns/minute. The CMP operation produces conductive interconnect structures formed within openings 34, each having a top surface 56 substantially co-planar with top surface 40 of film 32 which may advantageously be a dielectric material.
The preceding merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.

Claims

1. A wafer processing apparatus comprising:

a first processing chamber comprising at least one of (a) a wet chemical etching apparatus; and (b) a mechanical polishing apparatus that removes material from a semiconductor wafer by relative motion between said semiconductor wafer and a cutting member;

a second processing chamber comprising a chemical mechanical polishing (CMP) apparatus; and

a wafer transfer apparatus that transfers said semiconductor wafer from said first processing chamber to said second processing chamber.

2. The wafer processing apparatus as in claim 1, wherein each of said first processing chamber, said second processing chamber and said wafer transfer apparatus are internally disposed within a common housing of said wafer processing apparatus.

3. The method as in claim 2, further comprising a wafer cleaning apparatus disposed within said housing.

4. The wafer processing apparatus as in claim 1, wherein said first processing chamber comprises each of said wet chemical etching apparatus and said mechanical polishing apparatus.

5. The wafer processing apparatus as in claim 1, wherein said wet chemical etching apparatus comprises a rotatable chuck and an input line that directs a stream of a wet chemical etching solution to said rotatable chuck.

6. The wafer processing apparatus as in claim 1, wherein said first processing chamber comprises said mechanical polishing apparatus and said cutting member comprises a diamond grit.

7. The wafer processing apparatus as in claim 1, wherein said first processing chamber comprises said mechanical polishing apparatus, said cutting member comprises at least one of a wheel, a blade and a tooth, and said mechanical polishing apparatus includes a chuck for retaining said semiconductor wafer, thereon.

8. The wafer processing apparatus as in claim 1, wherein said first processing chamber is capable of removing a first metal from said semiconductor wafer at a removal rate that is about 2-10 times faster than a removal rate of said first metal in said second processing chamber

9. A wafer processing apparatus comprising:

a first processing chamber comprising a wet chemical etching apparatus;

a second processing chamber comprising a mechanical polishing apparatus that removes material from a semiconductor wafer seated on a chuck therein by relative motion between said chuck and a cutting member;

a third processing chamber comprising a chemical mechanical polishing (CMP) apparatus; and

a wafer transfer apparatus that transfers said semiconductor wafer from said first processing chamber to said third processing chamber and from said second processing chamber to said third processing chamber,

wherein said first, second and third processing chambers and said wafer transfer apparatus are each internally disposed within a common housing of said wafer processing apparatus.

10. A method for processing a semiconductor wafer within a single apparatus comprising:

providing a semiconductor wafer with a bulk material layer formed over a surface thereof;

removing an upper portion of said bulk material layer from said semiconductor wafer using wet chemical etching or mechanical cutting in a first processing chamber of said apparatus; and

thereafter, polishing in a second processing chamber of said apparatus thereby removing a remaining portion of said bulk material layer and exposing said surface, said polishing comprising chemical mechanical polishing (CMP).

11. The method as in claim 10, wherein each of said first and second processing chambers are disposed within a common housing and further comprising internally transferring said semiconductor wafer from said first process chamber to said second process chamber within said common housing.

12. The method as in claim 10, wherein said bulk material layer comprises metal and said removing an upper portion comprises a removal rate within the range of about 3-4 um/min.

13. The method as in claim 10, wherein said material comprises metal and said removing an upper portion comprises said wet chemical etching using a mixture of deionized water, H₃PO₄and H₂O₂.

14. The method as in claim 13, wherein said deionized water, H₃PO₄and H₂O₂are present in about a 20:1:1 ratio.

15. The method as in claim 10, wherein said removing an upper portion comprises said mechanical cutting and includes using a diamond grit cutting surface that rotates relative said semiconductor wafer.

16. The method as in claim 10, wherein said bulk material layer comprises a copper layer having a thickness of about 9 microns and wherein said removing an upper portion includes removing about 6-7 microns of said copper layer.

17. The method as in claim 10, wherein said bulk material layer comprises a bulk metal layer, said bulk metal layer further filling openings that extend downward from said surface and wherein said polishing further comprises producing metal interconnect structures within said openings and having respective top surfaces being essentially coplanar with said surface.

18. The method as in claim 10, wherein said bulk material layer comprises a bulk metal layer and said removing an upper portion includes a first removal rate and said polishing comprises a second removal rate, said first removal rate being about 2-10 times greater than said second removal rate.

19. The method as in claim 18, wherein said bulk metal layer comprises copper and said first removal rate is about 3-4 micros/minute.