US20100169849A1 - Extracting Consistent Compact Model Parameters for Related Devices - Google Patents
Extracting Consistent Compact Model Parameters for Related Devices Download PDFInfo
- Publication number
- US20100169849A1 US20100169849A1 US12/344,724 US34472408A US2010169849A1 US 20100169849 A1 US20100169849 A1 US 20100169849A1 US 34472408 A US34472408 A US 34472408A US 2010169849 A1 US2010169849 A1 US 2010169849A1
- Authority
- US
- United States
- Prior art keywords
- parameters
- data
- semiconductor device
- devices
- measured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
Definitions
- the invention relates generally to semiconductor device fabrication and, in particular, to parameter extraction for device models.
- CMOS complementary metal oxide semiconductor
- Physically-based device modeling for the operational description of semiconductor devices is essential during the design phase to ensure the reliability of integrated circuits containing the semiconductor devices.
- the device model is an input for a circuit simulator.
- Semiconductor manufacturing technologies generally consist of a group of different transistor types to facilitate many types of circuit designs. Compact models are created for each of these transistor types. Because many of the processing steps are shared among different devices, different devices can often have similar characteristics. However, because compact model extraction is done on a device-by-device basis, these similarities can be lost in the model. This is generally more apparent where the device model has to be extrapolated into a space where no hardware data exists.
- Some devices may be categorized into device families, sharing many device characteristic but different in certain other characteristics (e.g., high V T , low V T ). These devices have characteristics that are similar in a lot of ways and should behave similarly as well.
- a single device model may have several hundred parameters to fit. Some parameters shared by these devices should have relationships and some should not.
- Contemporary modeling tools generally address one device at a time. When device modelers extract a device model for a device with a high V T , for example, they may fit the device model to achieve better correlation to data physically obtained from the device. Other device modelers may encounter a device model for a similar device with a low V T and fit the parameters for this model differently, where if they were evaluated together, might result in a simple scaling of some parameters of the device model.
- Consistency is generally checked at the end of the modeling process and if problems exist, they are typically corrected by adjusting parameters and reextraction, forcing repetition of steps in the process and adding time to the overall design.
- Embodiments of the present invention address these and other challenges in the art by providing a method, apparatus and program product for extracting parameters for compact models for semiconductor devices.
- a first set of parameters associated with first and second semiconductor devices is defined and has the same value for all devices.
- a second set of parameters associated with the first and second semiconductor devices is defined having values that differ among the devices.
- Data is measured from the first and second semiconductor devices related to the first and second set of parameters.
- a mathematical relationship is established between the measured data, and the values of the second set of parameters are adjusted to fit the established mathematical relationship.
- the mathematical relationship may include a ratio between the measured data of the first semiconductor device and the measured data of the second semiconductor device.
- Other relationships may include an offset between the measured data of the first semiconductor device and the measured data of the second semiconductor device, while still other mathematical relationships may enforce parameters in the first and second sets of parameters to have the same value.
- the mathematical relationships for some embodiments may be stored with model parameters.
- the values of the second sets of parameters may be adjusted by optimizing the values of the second set of parameters with the measured data and may include a complex fitness function, which contain penalty functions.
- the values of the second set of parameters may be adjusted by calculating correlation coefficients between the measured data and selected parameters of the second set of parameters to measure consistency between the compact models, which may then be used to determine of parameters need be re-extracted.
- the physical data from a first semiconductor device and physical data from a second semiconductor device may be measured.
- the measured physical data from the first semiconductor device may then be correlated with the measured physical data from the second semiconductor device in order to create a data set for parameter extraction.
- Parameters are extracted from the data set relating to the first and second semiconductor devices.
- the correlation may include correlating key parameters of the measured data to a specific device parameter, such as threshold voltage (V T ) for example.
- V T threshold voltage
- the correlation may also fit measured physical data from the first semiconductor device and the second semiconductor device to a curve, in other embodiments.
- FIG. 1 is a flowchart illustrating an exemplary prior art design methodology with device consistency checks.
- FIG. 2 is a flowchart illustrating a design methodology for an embodiment of the invention.
- FIG. 3 is a flowchart illustrating a design methodology for an alternative embodiment of the invention.
- FIG. 4 is a flowchart illustrating a design methodology for another alternative embodiment of the invention.
- FIG. 5 is a block diagram of an exemplary hardware and software environment suitable for implementing the design methodologies of FIGS. 1-4 .
- Contemporary design tools for semiconductor devices generally do not account for consistency in device models for families of device because the contemporary tools analyze only one device at a time. This necessitates additional checks, which tend to happen late in the design process.
- a set of devices is to be analyzed. These devices may be part of a family of devices or the devices may share at least one process step but fewer than all process steps in the fabrication of the devices.
- a contemporary analysis process begins by performing hardware measurements (block 12 ) for each of the devices. For example, if this set of devices contains device 1 , device 2 , and device 3 , hardware measurements may be performed on each device.
- the devices may be contained on a single test chip or be located on other test chips on other parts of a test wafer, for example.
- Associated with the hardware measurements for each of the devices is a set of parameters, which when extracted from the measured data can be used with the device models in simulations.
- Transistor models are used for almost all modern electronic design work. Analog circuit simulators use models to predict the behavior of a design. Much of the design work is related to integrated circuit designs which have a very large tooling cost, primarily for the photomasks used to create the devices, and there is a large economic incentive to get the design working without any iterations. Complete and accurate models allow a large percentage of designs to work the first time. Modern circuits are usually very complex making the performance of such circuits difficult to predict without accurate computer models, including but not limited to models of the devices used.
- the device models generally include effects of transistor layout: width, length, interdigitation, proximity to other devices; transient and DC current-voltage characteristics; parasitic device capacitance, resistance, and inductance; time delays; and temperature effects; to name a few items.
- each device may have a parameter set ⁇ x 1 , x 2 , x 3 , . . . , x i , x j , x k , . . . , x N-1 , x N ⁇ .
- These devices may belong to a family of devices and as being part of a family one skilled in the art would expect that many of these parameters may have the same value across each of the devices; however, a subset of the parameters that control the device models may have different values but still cause the model to have similar behavior in each of the devices. This subset may be ⁇ x i , x j , x k ⁇ from the example parameter set above.
- Each of the parameters for each of the devices is extracted from the hardware measurements (block 14 ) and the model parameters then go through a device centering step (block 16 ).
- a device centering step Generally during the device centering steps, a limited set of model parameters is adjusted to make key model characteristics match set technology targets. This step is typically performed to account for variations in processing, which make it challenging to identify a set of “perfect” nominal devices to use for model extraction. This becomes even more challenging when a new technology is in development and is not yet achieving target values.
- quality checks are performed on the extracted device model (block 18 ) for each of the devices. Once the set of devices have passed the quality check, a family consistency check is performed (block 20 ).
- the model is used for simulations of key device characteristics across the entire allowable range of device size, temperature, and bias conditions and checked for consistency between all devices in a family of devices. If the consistency checks fail, (“No” branch of decision block 22 ), then the portions of the models that are failing need to be modified and re-extracted (block 14 ) from the measured data which may need to be adjusted, or further manipulated or optimized prior to extraction. Then the device centering (block 16 ) and quality checks (block 18 ) are repeated. This continues until the family consistency checks pass (“Yes” branch of decision block 22 ) allowing the process to continue (block 24 ) to the next stages of the simulation process, adding time to the overall design process.
- the device family consistency checks may be moved up in the design process. Similar to the contemporary method of FIG. 1 , hardware measurements are performed on multiple devices (block 52 ). Parameters may then be extracted from the measured data (block 54 ). When parameter extraction for a device is completed up to a consistency checkpoint, it is compared against the other devices in the grouping or family that have been completed to the same point (block 56 ). The comparison may include checking for relationships of specific parameters in the models for each device and relationships between predicted V T , currents, and derivatives at specific geometries and biases for the different models.
- the inconsistent parameters may be re-extracted (block 54 ) as disclosed above, but prior to continuing with the process. If the consistency check passes (“Yes” branch of decision block 58 ), then a check is made to see if the parameter extraction is complete (block 60 ). If the parameter extraction is not complete (“No” branch of decision block 60 ), then the parameter extraction (block 54 ) and consistency checks (blocks 56 , 58 ) are repeated. Once all of the parameters have been extracted (“Yes” branch of decision block 60 ), the device centering (block 62 ) and quality checks (block 64 ) are performed, similar to the contemporary process. The process may then continue (block 66 ) to the next stages of the simulation process. By moving the consistency checks up in the process, this embodiment assists in streamlining the design process by avoiding repetition of some of the later process steps such as centering and quality checks.
- parameter extraction may be accomplished with fixed relationships, minimizing the need to perform device family consistency checks.
- consistencies between models and model parameters may be built into the parameter extraction rather than checking for consistency later as with the contemporary method of FIG. 1 or the embodiment in FIG. 2 .
- hardware measurements are performed on multiple devices (block 102 ).
- mathematical relationships may be determined between the measured data (block 104 ) and the device models. For example, first order analysis of the hardware data against physically based device equations may be used to determine starting values for key model parameters. These parameters may be fixed at these values or allowed to change only a limited amount from their respective values. Examples may include V THO being set to the relation determined by long device V tlin or LPE0 being set by measured V T roll-up.
- model parameters may also be optimized with a complex fitness functions to establish relationships between the parameters for a family of devices.
- These fitness functions may include penalty functions for parameters that did not maintain a mathematically defined relationship to the same parameter for other devices.
- Penalty functions may also include V T , current, or derivatives calculated at specific bias and geometry points that may have deviated from a target value derived from hardware for multiple devices. These penalty functions may be used to maintain similarity between devices. Additionally, the penalty functions may be used for deviation from specified geometric trends such as V T roll-off with width or ratio of off currents between devices of different lengths.
- the establishment of the mathematical relationships may be an interactive process with the device designer. Data for the same device geometries and biases may be shown for all devices in a group with measured and simulated data overlaid. Trend plots with length, width, and temperature may also be available. The trend plots may allow measured and simulated data to be displayed simultaneously for all devices in a group for analysis. The device modeler may then select parameters for optimization, which may then be optimized for all device types simultaneously. Other mathematical relations may be enforced as part of the optimization such as an offset or ratio between parameters. This offset or ratio may be optimized within user-controlled limits or could be fixed. Alternatively, the offset or ratio may be set to a fixed value determined from parameters outside of the optimization. An offset of zero may indicate that some of the selected parameters may have the same value in all models.
- parameters may be simultaneously extracted (block 106 ) using the relationships. For example, during parameter extraction, limits may be set based on the value of a parameter in a model or models in other related devices. A parameter could be limited to the value of the same parameter for another device within a tolerance, or it could be limited to be between the values in two other devices.
- the device centering (block 108 ) and quality checks (block 110 ) steps may be performed similar to the embodiments above. After the quality checks, the process may continue (block 112 ) to the next stages of the simulation process. This embodiment minimizes the need for device family consistency checks as part of the process because the consistency between parameters for the family of devices is built in to the extraction process by way of the mathematical relationships established as part of the process.
- a consistent data set may be established before parameter extraction to provide for consistency between parameters of device families.
- again hardware measurements are performed for multiple devices (block 152 ).
- a consistent data set is generated for all devices that has the expected device characteristics and relational consistency (block 154 ).
- the calculation of correlation coefficients between the measured values and corresponding simulated values may be used as a measure of consistency between models.
- This may then be used as part of a complex fitness function, during optimization for example, for simultaneous extraction or for checking during parallel extraction.
- Correlation coefficients between these measured values and selected model parameters of each FET type may be a measure of model consistency. Although this measure is less direct than the correlation of measured and simulated data, it may assist in ensuring consistency for geometries not measured.
- This correlation coefficient may then be used as part of a complex fitness function during optimization for simultaneous extraction or for checking during parallel extraction.
- parameters may be extracted (block 156 ) with a confidence level that the data used for the extraction has consistent behavior.
- device centering (block 158 ) and quality checks (block 160 ) may be performed. The process may then continue (block 162 ) to the next stages of the simulation process.
- each of these methods in the embodiments above may be available to a designer with the designer being able to interact with some or all of steps including analyzing and creating the mathematical relationships, generating the consistent data set, correlating data, verifying consistency in device families, and adjusting models in the device centering steps.
- the present invention may be embodied as a system, method or computer program product.
- the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.”
- the present invention may take the form of a computer program product embodied in any tangible medium of expression having computer-usable program code embodied in the medium.
- the computer-usable or computer-readable medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium.
- the computer-readable medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CDROM), an optical storage device, a transmission media such as those supporting the Internet or an intranet, or a magnetic storage device.
- a computer-usable or computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
- a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
- the computer-usable medium may include a propagated data signal with the computer-usable program code embodied therewith, either in baseband or as part of a carrier wave.
- the computer usable program code may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc.
- Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.
- the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
- the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
- LAN local area network
- WAN wide area network
- Internet Service Provider for example, AT&T, MCI, Sprint, EarthLink, MSN, GTE, etc.
- These computer program instructions may also be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instruction means which implement the function/act specified in the flowchart and/or block diagram block or blocks.
- the computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
- FIG. 5 illustrates an exemplary hardware and software environment for an apparatus 200 suitable for extracting parameters for compact models for semiconductor devices consistent with embodiments of the invention.
- apparatus 200 may represent practically any computer, computer system, or programmable device e.g., multi-user or single-user computers, desktop computers, portable computers and devices, handheld devices, network devices, mobile phones, etc.
- Apparatus 200 will hereinafter be referred to as a “computer” although it should be appreciated that the term “apparatus” may also include other suitable programmable electronic devices.
- Computer 200 typically includes at least one processor 202 coupled to a memory 204 .
- Processor 202 may represent one or more processors (e.g. microprocessors), and memory 204 may represent the random access memory (RAM) devices comprising the main storage of computer 200 , as well as any supplemental levels of memory, e.g., cache memories, non-volatile or backup memories (e.g. programmable or flash memories), read-only memories, etc.
- RAM random access memory
- memory 204 may be considered to include memory storage physically located elsewhere in computer 200 , e.g., any cache memory in a processor 202 , as well as any storage capacity used as a virtual memory, e.g., as stored on a mass storage device 206 or another computer coupled to computer 200 via a network 208 .
- Computer 200 also typically receives a number of inputs and outputs for communicating information externally.
- computer 200 typically includes one or more user input devices 210 (e.g., a keyboard, a mouse, a trackball, a joystick, a touchpad, a keypad, a stylus, and/or a microphone, among others).
- Computer 200 may also include a display 212 (e.g., a CRT monitor, an LCD display panel, and/or a speaker, among others).
- the interface to computer 200 may also be through an external terminal connected directly or remotely to computer 200 , or through another computer communicating with computer 200 via a network 208 , modem, or other type of communications device.
- Computer 200 operates under the control of an operating system 214 , and executes or otherwise relies upon various computer software applications, components, programs, objects, modules, data structures, etc. (e.g. simulator 218 or parameter extraction tool 220 ). Simulator 218 , for example, may require device parameters extracted by the parameter extraction tool 220 from the compact device models and physical data. Computer 200 communicates on the network 208 through a network interface 224 .
- each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s).
- the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
- Embodiments of the invention assist in building consistency into the device models during the extraction process. This may be accomplished by forcing key model parameters to the same value for device models or by forcing key model parameters to a specified relationship for the device models. Enforced checking of key model parameters relationships during the extraction process and limiting allowed model parameter ranges during extraction to values determined by a theoretical analysis of the data and known relationships between the devices assists in improving parameter consistency and also assists in creating a set of self consistent targets for devices that are used during the extraction of some model components. Simultaneous extraction of devices may also be employed to force the model consistency during the extraction process, potentially avoiding later problems with consistency. Generally it is more efficient to build consistency into the models during the extraction process than to try to correct issues with consistency at the end of the process.
Abstract
Description
- The invention relates generally to semiconductor device fabrication and, in particular, to parameter extraction for device models.
- Device models are commonly used to scientifically model the physical phenomena observed during the operation of semiconductor devices, such as complementary metal oxide semiconductor (CMOS) devices like field effect transistors. Physically-based device modeling for the operational description of semiconductor devices is essential during the design phase to ensure the reliability of integrated circuits containing the semiconductor devices. The device model is an input for a circuit simulator.
- Semiconductor manufacturing technologies generally consist of a group of different transistor types to facilitate many types of circuit designs. Compact models are created for each of these transistor types. Because many of the processing steps are shared among different devices, different devices can often have similar characteristics. However, because compact model extraction is done on a device-by-device basis, these similarities can be lost in the model. This is generally more apparent where the device model has to be extrapolated into a space where no hardware data exists.
- Some devices may be categorized into device families, sharing many device characteristic but different in certain other characteristics (e.g., high VT, low VT). These devices have characteristics that are similar in a lot of ways and should behave similarly as well. A single device model may have several hundred parameters to fit. Some parameters shared by these devices should have relationships and some should not. Contemporary modeling tools generally address one device at a time. When device modelers extract a device model for a device with a high VT, for example, they may fit the device model to achieve better correlation to data physically obtained from the device. Other device modelers may encounter a device model for a similar device with a low VT and fit the parameters for this model differently, where if they were evaluated together, might result in a simple scaling of some parameters of the device model. Because different individuals may be extracting device models and because the extractions for the device models of families of devices may be done at different times, inconsistencies may be introduced into the models that are not discovered until quality checking is performed. Additionally, contemporary model extraction tools do not force any consistency between related devices. Consistency is generally checked at the end of the modeling process and if problems exist, they are typically corrected by adjusting parameters and reextraction, forcing repetition of steps in the process and adding time to the overall design.
- What is needed therefore is a methodology to provide better consistency between models and model parameters.
- Embodiments of the present invention address these and other challenges in the art by providing a method, apparatus and program product for extracting parameters for compact models for semiconductor devices. A first set of parameters associated with first and second semiconductor devices is defined and has the same value for all devices. A second set of parameters associated with the first and second semiconductor devices is defined having values that differ among the devices. Data is measured from the first and second semiconductor devices related to the first and second set of parameters. A mathematical relationship is established between the measured data, and the values of the second set of parameters are adjusted to fit the established mathematical relationship.
- For some of the parameters in some embodiments, the mathematical relationship may include a ratio between the measured data of the first semiconductor device and the measured data of the second semiconductor device. Other relationships may include an offset between the measured data of the first semiconductor device and the measured data of the second semiconductor device, while still other mathematical relationships may enforce parameters in the first and second sets of parameters to have the same value. The mathematical relationships for some embodiments may be stored with model parameters.
- In some embodiments, the values of the second sets of parameters may be adjusted by optimizing the values of the second set of parameters with the measured data and may include a complex fitness function, which contain penalty functions. Alternatively, in some embodiments, the values of the second set of parameters may be adjusted by calculating correlation coefficients between the measured data and selected parameters of the second set of parameters to measure consistency between the compact models, which may then be used to determine of parameters need be re-extracted.
- In other embodiments of the invention, the physical data from a first semiconductor device and physical data from a second semiconductor device may be measured. The measured physical data from the first semiconductor device may then be correlated with the measured physical data from the second semiconductor device in order to create a data set for parameter extraction. Parameters are extracted from the data set relating to the first and second semiconductor devices. The correlation may include correlating key parameters of the measured data to a specific device parameter, such as threshold voltage (VT) for example. The correlation may also fit measured physical data from the first semiconductor device and the second semiconductor device to a curve, in other embodiments.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description given below, serve to explain the principles of the invention.
-
FIG. 1 is a flowchart illustrating an exemplary prior art design methodology with device consistency checks. -
FIG. 2 is a flowchart illustrating a design methodology for an embodiment of the invention. -
FIG. 3 is a flowchart illustrating a design methodology for an alternative embodiment of the invention. -
FIG. 4 is a flowchart illustrating a design methodology for another alternative embodiment of the invention. -
FIG. 5 is a block diagram of an exemplary hardware and software environment suitable for implementing the design methodologies ofFIGS. 1-4 . - Contemporary design tools for semiconductor devices generally do not account for consistency in device models for families of device because the contemporary tools analyze only one device at a time. This necessitates additional checks, which tend to happen late in the design process. For example and with reference to the
flowchart 10 inFIG. 1 , a set of devices is to be analyzed. These devices may be part of a family of devices or the devices may share at least one process step but fewer than all process steps in the fabrication of the devices. A contemporary analysis process, as shown inFIG. 1 , begins by performing hardware measurements (block 12) for each of the devices. For example, if this set of devices contains device 1, device 2, and device 3, hardware measurements may be performed on each device. This may be done serially or in parallel, and the devices may be contained on a single test chip or be located on other test chips on other parts of a test wafer, for example. Associated with the hardware measurements for each of the devices is a set of parameters, which when extracted from the measured data can be used with the device models in simulations. - Transistor models are used for almost all modern electronic design work. Analog circuit simulators use models to predict the behavior of a design. Much of the design work is related to integrated circuit designs which have a very large tooling cost, primarily for the photomasks used to create the devices, and there is a large economic incentive to get the design working without any iterations. Complete and accurate models allow a large percentage of designs to work the first time. Modern circuits are usually very complex making the performance of such circuits difficult to predict without accurate computer models, including but not limited to models of the devices used. The device models generally include effects of transistor layout: width, length, interdigitation, proximity to other devices; transient and DC current-voltage characteristics; parasitic device capacitance, resistance, and inductance; time delays; and temperature effects; to name a few items.
- Traditional model-extraction methods are generally based on a combination of direct parameter extraction that uses mathematical simplification of the model equations, and optimization that uses the full, highly non-linear model equations. Because of the complexity of the model and data, these methods allow optimization of only a few parameters at at time. Optimization also often leads to local optimas which do not result in a model that is accurate enough to be useful, or may lead to inconsistencies between models of related devices.
- For example, each device (1, 2, and 3) may have a parameter set {x1, x2, x3, . . . , xi, xj, xk, . . . , xN-1, xN}. These devices may belong to a family of devices and as being part of a family one skilled in the art would expect that many of these parameters may have the same value across each of the devices; however, a subset of the parameters that control the device models may have different values but still cause the model to have similar behavior in each of the devices. This subset may be {xi, xj, xk} from the example parameter set above.
- Each of the parameters for each of the devices is extracted from the hardware measurements (block 14) and the model parameters then go through a device centering step (block 16). Generally during the device centering steps, a limited set of model parameters is adjusted to make key model characteristics match set technology targets. This step is typically performed to account for variations in processing, which make it challenging to identify a set of “perfect” nominal devices to use for model extraction. This becomes even more challenging when a new technology is in development and is not yet achieving target values. After the centering steps, quality checks are performed on the extracted device model (block 18) for each of the devices. Once the set of devices have passed the quality check, a family consistency check is performed (block 20). At this stage the model is used for simulations of key device characteristics across the entire allowable range of device size, temperature, and bias conditions and checked for consistency between all devices in a family of devices. If the consistency checks fail, (“No” branch of decision block 22), then the portions of the models that are failing need to be modified and re-extracted (block 14) from the measured data which may need to be adjusted, or further manipulated or optimized prior to extraction. Then the device centering (block 16) and quality checks (block 18) are repeated. This continues until the family consistency checks pass (“Yes” branch of decision block 22) allowing the process to continue (block 24) to the next stages of the simulation process, adding time to the overall design process.
- An alternative to the contemporary process of
FIG. 1 is shown in an embodiment of the process in theflowchart 50 inFIG. 2 . In this embodiment, the device family consistency checks may be moved up in the design process. Similar to the contemporary method ofFIG. 1 , hardware measurements are performed on multiple devices (block 52). Parameters may then be extracted from the measured data (block 54). When parameter extraction for a device is completed up to a consistency checkpoint, it is compared against the other devices in the grouping or family that have been completed to the same point (block 56). The comparison may include checking for relationships of specific parameters in the models for each device and relationships between predicted VT, currents, and derivatives at specific geometries and biases for the different models. If the consistency checks do not pass (“No” branch of decision block 58), then the inconsistent parameters may be re-extracted (block 54) as disclosed above, but prior to continuing with the process. If the consistency check passes (“Yes” branch of decision block 58), then a check is made to see if the parameter extraction is complete (block 60). If the parameter extraction is not complete (“No” branch of decision block 60), then the parameter extraction (block 54) and consistency checks (blocks 56, 58) are repeated. Once all of the parameters have been extracted (“Yes” branch of decision block 60), the device centering (block 62) and quality checks (block 64) are performed, similar to the contemporary process. The process may then continue (block 66) to the next stages of the simulation process. By moving the consistency checks up in the process, this embodiment assists in streamlining the design process by avoiding repetition of some of the later process steps such as centering and quality checks. - In an alternative embodiment shown in the
flowchart 100 inFIG. 3 , parameter extraction may be accomplished with fixed relationships, minimizing the need to perform device family consistency checks. In this embodiment, consistencies between models and model parameters may be built into the parameter extraction rather than checking for consistency later as with the contemporary method ofFIG. 1 or the embodiment inFIG. 2 . In this embodiment, hardware measurements are performed on multiple devices (block 102). With knowledge of the devices and the data measured from each of the devices, mathematical relationships may be determined between the measured data (block 104) and the device models. For example, first order analysis of the hardware data against physically based device equations may be used to determine starting values for key model parameters. These parameters may be fixed at these values or allowed to change only a limited amount from their respective values. Examples may include VTHO being set to the relation determined by long device Vtlin or LPE0 being set by measured VT roll-up. - Additionally, model parameters may also be optimized with a complex fitness functions to establish relationships between the parameters for a family of devices. These fitness functions may include penalty functions for parameters that did not maintain a mathematically defined relationship to the same parameter for other devices. Penalty functions may also include VT, current, or derivatives calculated at specific bias and geometry points that may have deviated from a target value derived from hardware for multiple devices. These penalty functions may be used to maintain similarity between devices. Additionally, the penalty functions may be used for deviation from specified geometric trends such as VT roll-off with width or ratio of off currents between devices of different lengths.
- In some embodiments, the establishment of the mathematical relationships (block 104) may be an interactive process with the device designer. Data for the same device geometries and biases may be shown for all devices in a group with measured and simulated data overlaid. Trend plots with length, width, and temperature may also be available. The trend plots may allow measured and simulated data to be displayed simultaneously for all devices in a group for analysis. The device modeler may then select parameters for optimization, which may then be optimized for all device types simultaneously. Other mathematical relations may be enforced as part of the optimization such as an offset or ratio between parameters. This offset or ratio may be optimized within user-controlled limits or could be fixed. Alternatively, the offset or ratio may be set to a fixed value determined from parameters outside of the optimization. An offset of zero may indicate that some of the selected parameters may have the same value in all models.
- After the mathematical relationships between the parameters have been established, parameters may be simultaneously extracted (block 106) using the relationships. For example, during parameter extraction, limits may be set based on the value of a parameter in a model or models in other related devices. A parameter could be limited to the value of the same parameter for another device within a tolerance, or it could be limited to be between the values in two other devices. Once the extraction is completed, the device centering (block 108) and quality checks (block 110) steps may be performed similar to the embodiments above. After the quality checks, the process may continue (block 112) to the next stages of the simulation process. This embodiment minimizes the need for device family consistency checks as part of the process because the consistency between parameters for the family of devices is built in to the extraction process by way of the mathematical relationships established as part of the process.
- In yet another alternative, similar to the embodiment above and seen in the
flowchart 150 inFIG. 4 , a consistent data set may be established before parameter extraction to provide for consistency between parameters of device families. In this embodiment, again hardware measurements are performed for multiple devices (block 152). From the hardware measurements, a consistent data set is generated for all devices that has the expected device characteristics and relational consistency (block 154). The calculation of correlation coefficients between the measured values and corresponding simulated values may be used as a measure of consistency between models. This may then be used as part of a complex fitness function, during optimization for example, for simultaneous extraction or for checking during parallel extraction. Correlation coefficients between these measured values and selected model parameters of each FET type may be a measure of model consistency. Although this measure is less direct than the correlation of measured and simulated data, it may assist in ensuring consistency for geometries not measured. This correlation coefficient may then be used as part of a complex fitness function during optimization for simultaneous extraction or for checking during parallel extraction. - Once a consistent data set is established from the measured data, parameters may be extracted (block 156) with a confidence level that the data used for the extraction has consistent behavior. After the parameters have been extracted, as with the previous embodiments, device centering (block 158) and quality checks (block 160) may be performed. The process may then continue (block 162) to the next stages of the simulation process.
- Each of these methods in the embodiments above may be available to a designer with the designer being able to interact with some or all of steps including analyzing and creating the mathematical relationships, generating the consistent data set, correlating data, verifying consistency in device families, and adjusting models in the device centering steps. As will be appreciated by one skilled in the art, the present invention may be embodied as a system, method or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, the present invention may take the form of a computer program product embodied in any tangible medium of expression having computer-usable program code embodied in the medium.
- Any combination of one or more computer usable or computer readable medium(s) may be utilized. The computer-usable or computer-readable medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CDROM), an optical storage device, a transmission media such as those supporting the Internet or an intranet, or a magnetic storage device. Note that the computer-usable or computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory. In the context of this document, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-usable medium may include a propagated data signal with the computer-usable program code embodied therewith, either in baseband or as part of a carrier wave. The computer usable program code may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc.
- Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). The present invention is described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
- These computer program instructions may also be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instruction means which implement the function/act specified in the flowchart and/or block diagram block or blocks.
- The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
-
FIG. 5 illustrates an exemplary hardware and software environment for anapparatus 200 suitable for extracting parameters for compact models for semiconductor devices consistent with embodiments of the invention. For the purposes of the invention,apparatus 200 may represent practically any computer, computer system, or programmable device e.g., multi-user or single-user computers, desktop computers, portable computers and devices, handheld devices, network devices, mobile phones, etc.Apparatus 200 will hereinafter be referred to as a “computer” although it should be appreciated that the term “apparatus” may also include other suitable programmable electronic devices. -
Computer 200 typically includes at least oneprocessor 202 coupled to amemory 204.Processor 202 may represent one or more processors (e.g. microprocessors), andmemory 204 may represent the random access memory (RAM) devices comprising the main storage ofcomputer 200, as well as any supplemental levels of memory, e.g., cache memories, non-volatile or backup memories (e.g. programmable or flash memories), read-only memories, etc. In addition,memory 204 may be considered to include memory storage physically located elsewhere incomputer 200, e.g., any cache memory in aprocessor 202, as well as any storage capacity used as a virtual memory, e.g., as stored on amass storage device 206 or another computer coupled tocomputer 200 via anetwork 208. -
Computer 200 also typically receives a number of inputs and outputs for communicating information externally. For interface with a user or operator,computer 200 typically includes one or more user input devices 210 (e.g., a keyboard, a mouse, a trackball, a joystick, a touchpad, a keypad, a stylus, and/or a microphone, among others).Computer 200 may also include a display 212 (e.g., a CRT monitor, an LCD display panel, and/or a speaker, among others). The interface tocomputer 200 may also be through an external terminal connected directly or remotely tocomputer 200, or through another computer communicating withcomputer 200 via anetwork 208, modem, or other type of communications device. -
Computer 200 operates under the control of anoperating system 214, and executes or otherwise relies upon various computer software applications, components, programs, objects, modules, data structures, etc. (e.g. simulator 218 or parameter extraction tool 220).Simulator 218, for example, may require device parameters extracted by theparameter extraction tool 220 from the compact device models and physical data.Computer 200 communicates on thenetwork 208 through anetwork interface 224. - The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
- Embodiments of the invention assist in building consistency into the device models during the extraction process. This may be accomplished by forcing key model parameters to the same value for device models or by forcing key model parameters to a specified relationship for the device models. Enforced checking of key model parameters relationships during the extraction process and limiting allowed model parameter ranges during extraction to values determined by a theoretical analysis of the data and known relationships between the devices assists in improving parameter consistency and also assists in creating a set of self consistent targets for devices that are used during the extraction of some model components. Simultaneous extraction of devices may also be employed to force the model consistency during the extraction process, potentially avoiding later problems with consistency. Generally it is more efficient to build consistency into the models during the extraction process than to try to correct issues with consistency at the end of the process.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (21)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/344,724 US8010930B2 (en) | 2008-12-29 | 2008-12-29 | Extracting consistent compact model parameters for related devices |
KR1020090089913A KR20100080331A (en) | 2008-12-29 | 2009-09-23 | Extracting consistent compact model parameters for related devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/344,724 US8010930B2 (en) | 2008-12-29 | 2008-12-29 | Extracting consistent compact model parameters for related devices |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100169849A1 true US20100169849A1 (en) | 2010-07-01 |
US8010930B2 US8010930B2 (en) | 2011-08-30 |
Family
ID=42286477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/344,724 Expired - Fee Related US8010930B2 (en) | 2008-12-29 | 2008-12-29 | Extracting consistent compact model parameters for related devices |
Country Status (2)
Country | Link |
---|---|
US (1) | US8010930B2 (en) |
KR (1) | KR20100080331A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110153055A1 (en) * | 2009-12-17 | 2011-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wide-range quick tunable transistor model |
US8539426B2 (en) | 2011-02-22 | 2013-09-17 | International Business Machines Corporation | Method and system for extracting compact models for circuit simulation |
US8560991B1 (en) * | 2010-10-05 | 2013-10-15 | Cadence Design Systems, Inc. | Automatic debugging using automatic input data mutation |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8453101B1 (en) | 2011-11-22 | 2013-05-28 | International Business Machines Corporation | Method, system and program storage device for generating accurate performance targets for active semiconductor devices during new technology node development |
US9679094B2 (en) | 2015-04-29 | 2017-06-13 | International Business Machines Corporation | Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types |
US10056224B2 (en) * | 2015-08-10 | 2018-08-21 | Kla-Tencor Corporation | Method and system for edge-of-wafer inspection and review |
KR102285516B1 (en) | 2021-02-05 | 2021-08-04 | 주식회사 알세미 | Semiconductor device modeling method and system |
Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4759675A (en) * | 1984-03-22 | 1988-07-26 | Sgs-Thomson Microelectronics, Inc. | Chip selection in automatic assembly of integrated circuit |
US5379232A (en) * | 1991-08-22 | 1995-01-03 | Mitsubishi Denki Kabushiki Kaisha | Logic simulator |
US5396615A (en) * | 1991-08-06 | 1995-03-07 | Mitsubishi Denki Kabushiki Kaisha | System for simulating electrical delay characteristics of logic circuits |
US5543334A (en) * | 1993-12-15 | 1996-08-06 | Kabushiki Kaisha Toshiba | Method of screening semiconductor device |
US5651099A (en) * | 1995-01-26 | 1997-07-22 | Hewlett-Packard Company | Use of a genetic algorithm to optimize memory space |
US5687355A (en) * | 1995-08-21 | 1997-11-11 | Motorola, Inc. | Apparatus and method for modeling a graded channel transistor |
US5867398A (en) * | 1996-06-28 | 1999-02-02 | Lsi Logic Corporation | Advanced modular cell placement system with density driven capacity penalty system |
US5994912A (en) * | 1995-10-31 | 1999-11-30 | Texas Instruments Incorporated | Fault tolerant selection of die on wafer |
US6314390B1 (en) * | 1998-11-30 | 2001-11-06 | International Business Machines Corporation | Method of determining model parameters for a MOSFET compact model using a stochastic search algorithm |
US6356861B1 (en) * | 1999-04-12 | 2002-03-12 | Agere Systems Guardian Corp. | Deriving statistical device models from worst-case files |
US6430729B1 (en) * | 2000-01-31 | 2002-08-06 | International Business Machines Corporation | Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing |
US6446022B1 (en) * | 1999-02-18 | 2002-09-03 | Advanced Micro Devices, Inc. | Wafer fabrication system providing measurement data screening |
US6577993B1 (en) * | 1998-08-31 | 2003-06-10 | Nec Corporation | Method of extracting parameters of diffusion model capable of extracting the parameters quickly |
US20030114944A1 (en) * | 2001-12-17 | 2003-06-19 | International Business Machines Corporation | System and method for target-based compact modeling |
US6594594B1 (en) * | 2000-04-28 | 2003-07-15 | Northrop Grumman Corporation | Method for unique determination of FET equivalent circuit model parameters |
US20030220779A1 (en) * | 2002-03-29 | 2003-11-27 | Ping Chen | Extracting semiconductor device model parameters |
US20050086033A1 (en) * | 2002-08-30 | 2005-04-21 | Cadence Design Systems, Inc. | Extracting semiconductor device model parameters |
US6934671B2 (en) * | 2001-05-29 | 2005-08-23 | International Business Machines Corporation | Method and system for including parametric in-line test data in simulations for improved model to hardware correlation |
US7089512B2 (en) * | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits |
US7099808B2 (en) * | 1999-08-26 | 2006-08-29 | Mentor Graphics Corp. | Capacitance and transmission line measurements for an integrated circuit |
US20060282802A1 (en) * | 2005-06-11 | 2006-12-14 | Yechuri Sitaramarao S | Method of extracting a semiconductor device compact model |
US7263477B2 (en) * | 2003-06-09 | 2007-08-28 | Cadence Design Systems, Inc. | Method and apparatus for modeling devices having different geometries |
US7289859B2 (en) * | 2005-09-30 | 2007-10-30 | Hitachi, Ltd. | Method for determining parameter of product design and its supporting system |
US20070261011A1 (en) * | 2006-05-04 | 2007-11-08 | Pino Robinson E | Modeling small mosfets using ensemble devices |
US7305332B1 (en) * | 2004-01-14 | 2007-12-04 | Adaptec, Inc. | System and method for automatic extraction of testing information from a functional specification |
US20090187525A1 (en) * | 2006-07-28 | 2009-07-23 | Persistent Systems Private Limited | System and method for network association inference, validation and pruning based on integrated constraints from diverse data |
US7624079B2 (en) * | 1996-05-06 | 2009-11-24 | Rockwell Automation Technologies, Inc. | Method and apparatus for training a system model with gain constraints using a non-linear programming optimizer |
US20100099033A1 (en) * | 2007-02-07 | 2010-04-22 | Yoel Cohen | Method and system for measuring in patterned structures |
US20100217568A1 (en) * | 2006-02-08 | 2010-08-26 | Nec Corporation | Variation simulation system, method for determining variations, apparatus for determining variations and program |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001148469A (en) | 1999-11-19 | 2001-05-29 | Rohm Co Ltd | Extracting device for ferroelectric fet characteristic constant |
US7337420B2 (en) | 2005-07-29 | 2008-02-26 | International Business Machines Corporation | Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models |
-
2008
- 2008-12-29 US US12/344,724 patent/US8010930B2/en not_active Expired - Fee Related
-
2009
- 2009-09-23 KR KR1020090089913A patent/KR20100080331A/en active IP Right Grant
Patent Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4759675A (en) * | 1984-03-22 | 1988-07-26 | Sgs-Thomson Microelectronics, Inc. | Chip selection in automatic assembly of integrated circuit |
US5396615A (en) * | 1991-08-06 | 1995-03-07 | Mitsubishi Denki Kabushiki Kaisha | System for simulating electrical delay characteristics of logic circuits |
US5379232A (en) * | 1991-08-22 | 1995-01-03 | Mitsubishi Denki Kabushiki Kaisha | Logic simulator |
US5543334A (en) * | 1993-12-15 | 1996-08-06 | Kabushiki Kaisha Toshiba | Method of screening semiconductor device |
US5651099A (en) * | 1995-01-26 | 1997-07-22 | Hewlett-Packard Company | Use of a genetic algorithm to optimize memory space |
US5687355A (en) * | 1995-08-21 | 1997-11-11 | Motorola, Inc. | Apparatus and method for modeling a graded channel transistor |
US5994912A (en) * | 1995-10-31 | 1999-11-30 | Texas Instruments Incorporated | Fault tolerant selection of die on wafer |
US7624079B2 (en) * | 1996-05-06 | 2009-11-24 | Rockwell Automation Technologies, Inc. | Method and apparatus for training a system model with gain constraints using a non-linear programming optimizer |
US5867398A (en) * | 1996-06-28 | 1999-02-02 | Lsi Logic Corporation | Advanced modular cell placement system with density driven capacity penalty system |
US6577993B1 (en) * | 1998-08-31 | 2003-06-10 | Nec Corporation | Method of extracting parameters of diffusion model capable of extracting the parameters quickly |
US6314390B1 (en) * | 1998-11-30 | 2001-11-06 | International Business Machines Corporation | Method of determining model parameters for a MOSFET compact model using a stochastic search algorithm |
US6446022B1 (en) * | 1999-02-18 | 2002-09-03 | Advanced Micro Devices, Inc. | Wafer fabrication system providing measurement data screening |
US6356861B1 (en) * | 1999-04-12 | 2002-03-12 | Agere Systems Guardian Corp. | Deriving statistical device models from worst-case files |
US7099808B2 (en) * | 1999-08-26 | 2006-08-29 | Mentor Graphics Corp. | Capacitance and transmission line measurements for an integrated circuit |
US6430729B1 (en) * | 2000-01-31 | 2002-08-06 | International Business Machines Corporation | Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing |
US6594594B1 (en) * | 2000-04-28 | 2003-07-15 | Northrop Grumman Corporation | Method for unique determination of FET equivalent circuit model parameters |
US6934671B2 (en) * | 2001-05-29 | 2005-08-23 | International Business Machines Corporation | Method and system for including parametric in-line test data in simulations for improved model to hardware correlation |
US20030114944A1 (en) * | 2001-12-17 | 2003-06-19 | International Business Machines Corporation | System and method for target-based compact modeling |
US20030220779A1 (en) * | 2002-03-29 | 2003-11-27 | Ping Chen | Extracting semiconductor device model parameters |
US20050086033A1 (en) * | 2002-08-30 | 2005-04-21 | Cadence Design Systems, Inc. | Extracting semiconductor device model parameters |
US7263477B2 (en) * | 2003-06-09 | 2007-08-28 | Cadence Design Systems, Inc. | Method and apparatus for modeling devices having different geometries |
US7305332B1 (en) * | 2004-01-14 | 2007-12-04 | Adaptec, Inc. | System and method for automatic extraction of testing information from a functional specification |
US7089512B2 (en) * | 2004-03-15 | 2006-08-08 | International Business Machines Corporation | Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits |
US20060282802A1 (en) * | 2005-06-11 | 2006-12-14 | Yechuri Sitaramarao S | Method of extracting a semiconductor device compact model |
US7289859B2 (en) * | 2005-09-30 | 2007-10-30 | Hitachi, Ltd. | Method for determining parameter of product design and its supporting system |
US20100217568A1 (en) * | 2006-02-08 | 2010-08-26 | Nec Corporation | Variation simulation system, method for determining variations, apparatus for determining variations and program |
US7353473B2 (en) * | 2006-05-04 | 2008-04-01 | International Business Machines Corporation | Modeling small mosfets using ensemble devices |
US20070261011A1 (en) * | 2006-05-04 | 2007-11-08 | Pino Robinson E | Modeling small mosfets using ensemble devices |
US20090187525A1 (en) * | 2006-07-28 | 2009-07-23 | Persistent Systems Private Limited | System and method for network association inference, validation and pruning based on integrated constraints from diverse data |
US20100099033A1 (en) * | 2007-02-07 | 2010-04-22 | Yoel Cohen | Method and system for measuring in patterned structures |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110153055A1 (en) * | 2009-12-17 | 2011-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wide-range quick tunable transistor model |
US8560991B1 (en) * | 2010-10-05 | 2013-10-15 | Cadence Design Systems, Inc. | Automatic debugging using automatic input data mutation |
US8539426B2 (en) | 2011-02-22 | 2013-09-17 | International Business Machines Corporation | Method and system for extracting compact models for circuit simulation |
Also Published As
Publication number | Publication date |
---|---|
US8010930B2 (en) | 2011-08-30 |
KR20100080331A (en) | 2010-07-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7761275B2 (en) | Synthesizing current source driver model for analysis of cell characteristics | |
US8010930B2 (en) | Extracting consistent compact model parameters for related devices | |
US20120023467A1 (en) | Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness | |
US6278964B1 (en) | Hot carrier effect simulation for integrated circuits | |
US8875077B1 (en) | Fault sensitivity analysis-based cell-aware automated test pattern generation flow | |
US8914760B2 (en) | Electrical hotspot detection, analysis and correction | |
US9817932B2 (en) | Recognizing and utilizing circuit topology in an electronic circuit design | |
US8230382B2 (en) | Model based simulation of electronic discharge and optimization methodology for design checking | |
US9177096B2 (en) | Timing closure using transistor sizing in standard cells | |
US20080092004A1 (en) | Method and system for automated path delay test vector generation from functional tests | |
US8032349B2 (en) | Efficient methodology for the accurate generation of customized compact model parameters from electrical test data | |
US8813006B1 (en) | Accelerated characterization of circuits for within-die process variations | |
KR20220048941A (en) | Systems, methods, and computer program products for transistor compact modeling using artificial neural networks | |
US8150638B1 (en) | Predicting parasitic capacitance in schematic circuit simulations using sub-circuit modeling | |
US11568113B2 (en) | Variation-aware delay fault testing | |
US8645883B2 (en) | Integrated circuit simulation using fundamental and derivative circuit runs | |
CN109214023B (en) | Test method and device for process design toolkit | |
CN112632891A (en) | SPICE model simulation system and simulation method | |
US10666255B1 (en) | System and method for compacting X-pessimism fixes for gate-level logic simulation | |
US8863050B1 (en) | Efficient single-run method to determine analog fault coverage versus bridge resistance | |
US20210165940A1 (en) | Method and apparatus for estimating aging of integrated circuit | |
Barke et al. | Formal approaches to analog circuit verification | |
US8332199B1 (en) | Graphical user interface for viewing intermediate calculations from a device model | |
WO2019142266A1 (en) | Test case generation device, test case generation method, and test case generation program | |
Hahne et al. | ReliaVision: In-circuit transistor reliability investigation using XML-based technology reliability information in PDKs |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION,NEW YO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TROMBLEY, HENRY W;WATTS, JOSEF S;REEL/FRAME:022032/0179 Effective date: 20080902 Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TROMBLEY, HENRY W;WATTS, JOSEF S;REEL/FRAME:022032/0179 Effective date: 20080902 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
SULP | Surcharge for late payment | ||
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20190830 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |