US20100187668A1 - Novel build-up package for integrated circuit devices, and methods of making same - Google Patents
Novel build-up package for integrated circuit devices, and methods of making same Download PDFInfo
- Publication number
- US20100187668A1 US20100187668A1 US12/753,562 US75356210A US2010187668A1 US 20100187668 A1 US20100187668 A1 US 20100187668A1 US 75356210 A US75356210 A US 75356210A US 2010187668 A1 US2010187668 A1 US 2010187668A1
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- die
- molded body
- integrated circuit
- active surface
- layer
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.
Description
- This application is a divisional of U.S. application Ser. No. 11/768,413 filed Jun. 26, 2007, issued as U.S. Pat. No. 7,691,682, which is incorporated herein by reference.
- 1. Technical Field
- The present invention is generally directed to the field of packaged integrated circuit devices, and, more particularly, to a novel build-up-package for integrated circuit devices and methods of making same.
- 2. Description of the Related Art
- Integrated circuit technology uses electrical devices, e.g., transistors, resistors, capacitors, etc., to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked electrical devices so that the circuit may perform its intended function. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and/or on different wafers or chips. In general, it is desirable in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
- In the manufacture of semiconductor device assemblies, a single semiconductor die is most commonly incorporated into each sealed package. Many different package styles are used, including dual inline packages (DIP), zig-zag inline packages (ZIP), small outline J-bends (SOJ), thin small outline packages (TSOP), plastic leaded chip carriers (PLCC), small outline integrated circuits (SOIC), plastic quad flat packs (PQFP) and interdigitated leadframe (IDF). Some semiconductor device assemblies are connected to a substrate, such as a circuit board, prior to encapsulation. Manufacturers are under constant pressure to reduce the size of the packaged integrated circuit device and to increase the packaging density in packaging integrated circuit devices.
- So-called build-up-packaging (BUP) is a commonly employed technique for packaging integrated circuit devices. In general, build-up-packaging involves forming a mold compound material adjacent the sides of an integrated circuit die. Typically, this is accomplished by placing a plurality of singulated die on a section of tape, with the active side of the integrated circuit die being in contact with the tape. Thereafter, mold compound material is formed in the regions between and around the plurality of die. Typically, the mold compound may take the shape of a generally circular wafer. The thickness of the mold compound is approximately the same as that of the die that are subjected to the molding process. Eventually, after subsequent processing, the packaged die are singulated by cutting the mold material to achieve the desired package size.
-
FIGS. 1A-1B are, respectively, a cross-sectional side view and a plan view of an illustrative integrated circuit device packaged using the build-up technique described above. The packaged integratedcircuit 10 is comprised of anintegrated circuit die 12, a moldedbody 14, afirst insulating layer 16, e.g., polyimide, alayer 18 of conductive lines or traces, and a secondinsulating layer 20. A schematically depictedbond pad 15 is formed on theactive surface 13 of the die 12. Thebond pad 15 is conductively coupled to theconductive layer 18, which may sometimes be referred to as a redistribution layer. Aball pad 22 andconductive ball 24 are conductively coupled to theconductive layer 18. InFIG. 1B , the first and secondinsulating layers FIGS. 1A-1B are schematic in nature and not intended to provide every detail associated with such prior art devices. - One problem associated with integrated circuit devices packaged using such build-up techniques is there is a tendency for the conductive lines or traces that are part of the
conductive layer 18 to fail or crack at or near theinterface 26 between the body of thedie 12 and themolded body 14 in the area indicated by the dashed-line circle inFIG. 1B . Obviously, such defects may be detrimental and perhaps fatal to the operation of the packaged integratedcircuit device 10. - The present subject matter may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
-
FIGS. 1A-1B schematically depict an illustrative integrated circuit device packaged using a build-up technique; -
FIGS. 2A-2F schematically depict an illustrative process flow for making a novel packaged integrated circuit device, as disclosed herein; and -
FIGS. 3A-3I schematically depict another illustrative process flow for making a novel packaged integrated circuit device, as disclosed herein. - While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. Although various regions and structures shown in the drawings are depicted as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features and doped regions depicted in the drawings may be exaggerated or reduced as compared to the size of those features or regions on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the subject matter disclosed herein.
-
FIGS. 2A-2F schematically depict one illustrative process flow for manufacturing the novel packaged integrated circuit devices disclosed herein. As shown inFIG. 2A , a layer ofmaterial 42 is formed above anactive face 41 of an integrated circuit die 40. The die 40 has a plurality ofbond pads 43, only one of which is depicted inFIG. 2A . The die 40 may be of any shape or thickness and it may be any type of integrated circuit device, e.g., a memory device, a logic device, an application specific integrated circuit device, etc. Thus, the present disclosure should not be considered as limited to any particular type of integrated circuit device. Thebond pad 43 is schematic in nature as it is intended to represent any arrangement or configuration of bond pads that may be formed on theactive surface 43 of thedie 40. Similarly, thelayer 42 may be comprised of a variety of materials and it may be formed using a variety of techniques. In one illustrative embodiment, the layer ofmaterial 42 is a layer of insulating material, e.g., polyimide, having a thickness of approximately 5-30 μm. Thelayer 42 may be formed by performing a variety of known techniques, e.g., spin-coating followed by curing, deposition, etc. Thus, the present subject matter should not be considered as limited to any particular material or method of manufacture for thelayer 42. - Next, as shown in
FIG. 2B , amasking layer 46 is formed above thelayer 42 and an etching process, as indicated by thearrows 48, is performed to remove the portions of thelayer 42 that are not covered by themasking layer 46. However, thewidth 50 need not be uniform around the entire perimeter of the die 40 in all applications. In one illustrative example, thewidth 50 of the removed portion may be approximately 100-500 μm. Themasking layer 46 may be comprised of any material that is capable of performing the masking function, e.g., photoresist. Theetching process 48 may be performed using traditional equipment and recipes to remove the exposed portions of thelayer 42. After theetching process 48 is completed, themasking layer 46 may be removed. - Next, as shown in
FIG. 2C , the structure is placed face down on a section oftape 51 and a moldedbody 44 is formed around thedie 40 using traditional compression molding techniques. Thetape 51 is removed inFIG. 2D . Although only asingle die 40 is depicted inFIG. 2C , those skilled in the art will understand that, typically, the moldedbody 44 may be formed around a plurality of individual die 40 that are coupled to thetape 51. The moldedbody 44 may have an overall circular configuration, much like a semiconductor wafer, with a plurality ofdie 40 embedded therein. The moldedbody 44 may be made using a variety of known compression molding techniques, materials and equipment. In one illustrative embodiment, the moldedbody 44 is comprised of mold compound or encapsulant material that is commonly employed in encapsulating integrated circuit die. Note that the moldedbody 44 has a thickness that approximately corresponds to the combined thickness of thedie 40 and thelayer 42. As shown inFIGS. 2C and 2D , a portion orlip 53 of the moldedbody 44 extends above thecorner 52 of the integrated circuit die 40. Stated another way, theportion 53 of the moldedbody 44 is positioned above the portions of theactive face 41 of the die 40 that is not covered by the etchedlayer 42. The portions orextensions 53 of the moldedbody 44 extend inward beyond the primaryvertical interface 61 between the die 40 and the moldedbody 44. In general, the compound molding process is continued until such time as thelips 53 of the moldedbody 44 engage or abut the reducedwidth layer 42 at theinterface 55. - Thereafter, traditional processing techniques and structures may be employed to further complete the packaged integrated circuit device, as reflected in
FIG. 2E . More specifically, such processing may involve formation of first and second insulatinglayers conductive layer 18 using techniques known to those skilled in the art. Additionally, aball pad 62 andball 64 may be formed and conductively coupled to theconductive layer 18 using known techniques and materials. The conductive components may be made of a variety of materials, e.g., copper, aluminum, gold, etc. -
FIG. 2F is a schematically depicted plan view of the resulting packaged die (without the insulating layers above thelayer 42 depicted). As shown therein, theextensions 53 of the moldedbody 44 extend inwardly above theactive face 41 of thedie 40 beyond the primaryvertical interface 61 between the die 40 and the moldedbody 44. Stated another way, theextensions 53 define awindow 65 that has a footprint or size that is less than the footprint or size of theactive face 41 of theunderlying die 40. Accordingly, the conductive traces tend to experience less stress in the region indicated by the dashed-line circle 59 as compared to prior art BUP packaged devices, like the illustrative package depicted inFIGS. 1A-1B . -
FIGS. 3A-3I depict another illustrative embodiment of a novel packaged integrated circuit device disclosed herein. InFIG. 3A , a plurality of singulated die 40 are attached to a section oftape 70. Theactive face 43 of the die 40 engages thetape 70. - Next, as shown in
FIG. 3B , a CTE (coefficient of thermal expansion)buffer material 72 is formed around at least a portion of the perimeter of each of thedie 40. In the illustrative example depicted inFIG. 3B , theCTE buffer material 72 is positioned around the entire perimeter of the die 40, although that is not required in all configurations. In general, theCTE buffer material 72 may have a coefficient of thermal expansion that is intermediate the coefficient of thermal expansion for the die 40 and the coefficient of thermal expansion for the moldedbody 44 that is to be formed adjacent thedie 40. TheCTE buffer material 72 may be comprised of a variety of different materials and it may be formed using a variety of techniques. In one illustrative example, theCTE buffer material 72 is a material that may be dispensed as a liquid or liquid-like material and thereafter cured. The size of theCTE buffer material 72 may also vary depending upon the particular application. In some cases, theCTE buffer material 72 may have an approximately triangular shaped cross-sectional configuration (as shown inFIG. 3B ), with a leg length equal to approximately one-half the thickness of thedie 40. In the illustrative example where thedie 40 has a thickness of approximately 300-500 μm, the leg length of theCTE buffer material 72 may be approximately 150-250 μm. In one particularly illustrative embodiment, theCTE buffer material 72 may be comprised of traditional underfill material, or other liquid encapsulant material, having a coefficient of thermal expansion of approximately 4.14 ppm/° C. As an example, thedie 40 may have a coefficient of thermal expansion of approximately 2.69 ppm/° C. while the moldedbody 44 may have a coefficient of thermal expansion of approximately 8.28 ppm/° C. - Next, as shown in
FIG. 3C , the moldedbody 44 is formed around the plurality of singulated die 40 using known compressed molded techniques. Thereafter, thetape 70 is removed, as shown inFIG. 3D . Then, as shown inFIG. 3E , if desired, a grinding process may be performed to remove excess amounts of the moldedbody 44 from above theback surface 45 of thedie 40. Of course, this grinding process need not be performed in all applications. After the grinding process is completed, another portion oftape 74 is attached to the back of the die 40/moldedbody 44. Next, as shown inFIG. 3G , traditional fabrication techniques are employed to form the necessary insulation layers, conductive layers andconductive balls 64, as described previously. Thereafter, as shown inFIG. 3H , the packaged die are singulated using traditional techniques. -
FIG. 3I is a plan view depicting the packaged die (without the insulating materials present). As shown in this particular example, theCTE buffer material 72 essentially rings the perimeter of thedie 40. Stated another way, in one illustrative embodiment, theCTE buffer material 72 is positioned between the die 40 and the moldedbody 44, at least at the substantially coplanar upper surfaces of the die 40,CTE buffer material 72 and moldedbody 44. In some cases, theCTE buffer material 72 may only be positioned along the side surfaces of the die 40 where the conductive traces will cross. The presence of theCTE buffer material 72, with its intermediate coefficient of thermal expansion, tends to reduce the localized stresses seen by the conductive traces in at least the region indicated by dashedlines 75.
Claims (9)
1. A device, comprising:
an integrated circuit die having an active surface;
and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die.
2. The device of claim 1 , wherein the lips extend inward from the perimeter of the die.
3. The device of claim 2 , wherein the lips engage the active surface of the die.
4. The device of claim 1 , wherein an upper surface of the molded body is vertically spaced apart from the active surface of the die.
5. The device of claim 1 , further comprising a layer of material formed on the active surface of the die, and wherein the molded body has a thickness that is approximately the same as a combined thickness of the die and the layer of material.
6. A device, comprising:
an integrated circuit die having an active surface; and
a molded body extending around a perimeter of the die, a portion of the molded body being positioned above a portion of the active surface of the die such that the molded body defines a window that has a footprint that is smaller than a footprint of the active surface of the die.
7. The device of claim 6 , wherein the portions of the molded body above the active surface of the die engage the active surface of the die.
8. The device of claim 6 , wherein an upper surface of the molded body is vertically spaced apart from the active surface of the die.
9. The device of claim 6 , further comprising a layer of material formed on an active surface of the die, and wherein the molded body has a thickness that is approximately the same as a combined thickness of the die and the layer of material.
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US14/307,238 US9355994B2 (en) | 2007-06-26 | 2014-06-17 | Build-up package for integrated circuit devices, and methods of making same |
US15/145,760 US10593607B2 (en) | 2007-06-26 | 2016-05-03 | Build-up package for integrated circuit devices, and methods of making same |
US16/819,486 US11367667B2 (en) | 2007-06-26 | 2020-03-16 | Build-up package for integrated circuit devices, and methods of making same |
US17/843,799 US20230005802A1 (en) | 2007-06-26 | 2022-06-17 | Build-up package for integrated circuit devices, and methods of making same |
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US12/753,562 US20100187668A1 (en) | 2007-06-26 | 2010-04-02 | Novel build-up package for integrated circuit devices, and methods of making same |
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US7691682B2 (en) * | 2007-06-26 | 2010-04-06 | Micron Technology, Inc. | Build-up-package for integrated circuit devices, and methods of making same |
US8936966B2 (en) | 2012-02-08 | 2015-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices |
US9064879B2 (en) * | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US20120268899A1 (en) * | 2011-04-21 | 2012-10-25 | Tessera Research Llc | Reinforced fan-out wafer-level package |
US9449908B2 (en) | 2014-07-30 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package system and method |
JP6711001B2 (en) * | 2016-02-17 | 2020-06-17 | 富士電機株式会社 | Semiconductor device and manufacturing method |
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US9355994B2 (en) | 2016-05-31 |
US20090001551A1 (en) | 2009-01-01 |
US20110266701A1 (en) | 2011-11-03 |
US20230005802A1 (en) | 2023-01-05 |
US10593607B2 (en) | 2020-03-17 |
US7691682B2 (en) | 2010-04-06 |
US11367667B2 (en) | 2022-06-21 |
US8754537B2 (en) | 2014-06-17 |
US20200286801A1 (en) | 2020-09-10 |
US20140295622A1 (en) | 2014-10-02 |
US20160247737A1 (en) | 2016-08-25 |
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