US20100213614A1 - Methods for Passivating Metallic Interconnects - Google Patents
Methods for Passivating Metallic Interconnects Download PDFInfo
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- US20100213614A1 US20100213614A1 US12/771,386 US77138610A US2010213614A1 US 20100213614 A1 US20100213614 A1 US 20100213614A1 US 77138610 A US77138610 A US 77138610A US 2010213614 A1 US2010213614 A1 US 2010213614A1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
Abstract
One or more embodiments of the present invention relates to a method for passivating metallic interconnects, said method including: forming a metallic conductor embedded in at least one surrounding dielectric layer, said metallic conductor including a metal or alloy chosen from a group consisting of Cu, Ag, and alloys including one or more of these metals, said metallic conductor and said at least one surrounding dielectric layer having top surfaces; and forming a capping passivation film directly on the top surface of the metallic conductor, but not over the top surface of the at least one surrounding dielectric layer, wherein said capping passivation film including one or more materials selected from the group consisting of copper sulfide, silver sulfide, copper selenide, silver selenide, copper telluride, and silver telluride, wherein the copper sulfide refers to CuSX or Cu2SX, the silver sulfide refers to AgSX or Ag2SX, the copper selenide refers to CuSeXor Cu2SeX, and the copper telluride refers to CuTeX or Cu2TeX, and wherein 0.7≦X≦1.3.
Description
- This is a Continuation of application Ser. No. 11/156,122, filed on Jun. 17, 2005, now U.S. Pat. 7,709,958, which claims the benefit of U.S. Provisional Application No. 60/581,285, filed on Jun. 18, 2004, which application is incorporated herein by reference.
- One or more embodiments of the present invention relates to the field of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) semiconductor devices, Thin Film Head (TFH) devices, Micro Electronic Machined Systems (MEMS), and high density electronic device packaging such as, for example and without limitation, Flip Chip, Chip Scale Packaging (CSP), and Wafer Scale Packaging (WSP).
- In fabricating Damascene and Dual Damascene (DD) copper interconnects in accordance with prior art techniques, copper is encased in one or more copper diffusion barrier layers. Typically, the bilayer Ta/TaNX is used as a barrier layer for sidewalls and at the bottom of lines, and a relatively high-k dielectric layer, typically silicon nitride (or silicon carbide, or silicon carbide nitride, or silicon oxide carbide nitride), is used as a top capping barrier layer.
- Sites of poor adhesion between copper and metallic barrier layers on sidewalls and/or at the bottom of openings may result in electromigration (EM) and/or Stress Induced Voids (SIV). Copper EM and SIV are important reasons for poor reliability and low yields in copper interconnects. Presently used sidewalls and bottom barrier layers, such as Ta, TaNX, Ta/TaNX, Ru, TaSiXNY, WNX, Ti/TiNX, TiSiXNY, or WSiXNY, are problematic because: (a) their relatively high resistivity increases the resistance of interconnect lines and vias—this is particularly problematic at the bottom of vias; (b) they may have poor adhesion to copper and/or to the dielectric surrounding the interconnect (inter layer dielectric or ILD), resulting in high EM and/or SIV; and (c) they are often discontinuously deposited by a PVD technique over sidewalls of high aspect ratio (HAR) Damascene and Dual Damascene vias and trenches (particularly on hard to reach lower sidewalls of HAR openings, and on negative slope vicinities of undercut crevices, nooks, and crannies)—which discontinuities provide easy diffusion routes for copper into surrounding dielectric and/or copper voids.
- In light of the above, there is a need for methods and materials that solve one or more of the above-identified problems.
- One or more embodiments of the present invention solve one or more of the above-identified problems. In particular, one or more embodiments of the present invention relate to methods for passivating metallic interconnects, said method including: forming a metallic conductor embedded in at least one surrounding dielectric layer, said metallic conductor including a metal or alloy chosen from a group consisting of Cu, Ag, and alloys including one or more of these metals, said metallic conductor and said at least one surrounding dielectric layer having top surfaces; and forming a capping passivation film directly on the top surface of the metallic conductor, but not over the top surface of the at least one surrounding dielectric layer, wherein said capping passivation film including one or more materials selected from the group consisting of copper sulfide, silver sulfide, copper selenide, silver selenide, copper telluride, and silver telluride, wherein the copper sulfide refers to CuSX or Cu2SX, the silver sulfide refers to AgSX or Ag2SX, the copper selenide refers to CuSeX or Cu2SeX, and the copper telluride refers to CuTeX or Cu2TeX, and wherein 0.7≦X≦1.3.
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FIGS. 1( a)-1(b) show a pictorial representation of a transverse (along the width) cross-section of an interconnect structure used to fabricate, for example and without limitation, a semiconductor device that includes a conductor structure fabricated in accordance with one or more embodiments of the present invention; -
FIGS. 2( a)-2(b) show a pictorial representation of a transverse (along the width) cross-section of an opening with its sidewalls covered with a conformal passivation and/or diffusion barrier film in accordance with one or more embodiments of the present invention; -
FIGS. 3( a)-3(b) show a pictorial representation of a transverse (along the width) cross-section of an embedded (or filled) conductive interconnect with its sidewalls covered with a conformal passivation and/or diffusion barrier film, and its top surface covered with a passivation capping film in accordance with one or more embodiments of the present invention; and -
FIGS. 4( a)-4(b) show a pictorial representation of a longitudinal (along the length) cross-section of an embedded (or filled) Dual Damascene conductive interconnect where the interconnect is encased by a passivation and/or diffusion barrier film on its sidewalls and bottom surfaces, and its top surface is covered with a passivation capping film in accordance with one or more embodiments of the present invention. -
FIG. 1( a) shows a pictorial representation of a transverse (along the width) cross-section (not to scale for ease of understanding) ofstructure 100 used to fabricate, for example and without limitation, a semiconductor device that includes a conductor structure comprised ofconductive interconnect 18.Conductive interconnect 18 may comprise a metal or metal alloy such as, for example and without limitation, Cu, Ag, or alloys comprising one or more of these metals.Structure 100 may be fabricated as follows. In accordance with any one of a number of methods that are well known to those of ordinary skill in the art,dielectric layer 11 may be deposited oversubstrate 10, whichsubstrate 10 may comprise one or more layers such as, for example and without limitation, a lower metallization level and/or another dielectric layer. Next, in accordance with any one of a number of methods that are well known to those of ordinary skill in the art, an opening havingsidewall surfaces 15 andbottom surface 17 may be pattern-etched indielectric layer 11, andbarrier layer 16 and one or more seed layers (not shown inFIG. 1) may be deposited oversidewalls 15 andbottom surface 17 of the opening.Barrier 16 may comprise, for example and without limitation, a refractory metal or an alloy comprising a refractory metal, such as Ta, TaNX, Ta/TaNX, Ru, TaSiXNY, WNX, Ti/TiNX, TiSiXNY, or WSiXNY. One or more seed layers (not shown) are then deposited over themetallic barrier layer 16. Next, in accordance with any one of a number of methods that are well known to those of ordinary skill in the art, for example and without limitation, using electrofilling methods, the opening may be filled withconductive interconnect 18. Next, in accordance with any one of a number of methods that are well known to those of ordinary skill in the art, for example and without limitation, using one or more planarization and/or removal techniques, such as chemical mechanical polishing (CMP), polishing, electro-dissolution, electropolishing, or chemical etching, excess conductor inconductor 18 and excess conductor over dielectric 11 infield 14, as well as any seed and barrierlayers overlying field 14, may be removed to expose a top surface ofconductor interconnect metal 18 and a top surface offield 14. This step is sometimes referred to in the art as a removal or planarization step. - In accordance with one or more embodiments of the present invention, following the removal or planarization step, the exposed top surface of
conductor interconnect 18 is covered withpassivation film 12. In accordance with one or more embodiments of the present invention, the step of covering the exposed top surface of conductor interconnect 18 withpassivation film 12 comprises providingpassivation film 12 over the exposed top surface ofconductive metal 18 by, for example and without limitation, an intermixing growth process or a deposition process. - The term “intermixing growth” process is defined herein as a process in which a film grows on a surface of a material, which film comprises one or more constituents of the material and one or more constituents of a reactant. One example, without limitation, of an intermixing growth process involves diffusion across a growing film of one or more constituents from the material to the surface of the growing film, and/or diffusion across the growing film of one or more constituents from the reactant to the interface between the material and the growing film. For example and without limitation, silicon dioxide growth by oxidation of a silicon surface (such as described in a book entitled “VLSI Fabrication Principles” by S. K. Ghandhi, pp. 377-383, John Wiley & Sons, Inc. (1983)) is an intermixing growth process. The term “deposition” is defined herein as any process in which all of the constituents of a film originate from reagents external to the surface of a material. Some examples, without limitation, of deposition processes are electrodeposition, electroless deposition, chemical bath deposition (CBD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).
- A. Intermixing Growth
- In accordance with one or more embodiments of the present invention,
passivation film 12 may be fabricated by reacting the exposed top surface of conductor interconnect 18 with one or more reactants to fabricate one or more materials that adhere strongly to the exposedconductor 18 surface. In accordance with one or more such embodiments, it is believed that strong adhesion is provided because at least one of such materials is chemically bonded to the material at the exposed top surface ofconductor interconnect 18. Advantageously, in accordance with one or more of such embodiments, it is believed thatpassivation film 12 grows selectively, i.e., it grows only on exposed surface of conductor interconnect 18, and not on dielectric 11 at the exposed surface offield 14. - In accordance with one or more embodiments of the present invention,
conductor interconnect 18 comprises copper or a copper alloy, andpassivation film 12 comprises a copper sulfide such as CuSX and/or Cu2SX (where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds), and/or other materials comprising one or more of these compounds.Copper sulfide film 12 can be grown by an intermixing growth process, for example and without limitation, by sulfidation of (or reacting) the exposed top surface ofcopper interconnect 18 with a sulfur-bearing reactant gas (or gas mixture) comprising sulfur atoms, molecules, or ions such as, for example and without limitation, H2S or vapors of elemental sulfur (Sn; where n is an integer). It is believed that in accordance with such embodiments,copper sulfide film 12 is grown by an intermixing growth process according to the following chemical reactions: - The rate of growth of
film 12 can be increased or decreased by raising or lowering, respectively, the temperature ofstructure 100 and/or the reactant gas. The growth rate can also be increased or decreased by increasing or decreasing, respectively, the concentration (or partial pressure) of the reactant gas. - For example and without limitation,
copper sulfide film 12, having a thickness of about 10 Å to about 2,000 Å, can be grown by an intermixing sulfidation process on the top surface ofcopper conductor 18 by subjecting a wafer with exposedconductor 18 to an H2S gas (or a gas mixture of H2S with inert gas, such as argon or nitrogen), or to a sublimed sulfur vapor, at a temperature from about 25° C. to about 500° C. The dry sulfidation can be performed in a furnace, such as a rapid thermal processing (RTP) furnace, a CVD chamber, or a plasma enhanced CVD (PECVD) chamber at sulfidation times ranging from a few seconds to about 10 minutes. The higher the substrate temperature and/or the longer the exposure time, the thicker thecopper sulfide film 12, and vice versa. -
Copper sulfide film 12 may also be grown by an intermixing growth process in accordance with one or more further embodiments of the present invention by reacting the exposed top surface ofcopper interconnect 18 with a wet solution which contains one or more sulfur-bearing compounds comprising sulfur atoms, molecules, or ions, such as, for example and without limitation, solutions comprising elemental sulfur (Sn) or sulfide ions (S−2) of Na2S, K2S, (NH4)2S, and dissolved H2S. It is believed that in accordance with such embodiments,copper sulfide film 12 is grown by an intermixing growth process according to the following chemical reactions: - In accordance with one or more of such embodiments, dipping or spraying the top surface of
copper interconnect 18 in the wet solution is continued until a predetermined thickness offilm 12 is approached or attained (as will be described below, it is believed that the predetermined thickness may be a self-limited thickness). The rate of growth offilm 12 can be increased or decreased by raising or lowering, respectively, the temperature of the wet solution and/orstructure 100. The growth rate offilm 12 can also be increased or decreased by increasing or decreasing, respectively, the concentration of the sulfur-bearing reactant in the solution. - It may be advantageous to grow
film 12 by an intermixing self-limiting growth process, to its self-limited thickness at a temperature higher (for example and without limitation, by at least 50° C., and more specifically, by at least 100° C.) than the operational temperatures attained during device operation. It is believed that this will help to reduce copper diffusion acrossfilm 12 during operation of the device, or it might even substantially prevent such copper diffusion. In such a case,passivation film 12 can also function (and be used) as a diffusion barrier layer, in addition to its passivation role (by immobilizing top surface atoms of conductor 18). However, as is well-known, the actual growth temperature might be limited by a thermal budget, or by other processing and/or integration considerations, and a trade-off might be required. In light of this information, appropriate values of temperature can be determined for a particular application by one of ordinary skill in the art routinely and without undue experimentation. “Self-limited thickness” is defined herein as the thickness attained after a certain growth time, Δt (at a specific growth temperature), which increases by less than about 25% when the growth time is extended by another Δt, or more. For example, if the thickness offilm 12 is about 200 Å after 5 minutes growth at a given temperature, and it is less than about 250 Å after additional 5 minutes growth at the same temperature, then the self-limited thickness offilm 12 is about 200 Å. The self-limited thickness is a strong function of the growth temperature, increasing with the growth temperature. It is believed that the thickness ofpassivation film 12 has to be larger than about 300 Å and, probably larger than about 500 Å, for it to function as an efficient diffusion barrier. Usingfilm 12 alone as a diffusion barrier (seeFIG. 1( a)), withoutdielectric barrier layer 19, would have the distinct advantages of significantly reducing the effective dielectric constant (keff) of the multilevel interconnect, while improving its reliability, structural strength, and integrity. - In General, the Cu2SX phases are thermally more stable than the CuSX phases. For example, the Cu2SX δ-phase has a maximum melting point of 1,131° C., whereas the CuSX ε-phase is not stable above 507° C., and undergoes phase transformations at 76° C. and at 115° C. See Metals Handbook, 8th Edition, Vol. 8,
pages 297, 300, 358, American Society for Metals, 1973. A reference herein to a Cu2SX phase may also include the case of more than a single phase and, similarly, a reference herein to a single CuSX phase may also include the case of more than a single phase. It is believed that whenfilm 12 comprises the Cu2SX phase, it is more stable and, therefore, may be more desirable. As a result, iffilm 12 is formed (by intermixing growth) by reacting a sulfur-bearing reactant gas or vapor oncopper conductor 18, at temperatures above about 507° C., only the Cu2SX phase is formed. Similarly, iffilm 12 is first formed as the phase CuSX (alone or in a multiple phase structure) and, if the film is subsequently heated (or annealed) to above about 507° C., then film 12 will convert to the Cu2SX phase. - However, depending on the thickness of
film 12 and subsequent heating (or annealing),film 12 may convert entirely into the Cu2SX phase at even lower temperatures than about 500° C. For example, it is believed that a relatively thin (about 30 Å to about 200 Å) copper sulfide(s)film 12 will convert entirely into the Cu2SX phase by annealing it for a relatively short time (about 0.5 minute to about 10 minutes) at a temperature between about 100° C. to about 400° C. and, more specifically, between about 150° C. to about 300° C. It is believed thatfilm 12 converts to the Cu2SX phase by reacting with excess copper on theconductor 18 side, while there is no fresh supply of sulfur species on the other side offilm 12.Thicker film 12 may require longer annealing time and/or higher annealing temperature to fully convert into the Cu2SX phase. Subsequent annealing offilm 12 can be performed as a separate dedicated processing step, or during another elevated temperature processing step such as, for example and without limitation, during deposition ofdielectric barrier 19 inFIG. 1( b), for example, by a CVD or a PECVD process. For example, it is believed that when the thickness offilm 12 is in a range of about 30 Å to about 200 Å, the processing temperature during a subsequent CVD or plasma enhanced CVD (PECVD) deposition step (for example and without limitation, of a silicon nitride or a silicon carbide barrier layer 19) is sufficiently high and is present for a long enough time to fully convert any other phase(s) offilm 12 into the Cu2SX phase. - In accordance with one or more still further embodiments of the present invention,
film 12 grown by an intermixing growth process oncopper interconnect 18 comprises one or more of CuSeX, Cu2SeX, CuTeX, Cu2TeX (where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds)—where copper selenide refers to CuSeX and/or Cu2SeX and copper telluride refers to CuTeX and/or Cu2TeX. In still further embodiments,film 12 comprises one or more of CuSX, Cu2SX, CuSeX, Cu2SeX, CuTeX, Cu2TeX (where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds), and other materials comprising one or more of these compounds. - Copper selenide can be grown by an intermixing growth process by reacting the exposed top surface of
copper interconnect 18 with a wet reactant, or a dry reactant gas (or gas mixture) or vapor of one or more selenium-bearing compounds comprising selenium atoms, molecules, or ions. Copper telluride can be grown by an intermixing growth process by reacting the exposed top surface ofcopper interconnect 18 with a wet reactant, or a dry reactant gas (or gas mixture) or vapor of one or more tellurium-bearing compounds comprising tellurium atoms, molecules, or ions. For example, in order to grow copper selenide by an intermixing growth process on the copper surface, the copper surface may be reacted with (for example and without limitation) H2Se, Na2Se, K2Se, or (NH4)2Se. Similarly, in order to grow copper telluride by an intermixing growth process on the copper surface, the copper surface may be reacted with (for example and without limitation) H2Te, Na2Te, K2Te, or (NH4)2Te. - It is believed that one or more of the above-described embodiments for growing
film 12 by an intermixing growth process is a self-limiting process. In particular, it is believed that the process is self-limiting by copper and/or sulfur (or sellenium or tellurium) diffusion through (or across) the film as it grows. In particular, it is believed that as the thickness of the growing film increases, the flux of copper species that travel fromcopper interconnect 18 throughfilm 12 and/or the flux of sulfur (or sellenium or tellurium) species that travel from the surface throughfilm 12 slows down until it or they become substantially negligible or insignificant. In particular, it is believed that a self-limited thickness offilm 12 depends on temperature, the density of the film, and its morphology. For example, if the growth temperature is higher, the limiting thickness will be greater (assuming sufficient growth time of the film to its self-limited thickness), and the film will form faster. However, it is also believed that, if the density of the film is so low that there are high rates of diffusion, or if the film contains voids and/or many defects, the process may not be self-limiting. It is further believed that the process is confined to a self-limiting process by enabling diffusion to take place fast enough (during film formation) to growth sites to avoid forming voids. This may be done by raising the growth temperature to ensure that the diffusing species can reach their proper growth sites without forming voids. In light of this information, appropriate values of temperature and reactant concentration or amounts can be determined for a particular application by one of ordinary skill in the art routinely and without undue experimentation. - It should be understood that in some semiconductor processes, the use of compounds containing alkali metal ions might be problematic due to the possibility of contamination. In such cases, for example and without limitation, ammonium sulfide or dissolved H2S may be used to avoid such alkali metal contamination. Other chemical reagents which comprise sulfur such as, for example and without limitation, elemental sulfur (S), SO2, sulfites, thioacetamide, thiourea, or thiosulfates may also be used to form
film 12. As such, one or more embodiments of the present invention include the use of any chemical reagent suitable for reaction with the exposed top surface ofconductor 18 to formpassivation film 12 comprising a copper sulfide. - Advantageously,
film 12 formed as described above is grown on top ofconductor interconnect 18, and does not grow ontop field 14 of the surroundingdielectric layer 11. As such, growth ofpassivation film 12 by an intermixing growth process provides a selective process which advantageously helps avoid current leakage throughdielectric layer 14. It is further believed that the passivating reactant can advantageously passivate any exposed copper residue (contamination) left on (or embedded onto)field 14 of surroundingdielectric 11 by a previous CMP step. This is advantageous because it may further reduce leakage currents between interconnect lines. In addition, and advantageously in accordance with one or more embodiments of the present invention related to copper interconnect, it is believed thatpassivation film 12 is chemically bonded to thecopper conductor 18 underneath it, thereby adhering well to the top surface of copper (or copper alloy)conductor interconnect 18. As such, it is believed thatfilm 12 can reduce or eliminate copper interfacial surface diffusion and, thereby, reduce or eliminate electromigration (EM). - Copper
sulfide passivation film 12 described above is further advantageous because it also adheres well to dielectric layers such as, for example and without limitation, dielectric layers that overlay in structures used to fabricate devices such as semiconductor devices, thereby improving the mechanical strength and the structural integrity of multi-level metallization devices. Furthermore, sincecopper sulfide film 12 is not a dielectric material (actually it is conductive, having a resistivity ρ value in a range of about 10−4 to about 10−2 ohm-cm), it does not increase the effective dielectric constant (keff) ofstructures - B. Deposition
- In accordance with one or more embodiments of the present invention,
film 12 may be deposited upon the exposed top surface ofconductor interconnect 18. Such a deposition may be carried out by a: (a) dry deposition process such as, for example and without limitation, atomic layer deposition (ALD) or chemical vapor deposition (CVD); (b) physical vapor deposition (PVD) process such as, for example and without limitation, sputtering or evaporation; or (c) wet deposition process such as, for example and without limitation, chemical bath deposition, electrodeposition, or electroless deposition. Except for electroless deposition and electrodeposition, the other deposition processes mentioned above are not selective. For example, using such other deposition processes, copper sulfide will be deposited over the top surface ofcopper interconnect 18 and the top surface of surroundingdielectric 11 onfield 14. As such, the use of non-selective deposition processes may require additional steps for removing copper sulfide deposited over the top surface of dielectric 11 infield 14. In accordance with one or more such embodiments, it is believed that strong adhesion is provided because at least one of such materials is chemically bonded to material at the exposed topsurface conductor interconnect 18. In addition, and advantageously in accordance with one or more embodiments of the present invention, becausefilm 12 is chemically bonded to copper underneath it,film 12 adheres well to the top surface ofcopper interconnect 18. As such, it is believed thatfilm 12 can reduce or eliminate copper surface diffusion, and thereby reduce or eliminate electromigration (EM). It is believed that chemical bonding is enhanced if the temperature of the substrate is elevated during deposition and/or during successive processing steps entailed in fabricating a device. - In accordance with one or more embodiments of the present invention, it is believed that copper atoms at the surface of
copper interconnect 18 are chemically bound, for example and without limitation, in a chalcogenide compound comprised of one or more constituents that have a high affinity for copper. In accordance with one or more such embodiments,film 12 may be utilized to passivate the top surface ofconductor interconnect 18. In accordance with one or more such embodiments, the thickness ofpassivation film layer 12 may be in a range from about 10 Å to about 500 Å, and more specifically in a range from about 50 Å to about 200 Å. In addition,film 12 may reduce the effective dielectric constant keff of a multi-level interconnect structure by reducing the required thickness of (or entirely eliminating) the relatively high-k silicon nitride (or other high-k) dielectric capping layer. Although the description above referred mostly to copper metal (Cu) interconnect and copper sulfide (CuSX and/or Cu2SX, where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds) films, it should be understood by those skilled in the art that one or more embodiments of the present invention also may be utilized with interconnects comprising any highly conductive metal or alloy, such as, for example and without limitation, silver metal (Ag) or alloys which comprise one or more of the metals Cu and Ag. Similarly, it should be understood that one or more embodiments of the present invention also include films which comprise silver sulfide (AgSX and/or Ag2SX, where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds) and/or mixtures of other sulfide compounds comprising one or more atoms selected from the group consisting of Cu and Ag. In addition, it should be understood that one or more embodiments of the present invention also include films which comprise copper selenides and/or tellurides, silver selenides and/or tellurides, and mixtures thereof (consisting of one or more of copper and/or silver sulfides, selenides, and tellurides). - Copper
sulfide passivation film 12 described above with respect to intermixing growth and deposition processes is further advantageous because it also adheres well to dielectric layers such as, for example and without limitation, dielectric layers that overlay in structures used to fabricate devices such as semiconductor devices, thereby improving the mechanical strength and the structural integrity of multi-level metallization devices. Furthermore, sincecopper sulfide film 12 is not a dielectric material (actually it is conductive, having a resistivity ρ value in a range of about 10−4 to about 10−2 ohm-cm), it does not increase the effective dielectric constant (keff) ofstructures - C. Capping Passivation Plus Capping Dielectric Barrier
-
FIG. 1( b) shows a pictorial representation of a transverse (along the width) cross-section (not to scale for ease of understanding) ofstructure 110 used to fabricate, for example and without limitation, a semiconductor device that includesstructure 100 shown inFIG. 1( a) and adielectric layer 19 that overlaysstructure 100. In accordance with one or more embodiments of the present invention,dielectric barrier layer 19 may be utilized as an etch-stop layer (ESL) during etching of successive vias and/or trenches for a higher metallization level.Dielectric barrier layer 19 may also serve as an additional capping diffusion barrier against copper outdiffusion.Dielectric barrier layer 19 may comprise, for example and without limitation, silicon nitride, silicon carbide, silicon carbide nitride, silicon carbide nitride oxide, silicon nitride oxide, SiCXHY, or SiCXOYHZ.Dielectric barrier layer 19 may be deposited using any one of a number of deposition processes that are well known to those skilled in the art, for example and without limitation, by a chemical vapor deposition (CVD) or by a plasma enhanced CVD (PECVD), at a temperature range of about 400-500° C., or less. As described above,passivation film 12 adheres well to dielectric layers, and as such,film 12 adheres well todielectric layer 19. As such,passivation film 12 may significantly improve the strength and structural integrity of multi-level metallization devices. - It is believed that conventional interfaces between copper lines and the capping dielectric barrier (such as silicon nitride or silicon carbide) effectively generate micro-crack precursors which, under thermal and/or mechanical stress, may propagate into the surrounding (mechanically weak) dielectric, thus adversely affecting the structural integrity. It is further believed that, many of the current mechanical strength and structural integration problems associated with low-k dielectrics in advanced interconnect structures (such as CMP delamination and packaging problems), are related to such interfacial micro-cracks precursors. Thus, interposing a copper chalcogenide film, such as a
copper sulfide film 12, between thecopper lines 18 and the cappingdielectric barrier layer 19, with strong adhesion to both, can effectively mitigate or eliminate the deleterious interfacial micro-crack precursors, thereby improving the mechanical strength and structural integrity of the device. - D. Further Processing
- When higher levels interconnects are used (not shown), successive vias (not shown) connecting
conductor 18 to an upper level metallization interconnect are formed. In order to minimize the successive vias resistance, it may be desirable and/or advantageous to removepassivation film 12 from under the bottom of the successive vias (not shown), prior to copper or silver filling, by a short etching step. In accordance with one or more embodiments of the present invention,passivation film 12 can be selectively removed from under the bottom of successive vias by an etching step such as, for example and without limitation, using a directional dry etching technique such as sputter etching, ion milling, or reactive ion etching (RIE) through the successive vias.Film 12 may also be selectively removed from under the bottom of the vias by wet chemical etching through the successive vias, utilizing, for example and without limitation, HNO3 and/or H2SO4. Wheredielectric barrier layer 19 is formed overfilm 12, the etching offilm 12 can be integrated into the removal (etching) step oflayer 19 from the successive vias' bottom, usually by a RIE technique. The chemistry used for etching thedielectric barrier layer 19 may also be utilized for the RIE etching offilm 12. Alternatively,film 12 may be removed by a separate subsequent step, utilizing ion milling, or by a different RIE gas chemistry, suitable for the removal offilm 12. - Structures comprising successive vias disposed over
film 12 and/ordielectric barrier 19, withfilm 12 and/ordielectric barrier 19 selectively removed from the successive vias' bottom, ensure minimal vias resistance by direct metallic contact to the preceding (i.e., lower)copper metallization level 18. -
FIG. 2( a) shows a pictorial representation of a transverse (along the width) cross-section (not to scale for ease of understanding) ofstructure 200 used to fabricate, for example and without limitation, a metallic interconnect in a semiconductor device, whereinopening 13 has sidewalls surfaces 15 andbottom surface 17 covered withmetallic barrier layer 16.Metallic barrier layer 16 is covered in turn, withfilm 22 in accordance with one or more embodiments of the present invention.Opening 13 ofstructure 200 may subsequently be filled, for example and without limitation, using electroplating (or electrofilling) methods.Structure 200 may be fabricated as follows. In accordance with any one of a number of methods that are well known to those of ordinary skill in the art,dielectric layer 11 may be deposited oversubstrate 10, whichsubstrate 10 may comprise one or more layers such as, for example and without limitation, a lower metallization level and/or another dielectric layer. Next, in accordance with any one of a number of methods that are well known to those of ordinary skill in the art, opening 13 having sidewalls surfaces 15 andbottom surface 17 may be pattern-etched indielectric layer 11, andbarrier layer 16 may be deposited oversidewalls 15 andbottom surface 17 ofopening 13.Metallic barrier layer 16 may comprise, for example and without limitation, at least one layer of one or more refractory metals or alloys comprising refractory metals, such as Ta, TaNX, binary Ta/TaNX, Ru, TaSiXNY, WNX, binary Ti/TiNX, TiSiXNY, or WSiXNY. Next,film 22 is grown by an intermixing growth process or by a deposition process overmetallic barrier layer 16 in accordance with one or more embodiments of the present invention. Next, one or more seed layers 24 are deposited overfilm 22 in accordance with any one of a number of methods that are well known to those of ordinary skill in the art. AlthoughFIGS. 2( a) and 2(b) show asingle seed layer 24, it is within the scope of the invention thatlayer 24 may also comprise two or more layers, deposited in two or more steps, such as, for example and without limitation, where one step produces a relatively thick seed layer which may be non-conformal (or discontinuous), and another step produces a relatively thin conformal (i.e., continuous on the bottom 17 and sidewalls 15) seed layer. - In accordance with one or more embodiments of the present invention, a relatively thin conductive continuous (or conformal) Ru layer (such as deposited by PVD, ALD, or CVD techniques) serves as a barrier layer and/or as a seed layer, followed by a thicker PVD seed layer 24 (comprising Cu, Ag, or an alloy comprising one or more of these metals). The Ru layer can be used as a
single barrier layer 16 or, preferably, in a combination (not shown) with one or more other metallic barrier layers (such as Ta, TaNX or bilayer Ta/TaNX). While the conformal conductive Ru seed layer ensures continuous sidewalls and bottom coverage, the thicker PVD seed layer provides sufficient field surface conduction, required for void-free electrofilling and for adequate plating uniformity across a wafer. The interposed Ru layer provides good adhesion to both therefractory metal barrier 16 on one side and to Cu on the other side, thus serving as a “glue”, enhancing strong adhesion between the two. When Ru layer is used as asingle barrier layer 16, it also provides good adhesion todielectric 11. In such embodiments, the Ru layer can be used in combinations with, or without,film 22. - As defined herein, “conformal” means “continuous”, and “substantially conformal” means “substantially continuous” coverage of a layer on at least the sidewalls (preferably also on the bottom) of the openings.
- In accordance with one or more preferred embodiments of the present invention, layer or
film 22 comprises one or more of CuSX, Cu2SX, CuSeX, Cu2SeX, CuTeX, Cu2TeX (where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds), and other materials comprising one or more of these compounds. In accordance with one or more further embodiments of the present invention,film 22 may also comprise silver sulfide (AgSX and/or Ag2SX, where 0.7≦X≦1.3; and X=1.0 for stoichiometric compounds) and/or other mixtures of sulfides comprising one or more atoms selected from the group consisting of Cu and Ag. Advantageously in accordance with one or more embodiments of the present invention, it is believed that becausefilm 22 is chemically bonded tobarrier 16 and to copper (or silver)seed layer 24,film 22 adheres well to both. In accordance with one or more further embodiments of the present invention, a conductiveconformal film 22 serves as a first seed layer, followed by a thicker PVD seed layer 24 (comprising Cu, Ag, or an alloy comprising one or more of these metals). While thefirst seed layer 22 ensures continuous sidewalls and bottom coverage, the thicker PVD seed layer provides sufficient field surface conduction, required for void-free electrofilling and for adequate plating uniformity across a wafer. As such, after electrofilling to form a copper (or silver) interconnect in opening 13,film 22 may advantageously also function as a passivation layer on sidewalls and/or on the bottom surfaces of the interconnect to reduce or eliminate EM and/or SIV, and to enhance adhesion between the copper (or silver) interconnect andmetallic barrier 16.Film 22 may also function as a diffusion barrier to reduce or eliminate copper (or silver) outdiffusion into surroundingdielectric 11. -
FIG. 2( b) shows a pictorial representation of a transverse (along the width) cross-section (not to scale for ease of understanding) ofstructure 210 used to fabricate, for example and without limitation, a semiconductor device that is the same asstructure 200 shown inFIG. 2( a), except thatbarrier layer 16 is not used. In accordance with one or more such embodiments of the present invention,film 22 functions as a passivation film and/or as a diffusion barrier to prevent or reduce copper or silver outdiffusion, depending on the application, into dielectric 11 from an interconnect that is subsequently formed inopening 13. - In accordance with one or more embodiments of the present invention,
film 22 inFIGS. 2( a) and 2(b) is substantially conformal (i.e., continuous) and may be utilized to passivate the sidewalls and bottom surfaces of an interconnect conductor that fillsopening 13. In accordance with one or more such embodiments, the thickness offilm layer 22 may be in a range from about 10 Å to about 500 Å and, more specifically in a range from about 20 Å to about 200 Å. - In accordance with one or more embodiments of the present invention, it is believed that copper atoms at interfaces with
film 22, such asseed layer 24 and/or copper-filled conductor interconnect 18 (inFIG. 1 ), are chemically bound, for example and without limitation, in a chalcogenide compound comprised of one or more constituents that have a high affinity for copper. - A. Deposition
- In accordance with one or more embodiments of the present invention,
film 22 may be deposited using a: (a) dry deposition process such as, for example and without limitation, atomic layer deposition (ALD) or chemical vapor deposition (CVD); (b) physical vapor deposition (PVD) process such as, for example and without limitation, sputtering or evaporation; or (c) wet deposition process such as, for example and without limitation, chemical bath deposition, electrodeposition, or electroless deposition. In accordance with a preferred embodiment,film 22 is deposited by a conformal deposition process, such as ALD (preferably), CVD, electroless, or electrodeposition. For example and without limitation, in accordance with one or more embodiments, an ALD technique or a CVD technique may be used to deposit a conformal CuSX or Cu2SX film 22 inside opening 13 of high aspect ratio (HAR). Such embodiments provide acontinuous film 22 oversidewalls 15, which may even comprise negative slopes, nooks, crevices, or crannies For an example of an ALD of CuSX, see a publication entitled “Growth of conductive copper sulfide thin films by atomic layer deposition” by Johansson et al., in J. Mater. Chem., Vol. 12, pp. 1022-1026 (2002). For example and without limitation, organometallic precursors such as Cu(thd)2, Cu(hfac)2, or (hfac)Cu(tmvs) can be reacted with H2 5 gas in ALD or CVD processes to deposit conformal CuSX or Cu2SX films. Due to the high affinity of refractory metals to carbon and oxygen, ametallic barrier layer 16, which is based on a refractory metal or alloy, tends to form interfacial oxides and/or carbides by reacting with the organic part of the copper organometallic precursors. Such interfacial oxides and/or carbides may impair adhesion (and/or nucleation) ofcopper sulfide film 22 tometallic barrier 16. For this reason, other copper precursors comprising inorganic compounds which do not include carbon and/or oxygen atoms can be used. For example and without limitation, precursors comprising copper halides, such as copper chlorides, copper bromides, or copper iodides may be used instead of the copper organometallic precursors. - In accordance with one or more such embodiments, it is believed that advantageously strong adhesion is provided because at least one of such materials comprising film 22 (copper or silver chalcogenide) is chemically bonded to material at the underlying surfaces of
barrier 16 and to overlying seed layer(s) 24. It is further believed thatfilm 22 is chemically bonded tometallic barrier 16 underneath it by sharing chalcogenide atoms (S, Se, or Te) with it, and to seed layer(s) 24 above it by sharing chalcogenide atoms withfilm 24, thus providing excellent adhesion to both. As such, it is believed thatfilm 22 can reduce or eliminate copper interfacial surface diffusion, and thereby reduce or eliminate electromigration (EM) and/or stress induced voids (SIV), while improving structural strength and integrity. It is also believed that chemical bonding is enhanced if the temperature of the substrate is elevated during deposition and/or during successive processing steps entailed in fabricating a device. When nobarrier layer 16 is used, such asstructure 210 ofFIG. 2( b), it is similarly believed that adhesion offilm 22 todielectric 11 is promoted by sharing or substituting chalcogenide atoms or ions of S, Se, or Te withdielectric 11. -
Film 22 can be grown on barrier layer 16 (FIG. 2( a)), or directly on dielectric 11 (FIG. 2( b)), by dry or by wet deposition techniques. The dry deposition techniques may include ALD, CVD, or PVD. Note that the ALD method may be particularly advantageous due to its highly conformal nature. As such, it can coat all surfaces continuously, including hard to reach negative slopes, crevices, nooks and crannies For an example of a method for ALD deposition of copper sulfide, see an article by Johansson et al. entitled “Growth of conductive copper sulfide thin films by atomic layer deposition” in Journal of Materials Chemistry, 2002, vol. 12, pp. 1022-1026, incorporated herein by reference. The wet deposition techniques may include, for example and without limitation, electroless, electroplating, or chemical bath deposition techniques. - In one or more other embodiments, sulfur (atoms, molecules, or ions) are first deposited directly onto, and/or “impregnated” into, the surface of
dielectric 11, and then reacted with a copper-bearing reactant (such as aqueous solution of cuprous or cupric ions) to formfilm 22 by intermixing growth. Such embodiments might be particularly useful when using porous low-k dielectric 11, capable of absorbing appreciable amounts of the sulfur species. - B. Intermixing Growth
- In accordance with one or more embodiments of the present invention,
layer 22 can be grown by an intermixing growth process by first depositing a thin layer of copper or silver (such as by ALD, CVD, electrodeposition, or electroless techniques) overbarrier layer 16, followed by an intermixing growth process like those described above for growingfilm 12 ofFIG. 1 . Accordingly,film 22 is grown in two steps: (a) a copper (or silver) layer (not shown) is first deposited (by a dry or by a wet deposition technique onmetallic barrier 16 or directly on dielectric 11 (seeFIG. 2( b)) and, (b) reacting the copper (or silver) layer with a sulfur (or sellenium or tellurium) bearing reactant to formfilm 22 by intermixing growth. For example, a copper layer can be deposited onbarrier 16 or directly on dielectric 11 by an ALD, CVD, PVD, or electroless technique, followed by reacting the copper (or silver) layer with a (wet or dry) sulfur-bearing reactant, such as H2S or elemental sulfur. - In yet another embodiment (not shown), one or more copper seed layer(s) 24 is first deposited over metallic barrier layer 16 (see
FIG. 2( a)), and the copper seed layer (s) 24 is then reacted with a dry or wet chalcogenide-bearing reactant to formfilm 22. Partially consumed seed layer(s) 24 thus underlay film 22 (not shown), and electrofilling of opening 13 is performed directly ontofilm 22. - Advantageously,
film 22 may provide improved device integrity and reliabilty because it may act to reduce voids in subsequently electroplated conductor that fills opening 13, whenseed layer 24 is too thin and/or when seed layer(s) 24 is discontinuous onsidewalls 15. - Further Processing
- 1. In order to minimize via resistance, it may be desirable or advantageous to remove
film 22 frombottom 17 of opening 13 (such as via inFIGS. 2( a) and 2(b)) prior to copper or silver filling. In accordance with one or more embodiments of the present invention,film 22 can be removed from bottom 17 ofvias 13 by an etching step such as, for example and without limitation, using a directional dry etching technique such as sputter etching, ion milling, or reactive ion etching (RIE).Film 22 may also be removed from bottom 17 of via 13 by wet chemical etching such as, for example and without limitation, using HNO3 and/or H2SO4. Structures comprising vias withlayer 22 removed from bottom 17 are shown, for example and without limitation, inFIG. 4 . Such removal (as well as the removal ofbarrier layer 16 from the via's bottom) ensures minimal via resistance, by providing copper to copper contact with a preceding (i.e., lower) metallization level (see 10 inFIG. 4) . Removal ofmetallic barrier 16 from the via's bottom further improves device reliability by mitigating or eliminating EM and/or SIV problems related to the vias' bottom. - As was discussed above in conjunction with
FIGS. 2( a) and 2(b), seed layer(s) 24 is deposited overfilm 22 inside opening 13 and overfield 14. In accordance with one or more embodiments of the present invention, acontinuous film 22 on thesidewalls 15 facilitates the use of a relatively thick seed layer 24 (which may be discontinuous inside the opening), which can be deposited, for example, by a PVD technique such as sputtering, ion plating, or evaporation. The main purpose of depositing the relativelythick seed layer 24 is to provide sufficient seed layer thickness for adequate surface conduction overfield 14. Adequate surface conduction is required to minimize “terminal effect” (i.e., a thickness non-uniformity across a wafer due to IR-drop from the wafer's edge contact to its center). Adequate surface conduction is required for good uniformity of an electroplated conductor across a wafer and for void-free electrofilling. The thickness ofseed layer 24 can be in a range from about 200 Å to about 2,000 Å overfield 14, and more particularly in a range from about 300 Å to about 1,000 Å overfield 14. As is discussed below, in accordance with one or more embodiments of the present invention, seed layer 24 (which may be discontinuous inside the opening) may also be used as a (sacrificial) mask during removal offilm 22 and/ormetallic barrier layer 16 from a via's bottom 17. - 2. In still another embodiment, as shown in
FIG. 2( b),film 22 may be formed directly (without barrier layer 16) overdielectric 11 and oversubstrate 10 atbottom 17 ofopening 13 and, following its formation, anon-conformal seed layer 24 is deposited overfilm 22. Then, if desired,film 22 may be removed from bottom 17 by an etching step, usingnon-conformal seed layer 24 as a mask to protectlayer 22 overfield 14 andsidewalls 15. The etching can be performed by wet chemical etching (for example, with HNO3 and/or H2SO4) or, more preferably, by directional (anisotropic) dry etching such as by sputter etching, ion milling, or reactive ion etching (RIE). Then, in order to improve conduction ofsidewalls 15, a relatively thin conformal seed layer (not shown) may be deposited over the entire structure. The conformal seed layer may be deposited following the step of removingfilm 22 frombottom 17. The conformal seed layer may preferably be deposited by an ALD or a CVD technique. However, it may also be deposited by any other conformal deposition technique, such as electroless or electrodeposition. In an alternative embodiment, a relatively thin conformal seed layer can be deposited as part of a combined seed layers 24 directly overfilm 22, followed by the deposition of a thicker seed layer (which can be non-conformal), to form a combinedseed layer 24. This embodiment is particularly advantageous in embodiments where there is no removal offilm 22 from the bottom 17. - 3. In accordance with one or more further embodiments,
film 22 may also serve as a conformal seed layer. In accordance with further such embodiments, another seed layer, which may be non-conformal, can be deposited thereon. - 1.
FIG. 3( a) shows a pictorial representation of a transverse (along the width) cross-section (not to scale for ease of understanding) ofstructure 300 used to fabricate, for example and without limitation, a conductor line in a metallic interconnect in a semiconductor device.Structure 300 comprises an embedded or filledconductive interconnect 18 indielectric 11, with itssidewalls 15 encased withfilm 30, and its top surface covered with cappingfilm 32, in accordance with one or more embodiments of the present invention. Cappingfilm 32 may be fabricated using any of the above-described methods relating to film 12 ofFIGS. 1( a) and 1(b).FIG. 3( a) also showsmetallic barrier layer 16 formed oversidewalls 15 and bottom 17 of the interconnect line embedded indielectric 11.FIG. 3( a) also shows a film orlayer 30 disposed betweenmetallic barrier layer 16 andmetallic conductor 18.Film 30 may be fabricated using any of the above-described methods relating to film 22 ofFIGS. 2( a) and 2(b). In accordance with one or more embodiments of the invention, film (or layer) 30 passivates the sides of conductor 18 (which conductor may comprise Cu, Ag, or an alloy comprising one or more of these metals), and capping film (or layer) 32 passivates the top surface ofconductor 18.Structure 300 shown inFIG. 3( a) may be fabricated by starting withstructure 200 shown inFIG. 2( a), electrofilling opening 13 withconductor 18, and removing by a planarization technique, such as, for example, a CMP technique, the excess platedconductor 18 over opening 13 (not shown), and themetallic barrier 16 andfilm 22 from thefield 14 ofdielectric 11. What wasfilm 22 inFIG. 2( a), will thus end up as film (or layer) 30 inFIG. 3( a). As forfilm 22 described above,layer 30 advantageously comprises one or more chalcogenide materials selected from the group consisting of copper sulfide, copper selenide, copper telluride, silver sulfide, silver selenide, silver telluride, and mixtures of two or more of these chalcogenides. - Advantageously, in accordance with one or more embodiments of the present invention, it is believed that because
film 30 is chemically bonded tometallic barrier layer 16 and to copper (or silver)conductor 18,film 30 adheres well to both. As such,film 30 may advantageously function as a passivation layer onsidewalls 15 and bottom 17 and/or as a barrier layer against copper (or silver) outdiffusion into surroundingdielectric 11, thereby reducing or eliminating EM and/or SIV. Similarly, it is believed that becausefilm 32 is chemically bonded (and adheres well) toconductor 18,film 32 may function as a passivation capping and/or barrier capping layer overconductor 18. -
FIG. 3( b) shows astructure 310, similar to structure 300 ofFIG. 3( a), but withoutmetallic barrier layer 16. In accordance with one or more embodiments of the present invention,film 30 functions as a passivation layer and/or as a barrier layer against outdiffusion ofconductor 18 intodielectric 11. - 2.
FIG. 4( a) shows a pictorial representation of a longitudinal (along the length) cross-section (not to scale for ease of understanding) ofstructure 400 used to fabricate, for example and without limitation, a Dual Damascene metallic interconnect in a semiconductor device.Structure 400 comprises an embedded or filledconductive interconnect 18 indielectrics Conductive interconnect 18 is encased byfilm 42 atsidewalls 15 and (line) bottom 41, and its top surface is covered withfilm 44, in accordance with one or more embodiments of the present invention.Structure 400 also comprises ametallic barrier layer 16 formed oversidewalls 15 ofdielectrics conductor 18. In accordance with one or more embodiments of the invention,film 42 and/orbarrier 16 are removed from bottom 17 of the via, as shown inFIG. 4( a). - In accordance with one or more embodiments of the present invention, layers or
films films film 42 is chemically bonded tometallic barrier layer 16 and to copper (or silver)conductor 18,film 42 adheres well to both. As such,film 42 may advantageously function as a passivation layer onsidewalls 15 and/or a barrier layer against copper (or silver) outdiffusion into surroundingdielectrics film 44 is chemically bonded (and adheres well) to the top ofconductor 18,film 44 may function as a passivation capping and/or barrier capping layer overconductor 18.Film 42 can be deposited or grown by a deposition process or by an intermixing process, similar to deposition or growth of film 22 (inFIGS. 2( a) and 2(b)), in accordance with one or more embodiments described above.Film 44 can be grown by an intermixing process or deposited similar to growth or deposition of film 12 (inFIGS. 1( a) and 1(b)), in accordance with one or more embodiments described above. -
FIG. 4( b) shows astructure 410, similar to structure 400 ofFIG. 4( a), but withoutmetallic barrier layer 16. In accordance with one or more embodiments of the present invention,film 42 functions as a passivation layer and/or as a barrier layer against outdiffusion ofconductor 18 intodielectrics - Although the description of the embodiments and examples above has concentrated on metallic interconnect structures used to fabricate a device such as a semiconductor integrated circuits, these embodiments can also be used in the fabrication of other devices, such as (coils in) thin film heads, Micromachined Microelectromechanical Systems (MEMS) devices, or interconnects in high density integrated circuit packages.
- Those skilled in the art will recognize that the foregoing description has been presented for the sake of illustration and description only. As such, it is not intended to be exhaustive or to limit the invention to the precise form disclosed.
Claims (22)
1. A method for passivating metallic interconnects, said method comprising:
forming a metallic conductor embedded in at least one surrounding dielectric layer, said metallic conductor comprising a metal or alloy chosen from a group consisting of Cu, Ag, and alloys comprising one or more of these metals, said metallic conductor and said at least one surrounding dielectric layer having top surfaces; and
forming a capping passivation film directly on the top surface of the metallic conductor, but not over the top surface of the at least one surrounding dielectric layer, wherein said capping passivation film comprising one or more materials selected from the group consisting of copper sulfide, silver sulfide, copper selenide, silver selenide, copper telluride, and silver telluride, wherein the copper sulfide refers to CuSX or Cu2SX, the silver sulfide refers to AgSX or Ag2SX, the copper selenide refers to CuSeX or Cu2SeX, and the copper telluride refers to CuTeX or Cu2TeX, and wherein 0.7≦X≦1.3.
2. The method of claim 1 further comprising depositing a capping dielectric barrier layer over the capping passivation film.
3. The method of claim 2 wherein the capping passivation film has a thickness in a range from about 10 Å to about 100 Å.
4. The method of claim 2 wherein the capping passivation film has a thickness in a range from about 30 Å to about 200 Å.
5. The method of claim 2 wherein the capping passivation film has a thickness in a range from about 10 Å to about 50 Å.
6. The method of claim 2 wherein the capping dielectric diffusion barrier layer comprises one or more materials selected from a group consisting of silicon nitride, silicon carbide, silicon carbide nitride, silicon carbide nitride oxide, silicon nitride oxide, SiCXHY, and SiCXOYHZ.
7. The method of claim 2 wherein the capping passivation film is formed in a plasma enhanced chemical vapor deposition (PECVD) chamber.
8. The method of claim 7 wherein the PECVD chamber is the same chamber used for depositing the capping dielectric barrier layer.
9. The method of claim 2 wherein the capping passivation film comprises copper sulfide.
10. The method of claim 9 wherein the capping passivation film has a thickness in a range from about 10 Å to about 100 Å.
11. The method of claim 9 wherein the capping passivation film has a thickness in a range from about 30 Å to about 200 Å.
12. The method of claim 9 wherein the capping passivation film has a thickness in a range from about 10 Å to about 50 Å.
13. The method of claim 9 wherein the capping dielectric diffusion barrier layer comprises one or more materials selected from a group consisting of silicon nitride, silicon carbide, silicon carbide nitride, silicon carbide nitride oxide, silicon nitride oxide, SiCXHY, and SiCXOYHZ.
14. The method of claim 9 wherein the capping passivation film is formed in a plasma enhanced chemical vapor deposition (PECVD) chamber.
15. The method of claim 14 wherein the PECVD chamber is the same chamber used for depositing the capping dielectric barrier layer.
16. The method of claim 14 wherein a sulfur-bearing reactant is utilized for sulfidation of the top surface of the metallic conductor.
17. The method of claim 16 wherein the sulfur-bearing reactant is selected from a group consisting of H2S gas, H2S gas mixture, and sublimed sulfur vapor.
18. The method of claim 9 wherein the capping passivation film is formed by reacting the top surface of the metallic conductor with a wet solution containing one or more sulfur-bearing compounds.
19. The method of claim 18 wherein the wet solution comprises one or more of dissolved elemental sulfur (Sn), sulfide ions (S−2), and dissolved H2S.
20. The method of claim 2 wherein the capping passivation film is formed by reacting the top surface of the metallic conductor with a wet solution containing one or more sulfur-bearing compounds.
21. A semiconductor device comprising a metallic interconnect passivated by the method of claim 2 .
22. A semiconductor device comprising a metallic interconnect passivated by the method of claim 14 .
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US12/771,386 US20100213614A1 (en) | 2004-06-18 | 2010-04-30 | Methods for Passivating Metallic Interconnects |
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US20060249849A1 (en) | 2006-11-09 |
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