US20100283087A1 - Electric Component - Google Patents
Electric Component Download PDFInfo
- Publication number
- US20100283087A1 US20100283087A1 US12/840,597 US84059710A US2010283087A1 US 20100283087 A1 US20100283087 A1 US 20100283087A1 US 84059710 A US84059710 A US 84059710A US 2010283087 A1 US2010283087 A1 US 2010283087A1
- Authority
- US
- United States
- Prior art keywords
- layer
- conductor track
- chip
- area
- areas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 122
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005538 encapsulation Methods 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims description 50
- 238000009413 insulation Methods 0.000 claims description 40
- 230000003993 interaction Effects 0.000 claims description 19
- 239000007788 liquid Substances 0.000 claims description 13
- 238000010292 electrical insulation Methods 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000011156 evaluation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 201
- 230000007797 corrosion Effects 0.000 description 15
- 238000005260 corrosion Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000005669 field effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000012491 analyte Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
- G01N27/403—Cells and electrode assemblies
- G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
- G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing
Definitions
- the invention relates to an electrical component having a sensor and/or actuator chip, in particular a CMOS chip, that has a substrate on which a passivation layer and at least one structure that has at least one active surface area for a sensor and/or actuator are located, and the chip is surrounded by an encapsulation that has at least one opening that forms an access to the active surface area, of which at least one is present, and to the passivation layer, and in the opening the chip has an interaction surface that extends, at least in some areas, over the passivation layer and the active surface area and that in the operating position is in contact with a liquid or viscous medium, and a first electrical insulation layer is provided between the passivation layer and the substrate, and a first conductor track layer is located in some areas between the passivation layer and the first insulation layer, and a second electrical insulation layer is provided between the first insulation layer and the substrate, and a second conductor track layer is located between the first insulation layer and the second insulation layer, and at least one of the conductor tracks is connected to the
- An electrical component of this type is known from actual practice. It has a CMOS chip with a semiconductor substrate into which an ion-sensitive field effect transistor (ISFET) is integrated.
- the sensor has an active surface area that is configured as a gate electrode and that can be brought into contact with a liquid medium in order to detect ions contained in this medium.
- a plurality of conductor track layers made of aluminum, in which the conductor tracks and/or sections of conductor tracks extend, are located on the substrate. Conductor track sections of conductor tracks that extend across to a plurality of conductor track layers are connected to each other by means of through-contacts.
- An electrical insulation layer is provided between each of the conductor track layers as well as between the lowermost conductor track layer, which is located closest to the substrate, and the substrate.
- a passivation layer is located as a cover layer on the stack of layers comprising the conductor track layers and the insulation layers.
- the circuit tracks connect the drain and source of the ISFET with bond pads that are spaced apart from the drain and source and are located on the surface of the CMOS chip.
- the CMOS chip is encapsulated with a plastic casting compound that is in close contact with the chip and that has an opening that is connected to the active surface area and into which the liquid medium may be filled.
- the medium comes into contact with the chip at an interaction surface that extends across a part of the passivation later and the active surface area.
- the conductor track layers and the insulation layers in each case extend into the area of the chip that is covered by the interaction surface.
- the passivation layer and the insulation layers serve as corrosion protection for the circuit track layers in order to prevent the circuit track layers from coming into contact with the liquid medium.
- the passivation layer only provides limited corrosion protection for the conductor track layers, and that the chips only have a relatively short service life when the opening is filled with a liquid or viscous medium. If a conductor track comes into contact with the medium, for example due to a defect in the passivation layer, the entire chip can fail.
- a semiconductor chip that has a silicon substrate on which an array having 16 approximately rectangular electrodes is disposed as disclosed in F. Fa ⁇ bender et. al., Optimization of Passivation Layers for Corrosion Protection of Silicon-Based Microelectrode Arrays, Sensors and Actuators B 68 (2000), p. 128-133.
- the electrodes are connected to bond pads by means of conductor tracks located in a single conductor track layer.
- the conductor track layer is covered by a passivation layer.
- a silicon dioxide layer is generated on the semiconductor substrate with the aid of a heat-treating process. Trench-like recesses are imparted in this layer at the locations at which the conductor tracks will later be present.
- a metal that forms the circuit tracks is deposited in these recesses.
- the recessed arrangement of the conductor tracks in the silicon dioxide layer causes the chip to have an essentially flat surface.
- the purpose of these is to prevent mechanical stresses in the passivation layer, which can lead to cracks through which an analyte that is to be analyzed using the electrodes can come into contact with the conductor track layer and can cause corrosion on the conductor track layer.
- the corrosion resistance of the chip can be improved with this measure, and thus the service life of the chip can be extended.
- placing the trenches in the silicon dioxide layer located on the substrate results in a substantial additional expense in the manufacturing of the chip, in particular with a CMOS process.
- the object of the invention is therefore to provide an electrical component of the type referred to above that can be manufactured in a cost-effective manner using the standard semiconductor manufacturing processes but that permits good corrosion resistance as well as long service life.
- At least those areas of the first conductor track layer adjacent to the passivation layer that carry an electrical potential or that are necessary for the electrical operation of the component are located completely outside of the area of the chip that is covered by the interaction surface.
- at least the first insulation layer is then located between the uppermost conductor track layer that has the least distance to the opening or to the liquid or viscous medium contained in it and the conductor track layer that is used for the electrical operation of the component, whereby the corrosion resistance is significantly improved compared with a chip in which only the passivation layer is provided between the uppermost conductor track layer and the liquid or viscous medium.
- At least one electrically insulated, floating partial area of the first conductor track layer which is not used to carry electrical voltage and/or current and therefore is not significant to the electrical operation of the component, may optionally be located.
- the first insulation layer is produced on or applied to the chip and after that the first conductor track layer and the passivation layer are produced on the chip or are applied to it.
- the surface structure caused by the contour of the conductor track, of which there is at least one, on the boundary surface of the insulation layer that is distant from the conductor track is already significantly flatter and smoother compared with the contour of the conductor track of the second conductor track layer.
- This surface structure is smoothed even more by the passivation layer, so that the passivation layer has a surface that is for the most part flat and free from abrupt steps or shoulders. This significantly reduces the risk that cracks will form in the passivation layer when mechanical stresses are present in the chip.
- the component of the invention therefore achieves good corrosion resistance and a long service life.
- the component chip can be manufactured economically using standard semiconductor manufacturing processes. Providing trenches in the chip surface, which is a complicated and expensive undertaking, is not necessary.
- the passivation layer may be comprised of a plurality of layers, each of which may be made of various materials. This results in even better corrosion protection.
- the electrical component may also be a gas sensor in which the liquid medium that comes into contact with the interaction surface is, for example, a 2-3-nanometer-thick moist layer.
- the distances between the electrically conductive layer areas of this conductor track layer that are laterally adjacent to each other and spaced apart from each other are in each case less than 1.2 times the thickness of the conductor track layer.
- the distances between the laterally adjacent areas of this conductor track layer in each case are less than 1.1 times the thickness of the first conductor track layer, in particular less than 1 0 times, possibly less than 0.9 times, and preferably less than 0.8 times this thickness, at the least in the area of the first conductor track layer covered by the interaction surface.
- the electric component makes even better corrosion resistance possible.
- the second conductor track layer has at least two electrically conducting layer areas that are laterally spaced apart from each other, it is advantageous if, at least in the area of the first conductor track layer covered by the interaction surface, the distances between the laterally adjacent areas of this circuit track layer are each less than 1.2 times the thickness of the second conductor track layer, in particular less than 1.1 times, in some cases less than 1.0 times, possibly less than 0.9 times, and preferably less than 0.8 times this thickness.
- the first conductor track layer is made of metal, preferably of aluminum, and for the second conductor track layer to be made of a doped semiconductor material, preferably polysilicon.
- the conductor tracks that are made of aluminum have good electrical conductivity. Since aluminum has relatively low corrosion resistance, the first conductor track layer, which is close to the surface, is only provided outside of the area of the chip covered by the interaction surface, and it is located at a distance to this area. Within the area of the chip covered by the interaction surface, only the conductor track layer(s) that is (are) made of polysilicon is (are) used to locate the conductor tracks. The chip therefore has even better corrosion resistance to a liquid or viscous medium located in the opening.
- the polysilicon conductor tracks may be connected to the aluminum conductor tracks.
- At least one additional conductor track layer of metal and the least one insulation layer allocated to this conductor track layer may perhaps be disposed between the first conductor track layer and the second conductor track layer, in other words, the second conductor track layer does not necessarily need to be the conductor track layer that is second from the top, and the second insulation layer does not necessarily need to be the installation layer that is second from the top of the sensor and/or actuator chip.
- a structure for an electronic switch in particular for an evaluation device, is disposed on the substrate outside of the area covered by the opening, and said structure is electrically connected to the sensor and/or actuator structure by means of at least one of the conductor track layers.
- the switching apparatus that is comprised of the electronic circuit and the sensor and/or actuator then allows particularly compact dimensions. Moreover, the switching apparatus may be manufactured economically in standard production using semiconductor manufacturing methods.
- FIG. 1 is a partial cross-sectional view through a first example of an embodiment of the electrical component of the invention.
- FIG. 2 shows a partial cross-sectional view through a second example of an embodiment of the component of the invention.
- An electrical component that is identified in its entirety in FIG. 1 by the reference number 1 has a sensor chip, which has a semiconductor substrate 2 of p-doped silicon, on which structures for sensors are disposed. As a cover layer, the sensor chip has a passivation layer 3 that is preferably comprised of silicon nitride and silicon oxide and that can be several 100 nm to a few ⁇ m thick.
- a sensor structure shown on the left side of FIG. 1 has a precious metal electrode 4 a with an active surface area 5 a
- a sensor structure shown on the right side in FIG. 1 has a silicon nitride layer 4 b with an active surface area 5 b .
- the chip is surrounded by an encapsulation 6 that is formed by a casting compound and that is only partially shown in FIGS. 1 and 2 .
- the encapsulation has an opening 7 which forms an access to the active surface areas 5 a , 5 b . At least the edge of the encapsulation 6 that surrounds the opening contacts the chip and performs a sealing function.
- a liquid or viscous medium 8 that is to be tested and that contacts the chip at an interaction surface that corresponds to the entire free surface area of the chip 1 that is shown in the embodiment example shown in FIG. 1 and that covers the opening can be placed in the opening 7 .
- the interaction surface only extends across part of the surface area of the chip 1 that is covered by the opening 7 , for example when the chip is only partially immersed in a liquid medium 8 .
- the electrode 4 a is disposed on a field oxide layer 9 provided on the substrate 2 .
- the electrode 4 b is configured as a gate electrode disposed adjacent to a channel area 10 of a field effect transistor (FET).
- FET field effect transistor
- the channel area 10 is formed between a p+ source 11 and a p+ drain of the field effect transistor in an n ⁇ doped area 13 that is recessed into the substrate 2 .
- the source 11 and the drain 12 are located in area 13 .
- the field oxide layer 9 is located on the source 11 and on the drain 12 .
- the field oxide layer 9 has an interruption in the vicinity of the channel area 10 . This is bypassed by the electrode 4 b.
- a first electrical insulation layer 14 is located between the passivation layer 3 and the substrate 2 . It constitutes an inter-metallic dielectric (IMD).
- IMD inter-metallic dielectric
- a first conductor track layer 15 which is made of aluminum, is provided in some areas between the passivation layer 3 and the first insulation layer 14 .
- the first conductor track layer 15 has a plurality of areas configured as conductor tracks.
- An inter-layer dielectric (ILD), which serves as a second electrical insulation layer 16 is located between the first insulation layer 14 and the substrate 2 .
- a second conductor track layer 17 is provided between the first insulation layer 14 and the second insulation layer 16 . It is made of aluminum and has areas configured as conductor tracks. As can be seen in FIG. 1 , a first conductor track of the second conductor track layer 17 is connected to the n-doped area 13 , a second conductor track is connected to the source 11 , and a third conductor track is connected to the drain 12 . Interruptions are provided in the second insulation layer 16 and the field oxide layer. They are interspersed in each case with a section of the conductor tracks. The first insulation layer 14 and the second insulation layer 16 have interruptions 18 on the active surface areas 5 a , 5 b , of the electrodes 4 a , 4 b .
- the second conductor track layer 17 is laterally spaced apart from the interruptions 18 by the insulation layers 14 , 16 , and is sealed relative to said insulation layers.
- the passivation layer 3 is interspersed with the interruptions 18 .
- the first conductor track layer 15 is located completely outside of the area of the chip that is covered by the opening 7 in the encapsulation 6 . Moreover, the first conductor track layer 15 is laterally separated from the interruptions 18 by the first insulation layer 14 and by the passivation layer 3 and is sealed relative to said interruptions. It can be clearly seen that the first conductor track layer 15 in the area of the chip covered by the opening is spaced apart from the opening 7 , in a direction that is normal to the plane of extension of the chip, by the passivation layer 3 and the first insulation layer 14 located beneath it. Good corrosion resistance is thereby achieved for the first conductor track layer 15 relative to the medium 8 located in the opening 7 .
- the surface of the passivation layer 3 that borders the opening 7 is largely flat in the areas that are separated by the interruptions 18 , so that the risk of a crack forming in the passivation layer 3 is reduced accordingly when mechanical stresses occur in the chip.
- a shoulder 19 in the passivation layer 3 caused by the first conductor track layer 15 on an area of the surface of the passivation layer 3 facing away from the substrate 2 is covered by the encapsulation 6 and is separated laterally from the opening 7 .
- the second conductor track layer 17 is largely sealed off from the opening 17 by the encapsulation 6 and is thus protected from corrosion caused by the medium 8 .
- the electric component 1 shown in FIG. 1 therefore has a sensor and/or actuator chip with a substrate 2 on which a passivation layer 3 and a sensor and/or actuation structure having an active surface region 5 a , 5 b are disposed.
- the chip is surrounded by an encapsulation 6 that has an opening 7 that forms an access to the active surface area 5 a , 5 b , of which there is at least one.
- a stack of layers is located on the substrate 2 ; beginning with the passivation layer 3 and extending to the substrate 3 , it has at least one first conductor track layer 15 , one first electrical insulation layer 14 , one second conductor track layer 17 , and one second electrical insulation layer 16 .
- the first conductor track layer 15 is located completely outside the area of the chip that is covered by the opening 7 . At least one conductor track of the second conductor track layer 15 is connected to the sensor and/or actuator structure.
- a field effect transistor having a source 11 , a drain 12 , and the channel area 10 is integrated into the substrate 2 .
- Adjacent to the channel area 10 the field effect transistor has a gate electrode 4 c with an active surface area 5 c .
- a field oxide layer 9 which has an interruption that is adjacent to the channel area 10 and that is bypassed by the gate electrode 4 c , is located at the source 11 and at the drain 12 .
- a first electrical insulation layer 14 is also located between the passivation layer 3 and the substrate 2 . It constitutes an inter-metallic dielectric (IMD).
- IMD inter-metallic dielectric
- a first conductor track layer 15 which is made of aluminum and has a plurality of electrically conductive layer areas 15 a , 15 b , 15 c , is provided in some areas between the passivation layer 3 and the first insulation layer 14 .
- the layer areas 15 a , 15 b are configured as conductor tracks.
- Layer area 15 c is not used as a conductor track.
- the distances a between the layer areas 15 a , 15 b , 15 c , which are laterally adjacent to each other, in each case are less than the thickness of the conductor track layer 15 .
- An inter-layer dielectric which functions as a second electrical insulation layer 16 , is disposed between the first insulation layer 14 and in the substrate 2 .
- a second conductor track layer 17 which is made of aluminum, is disposed in some areas between the first insulation layer 14 and the second insulation layer 16 .
- the second conductor track layer 17 and the first insulation layer 14 are interspersed with the interruption 18 .
- the second insulation layer 17 ends at a distance to the interruption 18 and is sealed off from the interruption 18 by the first insulation layer 14 and the second insulation layer 16 .
- the second conductor track layer 17 has a plurality of electrically conductive layer areas 17 a , 17 b , 17 c .
- Layer areas 17 a , 17 b are configured as conductor tracks, while layer area 17 c is not used as a conductor track.
- the distances b between the laterally adjacent layer areas 17 a , 17 b , 17 c are each less than the thickness of the conductor track layer 17 . This thickness more or less corresponds to the thickness of the first electrical insulation layer 14 , the first conductor track layer 15 , and the passivation layer 3 .
- the areas of the surface of the passivation layer 3 which correspond to the orthogonal projection of the spaces between the layer areas 15 a , 15 b , 15 c , 17 a , 17 b , 17 c of a conductor track layer 15 , 17 , which are arranged adjacent to each other, are largely flat. As a consequence, the risk that a crack will form in the passivation layer 3 when mechanical stresses are present in the chip is reduced accordingly.
- a third electrical insulation layer 20 which is embodied as an oxide layer, is disposed between the second insulation layer 16 and the field oxide layer 9 .
- a third conductor track layer 21 which is comprised of a polysilicon layer and which forms conductor tracks, is located between this insulation layer and the second insulation layer 16 .
- a fourth conductor track layer 22 is located between the third insulation layer 20 and the field oxide layer 9 . It is also made of a polysilicon layer 22 and has further electrical conductor tracks.
- conductor tracks in conductor track layers 15 , 17 , 21 , 22 may be connected to each other by means of through-contacts.
- the substrate 2 may also be made of glass.
Abstract
Description
- This application is a divisional of U.S. application Ser. No. 11/791,501, filed May 24, 2007, which is a National Phase Application of PCT/EP2004/013464, filed Nov. 26, 2004, both of which are incorporated herein by reference.
- 1. Field of the Invention
- The invention relates to an electrical component having a sensor and/or actuator chip, in particular a CMOS chip, that has a substrate on which a passivation layer and at least one structure that has at least one active surface area for a sensor and/or actuator are located, and the chip is surrounded by an encapsulation that has at least one opening that forms an access to the active surface area, of which at least one is present, and to the passivation layer, and in the opening the chip has an interaction surface that extends, at least in some areas, over the passivation layer and the active surface area and that in the operating position is in contact with a liquid or viscous medium, and a first electrical insulation layer is provided between the passivation layer and the substrate, and a first conductor track layer is located in some areas between the passivation layer and the first insulation layer, and a second electrical insulation layer is provided between the first insulation layer and the substrate, and a second conductor track layer is located between the first insulation layer and the second insulation layer, and at least one of the conductor tracks is connected to the sensor and/or actuator structure.
- 2. Description of Related Art
- An electrical component of this type is known from actual practice. It has a CMOS chip with a semiconductor substrate into which an ion-sensitive field effect transistor (ISFET) is integrated. The sensor has an active surface area that is configured as a gate electrode and that can be brought into contact with a liquid medium in order to detect ions contained in this medium. A plurality of conductor track layers made of aluminum, in which the conductor tracks and/or sections of conductor tracks extend, are located on the substrate. Conductor track sections of conductor tracks that extend across to a plurality of conductor track layers are connected to each other by means of through-contacts. An electrical insulation layer is provided between each of the conductor track layers as well as between the lowermost conductor track layer, which is located closest to the substrate, and the substrate. A passivation layer is located as a cover layer on the stack of layers comprising the conductor track layers and the insulation layers. The circuit tracks connect the drain and source of the ISFET with bond pads that are spaced apart from the drain and source and are located on the surface of the CMOS chip.
- The CMOS chip is encapsulated with a plastic casting compound that is in close contact with the chip and that has an opening that is connected to the active surface area and into which the liquid medium may be filled. Thus, the medium [typo in German] comes into contact with the chip at an interaction surface that extends across a part of the passivation later and the active surface area. The conductor track layers and the insulation layers in each case extend into the area of the chip that is covered by the interaction surface. The passivation layer and the insulation layers serve as corrosion protection for the circuit track layers in order to prevent the circuit track layers from coming into contact with the liquid medium. However, it has been found in actual practice that the passivation layer only provides limited corrosion protection for the conductor track layers, and that the chips only have a relatively short service life when the opening is filled with a liquid or viscous medium. If a conductor track comes into contact with the medium, for example due to a defect in the passivation layer, the entire chip can fail.
- A semiconductor chip that has a silicon substrate on which an array having 16 approximately rectangular electrodes is disposed as disclosed in F. Faβbender et. al., Optimization of Passivation Layers for Corrosion Protection of Silicon-Based Microelectrode Arrays, Sensors and Actuators B 68 (2000), p. 128-133. The electrodes are connected to bond pads by means of conductor tracks located in a single conductor track layer. The conductor track layer is covered by a passivation layer. When the chip is manufactured, a silicon dioxide layer is generated on the semiconductor substrate with the aid of a heat-treating process. Trench-like recesses are imparted in this layer at the locations at which the conductor tracks will later be present. A metal that forms the circuit tracks is deposited in these recesses. The recessed arrangement of the conductor tracks in the silicon dioxide layer causes the chip to have an essentially flat surface. The purpose of these is to prevent mechanical stresses in the passivation layer, which can lead to cracks through which an analyte that is to be analyzed using the electrodes can come into contact with the conductor track layer and can cause corrosion on the conductor track layer. The corrosion resistance of the chip can be improved with this measure, and thus the service life of the chip can be extended. However, placing the trenches in the silicon dioxide layer located on the substrate results in a substantial additional expense in the manufacturing of the chip, in particular with a CMOS process.
- The object of the invention is therefore to provide an electrical component of the type referred to above that can be manufactured in a cost-effective manner using the standard semiconductor manufacturing processes but that permits good corrosion resistance as well as long service life.
- In the invention, at least those areas of the first conductor track layer adjacent to the passivation layer that carry an electrical potential or that are necessary for the electrical operation of the component are located completely outside of the area of the chip that is covered by the interaction surface. In the area of the chip that is covered by the interaction surface, in addition to the passivation layer at least the first insulation layer is then located between the uppermost conductor track layer that has the least distance to the opening or to the liquid or viscous medium contained in it and the conductor track layer that is used for the electrical operation of the component, whereby the corrosion resistance is significantly improved compared with a chip in which only the passivation layer is provided between the uppermost conductor track layer and the liquid or viscous medium. Inside of the area of the chip that is covered by the interaction surface, at least one electrically insulated, floating partial area of the first conductor track layer, which is not used to carry electrical voltage and/or current and therefore is not significant to the electrical operation of the component, may optionally be located. When the chip is manufactured, after the conductor track, of which there is at least one, of the second conductor track layer is produced, the first insulation layer is produced on or applied to the chip and after that the first conductor track layer and the passivation layer are produced on the chip or are applied to it. The surface structure caused by the contour of the conductor track, of which there is at least one, on the boundary surface of the insulation layer that is distant from the conductor track is already significantly flatter and smoother compared with the contour of the conductor track of the second conductor track layer. This surface structure is smoothed even more by the passivation layer, so that the passivation layer has a surface that is for the most part flat and free from abrupt steps or shoulders. This significantly reduces the risk that cracks will form in the passivation layer when mechanical stresses are present in the chip. The component of the invention therefore achieves good corrosion resistance and a long service life. The component chip can be manufactured economically using standard semiconductor manufacturing processes. Providing trenches in the chip surface, which is a complicated and expensive undertaking, is not necessary. The passivation layer may be comprised of a plurality of layers, each of which may be made of various materials. This results in even better corrosion protection. The electrical component may also be a gas sensor in which the liquid medium that comes into contact with the interaction surface is, for example, a 2-3-nanometer-thick moist layer.
- In the invention, at least in the area of the first conductor track layer that is covered by the interaction surface, the distances between the electrically conductive layer areas of this conductor track layer that are laterally adjacent to each other and spaced apart from each other are in each case less than 1.2 times the thickness of the conductor track layer. This ensures in a simple way that the surface of the passivation layer that is located on the first conductor track layer and that in the operating position is in contact with the liquid or viscous medium is for the most part flat in the areas that cover the spacings between areas of the first conductor track layer. This significantly reduces the risk that cracks will form in the passivation layer went mechanical stresses are present in the chip. The electrical component of the invention therefore has good corrosion resistance and a long service life. The component chip can be manufactured economically using standard semiconductor manufacturing processes. The interaction surface that is provided for contact with the medium preferably extends across the entire surface area of the chip that is covered by the opening of the encapsulation.
- In a preferred embodiment of the invention, the distances between the laterally adjacent areas of this conductor track layer in each case are less than 1.1 times the thickness of the first conductor track layer, in particular less than 1 0 times, possibly less than 0.9 times, and preferably less than 0.8 times this thickness, at the least in the area of the first conductor track layer covered by the interaction surface. In this case, the electric component makes even better corrosion resistance possible.
- When the second conductor track layer has at least two electrically conducting layer areas that are laterally spaced apart from each other, it is advantageous if, at least in the area of the first conductor track layer covered by the interaction surface, the distances between the laterally adjacent areas of this circuit track layer are each less than 1.2 times the thickness of the second conductor track layer, in particular less than 1.1 times, in some cases less than 1.0 times, possibly less than 0.9 times, and preferably less than 0.8 times this thickness. This makes the surface of the passivation layer even flatter, which reduces further the risk that a crack will form in the passivation layer when mechanical stresses are present in the chip. Therefore, the electrical component has an even longer service life.
- It is advantageous for the first conductor track layer to be made of metal, preferably of aluminum, and for the second conductor track layer to be made of a doped semiconductor material, preferably polysilicon. The conductor tracks that are made of aluminum have good electrical conductivity. Since aluminum has relatively low corrosion resistance, the first conductor track layer, which is close to the surface, is only provided outside of the area of the chip covered by the interaction surface, and it is located at a distance to this area. Within the area of the chip covered by the interaction surface, only the conductor track layer(s) that is (are) made of polysilicon is (are) used to locate the conductor tracks. The chip therefore has even better corrosion resistance to a liquid or viscous medium located in the opening. Outside of the chip area that is covered by the interaction surface, the polysilicon conductor tracks may be connected to the aluminum conductor tracks. At least one additional conductor track layer of metal and the least one insulation layer allocated to this conductor track layer may perhaps be disposed between the first conductor track layer and the second conductor track layer, in other words, the second conductor track layer does not necessarily need to be the conductor track layer that is second from the top, and the second insulation layer does not necessarily need to be the installation layer that is second from the top of the sensor and/or actuator chip.
- In a preferred embodiment of the invention, a structure for an electronic switch, in particular for an evaluation device, is disposed on the substrate outside of the area covered by the opening, and said structure is electrically connected to the sensor and/or actuator structure by means of at least one of the conductor track layers. The switching apparatus that is comprised of the electronic circuit and the sensor and/or actuator then allows particularly compact dimensions. Moreover, the switching apparatus may be manufactured economically in standard production using semiconductor manufacturing methods.
- Examples of embodiments of the invention are explained further below based on the drawing. The drawing shows:
-
FIG. 1 is a partial cross-sectional view through a first example of an embodiment of the electrical component of the invention, and -
FIG. 2 shows a partial cross-sectional view through a second example of an embodiment of the component of the invention. - An electrical component that is identified in its entirety in
FIG. 1 by the reference number 1 has a sensor chip, which has asemiconductor substrate 2 of p-doped silicon, on which structures for sensors are disposed. As a cover layer, the sensor chip has apassivation layer 3 that is preferably comprised of silicon nitride and silicon oxide and that can be several 100 nm to a few μm thick. A sensor structure shown on the left side ofFIG. 1 has aprecious metal electrode 4 a with anactive surface area 5 a, and a sensor structure shown on the right side inFIG. 1 has a silicon nitride layer 4 b with anactive surface area 5 b. The chip is surrounded by an encapsulation 6 that is formed by a casting compound and that is only partially shown inFIGS. 1 and 2 . The encapsulation has anopening 7 which forms an access to theactive surface areas viscous medium 8 that is to be tested and that contacts the chip at an interaction surface that corresponds to the entire free surface area of the chip 1 that is shown in the embodiment example shown inFIG. 1 and that covers the opening can be placed in theopening 7. However, it is also conceivable that the interaction surface only extends across part of the surface area of the chip 1 that is covered by theopening 7, for example when the chip is only partially immersed in aliquid medium 8. - In the example of the embodiment shown in
FIG. 1 , theelectrode 4 a is disposed on afield oxide layer 9 provided on thesubstrate 2. The electrode 4 b is configured as a gate electrode disposed adjacent to achannel area 10 of a field effect transistor (FET). Thechannel area 10 is formed between ap+ source 11 and a p+ drain of the field effect transistor in an n− dopedarea 13 that is recessed into thesubstrate 2. InFIG. 1 one can see that thesource 11 and thedrain 12 are located inarea 13. On both sides of thechannel area 10 thefield oxide layer 9 is located on thesource 11 and on thedrain 12. Thefield oxide layer 9 has an interruption in the vicinity of thechannel area 10. This is bypassed by the electrode 4 b. - A first
electrical insulation layer 14 is located between thepassivation layer 3 and thesubstrate 2. It constitutes an inter-metallic dielectric (IMD). In some areas between thepassivation layer 3 and thefirst insulation layer 14, a firstconductor track layer 15, which is made of aluminum, is provided. The firstconductor track layer 15 has a plurality of areas configured as conductor tracks. An inter-layer dielectric (ILD), which serves as a secondelectrical insulation layer 16, is located between thefirst insulation layer 14 and thesubstrate 2. - A second
conductor track layer 17 is provided between thefirst insulation layer 14 and thesecond insulation layer 16. It is made of aluminum and has areas configured as conductor tracks. As can be seen inFIG. 1 , a first conductor track of the secondconductor track layer 17 is connected to the n-dopedarea 13, a second conductor track is connected to thesource 11, and a third conductor track is connected to thedrain 12. Interruptions are provided in thesecond insulation layer 16 and the field oxide layer. They are interspersed in each case with a section of the conductor tracks. Thefirst insulation layer 14 and thesecond insulation layer 16 haveinterruptions 18 on theactive surface areas electrodes 4 a, 4 b. These interruptions communicate with theopening 7 in the encapsulation 6. The secondconductor track layer 17 is laterally spaced apart from theinterruptions 18 by the insulation layers 14, 16, and is sealed relative to said insulation layers. Thepassivation layer 3 is interspersed with theinterruptions 18. - In
FIG. 1 one can see that the firstconductor track layer 15 is located completely outside of the area of the chip that is covered by theopening 7 in the encapsulation 6. Moreover, the firstconductor track layer 15 is laterally separated from theinterruptions 18 by thefirst insulation layer 14 and by thepassivation layer 3 and is sealed relative to said interruptions. It can be clearly seen that the firstconductor track layer 15 in the area of the chip covered by the opening is spaced apart from theopening 7, in a direction that is normal to the plane of extension of the chip, by thepassivation layer 3 and thefirst insulation layer 14 located beneath it. Good corrosion resistance is thereby achieved for the firstconductor track layer 15 relative to the medium 8 located in theopening 7. The surface of thepassivation layer 3 that borders theopening 7 is largely flat in the areas that are separated by theinterruptions 18, so that the risk of a crack forming in thepassivation layer 3 is reduced accordingly when mechanical stresses occur in the chip. Ashoulder 19 in thepassivation layer 3 caused by the firstconductor track layer 15 on an area of the surface of thepassivation layer 3 facing away from thesubstrate 2 is covered by the encapsulation 6 and is separated laterally from theopening 7. Thus, if a crack in the passivation layer happens to form at theshoulder 19, the secondconductor track layer 17 is largely sealed off from theopening 17 by the encapsulation 6 and is thus protected from corrosion caused by themedium 8. - The electric component 1 shown in
FIG. 1 therefore has a sensor and/or actuator chip with asubstrate 2 on which apassivation layer 3 and a sensor and/or actuation structure having anactive surface region opening 7 that forms an access to theactive surface area substrate 2; beginning with thepassivation layer 3 and extending to thesubstrate 3, it has at least one firstconductor track layer 15, one firstelectrical insulation layer 14, one secondconductor track layer 17, and one secondelectrical insulation layer 16. The firstconductor track layer 15 is located completely outside the area of the chip that is covered by theopening 7. At least one conductor track of the secondconductor track layer 15 is connected to the sensor and/or actuator structure. - In the example of an embodiment shown in
FIG. 2 , a field effect transistor having asource 11, adrain 12, and thechannel area 10 is integrated into thesubstrate 2. Adjacent to thechannel area 10 the field effect transistor has a gate electrode 4 c with an active surface area 5 c. With the aid of the field effect transistor it is possible, for example, to detect ions located in a medium 8 that is present in the opening and that is in contact with the gate electrode 4 c. Afield oxide layer 9, which has an interruption that is adjacent to thechannel area 10 and that is bypassed by the gate electrode 4 c, is located at thesource 11 and at thedrain 12. - In this example of an embodiment a first
electrical insulation layer 14 is also located between thepassivation layer 3 and thesubstrate 2. It constitutes an inter-metallic dielectric (IMD). A firstconductor track layer 15, which is made of aluminum and has a plurality of electricallyconductive layer areas passivation layer 3 and thefirst insulation layer 14. Thelayer areas 15 a, 15 b are configured as conductor tracks.Layer area 15 c is not used as a conductor track. In the area of the firstconductor track layer 15 that is covered by theopening 7 and thepassivation layer 3, the distances a between thelayer areas conductor track layer 15. - An inter-layer dielectric (ILD), which functions as a second
electrical insulation layer 16, is disposed between thefirst insulation layer 14 and in thesubstrate 2. A secondconductor track layer 17, which is made of aluminum, is disposed in some areas between thefirst insulation layer 14 and thesecond insulation layer 16. The secondconductor track layer 17 and thefirst insulation layer 14 are interspersed with theinterruption 18. Thesecond insulation layer 17 ends at a distance to theinterruption 18 and is sealed off from theinterruption 18 by thefirst insulation layer 14 and thesecond insulation layer 16. - The second
conductor track layer 17 has a plurality of electrically conductive layer areas 17 a, 17 b, 17 c. Layer areas 17 a, 17 b are configured as conductor tracks, while layer area 17 c is not used as a conductor track. In the area of the secondconductor track layer 17 covered by theopening 7 and thepassivation layer 3, the distances b between the laterally adjacent layer areas 17 a, 17 b, 17 c are each less than the thickness of theconductor track layer 17. This thickness more or less corresponds to the thickness of the firstelectrical insulation layer 14, the firstconductor track layer 15, and thepassivation layer 3. Because of the small lateral distances a, b between thelayer areas conductor track layer 15 or the layer areas 17 a, 17 b, 17 c of the secondconductor track layer 17, the areas of the surface of thepassivation layer 3, which correspond to the orthogonal projection of the spaces between thelayer areas conductor track layer passivation layer 3 when mechanical stresses are present in the chip is reduced accordingly. - A third
electrical insulation layer 20, which is embodied as an oxide layer, is disposed between thesecond insulation layer 16 and thefield oxide layer 9. In some areas a thirdconductor track layer 21, which is comprised of a polysilicon layer and which forms conductor tracks, is located between this insulation layer and thesecond insulation layer 16. A fourthconductor track layer 22 is located between thethird insulation layer 20 and thefield oxide layer 9. It is also made of apolysilicon layer 22 and has further electrical conductor tracks. - It must also be noted that the conductor tracks in conductor track layers 15, 17, 21, 22 may be connected to each other by means of through-contacts. The
substrate 2 may also be made of glass.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/840,597 US8084792B2 (en) | 2004-11-26 | 2010-07-21 | Electric component |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2004/013464 WO2006056226A1 (en) | 2004-11-26 | 2004-11-26 | Electric component |
US79150107A | 2007-05-24 | 2007-05-24 | |
US12/840,597 US8084792B2 (en) | 2004-11-26 | 2010-07-21 | Electric component |
Related Parent Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/791,501 Division US7777283B2 (en) | 2004-11-26 | 2004-11-26 | Electric component |
PCT/EP2004/013464 Division WO2006056226A1 (en) | 2004-11-26 | 2004-11-26 | Electric component |
US79150107A Division | 2004-11-26 | 2007-05-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100283087A1 true US20100283087A1 (en) | 2010-11-11 |
US8084792B2 US8084792B2 (en) | 2011-12-27 |
Family
ID=34959762
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/791,501 Expired - Fee Related US7777283B2 (en) | 2004-11-26 | 2004-11-26 | Electric component |
US12/840,597 Expired - Fee Related US8084792B2 (en) | 2004-11-26 | 2010-07-21 | Electric component |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/791,501 Expired - Fee Related US7777283B2 (en) | 2004-11-26 | 2004-11-26 | Electric component |
Country Status (5)
Country | Link |
---|---|
US (2) | US7777283B2 (en) |
EP (1) | EP1815238B1 (en) |
JP (1) | JP4637914B2 (en) |
CN (1) | CN101048655A (en) |
WO (1) | WO2006056226A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140073039A1 (en) * | 2012-09-08 | 2014-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Direct sensing biofets and methods of manufacture |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2672315A1 (en) | 2006-12-14 | 2008-06-26 | Ion Torrent Systems Incorporated | Methods and apparatus for measuring analytes using large scale fet arrays |
US8349167B2 (en) | 2006-12-14 | 2013-01-08 | Life Technologies Corporation | Methods and apparatus for detecting molecular interactions using FET arrays |
US11339430B2 (en) | 2007-07-10 | 2022-05-24 | Life Technologies Corporation | Methods and apparatus for measuring analytes using large scale FET arrays |
US8262900B2 (en) | 2006-12-14 | 2012-09-11 | Life Technologies Corporation | Methods and apparatus for measuring analytes using large scale FET arrays |
US8099757B2 (en) | 2007-10-15 | 2012-01-17 | Time Warner Cable Inc. | Methods and apparatus for revenue-optimized delivery of content in a network |
US8813143B2 (en) | 2008-02-26 | 2014-08-19 | Time Warner Enterprises LLC | Methods and apparatus for business-based network resource allocation |
US7947524B2 (en) * | 2008-09-30 | 2011-05-24 | Stion Corporation | Humidity control and method for thin film photovoltaic materials |
US20100301398A1 (en) | 2009-05-29 | 2010-12-02 | Ion Torrent Systems Incorporated | Methods and apparatus for measuring analytes |
US20100137143A1 (en) | 2008-10-22 | 2010-06-03 | Ion Torrent Systems Incorporated | Methods and apparatus for measuring analytes |
US20120261274A1 (en) | 2009-05-29 | 2012-10-18 | Life Technologies Corporation | Methods and apparatus for measuring analytes |
US8776573B2 (en) | 2009-05-29 | 2014-07-15 | Life Technologies Corporation | Methods and apparatus for measuring analytes |
JP5952813B2 (en) | 2010-06-30 | 2016-07-13 | ライフ テクノロジーズ コーポレーション | Method and apparatus for testing ISFET arrays |
US8731847B2 (en) | 2010-06-30 | 2014-05-20 | Life Technologies Corporation | Array configuration and readout scheme |
AU2011226767B1 (en) | 2010-06-30 | 2011-11-10 | Life Technologies Corporation | Ion-sensing charge-accumulation circuits and methods |
US11307166B2 (en) | 2010-07-01 | 2022-04-19 | Life Technologies Corporation | Column ADC |
EP2589065B1 (en) | 2010-07-03 | 2015-08-19 | Life Technologies Corporation | Chemically sensitive sensor with lightly doped drains |
WO2012036679A1 (en) | 2010-09-15 | 2012-03-22 | Life Technologies Corporation | Methods and apparatus for measuring analytes |
EP2619564B1 (en) | 2010-09-24 | 2016-03-16 | Life Technologies Corporation | Matched pair transistor circuits |
US20120167392A1 (en) * | 2010-12-30 | 2012-07-05 | Stmicroelectronics Pte. Ltd. | Razor with chemical and biological sensor |
KR20130045047A (en) * | 2011-10-25 | 2013-05-03 | 에스케이하이닉스 주식회사 | 3-dimensional nonvolatile memory device and method for manyfacturing the same |
US9970984B2 (en) | 2011-12-01 | 2018-05-15 | Life Technologies Corporation | Method and apparatus for identifying defects in a chemical sensor array |
US9019688B2 (en) | 2011-12-02 | 2015-04-28 | Stmicroelectronics Pte Ltd. | Capacitance trimming with an integrated heater |
US9027400B2 (en) | 2011-12-02 | 2015-05-12 | Stmicroelectronics Pte Ltd. | Tunable humidity sensor with integrated heater |
CN102637641B (en) * | 2012-03-20 | 2015-05-20 | 华中科技大学 | Method for integrating phase-change random memory array and peripheral circuit chip |
US8786331B2 (en) | 2012-05-29 | 2014-07-22 | Life Technologies Corporation | System for reducing noise in a chemical sensor array |
US8862155B2 (en) | 2012-08-30 | 2014-10-14 | Time Warner Cable Enterprises Llc | Apparatus and methods for enabling location-based services within a premises |
US9080968B2 (en) | 2013-01-04 | 2015-07-14 | Life Technologies Corporation | Methods and systems for point of use removal of sacrificial material |
US9841398B2 (en) | 2013-01-08 | 2017-12-12 | Life Technologies Corporation | Methods for manufacturing well structures for low-noise chemical sensors |
US8963216B2 (en) | 2013-03-13 | 2015-02-24 | Life Technologies Corporation | Chemical sensor with sidewall spacer sensor surface |
CN105051525B (en) | 2013-03-15 | 2019-07-26 | 生命科技公司 | Chemical device with thin conducting element |
CN105264366B (en) * | 2013-03-15 | 2019-04-16 | 生命科技公司 | Chemical sensor with consistent sensor surface area |
US9835585B2 (en) | 2013-03-15 | 2017-12-05 | Life Technologies Corporation | Chemical sensor with protruded sensor surface |
US10368255B2 (en) | 2017-07-25 | 2019-07-30 | Time Warner Cable Enterprises Llc | Methods and apparatus for client-based dynamic control of connections to co-existing radio access networks |
CN105283758B (en) * | 2013-03-15 | 2018-06-05 | 生命科技公司 | Chemical sensor with consistent sensor surface area |
US9066153B2 (en) | 2013-03-15 | 2015-06-23 | Time Warner Cable Enterprises Llc | Apparatus and methods for multicast delivery of content in a content delivery network |
US20140336063A1 (en) | 2013-05-09 | 2014-11-13 | Life Technologies Corporation | Windowed Sequencing |
US10458942B2 (en) | 2013-06-10 | 2019-10-29 | Life Technologies Corporation | Chemical sensor array having multiple sensors per well |
US9313568B2 (en) | 2013-07-23 | 2016-04-12 | Chicago Custom Acoustics, Inc. | Custom earphone with dome in the canal |
US11540148B2 (en) | 2014-06-11 | 2022-12-27 | Time Warner Cable Enterprises Llc | Methods and apparatus for access point location |
US10028025B2 (en) | 2014-09-29 | 2018-07-17 | Time Warner Cable Enterprises Llc | Apparatus and methods for enabling presence-based and use-based services |
US9935833B2 (en) | 2014-11-05 | 2018-04-03 | Time Warner Cable Enterprises Llc | Methods and apparatus for determining an optimized wireless interface installation configuration |
KR102593647B1 (en) | 2014-12-18 | 2023-10-26 | 라이프 테크놀로지스 코포레이션 | High data rate integrated circuit with transmitter configuration |
US10077472B2 (en) | 2014-12-18 | 2018-09-18 | Life Technologies Corporation | High data rate integrated circuit with power management |
EP3234575B1 (en) | 2014-12-18 | 2023-01-25 | Life Technologies Corporation | Apparatus for measuring analytes using large scale fet arrays |
US10327187B2 (en) | 2015-12-04 | 2019-06-18 | Time Warner Cable Enterprises Llc | Apparatus and method for wireless network extensibility and enhancement |
US9986578B2 (en) | 2015-12-04 | 2018-05-29 | Time Warner Cable Enterprises Llc | Apparatus and methods for selective data network access |
US9918345B2 (en) | 2016-01-20 | 2018-03-13 | Time Warner Cable Enterprises Llc | Apparatus and method for wireless network services in moving vehicles |
US10492034B2 (en) | 2016-03-07 | 2019-11-26 | Time Warner Cable Enterprises Llc | Apparatus and methods for dynamic open-access networks |
US10586023B2 (en) | 2016-04-21 | 2020-03-10 | Time Warner Cable Enterprises Llc | Methods and apparatus for secondary content management and fraud prevention |
US10164858B2 (en) | 2016-06-15 | 2018-12-25 | Time Warner Cable Enterprises Llc | Apparatus and methods for monitoring and diagnosing a wireless network |
US10645547B2 (en) | 2017-06-02 | 2020-05-05 | Charter Communications Operating, Llc | Apparatus and methods for providing wireless service in a venue |
US10638361B2 (en) | 2017-06-06 | 2020-04-28 | Charter Communications Operating, Llc | Methods and apparatus for dynamic control of connections to co-existing radio access networks |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4644380A (en) * | 1977-12-08 | 1987-02-17 | University Of Pennsylvania | Substance-sensitive electrical structures |
US4743954A (en) * | 1985-06-07 | 1988-05-10 | University Of Utah | Integrated circuit for a chemical-selective sensor with voltage output |
US5319226A (en) * | 1991-09-06 | 1994-06-07 | Dong Jin Kim | Method of fabricating an ion sensitive field effect transistor with a Ta2 O5 hydrogen ion sensing membrane |
US5944970A (en) * | 1997-04-29 | 1999-08-31 | Honeywell Inc. | Solid state electrochemical sensors |
US20020117694A1 (en) * | 2000-12-22 | 2002-08-29 | Seiko Epson Corporation | Sensor cell |
US20030107097A1 (en) * | 1999-07-14 | 2003-06-12 | Mcarthur Douglas C. | Ultra-rugged biometric I.C. sensor and method of making the same |
US20060108219A1 (en) * | 2003-06-23 | 2006-05-25 | Canon Kabushiki Kaisha | Chemical sensor and chemical sensor apparatus |
US7061061B2 (en) * | 1998-04-09 | 2006-06-13 | California Institute Of Technology | Techniques and systems for analyte detection |
US20060197118A1 (en) * | 2003-09-19 | 2006-09-07 | Piero Migliorato | Detection of molecular interactions using a field effect transistor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2096825A (en) | 1981-04-09 | 1982-10-20 | Sibbald Alastair | Chemical sensitive semiconductor field effect transducer |
DE3637513A1 (en) | 1986-11-04 | 1988-05-11 | Semikron Elektronik Gmbh | Method of producing finely structured contact electrodes of power semiconductor components |
DE19641777C2 (en) * | 1996-10-10 | 2001-09-27 | Micronas Gmbh | Method for producing a sensor with a metal electrode in a MOS arrangement |
DE59909242D1 (en) * | 1998-03-10 | 2004-05-27 | Micronas Gmbh | REFERENCE ELECTRODE |
US6482639B2 (en) | 2000-06-23 | 2002-11-19 | The United States Of America As Represented By The Secretary Of The Navy | Microelectronic device and method for label-free detection and quantification of biological and chemical molecules |
CA2456765A1 (en) * | 2001-08-08 | 2003-02-20 | The Arizona Board Of Regents | Nucleic acid field effect transistor |
JP2003322633A (en) * | 2002-05-01 | 2003-11-14 | Seiko Epson Corp | Sensor cell, biosensor, and manufacturing method therefor |
-
2004
- 2004-11-26 EP EP04803308A patent/EP1815238B1/en not_active Not-in-force
- 2004-11-26 WO PCT/EP2004/013464 patent/WO2006056226A1/en active IP Right Grant
- 2004-11-26 JP JP2007541701A patent/JP4637914B2/en not_active Expired - Fee Related
- 2004-11-26 CN CN200480044289.1A patent/CN101048655A/en active Pending
- 2004-11-26 US US11/791,501 patent/US7777283B2/en not_active Expired - Fee Related
-
2010
- 2010-07-21 US US12/840,597 patent/US8084792B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4644380A (en) * | 1977-12-08 | 1987-02-17 | University Of Pennsylvania | Substance-sensitive electrical structures |
US4743954A (en) * | 1985-06-07 | 1988-05-10 | University Of Utah | Integrated circuit for a chemical-selective sensor with voltage output |
US5319226A (en) * | 1991-09-06 | 1994-06-07 | Dong Jin Kim | Method of fabricating an ion sensitive field effect transistor with a Ta2 O5 hydrogen ion sensing membrane |
US5944970A (en) * | 1997-04-29 | 1999-08-31 | Honeywell Inc. | Solid state electrochemical sensors |
US7061061B2 (en) * | 1998-04-09 | 2006-06-13 | California Institute Of Technology | Techniques and systems for analyte detection |
US20030107097A1 (en) * | 1999-07-14 | 2003-06-12 | Mcarthur Douglas C. | Ultra-rugged biometric I.C. sensor and method of making the same |
US20020117694A1 (en) * | 2000-12-22 | 2002-08-29 | Seiko Epson Corporation | Sensor cell |
US20060108219A1 (en) * | 2003-06-23 | 2006-05-25 | Canon Kabushiki Kaisha | Chemical sensor and chemical sensor apparatus |
US20060197118A1 (en) * | 2003-09-19 | 2006-09-07 | Piero Migliorato | Detection of molecular interactions using a field effect transistor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140073039A1 (en) * | 2012-09-08 | 2014-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Direct sensing biofets and methods of manufacture |
US9091647B2 (en) * | 2012-09-08 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Direct sensing bioFETs and methods of manufacture |
US10502706B2 (en) | 2012-09-08 | 2019-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Direct sensing BioFETs and methods of manufacture |
US11353421B2 (en) | 2012-09-08 | 2022-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Direct sensing BioFETs and methods of manufacture |
Also Published As
Publication number | Publication date |
---|---|
US7777283B2 (en) | 2010-08-17 |
CN101048655A (en) | 2007-10-03 |
EP1815238B1 (en) | 2008-07-16 |
JP2008522139A (en) | 2008-06-26 |
JP4637914B2 (en) | 2011-02-23 |
US8084792B2 (en) | 2011-12-27 |
US20070290235A1 (en) | 2007-12-20 |
WO2006056226A1 (en) | 2006-06-01 |
EP1815238A1 (en) | 2007-08-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8084792B2 (en) | Electric component | |
US7741675B2 (en) | Semiconductor component and method for fabricating it | |
JP5490208B2 (en) | Semiconductor gas sensor | |
US7417295B2 (en) | Insulated gate semiconductor device and manufacturing method thereof | |
US20140061729A1 (en) | Ion sensitive field effect transistor | |
KR101909948B1 (en) | Multi-level options for power mosfets | |
US9761550B2 (en) | Power semiconductor device with a double metal contact and related method | |
JPH1084145A (en) | Manufacture of combined sensor of pressure and electrochemical sensors | |
US20060273390A1 (en) | Gate contact and runners for high density trench MOSFET | |
US8319284B2 (en) | Laterally diffused metal-oxide-semiconductor device | |
US9620467B2 (en) | Electronic component | |
US10475919B2 (en) | Method of producing an integrated power transistor circuit having a current-measuring cell | |
US8242545B2 (en) | Device for detection of a gas or gas mixture and method for manufacturing such a device | |
US9698103B2 (en) | Semiconductor device and manufacturing method therefor | |
US11004815B2 (en) | Semiconductor device | |
CN100499125C (en) | Semiconductor device | |
JP4546796B2 (en) | Semiconductor device | |
JP2008181988A (en) | Semiconductor device | |
JP2006245391A (en) | Semiconductor apparatus | |
US20130140702A1 (en) | Fastening device | |
EP1916520B1 (en) | Electric component | |
DE10353121B4 (en) | Electrical component |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICRONAS GMBH, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEHMANN, MIRKO;FREUND, INGO;SIGNING DATES FROM 20080206 TO 20080226;REEL/FRAME:025494/0847 |
|
ZAAA | Notice of allowance and fees due |
Free format text: ORIGINAL CODE: NOA |
|
ZAAB | Notice of allowance mailed |
Free format text: ORIGINAL CODE: MN/=. |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: TDK-MICRONAS GMBH, GERMANY Free format text: CHANGE OF NAME;ASSIGNOR:MICRONAS GMBH;REEL/FRAME:041901/0191 Effective date: 20161212 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20231227 |