US20110018072A1 - Metal gate transistor and method for fabricating the same - Google Patents
Metal gate transistor and method for fabricating the same Download PDFInfo
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- US20110018072A1 US20110018072A1 US12/894,130 US89413010A US2011018072A1 US 20110018072 A1 US20110018072 A1 US 20110018072A1 US 89413010 A US89413010 A US 89413010A US 2011018072 A1 US2011018072 A1 US 2011018072A1
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- metal gate
- layer
- metal
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- gate transistor
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 108
- 239000002184 metal Substances 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title description 27
- 239000000758 substrate Substances 0.000 claims abstract description 35
- NLQFUUYNQFMIJW-UHFFFAOYSA-N dysprosium(III) oxide Inorganic materials O=[Dy]O[Dy]=O NLQFUUYNQFMIJW-UHFFFAOYSA-N 0.000 claims description 4
- 229910000311 lanthanide oxide Inorganic materials 0.000 claims description 4
- 229910004129 HfSiO Inorganic materials 0.000 claims description 3
- -1 HfSiON Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 3
- 229910010037 TiAlN Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910006501 ZrSiO Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 113
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 31
- 229920005591 polysilicon Polymers 0.000 description 31
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 125000006850 spacer group Chemical group 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
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- 239000003989 dielectric material Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
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- 230000015572 biosynthetic process Effects 0.000 description 3
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- 238000005468 ion implantation Methods 0.000 description 3
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- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
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- 238000000151 deposition Methods 0.000 description 2
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- 238000011065 in-situ storage Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910017109 AlON Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/926—Dummy metallization
Definitions
- the invention relates to a method for fabricating a transistor, and more particularly, to a method for fabricating a metal gate transistor.
- polysilicon material In the field of semiconductor fabrication, the use of polysilicon material is diverse. Having a strong resistance for heat, polysilicon materials are commonly used to fabricate gate electrodes for metal-oxide semiconductor transistors. The gate pattern fabricated by polysilicon materials is also used to form self-aligned source/drain regions as polysilicon readily blocks ions from entering the channel region.
- Gate electrodes fabricated by polysilicon also causes a depletion effect.
- the optimum doping concentration for polysilicon is between about 2 ⁇ 20 20 /cm 3 and 3 ⁇ 10 20 /cm 3 .
- the limited doping concentration of polysilicon gates often results in a depletion region at the interface between the gate and the gate dielectric layer. This depletion region not only thickens the gate dielectric layer, but also lowers the capacitance of the gate, and ultimately reduces the driving ability of the device.
- double work function metal gates are used to replace conventional polysilicon to fabricate gate electrodes for MOS transistors.
- the method for fabricating metal gate transistor includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a plurality of dummy gates on the substrate and within the first transistor region and the second transistor region; forming a source/drain region at two sides of each dummy gate; forming a dielectric layer to cover the dummy gates; removing the dummy gates to form a plurality of openings in the dielectric layer of the first transistor region and the second transistor region; forming a high-k dielectric layer to cover the dielectric layer and surface of each opening; depositing a first cap layer on the high-k dielectric layer; removing the first cap layer disposed in the second transistor region; forming a metal layer on the first cap layer of the first transistor region and the high-k dielectric layer of the second transistor region; forming a conductive layer to fill the openings of the first transistor region and the second transistor region.
- the metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate.
- the metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.
- FIGS. 1-8 illustrate a method for fabricating a metal gate transistor according to a preferred embodiment of the present invention.
- FIG. 9 illustrates a metal gate transistor according to an embodiment of the present invention.
- FIGS. 1-8 illustrate a method for fabricating a metal gate transistor according to a preferred embodiment of the present invention.
- a substrate 12 such as a silicon substrate or a silicon-on-insulator substrate is provided.
- At least a NMOS transistor region 14 and a PMOS transistor region 16 are defined in the substrate 12 and a plurality of shallow trench isolations 18 is formed to isolate the transistor regions 14 and 16 .
- a gate insulating layer 20 composed of dielectric material such as oxides or nitrides is then formed on the surface of the substrate 12 .
- the gate insulating layer 20 could also be composed of pad oxide or a high-k dielectric layer composed of HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, or HfZrO, and the cap layer 56 comprises LaO, MgO, Dy 2 O 3 , or other lanthanide oxides.
- a polysilicon layer 22 serving as a dummy gate layer is deposited on the gate insulating layer 20 , and a hard mask 24 is disposed on the polysilicon layer 22 , in which the polysilicon layer 22 includes a depth of approximately 1000 angstroms.
- the hard mask 24 is composed of silicon oxide, silicon nitride, or silicon oxynitride
- the polysilicon layer 22 is composed of undoped polysilicon or polysilicon having n+dopants therein, which are all within the scope of the present invention.
- a patterned photoresist (not shown) is formed on the polysilicon layer 22 , and a pattern transfer process is performed by using the patterned photoresist as mask to remove a portion of the hard mask 24 , the polysilicon layer 22 and the gate insulating layer 20 through one or a plurality of etching processes.
- a plurality of dummy gates such as the polysilicon gates 26 shown in this embodiment is formed in the NMOS transistor region 14 and the PMOS transistor region 16 .
- a light doping process is conducted in the NMOS transistor region 14 and the PMOS transistor region 16 to form a plurality of lightly doped drains.
- a patterned photoresist (not shown) can be disposed on regions outside the NMOS transistor region 14 , and an ion implantation is conducted by using the patterned photoresist as mask to implant n-type dopants into the substrate 12 at two sides of the polysilicon gate 26 of the NMOS transistor region 14 to form a lightly doped drain 28 .
- another patterned photoresist is disposed on regions outside the PMOS transistor region 16 , and another ion implantation is conducted by using this patterned photoresist as mask to implant p-type dopants into the substrate 12 at two sides of the polysilicon gate 26 of the PMOS transistor region 16 for forming a lightly doped drain 30 .
- a first stage of spacer formation is conducted thereafter.
- a silicon oxide layer 32 is formed by oxidizing the sidewall surface of the polysilicon gate 26
- a spacer 34 composed of silicon nitride is formed on the sidewall of the polysilicon gates 26 of the NMOS transistor region 14 and the PMOS transistor region 16 .
- a passivation layer 36 composed of silicon nitride is deposited over the surface of the spacer 34 , and a selective epitaxial growth process is conducted to grow a strained silicon in the substrate 12 of the two transistor regions 14 , 16 .
- a selective epitaxial growth process is conducted to grow a strained silicon in the substrate 12 of the two transistor regions 14 , 16 .
- two recesses could be formed in the substrate 12 at two sides of the polysilicon gate 26 of the PMOS transistor region 16 , and an epitaxial layer 38 composed of silicon germanium is epitaxially grown to substantially fill the two recesses.
- the epitaxial layer 38 preferably provides a compressive strain to the channel region of the PMOS transistor region 16 , thereby increasing the hole mobility of the PMOS transistor.
- a second stage of the spacer formation is performed to form a spacer 40 composed of silicon oxide on the sidewall of the passivation layer 36 of the NMOS transistor region 14 and the PMOS transistor region 16 .
- a heavy doping process is then conducted to form a plurality of source/drain regions in the NMOS transistor region 14 .
- a patterned photoresist (not shown) can be disposed on regions outside the NMOS transistor region 14 , and an ion implantation is conducted by using this patterned photoresist as mask to implant n-type dopants into the substrate 12 at two sides of the spacer 40 of the NMOS transistor region 14 to form a source/drain region 42 .
- a source/drain region 44 for the PMOS transistor region 16 could also be fabricated with a similar manner as the source/drain region 42 of the NMOS transistor region 14 .
- the source/drain region 44 is preferably formed by an in-situ doping performed with the selective epitaxial growth process shown FIG. 4 , in which the undoped selective epitaxial growth is preferably performed before the in-situ doping process.
- a salicide process is performed by first depositing a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, or molybdenum over the surface of the substrate 12 and the spacer 40 , and a rapid thermal annealing process is conducted thereafter to form a silicide 46 at two sides of the spacer 40 . The un-reacted metal layer is removed thereafter.
- a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, or molybdenum
- a silicon nitride layer 48 is deposited on each polysilicon gate 26 , the spacer 40 , and the substrate 12 .
- the silicon nitride layer 48 primarily serving as an etch stop layer in the later planarizing process, preferably includes a depth of approximately 100 angstroms.
- An interlayer dielectric layer 50 composed of oxides is then deposited on the silicon nitride layer 48 of both NMOS transistor region 14 and PMOS transistor region 16 .
- a chemical mechanical polishing process or a dry etching process is performed to remove a portion of the interlayer dielectric layer 50 , the silicon nitride layer 48 , and the hard mask 24 until reaching the surface of the polysilicon gate 26 , such that the top of the polysilicon gate 26 is substantially even to the surface of the interlayer dielectric layer 50 .
- a selective etching process is conducted by using etchant such as ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the polysilicon gate 26 disposed in the NMOS transistor region 14 and the PMOS transistor region 16 without damaging the interlayer dielectric layer 50 .
- etchant such as ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the polysilicon gate 26 disposed in the NMOS transistor region 14 and the PMOS transistor region 16 without damaging the interlayer dielectric layer 50 .
- the etching process preferably removes the polysilicon gate 26 and forms an opening 52 in each transistor region 14 , 16 for exposing the gate insulating layer 20 underneath.
- the gate insulating layer 20 is composed of common dielectric material, the gate insulating layer 20 is preferably removed to expose the substrate 12 underneath, and a pad oxide 68 , a high-k dielectric layer 54 and a cap layer 56 are sequentially deposited over the surface of the interlayer dielectric layer 50 of the two transistor regions 14 , 16 and the sidewall and bottom of the openings 52 .
- the high-k dielectric layer 54 comprises HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, or HfZrO
- the cap layer 56 comprises LaO, MgO, Dy 2 O 3 , or other lanthanide oxides.
- the cap layer 56 is deposited directly on the interlayer dielectric layer 50 of the NMOS transistor region 14 and the PMOS transistor region 16 , as well as the sidewall and bottom of the opening 52 .
- a patterned photoresist 58 is then disposed on the NMOS transistor region 14 , and an etching process is carried out by using the patterned photoresist 58 as a mask to remove the cap layer 56 in the PMOS transistor region 16 .
- a metal layer 60 is deposited on the cap layer 56 of the NMOS transistor region 14 and the high-k dielectric layer 54 of the PMOS transistor region 16 .
- the metal layer 60 is preferably composed of TiN, TaC, Ta, TaSiN, Al, or TiAlN.
- the present invention specifically uses the cap layer 56 to define the work function of the metal layer 60 , thereby forming metals with Quasi Fermi level close to that of the N-type silicon or P-type silicon and increasing the performance of the CMOS transistor.
- a cap layer 56 composed of LaO is deposited before the formation of the metal layer 60 to define the work function of n-type metal.
- a cap layer (not shown) could also be deposited between the high-k dielectric layer 54 and the metal layer 60 of the PMOS transistor region 16 to define the work function of the p-type metal.
- a cap layer composed of Al 2 O 3 , AN, or AlON could be formed on the high-k dielectric layer 54 of the PMOS transistor region 16 , and the metal layer 60 is covered on the newly deposited cap layer thereafter, which are all within the scope of the present invention.
- a conductive layer 62 composed of low resistance material is selectively deposited on the metal layer 60 of the NMOS transistor region 14 and the PMOS transistor region 16 to fill the openings 52 .
- the conductive layer 62 is preferably composed of Al, W, TiAl or CoWP. Another chemical mechanical polishing process is performed thereafter to remove a portion of the conductive layer 62 and the metal layer 60 for forming a CMOS transistor with metal gates 64 and 66 .
- FIG. 8 illustrates a schematic view of a CMOS transistor with metal gates 64 , 66 fabricated by the aforementioned process.
- the CMOS transistor includes a substrate 12 , two metal gates 64 , 66 disposed on the substrate 12 of the NMOS transistor region 14 and the PMOS transistor region 16 , and two source/drain regions 42 , 44 formed in the substrate 12 with respect to two sides of the metal gates 64 , 66 .
- the metal gate 64 of the NMOS transistor region 14 includes a pad oxide 68 disposed on the bottom of the metal gate 64 , a U-shaped high-k dielectric layer 54 disposed on the pad oxide 68 and covering the sidewall of the metal gate 64 , a U-shaped cap layer 56 disposed on the U-shaped high-k dielectric layer 54 , a U-shaped metal layer 60 disposed on the U-shaped cap layer 56 , and a substantially I-shaped conductive layer 62 filling the remaining opening of the metal gate 64 .
- the metal gate 66 disposed in the PMOS transistor region 16 includes a pad oxide 68 disposed on the bottom of the metal gate 66 , a U-shaped high-k dielectric layer 54 disposed on the pad oxide 68 and covering the sidewall of the metal gate 66 , a U-shaped metal layer 60 disposed on the U-shaped high-k dielectric layer 54 , and a substantially I-shaped conductive layer 62 disposed on the U-shaped metal layer 60 to fill the remaining opening of the metal gate 66 .
- no cap layer is disposed in the PMOS transistor region 16 .
- a U-shaped cap layer could also be disposed between the high-k dielectric layer 54 and the U-shaped metal layer 60 of the PMOS transistor region 16 to define the work function of the p-type metal, which is also within the scope of the present invention.
- the cap layer 56 could be deposited directly on the interlayer dielectric layer 50 of the NMOS transistor region 14 and the PMOS transistor region 16 as well as the sidewall and bottom of the opening 52 while the gate insulating layer 20 is composed of high-k dielectric material
- a CMOS transistor shown in FIG. 9 is fabricated.
- the CMOS transistor includes a substrate 12 , two metal gates 64 , 66 disposed on the substrate 12 of the NMOS transistor region 14 and the PMOS transistor region 16 , and two source/drain regions 42 , 44 formed in the substrate 12 with respect to two sides of the metal gates 64 , 66 .
- the metal gate 64 of the NMOS transistor region 14 includes a gate insulating layer 20 disposed on the bottom of the metal gate 64 , a U-shaped cap layer 56 disposed on the gate insulating layer 20 and covering the sidewall of the metal gate 64 , a U-shaped metal layer 60 disposed on the U-shaped cap layer 56 , and a conductive layer 62 filling the remaining opening of the metal gate 64 .
- the metal gate 66 disposed in the PMOS transistor region 16 includes a gate insulating layer 20 disposed on the bottom of the metal gate 66 , a U-shaped metal layer 60 disposed on the gate insulating layer 20 and covering the sidewall of the metal gate 66 , and a conductive layer 62 disposed on the U-shaped metal layer 60 to fill the remaining opening of the metal gate 66 .
- no cap layer is disposed in the PMOS transistor region 16 .
- a U-shaped cap layer could also be disposed between the gate insulating layer 20 and the U-shaped metal layer 60 of the PMOS transistor region 16 to define the work function of the p-type metal, which is also within the scope of the present invention.
Abstract
A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.
Description
- This is a continuation application of U.S. patent application Ser. No. 12/198,128, filed on Aug. 26, 2008, and all benefits of such earlier application are hereby claimed for this new continuation application.
- 1. Field of the Invention
- The invention relates to a method for fabricating a transistor, and more particularly, to a method for fabricating a metal gate transistor.
- 2. Description of the Prior Art
- In the field of semiconductor fabrication, the use of polysilicon material is diverse. Having a strong resistance for heat, polysilicon materials are commonly used to fabricate gate electrodes for metal-oxide semiconductor transistors. The gate pattern fabricated by polysilicon materials is also used to form self-aligned source/drain regions as polysilicon readily blocks ions from entering the channel region.
- However, devices fabricated by polysilicon still have many drawbacks. In contrast to most metal, polysilicon gates are fabricated by semiconductor materials having high resistance, which causes the polysilicon gate to work under a much lower rate than other metal gates. In order to compensate for slightly lowered rate of performance, a significant amount of silicides is applied during the fabrication of polysilicon processes, such that the performance of the device could be increased to an acceptable level.
- Gate electrodes fabricated by polysilicon also causes a depletion effect. In most circumstances, the optimum doping concentration for polysilicon is between about 2×2020/cm3 and 3×1020/cm3. As most gate electrodes have a doping concentration of at least 5×1021/cm3, the limited doping concentration of polysilicon gates often results in a depletion region at the interface between the gate and the gate dielectric layer. This depletion region not only thickens the gate dielectric layer, but also lowers the capacitance of the gate, and ultimately reduces the driving ability of the device. In order to solve this problem, double work function metal gates are used to replace conventional polysilicon to fabricate gate electrodes for MOS transistors.
- However, it is well known in the art that the degree of difficulty for fabricating a well-controlled double work function metal is immense as the process often involves complicated integration between NMOS device and PMOS device. The difficulty increases even more as the thickness and materials used in double work function metal gates requires a much more strict demand. Hence, how to successfully fabricate double work function metal gate transistors with lower cost and improved performance has become an important task in this field.
- It is an objective of the present invention to provide a method for fabricating a metal gate transistor.
- According to a preferred embodiment of the present invention, the method for fabricating metal gate transistor includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a plurality of dummy gates on the substrate and within the first transistor region and the second transistor region; forming a source/drain region at two sides of each dummy gate; forming a dielectric layer to cover the dummy gates; removing the dummy gates to form a plurality of openings in the dielectric layer of the first transistor region and the second transistor region; forming a high-k dielectric layer to cover the dielectric layer and surface of each opening; depositing a first cap layer on the high-k dielectric layer; removing the first cap layer disposed in the second transistor region; forming a metal layer on the first cap layer of the first transistor region and the high-k dielectric layer of the second transistor region; forming a conductive layer to fill the openings of the first transistor region and the second transistor region.
- Another aspect of the present invention provides a metal gate transistor. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-8 illustrate a method for fabricating a metal gate transistor according to a preferred embodiment of the present invention. -
FIG. 9 illustrates a metal gate transistor according to an embodiment of the present invention. - Referring to
FIGS. 1-8 ,FIGS. 1-8 illustrate a method for fabricating a metal gate transistor according to a preferred embodiment of the present invention. As shown inFIG. 1 , asubstrate 12, such as a silicon substrate or a silicon-on-insulator substrate is provided. At least aNMOS transistor region 14 and aPMOS transistor region 16 are defined in thesubstrate 12 and a plurality ofshallow trench isolations 18 is formed to isolate thetransistor regions - A
gate insulating layer 20 composed of dielectric material such as oxides or nitrides is then formed on the surface of thesubstrate 12. Thegate insulating layer 20 could also be composed of pad oxide or a high-k dielectric layer composed of HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, or HfZrO, and thecap layer 56 comprises LaO, MgO, Dy2O3, or other lanthanide oxides. Apolysilicon layer 22 serving as a dummy gate layer is deposited on thegate insulating layer 20, and ahard mask 24 is disposed on thepolysilicon layer 22, in which thepolysilicon layer 22 includes a depth of approximately 1000 angstroms. In this embodiment, thehard mask 24 is composed of silicon oxide, silicon nitride, or silicon oxynitride, and thepolysilicon layer 22 is composed of undoped polysilicon or polysilicon having n+dopants therein, which are all within the scope of the present invention. - As shown in
FIG. 2 , a patterned photoresist (not shown) is formed on thepolysilicon layer 22, and a pattern transfer process is performed by using the patterned photoresist as mask to remove a portion of thehard mask 24, thepolysilicon layer 22 and thegate insulating layer 20 through one or a plurality of etching processes. After stripping the patterned photoresist, a plurality of dummy gates, such as thepolysilicon gates 26 shown in this embodiment is formed in theNMOS transistor region 14 and thePMOS transistor region 16. - As shown in
FIG. 3 , a light doping process is conducted in theNMOS transistor region 14 and thePMOS transistor region 16 to form a plurality of lightly doped drains. For instance, a patterned photoresist (not shown) can be disposed on regions outside theNMOS transistor region 14, and an ion implantation is conducted by using the patterned photoresist as mask to implant n-type dopants into thesubstrate 12 at two sides of thepolysilicon gate 26 of theNMOS transistor region 14 to form a lightly dopeddrain 28. After removing the aforementioned photoresist, another patterned photoresist is disposed on regions outside thePMOS transistor region 16, and another ion implantation is conducted by using this patterned photoresist as mask to implant p-type dopants into thesubstrate 12 at two sides of thepolysilicon gate 26 of thePMOS transistor region 16 for forming a lightly dopeddrain 30. - A first stage of spacer formation is conducted thereafter. For instance, a
silicon oxide layer 32 is formed by oxidizing the sidewall surface of thepolysilicon gate 26, and aspacer 34 composed of silicon nitride is formed on the sidewall of thepolysilicon gates 26 of theNMOS transistor region 14 and thePMOS transistor region 16. - As shown in
FIG. 4 , apassivation layer 36 composed of silicon nitride is deposited over the surface of thespacer 34, and a selective epitaxial growth process is conducted to grow a strained silicon in thesubstrate 12 of the twotransistor regions substrate 12 at two sides of thepolysilicon gate 26 of thePMOS transistor region 16, and anepitaxial layer 38 composed of silicon germanium is epitaxially grown to substantially fill the two recesses. Theepitaxial layer 38 preferably provides a compressive strain to the channel region of thePMOS transistor region 16, thereby increasing the hole mobility of the PMOS transistor. - Next, a second stage of the spacer formation is performed to form a
spacer 40 composed of silicon oxide on the sidewall of thepassivation layer 36 of theNMOS transistor region 14 and thePMOS transistor region 16. - A heavy doping process is then conducted to form a plurality of source/drain regions in the
NMOS transistor region 14. Similar to the aforementioned light doping process, a patterned photoresist (not shown) can be disposed on regions outside theNMOS transistor region 14, and an ion implantation is conducted by using this patterned photoresist as mask to implant n-type dopants into thesubstrate 12 at two sides of thespacer 40 of theNMOS transistor region 14 to form a source/drain region 42. After stripping the patterned photoresist, a source/drain region 44 for thePMOS transistor region 16 could also be fabricated with a similar manner as the source/drain region 42 of theNMOS transistor region 14. For instance, the source/drain region 44 is preferably formed by an in-situ doping performed with the selective epitaxial growth process shownFIG. 4 , in which the undoped selective epitaxial growth is preferably performed before the in-situ doping process. - After the source/
drain regions substrate 12 and thespacer 40, and a rapid thermal annealing process is conducted thereafter to form asilicide 46 at two sides of thespacer 40. The un-reacted metal layer is removed thereafter. - Next, a
silicon nitride layer 48 is deposited on eachpolysilicon gate 26, thespacer 40, and thesubstrate 12. In this embodiment, thesilicon nitride layer 48, primarily serving as an etch stop layer in the later planarizing process, preferably includes a depth of approximately 100 angstroms. An interlayerdielectric layer 50 composed of oxides is then deposited on thesilicon nitride layer 48 of bothNMOS transistor region 14 andPMOS transistor region 16. - As shown in
FIG. 5 , a chemical mechanical polishing process or a dry etching process is performed to remove a portion of the interlayerdielectric layer 50, thesilicon nitride layer 48, and thehard mask 24 until reaching the surface of thepolysilicon gate 26, such that the top of thepolysilicon gate 26 is substantially even to the surface of the interlayerdielectric layer 50. - As shown in
FIG. 6 , a selective etching process is conducted by using etchant such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove thepolysilicon gate 26 disposed in theNMOS transistor region 14 and thePMOS transistor region 16 without damaging the interlayerdielectric layer 50. In this embodiment, the etching process preferably removes thepolysilicon gate 26 and forms anopening 52 in eachtransistor region gate insulating layer 20 underneath. - If the
gate insulating layer 20 is composed of common dielectric material, thegate insulating layer 20 is preferably removed to expose thesubstrate 12 underneath, and apad oxide 68, a high-kdielectric layer 54 and acap layer 56 are sequentially deposited over the surface of the interlayerdielectric layer 50 of the twotransistor regions openings 52. Preferably, the high-k dielectric layer 54 comprises HfSiO, HfSiON, HfO, LaO, LaAlO, ZrO, ZrSiO, or HfZrO, and thecap layer 56 comprises LaO, MgO, Dy2O3, or other lanthanide oxides. - If the
gate insulating layer 20 is composed of high-k dielectric material, thecap layer 56 is deposited directly on theinterlayer dielectric layer 50 of theNMOS transistor region 14 and thePMOS transistor region 16, as well as the sidewall and bottom of theopening 52. - A patterned
photoresist 58 is then disposed on theNMOS transistor region 14, and an etching process is carried out by using the patternedphotoresist 58 as a mask to remove thecap layer 56 in thePMOS transistor region 16. - As shown in
FIG. 7 , after stripping the patternedphotoresist 58, ametal layer 60 is deposited on thecap layer 56 of theNMOS transistor region 14 and the high-k dielectric layer 54 of thePMOS transistor region 16. Themetal layer 60 is preferably composed of TiN, TaC, Ta, TaSiN, Al, or TiAlN. - It should be noted that the present invention specifically uses the
cap layer 56 to define the work function of themetal layer 60, thereby forming metals with Quasi Fermi level close to that of the N-type silicon or P-type silicon and increasing the performance of the CMOS transistor. In the aforementioned embodiment, acap layer 56 composed of LaO is deposited before the formation of themetal layer 60 to define the work function of n-type metal. - In addition to the above process, a cap layer (not shown) could also be deposited between the high-
k dielectric layer 54 and themetal layer 60 of thePMOS transistor region 16 to define the work function of the p-type metal. For instance, after removing thecap layer 56 disposed in thePMOS transistor region 16, a cap layer composed of Al2O3, AN, or AlON could be formed on the high-k dielectric layer 54 of thePMOS transistor region 16, and themetal layer 60 is covered on the newly deposited cap layer thereafter, which are all within the scope of the present invention. - As shown in
FIG. 8 , when theopenings 52 are unfilled to the full, aconductive layer 62 composed of low resistance material is selectively deposited on themetal layer 60 of theNMOS transistor region 14 and thePMOS transistor region 16 to fill theopenings 52. Theconductive layer 62 is preferably composed of Al, W, TiAl or CoWP. Another chemical mechanical polishing process is performed thereafter to remove a portion of theconductive layer 62 and themetal layer 60 for forming a CMOS transistor withmetal gates - Referring to
FIG. 8 again, which illustrates a schematic view of a CMOS transistor withmetal gates substrate 12, twometal gates substrate 12 of theNMOS transistor region 14 and thePMOS transistor region 16, and two source/drain regions substrate 12 with respect to two sides of themetal gates metal gate 64 of theNMOS transistor region 14 includes apad oxide 68 disposed on the bottom of themetal gate 64, a U-shaped high-k dielectric layer 54 disposed on thepad oxide 68 and covering the sidewall of themetal gate 64, aU-shaped cap layer 56 disposed on the U-shaped high-k dielectric layer 54, aU-shaped metal layer 60 disposed on theU-shaped cap layer 56, and a substantially I-shapedconductive layer 62 filling the remaining opening of themetal gate 64. - The
metal gate 66 disposed in thePMOS transistor region 16 on the other hand includes apad oxide 68 disposed on the bottom of themetal gate 66, a U-shaped high-k dielectric layer 54 disposed on thepad oxide 68 and covering the sidewall of themetal gate 66, aU-shaped metal layer 60 disposed on the U-shaped high-k dielectric layer 54, and a substantially I-shapedconductive layer 62 disposed on theU-shaped metal layer 60 to fill the remaining opening of themetal gate 66. According to the embodiment illustrated inFIG. 8 , no cap layer is disposed in thePMOS transistor region 16. However, as mentioned above, a U-shaped cap layer could also be disposed between the high-k dielectric layer 54 and theU-shaped metal layer 60 of thePMOS transistor region 16 to define the work function of the p-type metal, which is also within the scope of the present invention. - According to an embodiment of the present invention, as the
cap layer 56 could be deposited directly on theinterlayer dielectric layer 50 of theNMOS transistor region 14 and thePMOS transistor region 16 as well as the sidewall and bottom of theopening 52 while thegate insulating layer 20 is composed of high-k dielectric material, a CMOS transistor shown inFIG. 9 is fabricated. As shown inFIG. 9 , the CMOS transistor includes asubstrate 12, twometal gates substrate 12 of theNMOS transistor region 14 and thePMOS transistor region 16, and two source/drain regions substrate 12 with respect to two sides of themetal gates metal gate 64 of theNMOS transistor region 14 includes agate insulating layer 20 disposed on the bottom of themetal gate 64, aU-shaped cap layer 56 disposed on thegate insulating layer 20 and covering the sidewall of themetal gate 64, aU-shaped metal layer 60 disposed on theU-shaped cap layer 56, and aconductive layer 62 filling the remaining opening of themetal gate 64. - The
metal gate 66 disposed in thePMOS transistor region 16 on the other hand includes agate insulating layer 20 disposed on the bottom of themetal gate 66, aU-shaped metal layer 60 disposed on thegate insulating layer 20 and covering the sidewall of themetal gate 66, and aconductive layer 62 disposed on theU-shaped metal layer 60 to fill the remaining opening of themetal gate 66. As shown inFIG. 9 , no cap layer is disposed in thePMOS transistor region 16. However, as mentioned above, a U-shaped cap layer could also be disposed between thegate insulating layer 20 and theU-shaped metal layer 60 of thePMOS transistor region 16 to define the work function of the p-type metal, which is also within the scope of the present invention. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (14)
1. A metal gate transistor, comprising:
a substrate;
a metal gate disposed on the substrate, comprising:
a high-k dielectric layer;
a U-shaped cap layer disposed over a surface of the high-k dielectric layer for adjusting the work function of the metal gate transistor, wherein the U-shaped cap layer comprises LaO, Dy2O3, or other lanthanide oxides;
a U-shaped metal layer disposed over the U-shaped cap layer; and
a source/drain region disposed in the substrate with respect to two sides of the metal gate.
2. The metal gate transistor of claim 1 , wherein the metal gate transistor is a NMOS transistor.
3. The metal gate transistor of claim 1 , wherein the U-shaped metal layer comprises TiN, TaC, Ta, TaSiN, Al, or TiAlN.
4. The metal gate transistor of claim 1 , wherein the high-k dielectric layer is U-shaped.
5. The metal gate transistor of claim 1 , further comprising a conductive layer disposed on the U-shaped metal layer.
6. The metal gate transistor of claim 5 , wherein the conductive layer comprises Al, W, TiAl or CoWP.
7. A metal gate transistor, comprising:
a substrate;
a first metal gate transistor having a first metal gate disposed on the substrate, wherein the first metal gate comprises:
a first U-shaped high-k dielectric layer;
a U-shaped cap layer; and
a first U-shaped metal layer;
a first source/drain region disposed in the substrate adjacent to two sides of the first metal gate;
a second metal gate transistor having a second metal gate disposed on the substrate, wherein the second metal gate comprises:
a second U-shaped high-k dielectric layer; and
a second U-shaped metal layer; and
a second source/drain region disposed in the substrate adjacent to two sides of the second metal gate.
8. The metal gate transistor of claim 7 , wherein the first metal gate transistor is a NMOS transistor.
9. The metal gate transistor of claim 7 , wherein the second metal gate transistor is a PMOS transistor.
10. The metal gate transistor of claim 7 , wherein the U-shaped cap layer comprises LaO, MgO, Dy2O3, or other lanthanide oxides.
11. The metal gate transistor of claim 7 , wherein the first U-shaped high-k dielectric layer and the second U-shaped high-k dielectric layer comprise HfSiO, HfSiON, HfO, LaO, LaA10, ZrO, ZrSiO, or HfZrO.
12. The metal gate transistor of claim 7 , wherein the first U-shaped metal layer and the second U-shaped metal layer comprise TiN, TaC, Ta, TaSiN, Al, or TiAlN.
13. The metal gate transistor of claim 7 , further comprising a conductive layer disposed on the first U-shaped metal layer and the second U-shaped metal layer.
14. The metal gate transistor of claim 13 , wherein the conductive layer comprises Al, W, TiAl or CoWP.
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