US20110024041A1 - Method of manufacturing semiconductor device, and etching apparatus - Google Patents

Method of manufacturing semiconductor device, and etching apparatus Download PDF

Info

Publication number
US20110024041A1
US20110024041A1 US12/923,711 US92371110A US2011024041A1 US 20110024041 A1 US20110024041 A1 US 20110024041A1 US 92371110 A US92371110 A US 92371110A US 2011024041 A1 US2011024041 A1 US 2011024041A1
Authority
US
United States
Prior art keywords
etching
shadow ring
hard mask
substrate
etching apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/923,711
Inventor
Masahiro Komuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to US12/923,711 priority Critical patent/US20110024041A1/en
Publication of US20110024041A1 publication Critical patent/US20110024041A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/944Shadow

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device making use of a shadow ring, and an etching apparatus.
  • a shadow ring is occasionally used for an etching apparatus or a film-making apparatus used for manufacture of semiconductor devices.
  • the shadow ring is a ring-form component disposed so as to cover a circumferential portion of a substrate, aimed at preventing a certain width of region ranging from the edge of the substrate from being etched or deposited with any film (see Japanese Laid-Open Patent Publication Nos. 2002-294441 and 2006-118004, for example). Without the shadow ring, the process would have an increased number of steps in the manufacturing, including a step of grinding the circumferential portion of the film so as to remove the deposited film.
  • One step of using the shadow ring is known as a step of forming relatively deep trenches or holes to a layer to be etched.
  • This step is such as forming a hard mask, typically composed of a silicon oxide film, on the layer to be etched, and then etching the layer using the hard mask as a mask.
  • the shadow ring is used to protect the circumferential portion of the layer to be etched during etching.
  • Japanese Laid-Open Patent Publication No. 2002-334879 describes a technique of forming a protective film on an insulating film formed on a wafer, specifically in the bevel region thereof in order to protect the insulating film in the bevel region.
  • the hard mask is removed by etching, after the trenches or holes are formed.
  • the circumferential portion of the layer to be etched is slightly etched. For this reason, the layer to be etched may be roughened in the circumferential portion, if the etching for removing the hard mask takes a long time.
  • a method of manufacturing a semiconductor device which includes:
  • the shadow ring has an irregular pattern on the inner circumferential edge thereof.
  • the hard mask is slightly etched in a region not covered by the shadow ring. Since the shadow ring has the irregular pattern on the inner circumferential edge thereof, the irregular pattern of the shadow ring is transferred to the etched region of the hard mask.
  • the hard mask has, therefore, an increased surface area, and may be etched within a short time in the step of removal. Accordingly, the circumferential portion of the layer to be etched may be suppressed from being roughened.
  • an etching apparatus which includes:
  • a shadow ring disposed in the process chamber and placed above the stage, so as to cover the circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner
  • the shadow ring has an irregular pattern on the inner circumferential edge thereof.
  • the circumferential portion of the layer to be etched may be suppressed from being roughened.
  • FIG. 1 is a drawing illustrating a configuration of an etching apparatus used for a method of manufacturing a semiconductor device in one embodiment
  • FIG. 2 is a plan view illustrating an example of a shadow ring
  • FIGS. 3A to 4B are sectional views sequentially illustrating steps of forming recesses or holes in the surficial portion of the substrate as the layer to be etched;
  • FIG. 5 is a schematic perspective view explaining an operation of the shadow ring illustrated in FIG. 4A ;
  • FIGS. 6A to 6E are plan views illustrating other examples of the shadow ring.
  • FIG. 1 is a drawing illustrating a configuration of an etching apparatus used for the method of manufacturing a semiconductor device according to this embodiment.
  • the etching apparatus has a process chamber 10 , an electrode 20 , a stage 30 , and a shadow ring 40 .
  • the process chamber 10 allows an etching gas to be introduced therein.
  • the electrode 20 is disposed in the process chamber 10 , and is used for generating plasma by ionizing the etching gas.
  • the stage 30 is disposed in the process chamber 10 , onto which a substrate 50 is disposed.
  • the shadow ring 40 is disposed in the process chamber 10 and placed above the stage 30 , so as to cover a circumferential portion and an inner region adjacent thereto of the substrate 50 in a non-contact manner.
  • the shadow ring 40 has an irregular pattern on the inner circumferential edge thereof.
  • the substrate 50 has a layer to be etched.
  • the layer to be etched may be a surficial portion of the substrate 50 , or may be a film formed over the substrate 50 , or may be a semiconductor layer of an SOI substrate.
  • a hard mask having an opening pattern is formed over the layer to be etched.
  • the hard mask herein is not formed in the circumferential portion of the layer to be etched. Dry etching is proceeded while covering a region of the hard mask adjacent to the circumferential portion, and the circumferential portion of the layer to be etched, with a shadow ring in a non-contact manner.
  • the trenches or holes are formed in the layer to be etched conforming to the opening pattern, wherein also a portion of the hard mask not covered with the shadow ring 40 is partially removed.
  • the hard mask is then removed by etching.
  • the shadow ring 40 has an irregular pattern on the inner circumferential edge thereof.
  • the irregular pattern of the shadow ring 40 is therefore transferred to the hard mask positioned below the shadow ring 40 .
  • the hard mask has, therefore, an increased area to be brought into contact with an etching solution or etching gas, and may be etched within a short time in the step of removal. Accordingly, the circumferential portion of the layer to be etched may be suppressed from being roughened. The process will be detailed below.
  • FIG. 2 is a plan view illustrating an example of the shadow ring 40 .
  • the shadow ring 40 has a plurality of recesses 42 at regular intervals on the inner circumferential surface thereof.
  • the plan geometry of each recess 42 is rectangle or square.
  • the width of each recess 42 is smaller than the distance between the adjacent recesses 42 .
  • the shadow ring 40 is typically made of alumina.
  • FIGS. 3A to 4B are sectional views sequentially showing steps of forming the recesses or holes in the surficial portion of the substrate 50 which serves as the layer to be etched.
  • FIG. 5 is a schematic perspective view explaining an operation of the shadow ring 40 illustrated in FIG. 4A .
  • the substrate 50 is typically composed of a semiconductor wafer such as a Si wafer.
  • a hard mask 60 is formed over the substrate 50 .
  • the hard mask 60 is typically a silicon oxide film, silicon nitride film, silicon oxide nitrogen, silicon nitrogen oxide, or a stacked film of at least two of these films, having an opening pattern 62 .
  • a portion of the hard mask 60 positioned on the circumferential portion 52 of the substrate 50 is removed, typically when the opening pattern 62 is formed in the hard mask 60 .
  • the thickness of the hard mask 60 is typically 0.3 ⁇ m or larger and 5 ⁇ m or smaller.
  • an etching protection film 70 is formed over the circumferential portion 52 of the substrate 50 .
  • the etching protection film 70 is typically composed of the same material with the hard mask 60 .
  • the etching protection film 70 is thinner than the hard mask 60 , and has a thickness of 10 nm or larger and 200 nm or smaller, for example. Since the etching protection film 70 is formed by vapor-phase deposition (CVD, for example), so that the film is formed also on the hard mask 60 and in the opening pattern 62 .
  • the hard mask 60 and the etching protection film 70 are formed in a process chamber different from the process chamber 10 .
  • the substrate 50 is placed in the process chamber 10 illustrated in FIG. 1 , and the shadow ring 40 is positioned over the circumferential portion 52 of the substrate 50 and the portion of the hard mask 60 adjacent to the circumferential portion 52 , in a non-contact manner.
  • an inert gas Ar gas, for example
  • sputtering is carried out using the inert gas.
  • an etching gas is introduced into the process chamber 10 , and the substrate 50 is etched using the etching gas.
  • trenches or holes 54 are formed in the portion of the substrate positioned in the opening pattern 60 .
  • the trenches or holes 54 are typically trenches to be filled with a device isolation film, or holes to be filled with through-electrode which extend vertically through the substrate 50 , or holes for forming trench capacitors.
  • the etching gas may be less likely to reach the circumferential portion 52 .
  • the circumferential portion 52 is covered also with the etching protection film 70 . Accordingly, the circumferential portion 52 of the substrate 50 may be suppressed from being roughened in this step of etching.
  • the portion of the hard mask 60 not covered with the shadow ring 40 is etched to produce a recess 64 .
  • An outer peripheral portion 65 of the hard mask 60 will consequently be thickened as compared with the other portion.
  • the shadow ring 40 has the recesses 42 on the inner circumference edge thereof.
  • the outer circumference of the recess 64 consequently has an irregularity transferred thereto, conforming to the recesses 42 .
  • the surface area of the hard mask 60 increases by contribution of the area of bottom faces 66 and the area of side faces 68 formed corresponding to the side faces of the recess 42 .
  • the substrate 50 is taken out from the process chamber 10 .
  • the hard mask 60 and the etching protection film 70 are then removed typically by wet etching. If the hard mask 60 and the etching protection film 70 are composed of the same material, only a single step of etching will suffice.
  • the outer peripheral portion 65 of the hard mask 60 remained to have no recess 64 formed therein, is therefore thicker as compared with the other portion. For this reason, the length of time necessary for this step may be governed by the length of time necessary for etching of the outer peripheral portion 65 of the hard mask 60 .
  • the surface area of the hard mask 60 increases by contribution of the area of bottom faces 66 and the area of side faces 68 formed corresponding to the side faces of the recess 42 , as compared with a hard mask possibly obtained by using the shadow ring 40 having no recesses 42 in the inner circumference thereof. Accordingly, the etchrate of the outer peripheral portion 65 of the hard mask 60 increases, and thereby the length of time necessary for the etching may decrease. By virtue of the etching, the circumferential portion 52 of the substrate 50 may consequently be suppressed from being roughened.
  • the surface area of the hard mask 60 may be increased by contribution of recesses 42 formed in the inner circumference of the shadow ring 40 , in the process of etching for forming the trenches or holes 54 in the substrate 50 .
  • the length of time necessary for removing the hard mask 60 may be reduced, and thereby the circumferential portion 52 of the substrate 50 may be suppressed from being roughened.
  • the circumferential portion 52 of the substrate 50 may be suppressed from being roughened, in the process of etching for forming the trenches or holes 54 in the substrate 50 .
  • the circumferential portion 52 is covered with the etching protection film 70 in this embodiment, the circumferential portion 52 may further effectively be suppressed from being roughened, both in the etching for forming the trenches or holes 54 , and in the etching for removing the hard mask 60 . Since the etching protection film 70 is thinner than the hard mask 60 , the etching protection film 70 and the hard mask 60 may be removed together in the same process of etching, if they are composed of the same material.
  • the etching protection film 70 is formed also in the opening pattern 62 , the portion of the etching protection film 70 in the opening pattern 62 is removed before the trenches or holes 54 are formed. Therefore, a process for forming the trenches or holes 54 may be prevented from being inhibited by the etching protection film 70 .
  • the irregular pattern formed in the inner circumference of the shadow ring 40 is not limited to that illustrated in FIG. 2 .
  • the number of recesses 42 may be increased.
  • the etchrate of the outer peripheral portion 65 of the hard mask 60 increases, since the number of the bottom faces 68 and the side faces 68 increases.
  • the projections between every adjacent recesses 42 may be rounded. In this case, the projections between every adjacent recesses 42 become less likely to be etched, and thereby the shadow ring 40 may be elongated in the service life thereof.
  • each recess 42 may have a triangle profile. Also in these cases, the distance between every adjacent recesses 42 may arbitrarily be set. The projections between every adjacent recesses 42 may have triangle, square, or rounded profile. Still alternatively, as illustrated in FIG. 6E , the irregularity in the inner circumference edge of the shadow ring 40 may have a wavy profile.
  • the etching protection film 70 may not be formed in the steps illustrated in FIGS. 3A to 4B .

Abstract

An etching apparatus includes a process chamber into which an etching gas is introduced, an electrode for generating plasma disposed in the process chamber, a stage disposed in the process chamber, on which a substrate is placed, and a shadow ring disposed in the process chamber and placed above the stage, so as to cover the circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner. The shadow ring has an irregular pattern on the inner circumferential edge thereof.

Description

  • This application is based on Japanese patent application No. 2008-125051 the content of which is incorporated hereinto by reference.
  • The present application is a Divisional application of U.S. patent application Ser. No. 12/385,845, filed on Apr. 21, 2009.
  • BACKGROUND
  • 1. Technical Field
  • The present invention relates to a method of manufacturing a semiconductor device making use of a shadow ring, and an etching apparatus.
  • 2. Related Art
  • A shadow ring is occasionally used for an etching apparatus or a film-making apparatus used for manufacture of semiconductor devices. The shadow ring is a ring-form component disposed so as to cover a circumferential portion of a substrate, aimed at preventing a certain width of region ranging from the edge of the substrate from being etched or deposited with any film (see Japanese Laid-Open Patent Publication Nos. 2002-294441 and 2006-118004, for example). Without the shadow ring, the process would have an increased number of steps in the manufacturing, including a step of grinding the circumferential portion of the film so as to remove the deposited film.
  • One step of using the shadow ring is known as a step of forming relatively deep trenches or holes to a layer to be etched. This step is such as forming a hard mask, typically composed of a silicon oxide film, on the layer to be etched, and then etching the layer using the hard mask as a mask. In this step, there is no hard mask formed in the circumferential portion of the layer to be etched, for the purpose of preventing generation of foreign matters from the hard mask in the process of handling. The shadow ring is used to protect the circumferential portion of the layer to be etched during etching.
  • On the other hand, Japanese Laid-Open Patent Publication No. 2002-334879 describes a technique of forming a protective film on an insulating film formed on a wafer, specifically in the bevel region thereof in order to protect the insulating film in the bevel region.
  • The hard mask is removed by etching, after the trenches or holes are formed. However, in this process, also the circumferential portion of the layer to be etched is slightly etched. For this reason, the layer to be etched may be roughened in the circumferential portion, if the etching for removing the hard mask takes a long time.
  • SUMMARY
  • According to the present invention, there is provided a method of manufacturing a semiconductor device which includes:
  • forming a hard mask having an opening pattern, on a layer to be etched over a region excluding an outer circumferential portion;
  • forming trenches or holes in the layer to be etched conforming to the opening pattern by dry etching, while covering a region of the hard mask adjacent to the circumferential portion, and the circumferential portion, with a shadow ring in a non-contact manner; and
  • removing the hard mask by etching,
  • wherein the shadow ring has an irregular pattern on the inner circumferential edge thereof.
  • In the step of forming the trenches or holes in the layer to be etched, also the hard mask is slightly etched in a region not covered by the shadow ring. Since the shadow ring has the irregular pattern on the inner circumferential edge thereof, the irregular pattern of the shadow ring is transferred to the etched region of the hard mask. The hard mask has, therefore, an increased surface area, and may be etched within a short time in the step of removal. Accordingly, the circumferential portion of the layer to be etched may be suppressed from being roughened.
  • According to the present invention, there is provided also an etching apparatus which includes:
  • a process chamber into which an etching gas is introduced;
  • an electrode for generating plasma disposed in the process chamber;
  • a stage disposed in the process chamber, on which a substrate is placed; and
  • a shadow ring disposed in the process chamber and placed above the stage, so as to cover the circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner,
  • wherein the shadow ring has an irregular pattern on the inner circumferential edge thereof.
  • According to the present invention, the circumferential portion of the layer to be etched may be suppressed from being roughened.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a drawing illustrating a configuration of an etching apparatus used for a method of manufacturing a semiconductor device in one embodiment;
  • FIG. 2 is a plan view illustrating an example of a shadow ring;
  • FIGS. 3A to 4B are sectional views sequentially illustrating steps of forming recesses or holes in the surficial portion of the substrate as the layer to be etched;
  • FIG. 5 is a schematic perspective view explaining an operation of the shadow ring illustrated in FIG. 4A; and
  • FIGS. 6A to 6E are plan views illustrating other examples of the shadow ring.
  • DETAILED DESCRIPTION
  • The invention will now be described herein with reference to an illustrative embodiment. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiment illustrated for explanatory purposes.
  • Embodiment of the present invention will be explained below. Note that any similar constituents will be given with similar reference numerals or symbols in all drawings, so that explanations therefor will not be repeated.
  • FIG. 1 is a drawing illustrating a configuration of an etching apparatus used for the method of manufacturing a semiconductor device according to this embodiment. The etching apparatus has a process chamber 10, an electrode 20, a stage 30, and a shadow ring 40. The process chamber 10 allows an etching gas to be introduced therein. The electrode 20 is disposed in the process chamber 10, and is used for generating plasma by ionizing the etching gas. The stage 30 is disposed in the process chamber 10, onto which a substrate 50 is disposed. The shadow ring 40 is disposed in the process chamber 10 and placed above the stage 30, so as to cover a circumferential portion and an inner region adjacent thereto of the substrate 50 in a non-contact manner. The shadow ring 40 has an irregular pattern on the inner circumferential edge thereof.
  • The substrate 50 has a layer to be etched. The layer to be etched may be a surficial portion of the substrate 50, or may be a film formed over the substrate 50, or may be a semiconductor layer of an SOI substrate. When the layer to be etched is etched, a hard mask having an opening pattern is formed over the layer to be etched. The hard mask herein is not formed in the circumferential portion of the layer to be etched. Dry etching is proceeded while covering a region of the hard mask adjacent to the circumferential portion, and the circumferential portion of the layer to be etched, with a shadow ring in a non-contact manner. By this step, the trenches or holes are formed in the layer to be etched conforming to the opening pattern, wherein also a portion of the hard mask not covered with the shadow ring 40 is partially removed. The hard mask is then removed by etching.
  • As described in the above, the shadow ring 40 has an irregular pattern on the inner circumferential edge thereof. The irregular pattern of the shadow ring 40 is therefore transferred to the hard mask positioned below the shadow ring 40. The hard mask has, therefore, an increased area to be brought into contact with an etching solution or etching gas, and may be etched within a short time in the step of removal. Accordingly, the circumferential portion of the layer to be etched may be suppressed from being roughened. The process will be detailed below.
  • FIG. 2 is a plan view illustrating an example of the shadow ring 40. In the example illustrated in the drawing, the shadow ring 40 has a plurality of recesses 42 at regular intervals on the inner circumferential surface thereof. The plan geometry of each recess 42 is rectangle or square. In the example illustrated in the drawing, the width of each recess 42 is smaller than the distance between the adjacent recesses 42. The shadow ring 40 is typically made of alumina.
  • FIGS. 3A to 4B are sectional views sequentially showing steps of forming the recesses or holes in the surficial portion of the substrate 50 which serves as the layer to be etched. FIG. 5 is a schematic perspective view explaining an operation of the shadow ring 40 illustrated in FIG. 4A. The substrate 50 is typically composed of a semiconductor wafer such as a Si wafer.
  • First, as illustrated in FIG. 3A, a hard mask 60 is formed over the substrate 50. The hard mask 60 is typically a silicon oxide film, silicon nitride film, silicon oxide nitrogen, silicon nitrogen oxide, or a stacked film of at least two of these films, having an opening pattern 62. A portion of the hard mask 60 positioned on the circumferential portion 52 of the substrate 50 is removed, typically when the opening pattern 62 is formed in the hard mask 60. The thickness of the hard mask 60 is typically 0.3 μm or larger and 5 μm or smaller.
  • Next, an etching protection film 70 is formed over the circumferential portion 52 of the substrate 50. The etching protection film 70 is typically composed of the same material with the hard mask 60. The etching protection film 70 is thinner than the hard mask 60, and has a thickness of 10 nm or larger and 200 nm or smaller, for example. Since the etching protection film 70 is formed by vapor-phase deposition (CVD, for example), so that the film is formed also on the hard mask 60 and in the opening pattern 62.
  • The hard mask 60 and the etching protection film 70 are formed in a process chamber different from the process chamber 10.
  • Next, as illustrated in FIG. 3B, the substrate 50 is placed in the process chamber 10 illustrated in FIG. 1, and the shadow ring 40 is positioned over the circumferential portion 52 of the substrate 50 and the portion of the hard mask 60 adjacent to the circumferential portion 52, in a non-contact manner. Next, an inert gas (Ar gas, for example) is introduced into the process chamber 10, and sputtering is carried out using the inert gas. By this process, a portion of the etching protection film 70 not covered with the shadow ring 40 (including portions of the etching protection film 70 formed in the opening pattern 62), and a native oxide film positioned on the surficial portion of the substrate 50 in the opening pattern 62 are removed. This step may be proceeded also by etching, typically dry etching.
  • Next, as illustrated in FIG. 4A, an etching gas is introduced into the process chamber 10, and the substrate 50 is etched using the etching gas. By this process, trenches or holes 54 are formed in the portion of the substrate positioned in the opening pattern 60. The trenches or holes 54 are typically trenches to be filled with a device isolation film, or holes to be filled with through-electrode which extend vertically through the substrate 50, or holes for forming trench capacitors.
  • Since the circumferential portion 52 of the substrate 50 in this step of etching is covered with the shadow ring 40, the etching gas may be less likely to reach the circumferential portion 52. The circumferential portion 52 is covered also with the etching protection film 70. Accordingly, the circumferential portion 52 of the substrate 50 may be suppressed from being roughened in this step of etching.
  • In this step of etching, the portion of the hard mask 60 not covered with the shadow ring 40 is etched to produce a recess 64. An outer peripheral portion 65 of the hard mask 60 will consequently be thickened as compared with the other portion.
  • As illustrated in FIG. 2 and FIG. 5, the shadow ring 40 has the recesses 42 on the inner circumference edge thereof. As illustrated in FIG. 5, the outer circumference of the recess 64 consequently has an irregularity transferred thereto, conforming to the recesses 42. As a consequence, the surface area of the hard mask 60 increases by contribution of the area of bottom faces 66 and the area of side faces 68 formed corresponding to the side faces of the recess 42.
  • Thereafter, as illustrated in FIG. 4B, the substrate 50 is taken out from the process chamber 10. The hard mask 60 and the etching protection film 70 are then removed typically by wet etching. If the hard mask 60 and the etching protection film 70 are composed of the same material, only a single step of etching will suffice. The outer peripheral portion 65 of the hard mask 60, remained to have no recess 64 formed therein, is therefore thicker as compared with the other portion. For this reason, the length of time necessary for this step may be governed by the length of time necessary for etching of the outer peripheral portion 65 of the hard mask 60.
  • In this embodiment, as explained referring to FIG. 5, the surface area of the hard mask 60 increases by contribution of the area of bottom faces 66 and the area of side faces 68 formed corresponding to the side faces of the recess 42, as compared with a hard mask possibly obtained by using the shadow ring 40 having no recesses 42 in the inner circumference thereof. Accordingly, the etchrate of the outer peripheral portion 65 of the hard mask 60 increases, and thereby the length of time necessary for the etching may decrease. By virtue of the etching, the circumferential portion 52 of the substrate 50 may consequently be suppressed from being roughened.
  • As has been described in the above, according to this embodiment, the surface area of the hard mask 60 may be increased by contribution of recesses 42 formed in the inner circumference of the shadow ring 40, in the process of etching for forming the trenches or holes 54 in the substrate 50. As a consequence, the length of time necessary for removing the hard mask 60 may be reduced, and thereby the circumferential portion 52 of the substrate 50 may be suppressed from being roughened.
  • Also since the shadow ring 40 is used, the circumferential portion 52 of the substrate 50 may be suppressed from being roughened, in the process of etching for forming the trenches or holes 54 in the substrate 50.
  • Since the circumferential portion 52 is covered with the etching protection film 70 in this embodiment, the circumferential portion 52 may further effectively be suppressed from being roughened, both in the etching for forming the trenches or holes 54, and in the etching for removing the hard mask 60. Since the etching protection film 70 is thinner than the hard mask 60, the etching protection film 70 and the hard mask 60 may be removed together in the same process of etching, if they are composed of the same material.
  • Although the etching protection film 70 is formed also in the opening pattern 62, the portion of the etching protection film 70 in the opening pattern 62 is removed before the trenches or holes 54 are formed. Therefore, a process for forming the trenches or holes 54 may be prevented from being inhibited by the etching protection film 70.
  • The irregular pattern formed in the inner circumference of the shadow ring 40 is not limited to that illustrated in FIG. 2. For example, as illustrated in FIG. 6A, the number of recesses 42 may be increased. In this case, the etchrate of the outer peripheral portion 65 of the hard mask 60 increases, since the number of the bottom faces 68 and the side faces 68 increases. Alternatively, as illustrated in FIG. 6B, the projections between every adjacent recesses 42 may be rounded. In this case, the projections between every adjacent recesses 42 become less likely to be etched, and thereby the shadow ring 40 may be elongated in the service life thereof.
  • Alternatively, as illustrated in FIGS. 6C and 6D, each recess 42 may have a triangle profile. Also in these cases, the distance between every adjacent recesses 42 may arbitrarily be set. The projections between every adjacent recesses 42 may have triangle, square, or rounded profile. Still alternatively, as illustrated in FIG. 6E, the irregularity in the inner circumference edge of the shadow ring 40 may have a wavy profile.
  • Alternatively, the etching protection film 70 may not be formed in the steps illustrated in FIGS. 3A to 4B.
  • The embodiments of the present invention have been described referring to the attached drawings. Note that these embodiments are only for exemplary purposes, while allowing adoption of any configurations other than those described in the above.
  • It is apparent that the present invention is not limited to the above embodiment, that may be modified and changed without departing from the scope and spirit of the invention.

Claims (8)

1. An etching apparatus comprising:
a process chamber into which an etching gas is introduced;
an electrode for generating plasma disposed in said process chamber;
a stage disposed in said process chamber, on which a substrate is placed; and
a shadow ring disposed in said process chamber and placed above said stage, so as to cover the circumferential portion and an inner region adjacent thereto of said substrate in a non-contact manner,
wherein said shadow ring has an irregular pattern on the inner circumferential edge thereof.
2. The etching apparatus according to claim 1,
wherein the inner circumferential surface of said shadow ring has a plurality of recesses at regular intervals.
3. The etching apparatus according to claim 2,
wherein said recesses are rectangular-shaped.
4. The etching apparatus according to claim 2,
wherein said recesses are square-shaped.
5. The etching apparatus according to claim 2,
wherein said recesses are triangular-shaped.
6. The etching apparatus according to claim 2,
wherein said recesses are rounded.
7. The etching apparatus according to claim 2,
wherein a width of a recess of said recesses is smaller than a distance between adjacent ones of said recesses.
8. The etching apparatus according to claim 1,
wherein said shadow ring comprises alumina.
US12/923,711 2008-05-12 2010-10-05 Method of manufacturing semiconductor device, and etching apparatus Abandoned US20110024041A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/923,711 US20110024041A1 (en) 2008-05-12 2010-10-05 Method of manufacturing semiconductor device, and etching apparatus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008125051A JP2009277720A (en) 2008-05-12 2008-05-12 Method of manufacturing semiconductor device and etching device
JP2008-125051 2008-05-12
US12/385,845 US7833909B2 (en) 2008-05-12 2009-04-21 Method of manufacturing semiconductor device, and etching apparatus
US12/923,711 US20110024041A1 (en) 2008-05-12 2010-10-05 Method of manufacturing semiconductor device, and etching apparatus

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/385,845 Division US7833909B2 (en) 2008-05-12 2009-04-21 Method of manufacturing semiconductor device, and etching apparatus

Publications (1)

Publication Number Publication Date
US20110024041A1 true US20110024041A1 (en) 2011-02-03

Family

ID=41364466

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/385,845 Active US7833909B2 (en) 2008-05-12 2009-04-21 Method of manufacturing semiconductor device, and etching apparatus
US12/923,711 Abandoned US20110024041A1 (en) 2008-05-12 2010-10-05 Method of manufacturing semiconductor device, and etching apparatus

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/385,845 Active US7833909B2 (en) 2008-05-12 2009-04-21 Method of manufacturing semiconductor device, and etching apparatus

Country Status (3)

Country Link
US (2) US7833909B2 (en)
JP (1) JP2009277720A (en)
CN (1) CN101582376B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021252758A1 (en) * 2020-06-11 2021-12-16 Lam Research Corporation Flat bottom shadow ring

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8536025B2 (en) 2011-12-12 2013-09-17 International Business Machines Corporation Resized wafer with a negative photoresist ring and design structures thereof
JP2014204062A (en) * 2013-04-09 2014-10-27 サムコ株式会社 Plasma etching method
CN103866260B (en) * 2014-02-24 2017-01-25 北京京东方光电科技有限公司 Coating method, coating device and coating generation system
KR102300039B1 (en) * 2014-08-04 2021-09-10 삼성디스플레이 주식회사 Apparatus for manufacturing display apparatus and method of manufacturing display apparatus
US9793129B2 (en) 2015-05-20 2017-10-17 Infineon Technologies Ag Segmented edge protection shield
CN106920728B (en) * 2015-12-25 2019-01-29 中微半导体设备(上海)有限公司 Plasma processing apparatus and its crystal round fringes processing component
CN107689326A (en) * 2016-08-05 2018-02-13 上海新昇半导体科技有限公司 A kind of wafer thining method and device
KR102273970B1 (en) * 2017-12-26 2021-07-07 주식회사 엘지화학 Method for plasma etching process using faraday box
EP3640973A4 (en) * 2018-01-17 2021-03-17 SPP Technologies Co., Ltd. Wide-gap semiconductor substrate, apparatus for manufacturing wide-gap semiconductor substrate, and method for manufacturing wide-gap semiconductor substrate
KR102102308B1 (en) * 2018-03-12 2020-04-20 한국표준과학연구원 Method for Patterning using Protection Layer, and Method for Fabricating Electronic Element using the Same
CN109806728A (en) * 2018-12-26 2019-05-28 上海谷奇核孔膜科技股份有限公司 Prepare the device and method of nucleopore membranes
CN112877655A (en) * 2021-03-08 2021-06-01 泰杋科技股份有限公司 Reaction cavity for sputtering deposition
CN113178378A (en) * 2021-04-29 2021-07-27 北京北方华创微电子装备有限公司 Reaction chamber and semiconductor processing equipment

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328722A (en) * 1992-11-06 1994-07-12 Applied Materials, Inc. Metal chemical vapor deposition process using a shadow ring
US5476548A (en) * 1994-06-20 1995-12-19 Applied Materials, Inc. Reducing backside deposition in a substrate processing apparatus through the use of a shadow ring
US5556476A (en) * 1994-02-23 1996-09-17 Applied Materials, Inc. Controlling edge deposition on semiconductor substrates
US5695831A (en) * 1995-02-03 1997-12-09 Nec Corporation CVD method for forming a metallic film on a wafer
US5766365A (en) * 1994-02-23 1998-06-16 Applied Materials, Inc. Removable ring for controlling edge deposition in substrate processing apparatus
US5855687A (en) * 1990-12-05 1999-01-05 Applied Materials, Inc. Substrate support shield in wafer processing reactors
US5888304A (en) * 1996-04-02 1999-03-30 Applied Materials, Inc. Heater with shadow ring and purge above wafer surface
US6022809A (en) * 1998-12-03 2000-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Composite shadow ring for an etch chamber and method of using
US6096135A (en) * 1998-07-21 2000-08-01 Applied Materials, Inc. Method and apparatus for reducing contamination of a substrate in a substrate processing system
US6186092B1 (en) * 1997-08-19 2001-02-13 Applied Materials, Inc. Apparatus and method for aligning and controlling edge deposition on a substrate
US6231674B1 (en) * 1994-02-23 2001-05-15 Applied Materials, Inc. Wafer edge deposition elimination
US6375748B1 (en) * 1999-09-01 2002-04-23 Applied Materials, Inc. Method and apparatus for preventing edge deposition
US6436192B2 (en) * 1997-07-11 2002-08-20 Applied Materials, Inc. Apparatus for aligning a wafer
US6589352B1 (en) * 1999-12-10 2003-07-08 Applied Materials, Inc. Self aligning non contact shadow ring process kit
US6623597B1 (en) * 1999-09-29 2003-09-23 Samsung Electronics Co., Ltd. Focus ring and apparatus for processing a semiconductor wafer comprising the same
US20030201069A1 (en) * 2000-09-18 2003-10-30 Johnson Wayne L. Tunable focus ring for plasma processing
US20030226822A1 (en) * 2002-06-07 2003-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Composite shadow ring assembled with dowel pins and method of using
US20040000375A1 (en) * 2002-06-27 2004-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Plasma etch chamber equipped with multi-layer insert ring
JP2006118004A (en) * 2004-10-21 2006-05-11 Canon Anelva Corp Substrate treatment device, method for monitoring generation of arcing in substrate treatment device, method for depositing tungsten thin film and tungsten thin film depositing device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4902051B2 (en) 2001-03-30 2012-03-21 キヤノンアネルバ株式会社 Bias sputtering equipment
JP2002334879A (en) 2001-05-08 2002-11-22 Hitachi Ltd Method for manufacturing semiconductor integrated circuit device

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5855687A (en) * 1990-12-05 1999-01-05 Applied Materials, Inc. Substrate support shield in wafer processing reactors
US5328722A (en) * 1992-11-06 1994-07-12 Applied Materials, Inc. Metal chemical vapor deposition process using a shadow ring
US6231674B1 (en) * 1994-02-23 2001-05-15 Applied Materials, Inc. Wafer edge deposition elimination
US5766365A (en) * 1994-02-23 1998-06-16 Applied Materials, Inc. Removable ring for controlling edge deposition in substrate processing apparatus
US5556476A (en) * 1994-02-23 1996-09-17 Applied Materials, Inc. Controlling edge deposition on semiconductor substrates
US5476548A (en) * 1994-06-20 1995-12-19 Applied Materials, Inc. Reducing backside deposition in a substrate processing apparatus through the use of a shadow ring
US5695831A (en) * 1995-02-03 1997-12-09 Nec Corporation CVD method for forming a metallic film on a wafer
US5888304A (en) * 1996-04-02 1999-03-30 Applied Materials, Inc. Heater with shadow ring and purge above wafer surface
US6436192B2 (en) * 1997-07-11 2002-08-20 Applied Materials, Inc. Apparatus for aligning a wafer
US6186092B1 (en) * 1997-08-19 2001-02-13 Applied Materials, Inc. Apparatus and method for aligning and controlling edge deposition on a substrate
US6328808B1 (en) * 1997-08-19 2001-12-11 Applied Materials, Inc. Apparatus and method for aligning and controlling edge deposition on a substrate
US6374512B1 (en) * 1998-07-21 2002-04-23 Applied Materials, Inc. Method for reducing contamination of a substrate in a substrate processing system
US6096135A (en) * 1998-07-21 2000-08-01 Applied Materials, Inc. Method and apparatus for reducing contamination of a substrate in a substrate processing system
US6022809A (en) * 1998-12-03 2000-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Composite shadow ring for an etch chamber and method of using
US6375748B1 (en) * 1999-09-01 2002-04-23 Applied Materials, Inc. Method and apparatus for preventing edge deposition
US6623597B1 (en) * 1999-09-29 2003-09-23 Samsung Electronics Co., Ltd. Focus ring and apparatus for processing a semiconductor wafer comprising the same
US6589352B1 (en) * 1999-12-10 2003-07-08 Applied Materials, Inc. Self aligning non contact shadow ring process kit
US20030201069A1 (en) * 2000-09-18 2003-10-30 Johnson Wayne L. Tunable focus ring for plasma processing
US20030226822A1 (en) * 2002-06-07 2003-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Composite shadow ring assembled with dowel pins and method of using
US20040000375A1 (en) * 2002-06-27 2004-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Plasma etch chamber equipped with multi-layer insert ring
JP2006118004A (en) * 2004-10-21 2006-05-11 Canon Anelva Corp Substrate treatment device, method for monitoring generation of arcing in substrate treatment device, method for depositing tungsten thin film and tungsten thin film depositing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021252758A1 (en) * 2020-06-11 2021-12-16 Lam Research Corporation Flat bottom shadow ring

Also Published As

Publication number Publication date
US7833909B2 (en) 2010-11-16
JP2009277720A (en) 2009-11-26
CN101582376B (en) 2011-06-22
CN101582376A (en) 2009-11-18
US20100144154A1 (en) 2010-06-10

Similar Documents

Publication Publication Date Title
US7833909B2 (en) Method of manufacturing semiconductor device, and etching apparatus
JP5591181B2 (en) Manufacturing method of semiconductor chip
US8771533B2 (en) Edge protection seal for bonded substrates
JP2005123425A (en) Semiconductor substrate manufacturing method, semiconductor substrate and method for manufacturing semiconductor device
US6670283B2 (en) Backside protection films
JP2008210909A (en) Manufacturing method for semiconductor device
KR100518587B1 (en) Fabrication Method for shallow trench isolation structure and microelectronic device having the same structure
US7402500B2 (en) Methods of forming shallow trench isolation structures in semiconductor devices
KR20000047991A (en) Method and apparatus for preventing formation of black silicon on edges of wafers
US7018905B1 (en) Method of forming isolation film in semiconductor device
US20100127317A1 (en) Semiconductor device and method for manufacturing the same
KR100564625B1 (en) Semiconductor device including trench isolation film and method of fabrication the same
US9449922B2 (en) Contact critical dimension control
JP2002373935A (en) Trench element separation method
US20070249118A1 (en) Semiconductor device and method of manufacturing the same
US20090023300A1 (en) Method of forming shadow layer on the wafer bevel
KR20070010913A (en) Edge ring of dry etching apparatus
CN115116838A (en) Method for improving dielectric layer peeling by wet process
US7501326B2 (en) Method for forming isolation layer of semiconductor device
US6521520B1 (en) Semiconductor wafer arrangement and method of processing a semiconductor wafer
KR100459693B1 (en) Trench isolation method of semiconductor device to prevent gate oxide layer from being deteriorated
US8524603B1 (en) Fabricating method for semiconductor device
KR100509846B1 (en) Method For Isolating Semiconductor Device
KR100464655B1 (en) Method for forming trench in semiconductor device
KR20030059474A (en) Methof for forming trench isolation in semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION