US20110031614A1 - Methods for fabricating semiconductor components and packaged semiconductor components - Google Patents
Methods for fabricating semiconductor components and packaged semiconductor components Download PDFInfo
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- US20110031614A1 US20110031614A1 US12/906,818 US90681810A US2011031614A1 US 20110031614 A1 US20110031614 A1 US 20110031614A1 US 90681810 A US90681810 A US 90681810A US 2011031614 A1 US2011031614 A1 US 2011031614A1
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Abstract
Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall.
Description
- This application is a divisional of U.S. application Ser. No. 11/681,648 filed Mar. 2, 2007, which is incorporated herein by reference in its entirety.
- This invention relates generally to manufacturing semiconductor components. More particularly, several embodiments are directed to packaged semiconductor components, methods for packaging semiconductor components, and systems incorporating packaged semiconductor components.
- Semiconductor devices are typically manufactured on semiconductor wafers or other types of workpieces using sophisticated equipment and processes that enable reliable, high-quality manufacturing. The individual dies (e.g., devices) generally include integrated circuits and a plurality of bond-pads coupled to the integrated circuits. The bond-pads provide external contacts through which supply voltage, electrical signals, and other input/output parameters are transmitted to/from the integrated circuits. The bond-pads are usually very small, and they are typically arranged in dense arrays having a fine pitch between bond-pads. The wafers and dies can also be quite delicate. As a result, the dies are packaged to protect the dies and to connect the bond-pads to arrays of larger terminals that can be soldered to printed circuit boards.
- Chip scale packages (CSPs) are semiconductor components that have outlines, or “footprints,” approximately the same size as the dies in the packages. CSPs typically include dense arrays of bond-pads and solder bumps on the bond-pads that permit the packages to be flip-chip mounted to substrates (e.g., module substrates or other circuit boards). Bumped dies are another type of semiconductor component that include dense arrays of solder bumps.
- One challenge of manufacturing semiconductor components is cost effectively packaging the dies. The sizes of computers, cell phones, hand-held devices, and other electronic products are continually decreasing, but at the same time the performance of electronic products is increasing. The sizes of the dies accordingly decrease while the number of components in the dies significantly increases to meet the demands of the market. As a result, the number and density of input/output terminals on the dies increase. This can significantly increase the cost of manufacturing semiconductor components.
- Several existing processes package high-performance semiconductor dies in six-sided CSPs that completely encapsulate the dies while the dies are arranged in the format of a wafer (i.e., wafer-level packaging). One existing wafer-level packaging process for CSPs includes cutting deep trenches on only the active side of the wafer between the dies and depositing a polymeric material on the active side to fill the trenches and cover the dies. The wafer is then thinned from the backside until the trenches are exposed such that each die is completely separated from adjacent dies by the polymeric material in the trenches. Another layer of the polymeric material is applied to the backside of the dies, and the assembly is then cut along the polymeric material in the trenches to separate the packaged dies from each other. This process accordingly forms six-sided packages that completely encapsulate the dies.
- One challenge of fabricating such six-sided packages is that it is difficult to cut deep channels into the wafer (e.g., channels deeper than approximately 250 microns). As a result, the wafer must be thinned to a thickness less than the depth of trenches to expose the polymeric material in the channels before the backside of the dies is coated with the additional layer of the polymeric material. In many cases the wafer is thinned to less than 250 microns to isolate the dies between the polymeric material in the trenches. This can be problematic because such thin dies are subject to warping or bending. More specifically, because the polymeric material and the dies have significantly different thermal expansion coefficients, thermal cycling can cause extensive warping and even breakage of the very thin dies. Therefore, it would be desirable to package semiconductor dies using wafer-level packaging techniques that provide more robust packages.
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FIGS. 1A-F are schematic cross-sectional views illustrating stages of a method for manufacturing semiconductor components in accordance with an embodiment of the invention. -
FIG. 2 is a schematic cross-sectional view of a semiconductor component in accordance with an embodiment of the invention. -
FIG. 3 is a flow chart of a method for fabricating semiconductor components in accordance with an embodiment of the invention. -
FIG. 4 is a flow chart of a method for fabricating semiconductor components in accordance with another embodiment of the invention. -
FIG. 5 is a flow chart of a method for fabricating semiconductor components in accordance with another embodiment of the invention. -
FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor wafer at a stage of a method for fabricating semiconductor components in accordance with an embodiment of the invention. -
FIG. 7 is a schematic view of a system that incorporates semiconductor components in accordance with embodiments of the invention. - Specific details of several embodiments of the disclosure are described below with reference to packaged semiconductor components and methods for manufacturing packaged semiconductor components. The semiconductor components are manufactured on semiconductor wafers that can include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, read/write components, and other features are fabricated. For example, SRAM, DRAM (e.g., DDR/SDRAM), flash memory (e.g., NAND flash-memory), processors, imagers, and other types of devices can be constructed on semiconductor wafers. Although many of the embodiments are described below with respect to semiconductor devices that have integrated circuits, other types of devices manufactured on other types of substrates may be within the scope of the invention. Moreover, several other embodiments of the invention can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the invention may have other embodiments with additional elements, or the invention may have other embodiments without several of the features shown and described below with reference to
FIGS. 1A-7 . -
FIG. 1A illustrates asemiconductor wafer 10 at one stage of an embodiment of a method for fabricating semiconductor components. Thewafer 10 includes asubstrate 12 having afirst side 14, aback surface 16, and a plurality of diecontacts 18 or other types of electrical input/output terminals at thefirst side 14. Thefirst side 14 is accordingly an active side or circuit side of thewafer 10. Thewafer 10 further includes a plurality ofdies 20, and individual dies include anintegrated circuit 26 electrically coupled to corresponding diecontacts 18 at thefirst side 14. Thedies 20 can comprise any type of semiconductor device having a desired configuration. For example, each die 20 can comprise a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a micro-processor, a digital signal processor, an application specific integrated circuit, an imager, or other type of semiconductor device. Thewafer 10 further includes a plurality oflanes 30 between thedies 20. Thedies 20 are typically arranged in a grid or other type of pattern on thewafer 10 according to the specific application. -
FIG. 1A provides one example of a semiconductor wafer in which thedie contacts 18 are located at thefirst side 14 of thewafer 10. In other embodiments, however, thedie contacts 18 can be located on theback surface 16 or at a second surface of the substrate formed later by thinning thewafer 10. In these embodiments, thedie contacts 18 are connected to the integratedcircuits 26 using interconnects that pass to the backside of the wafer. As such, although the following processes are described as being performed on thefirst side 14 and then theback surface 16, it is to be understood that any of the operations can be reversed. Moreover, even though the illustrated diecontacts 18 are arranged in two rows along the center of eachdie 20, thedie contacts 18 can be in arrays that have different configurations. The diecontacts 18 are generally circular-shaped metal pads having a desired size and spacing. For example, thedie contacts 18 can comprise nickel, copper, gold, silver, platinum, palladium, tin, zinc, alloys of these metals, and/or other metals suitable for soldering. -
FIG. 1B illustrates thewafer 10 at a stage in which contact bumps 24 or other connectors are formed on thedie contacts 18. The contact bumps 24 can comprise metal bumps deposited on thedie contacts 18 using a suitable deposition process, such as stenciling/reflow, ball deposits, and other processes. The contact bumps 24 can comprise solder, gold balls, other metals, or a conductive polymer. The contact bumps 24 are used to interconnect thedie contacts 18 to corresponding terminals on a printed circuit board, lead frame, module, or other suitable device. As shown inFIG. 1B , a dicingtape 32 can be attached to theback surface 16 of thewafer 10. -
FIG. 1C illustrates thewafer 10 at a subsequent stage of the method in which a plurality offirst trenches 40 are formed along thelanes 30 at thefirst side 14 of thewafer 10. In this embodiment, thefirst trenches 40 are arranged in a grid between the dies 20. Thefirst trenches 40 can be formed by scribing the wafer along thelanes 30 using a dicing saw having blades set such that the kerfs extend to only an intermediate depth d1 within thewafer 10. Thefirst trenches 40 can alternatively be formed using an etching process that etches thefirst trenches 40 through an etch mask (not shown) formed on thefirst side 14 of thewafer 10. The etching process can be a wet etching process, a dry etching process, or a plasma etching process. In the case of etching, the depth d1 of thefirst trenches 40 can be controlled using suitable endpointing techniques. Another alternative for forming thefirst trenches 40 is laser machining thewafer 10. Suitable laser systems for forming thefirst trenches 40 are manufactured by Electro Scientific, Inc., of Portland, Oreg. (e.g., Model Number 2700). - As shown in
FIG. 1C , thefirst trenches 40 do not extend through the full thickness Tw1 of thewafer 10 defined by the distance between thefirst side 14 and theback surface 16. Rather, thefirst trenches 40 have an intermediate depth d1 measured from the surface of thefirst side 14 of thewafer 10 that is less than the thickness Tw1. In one example, the initial thickness Tw1 of thewafer 10 is approximately 700-1,000 microns (e.g., approximately 750 microns), and thefirst trenches 40 have a depth d1 of less than approximately 250 microns. The depth d1 of thefirst trenches 40, for example, can be approximately 50-200 microns. As explained more fully below, the depth d1 is also less than a final wafer thickness of thewafer 10 after it has been thinned. -
FIG. 1D illustrates a subsequent stage in the method in which thefirst trenches 40 are filled with a firstprotective material 50. The firstprotective material 50 can form a first cover member having afront side portion 52 covering thefirst side 14 andfirst extensions 54 in thefirst trenches 40. The first cover member can be formed by depositing a polymeric material onto thefirst side 14 of thewafer 10 using suitable molding techniques, screen printing, stenciling, or spin-on processes. The firstprotective material 50 can comprise a curable polymer, such as a silicone, a polyimide, or an epoxy. In addition, the firstprotective material 50 can include fillers, such as silicates, or other materials that reduce the coefficient of thermal expansion and control the viscosity of the firstprotective material 50. One suitable curable polymer material is manufactured by Dexter Electronic Materials of Rocky Hill, Conn. under the trademark “HYSOL” FP 4450. The firstprotective material 50 can be cured at this stage to harden the material. For example, curing can be formed by placing thewafer 10 in a chamber having a temperature of about 90 degrees to 165 degrees C. for about 30-60 minutes. In other embodiments, however, the firstprotective material 50 can be cured at a later stage of the method. -
FIG. 1E illustrates thewafer 10 at a subsequent stage of the method in which thewafer 10 has been thinned to form asecond side 17 opposite thefirst side 14. Thewafer 10 can be thinned by grinding thewafer 10 from the back surface 16 (FIG. 1D ) at the first thickness Tw1 to thesecond side 17 at a second thickness Tw2. The second thickness Tw2, for example, can be approximately 300-500 microns (e.g., approximately 450 microns). In other embodiments, the second thickness can be more or less than 300-500 microns. - After thinning the
wafer 10, a plurality ofsecond trenches 60 are formed in thesecond side 17 along thelanes 30. Thesecond trenches 60 are at least generally aligned with thefirst trenches 40 at thefirst side 14 of thewafer 10, and thesecond trenches 60 have a second intermediate depth d2 from thesecond side 17 that does not extend to the intermediate depth d1 of thefirst trenches 40. In specific embodiments, the widths and depths of the first andsecond trenches second trenches 60 are separated from thefirst trenches 40 byshoulders 19 in thelanes 30. Theshoulders 19 are portions of thewafer 10. As a result, the sum of the first intermediate depth d1 and second intermediate depth d2 is less than the second thickness Tw2 of thewafer 10. Thesecond trenches 60 can be formed by sawing, etching, or laser cutting, as described above with respect to thefirst trenches 40 inFIG. 1C . -
FIG. 1F illustrates thewafer 10 at another stage of the method in which a secondprotective material 70 is deposited onto thesecond side 17 of thewafer 10. The secondprotective material 70 fills at least a portion of thesecond trenches 60. The secondprotective material 70 can be the same as the firstprotective material 50, or the secondprotective material 70 can be different than the firstprotective material 50. For example, the secondprotective material 70 can be a polymeric material, such as a silicone, a polyimide, or an epoxy, either with or without suitable fillers. The secondprotective material 70 can be molded to form a second cover member having abackside portion 72 that covers thesecond side 17 andsecond extensions 74 in thesecond trenches 60. The secondprotective material 70 can be cured to harden the second cover member. In practice, the firstprotective material 50 and the secondprotective material 70 can be cured at the same time after depositing the secondprotective material 70 onto thesecond side 17 of thewafer 10. - After forming the second cover member from the second
protective material 70, thewafer 10 can be cut along thelanes 30 between the dies 20 to separate the dies 20 from each other. Thewafer 10 is cut such that the kerf k of the cut is less than the width w of the first andsecond trenches second trenches -
FIG. 2 is a schematic cross-sectional view illustrating asemiconductor component 100 formed from a portion of the wafer 10 (FIG. 1 ) after cutting thewafer 10 along thelanes 30. Like reference numbers refer to like components inFIGS. 1A-2 . Thesemiconductor component 100 includes a die 20, a firstexterior cover 51 of the firstprotective material 50 formed from the first cover member, and asecond exterior cover 71 of the secondprotective material 70 formed from the second cover member. Thedie 20 has a sidewall with afirst indentation 21 a around the periphery of the die 20 at thefirst side 14, asecond indentation 21 b around the periphery of the die 20 at thesecond side 17, and theshoulder 19 projecting outwardly around the periphery of thedie 20. The firstexterior cover 51 accordingly has thefront side portion 52 over thefirst side 14 and thefirst extension 54 projecting from thefront side portion 52 in thefirst indentation 21 a. Thesecond exterior cover 71 has abackside portion 72 over thesecond side 17 and thesecond extension 74 projecting from thebackside portion 72 in thesecond indentation 21 b. The firstprotective cover 51 and the secondprotective cover 71 encase virtually all of the die 20 except for an exposedportion 23 of theshoulder 19 between thefirst extension 54 and thesecond extension 74. As a result, thesemiconductor component 100 has pseudo six-sided protection except for the exposedportion 23 of theshoulder 19. - In a particular embodiment, the
front side portion 52 of the firstexterior cover 51 has a thickness T1 and thefirst extension 54 has a thickness of T2 at least substantially equal to the thickness T1. Accordingly, the forces exerted by the firstexterior cover 51 on the die 20 during thermal cycling are equal for both thefront side portion 52 and thefirst extension 54. Similarly, thebackside portion 72 of thesecond exterior cover 71 has a thickness T3 and thesecond extension 74 has a thickness T4 substantially equal to the thickness T3. Moreover, in a specific embodiment, the thicknesses T1, T2, T3, and T4 can all be substantially equal to each other such that the forces exerted on the die 20 by the firstexterior cover 51 are substantially equal to the forces exerted on the die 20 by thesecond exterior cover 71. Such equal loading on the front side and backside of the die 20 can reduce flexing and warpage of thedie 20. - Several embodiments of the
semiconductor component 100 can provide the virtual equivalent of complete six-sided protection for the die 20 with a thicker substrate than existing six-sided packages formed using trenches cut in only one side of the wafer. More specifically, it is difficult to cut trenches deeper than approximately 250 microns in the wafer, and thus the dies in many existing six-sided packages are thinned to less than approximately 250 microns before applying the polymeric material to the backside of the dies. Such thin dies are subject to warping or breaking during subsequent handling and/or thermal cycling. Several embodiments of thesemiconductor component 100, however, can have a thickness substantially greater than 250 microns (e.g., 300-700 microns) because the first and second trenches are aligned with each other and spaced apart by a portion of the wafer (e.g., the shoulders). As a result, thesemiconductor component 100 provides a robust device with the virtual equivalent of complete six-sided encapsulation. - Several embodiments of the
semiconductor component 100, moreover, can be packaged at the wafer level without having to handle individual dies before they are fully protected. This may reduce the damage caused by handling unprotected dies before they are encapsulated that may occur in many existing packaging processes. More specifically, by performing a partial scribe from each side of the wafer, the motion of the wafer is constrained while still allowing formation of full front side and backside encapsulation for protection of the exposed corners of thedie 20. The full corner protection shown in the illustrated embodiment of thesemiconductor component 100 can survive the environmental testing and operation conditions while preventing edge separation. - Specific embodiments of the
semiconductor component 100 can further provide uniform loading on the wafer. For example, by forming the first exterior cover and the second exterior cover to have approximately equal thicknesses, the stresses induced by thermal contraction/expansion of the first and second exterior covers can be approximately equal. In these embodiments, the loading on the front side counteracts the loading on the backside to mitigate or eliminate warpage and cracking. -
FIG. 3 is a flow chart of an embodiment of amethod 300 for manufacturing semiconductor components. Themethod 300 includes forming a plurality of first trenches in lanes between dies on a first side of a semiconductor wafer (block 310), and filling at least a portion of the first trenches with a protective material (block 320). Themethod 300 continues by forming a plurality of second trenches on a second side of the wafer that are at least generally aligned with the first trenches along the cutting lanes (block 330). As explained above, many applications should have good alignment between the first and second trenches, but a certain degree of misalignment can be acceptable. Themethod 300 further includes filling at least a portion of the second trenches with the protective material (block 340), and cutting through the wafer along the lanes (block 350). The semiconductor components are thus formed after cutting through the wafer along the cutting lanes. -
FIG. 4 illustrates an embodiment of anothermethod 400 for manufacturing semiconductor components. Themethod 400 includes depositing a protective material on a first side of a semiconductor wafer having a plurality of dies so that the protective material is in first trenches between the dies on the first side of the wafer (block 410). Themethod 400 also includes depositing a protective material on a second side of the wafer so that the protective material is in second trenches on the second side of the wafer (block 420). The second trenches are at least generally aligned with the first trenches. The protective material in the first trenches can be the same as the protective material in the second trenches. In alternative embodiments, however, the protective material in the second trenches is different than that in the first trenches. Themethod 400 further includes separating the wafer along the first and second trenches (block 430). -
FIG. 5 is a flow chart illustrating an embodiment of still anothermethod 500 for manufacturing semiconductor components. Themethod 500 includes mounting conductive balls or bumps to die contacts connected to integrated circuits of dies on a semiconductor wafer (block 510). The die contacts are at a first side of the wafer. Themethod 500 continues by cutting first trenches into the first side of the wafer along lanes adjacent to the dies such that the first trenches have a first depth in the wafer (block 520). Themethod 500 further includes molding a polymeric material onto the first side and into the first trenches (block 530) and thinning the wafer to a second side opposite the first side (block 540). Themethod 500 also includes cutting second trenches into the second side of the wafer after the thinning procedure so that the second trenches are at least generally aligned with the first trenches along the lanes (block 550) and molding the polymeric material onto the second side and into the second trenches (block 560). Themethod 500 further includes cutting the wafer along the dicing lanes (block 570). The process of cutting the wafer forms individual packaged components that have a first exterior cover at the first side with a first extension extending toward the second side, a second exterior cover at the second side with a second extension extending toward the first side, and a sidewall between the first and second sides. The sidewall includes an exterior portion of the first extension, an exterior portion of the second extension, and an exposed portion of the semiconductor wafer between the first and second extensions. -
FIG. 6 is a cross-sectional view illustratingsemiconductor components 600 in accordance with another embodiment. Like reference numbers refer to like components inFIGS. 1A-2 and 6. Thesemiconductor components 600 are similar to thesemiconductor component 100 illustrated inFIG. 2 , but thesemiconductor components 600 have first and second channels ortrenches second indentations second indentations second channels lanes 30, eachsemiconductor component 600 has a firstexterior cover 51 with a firstbeveled extension 654 and asecond exterior cover 71 with a secondbeveled extension 674. - Any one of the semiconductor components described above with reference to
FIGS. 1A-6 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which issystem 700 shown schematically inFIG. 7 . Thesystem 700 can include aprocessor 701, a memory 702 (e.g., SRAM, DRAM, flash, and/or other memory device), input/output devices 703, and/or other subsystems orcomponents 704. The foregoing semiconductor components described above with reference toFIGS. 1A-6 may be included in any of the components shown inFIG. 7 . The resultingsystem 700 can perform any of a wide variety of computing, processing, storage, sensing, imaging, and/or other functions. Accordingly,representative systems 700 include, without limitation, computers and/or other data processors, for example, desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, etc.), multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Otherrepresentative systems 700 include cameras, light or other radiation sensors, servers and associated server subsystems, display devices, and/or other memory devices. In such systems, individual dies can include imager arrays, such as CMOS imagers. Components of thesystem 700 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of thesystem 700 can accordingly include local and/or remote memory storage devices, and any of a wide variety of computer readable media. - From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the inventions. For example, many of the elements of one embodiment can be combined with other embodiments in addition to, or in lieu of, the elements of the other embodiments. For example, the solder balls can be deposited onto the first side of the wafer after forming the first trenches. In still additional embodiments, the second trenches can be formed from the back surface 16 (
FIG. 1D ) before thinning the wafer to form the second side 17 (FIG. 1E ). Additionally, where the context permits, singular or plural terms may also include plural or singular terms, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list means including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout the following disclosure to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of features or components are not precluded. Accordingly, the invention is not limited except as by the appended claims.
Claims (17)
1. A semiconductor component, comprising:
a die having a semiconductor substrate and an integrated circuit, wherein the substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side;
a first exterior cover at the first side, the first exterior cover having a first extension in the first indentation; and
a second exterior cover at the second side, the second exterior cover having a second extension in the second indentation, and wherein the first and second extensions are spaced apart from each other by an exposed portion of the sidewall.
2. The semiconductor component of claim 1 , wherein the sidewall of the substrate further comprises a shoulder between the first and second indentations having a peripheral surface that defines the exposed portion of the sidewall.
3. The semiconductor component of claim 1 , wherein:
the die further includes a plurality of electrical terminals at the first side that are electrically coupled to the integrated circuit; and
the first exterior cover has a front section over the first side, and the first extension projects from the front section toward the second side.
4. The semiconductor component of claim 1 , wherein the second exterior cover has a back section over the second side, and the second extension projects from the back section toward the first side.
5. The semiconductor component of claim 1 , wherein:
the first exterior cover comprises a first polymeric cap having a front section and the first extension, the front section having a thickness, and the first extension projecting from the front section toward the second side; and
the second exterior cover comprises a second polymeric cap having a back section and the second extension, the back section having the same thickness as the front section, and the second extension projecting from the back section toward the first side.
6. The semiconductor component of claim 5 , wherein the first extension and the second extension have the same thickness as the front and back sections.
7. The semiconductor component of claim 1 wherein the substrate has a thickness between the first side and the second side of approximately 300-750 microns.
8. The semiconductor component of claim 1 wherein the substrate has a thickness between the first side and the second side, the first extension projects into the substrate by a first depth, and the second extension projects into the substrate by a second depth, and wherein a sum of the first and second depths is less than the thickness of the substrate.
9. A semiconductor component, comprising:
a die having a semiconductor substrate with a front surface, a back surface, and a sidewall between the front surface and the back surface, wherein the sidewall has a shoulder projecting outwardly;
a first polymeric cover having a front portion covering the front surface and a first extension projecting from the front portion to the shoulder; and
a second polymeric cover having a back portion covering the back surface and a second extension projecting from the back portion to the shoulder, wherein the shoulder separates the first extension from the second extension.
10. The component of claim 9 wherein the first polymeric cover and the second polymeric cover have at least approximately equal thicknesses.
11. The component of claim 9 wherein the first and second extensions have at least approximately equal thicknesses.
12. A semiconductor apparatus, comprising:
a semiconductor wafer having a plurality of dies with integrated circuits, a first side, a plurality of first channels in the first side located in lanes between the dies, a second side, and a plurality of second channels in the second side in the lanes;
a first polymeric material on the first side, wherein a portion of the first polymeric material is in the first channels; and
a second polymeric material on the second side, wherein a portion of the second polymeric material is in the second channels.
13. The apparatus of claim 12 , wherein the first polymeric material comprises a first cover member having a front side portion and first extensions projecting from the front side portion and the second polymeric material comprises a second cover member having a backside portion and second extensions projecting from the backside portion, and wherein the first extensions are in the first trenches and the second extensions are in the second trenches.
14. The apparatus of claim 12 , wherein the first trenches have a first depth only partially through the wafer, the second trenches have a second depth only partially through the wafer, and the first and second trenches are spaced apart by a portion of the wafer.
15. The apparatus of claim 12 , wherein the wafer has a thickness between the first side and the second side of approximately 300-500 microns.
16. The apparatus of claim 12 , wherein the wafer has a thickness between the first side and the second side of approximately 300-500 microns, the first trenches have a first depth of not more than 250 microns, the second trenches have a second depth of not more than 250 microns, and the first and second trenches are aligned with each other with a portion of the wafer between the first and second trenches.
17. The apparatus of claim 12 , wherein the first polymeric material comprises a first cover member having a front side portion and first extensions projecting from the front side portion and the second polymeric material comprises a second cover member having a backside portion and second extensions projecting from the backside portion, and wherein the first extensions are in the first trenches and the second extensions are in the second trenches, and wherein the first and second cover members have at least approximately equal thicknesses.
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US20200357697A1 (en) * | 2017-08-17 | 2020-11-12 | Semiconductor Components Industries, Llc | Thin semiconductor package and related methods |
US11942369B2 (en) * | 2017-08-17 | 2024-03-26 | Semiconductor Components Industries, Llc | Thin semiconductor package for notched semiconductor die |
Also Published As
Publication number | Publication date |
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WO2008109457A1 (en) | 2008-09-12 |
TW200901339A (en) | 2009-01-01 |
US20080213976A1 (en) | 2008-09-04 |
US7833881B2 (en) | 2010-11-16 |
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