US20110058340A1 - Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method - Google Patents
Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method Download PDFInfo
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- US20110058340A1 US20110058340A1 US12/941,899 US94189910A US2011058340A1 US 20110058340 A1 US20110058340 A1 US 20110058340A1 US 94189910 A US94189910 A US 94189910A US 2011058340 A1 US2011058340 A1 US 2011058340A1
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- insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/422—Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
- B23K26/382—Removing material by boring or cutting by boring
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- providing the first patterned conductive layer includes patterning the initial conductive layer 12 by way of etching
- providing the second patterned conductive layer includes providing a second conductive layer 24 onto a side of the starting insulating layer 10 opposite the side including the initial conductive layer 12 , and then patterning the second conductive layer 24 , such as, for example, by way of etching.
- the second conductive layer 24 is provided by laminating the second conductive layer 24 onto the starting insulating layer 10 . According to the second embodiment as shown in FIGS.
- method embodiments include providing a supplemental insulating layer 26 onto the first patterned conductive layer 19 .
- an additional supplemental insulating layer 28 may be provided onto the second patterned conductive layer 20 as shown.
- a supplemental insulating layer according to embodiments may include the same material as the one used for the starting insulating layer as noted above.
- provision of a supplemental insulating layer according to embodiments may include laminating the supplemental insulating layer onto a corresponding patterned conductive layer.
- laser drilling allows for higher starting insulating layer connection density as compared with prior art structures, owing to small via sizes and pitches, thus allowing for smaller sized vias and smaller pitches, in this way leading to an improved design and to scalable miniaturization at low cost.
- Laser drilling features high alignment accuracy (15 um POR), and through-put (up to about 2000 vias/sec), a wide range of possible via sizes (such as between about 50 microns and about 300 microns), and low cost (about 2 cents per one thousand vias).
- the combination of high alignment accuracy and small via size make possible via pitches as low as about 150 microns, those pitches being much less than typically plated through hole pitches of about 400 microns.
Abstract
A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.
Description
- This is a Continuation Application of Ser. No. 11/769,852 filed Jun. 28, 2007, which is presently pending.
- Embodiments of the present invention relate generally to the field of multilayer substrate core structure fabrication, and, in particular, to methods for fabricating such a board by laser drilling microvias therein.
- A multilayer substrate core structure (MPWB) may be conventionally fabricated by first providing a copper clad core. The copper clad core (CCL) may be a laminate that is copper clad on one or two sides depending on application needs. An example of such a fabrication process is shown in
FIGS. 1-8 . As seen inFIG. 1 , a twosided CCL 101 is first provided including aninsulating laminate 12 and top andbottom copper films FIG. 2 , the top andbottom copper films laminate 120, such as by way of etching, to provide patternedcopper films FIG. 3 , dielectric layer, such asABF layers 190 and 210 (Ajinomoto Build-Up Film), are laminated onto the patternedcopper films FIG. 4 to provide a firstintermediate laminate 180. As seen inFIG. 4 , the firstintermediate laminate 180 is then provided with throughholes 201 by way of mechanical drilling and des-mearing to provide a secondintermediate laminate 220. The de-smearing involves using a desmear solution to process the board to dissolve and remove any smears caused by drilling. As seen inFIG. 5 , the through-holes 201 and the top and bottom surfaces of theintermediate laminate 220 are then plated to provide a platedintermediate laminate 240 with plated throughholes 260. As seen inFIG. 6 , the platedintermediate laminate 240 may be subjected thereafter to PTH plugging with aconductive material 250 such as copper to yield a pluggedintermediate laminate 280. In a next stage, as shown inFIG. 7 , the pluggedintermediate laminate 280 may be lid plated with a conductive material such as copper to providelids laminate 280 ofFIG. 6 to yield a lid platedintermediate laminate 300. Thereafter, the copper existing at the top and bottom surfaces of lid platedintermediate laminate 30 is patterned, such as by way of etching, to yield thewiring board 320 as shown inFIG. 8 . - Prior art substrate are typically built on the base of a thick core (for example one having a thickness of about 0.7 mm (not including any build-up or conductive layers). The prior art core build up process can be lengthy. Taking a four layer core as an example, the macro process stages of a prior art fabrication process may include all of: core baking and cleaning, core copper patterning, copper roughening, ABF lamination, plated through hole drilling, desmear, copper plating, copper roughening, plated through hole plugging, surface flattening, copper plating, and finally, copper patterning. However, mechanical plated through hole drilling can be the most expensive single process in the fabrication of a prior art multilayer substrate core structure. The need for plugging as explained above can add more to the manufacturing costs according to the prior art.
- Disadvantageously, substrate core structures for substrate core structures according to the prior art can be costly, and can carry high manufacturing costs as a result of the use of mechanical drilling technology. These costs can skyrocket where the substrate core structures are miniaturized and scaled for future applications. In addition, mechanical drilling is not suitable for producing holes smaller than about 150 microns.
- The prior art fails to provide a cost-effective, expedient and reliable method of providing a multilayer substrate core structure.
-
FIGS. 1-8 show stages of forming a substrate core structure according to the prior art; -
FIGS. 9 a-9 h show stages of forming a substrate core structure according to a first embodiment; -
FIGS. 10 a-10 h show stages of forming a substrate core structure according to a second embodiment; -
FIG. 11 is a schematic view of an embodiment of a system incorporating a substrate core as shown in either ofFIG. 9 h or 10 h. - For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.
- In the following detailed description, a method of fabricating a substrate core structure, such as a substrate core structure, a substrate core structure formed according to the method, and a system including the substrate core structure, are disclosed. Reference is made to the accompanying drawings within which are shown, by way of illustration, specific embodiments by which the present invention may be practiced. It is to be understood that other embodiments may exist and that other structural changes may be made without departing from the scope and spirit of the present invention.
- The terms on, above, below, and adjacent as used herein refer to the position of one element relative to other elements. As such, a first element disposed on, above, or below a second element may be directly in contact with the second element or it may include one or more intervening elements. In addition, a first element disposed next to or adjacent a second element may be directly in contact with the second element or it may include one or more intervening elements. In addition, in the instant description, figures and/or elements may be referred to in the alternative. In such a case, for example where the description refers to Figs. X/Y showing an element A/B, what is meant is that Fig. X shows element A and Fig. Y shows element B. In addition, a “layer” as used herein may refer to a layer made of a single material, a layer made of a mixture of different components, a layer made of various sub-layers, each sub-layer also having the same definition of layer as set forth above.
- Aspects of this and other embodiments will be discussed herein with respect to
FIGS. 9 a-11 below.FIGS. 9 a-9 h show stages for the fabrication of a multilayer substrate core structure according to a first method embodiment involving subtractive patterning of the conductive layers, andFIGS. 10 a-10 h show stages for the fabrication of a multilayer substrate core structure according to a second method embodiment involving semi-additive patterning of the conductive layers, such as for FLS (fine line and space) routing.FIG. 11 shows a system incorporated a multilayer substrate core structure according to an embodiment. The figures, however, should not be taken to be limiting, as it is intended for the purpose of explanation and understanding. - Referring to
FIGS. 9 a and 10 a, method embodiments include providing a startinginsulating layer 10. The starting insulating layer may include any one of well known core insulating/dielectric materials, such as, for example, glass epoxy resin or bismaleimide-triazine (BT), or ABF. Preferably, the starting insulating layer comprises a fiber reinforced glass epoxy resin. According to one embodiment, as shown inFIGS. 9 a and 10 a, the starting insulatinglayer 10 may include an initialconductive layer 12 thereon, such as one made of copper, or one made of silver or nickel. In the shown embodiments ofFIGS. 9 a and 10 a, the starting insulatinglayer 10 may be part of a conventional copper clad core orCCL 14. In the first embodiment, the initialconductive layer 12 may, for example, have a thickness between about 50 and about 70 microns, whereas, in the second embodiment as shown inFIG. 10 a, the initialconductive layer 12 may have a thickness between about 1 micron and about 2 microns. - Referring next to
FIGS. 9 b and 10 b, embodiments include laser drilling a first set ofvia openings 14 through the startinginsulating layer 10 as shown. In the shown embodiments, the vias extend to theconductive layer 12. For laser drilling, a carbon dioxide gas laser beam, an ultraviolet laser beam or an excimer laser beam may be used. For example, an embodiment contemplates using a carbon dioxide laser on a glass fiber reinforced starting insulating layer having a power range between about 1 to about 10 mJ, and a pulse width between about 1 and about 100 ms. The determination of laser drilling parameters would be, among others, a function of the material being laser drilled, its thickness, and the dimensions of the via to be provided. - Referring next to
FIGS. 9 c and 10 c, embodiments include filling the first set ofvia openings 14 with a conductive material 16 to provide a first set ofconductive vias 18 as shown. According to a preferred embodiment, provision of the conductive material 16 may be effected by way of selective fast electroless plating. Preferably, the conductive material 16 includes copper, but it may also include nickel and/or silver. In the embodiment ofFIG. 10 c, the provision of the conductive material 16 may also be effected by way of selective fast electroless plating. As is well known, selective fast electroless copper plating may be achieved by using an electroless plating solution which includes a catalyst therein, that is, a substance present in an amount such that a substantially increased deposition rate of the material to be plated is obtained in comparison with a solution where the catalyst is not present, the catalyst further having the property of depositing itself only on the copper area of the initial conductive layer in order to allow the provision of selective fast electroless plating. - Referring next to
FIGS. 9 d and 9 e on the one hand, and toFIGS. 10 d and 10 e on the other hand, method embodiments include providing a first patternedconductive layer 19 on one side of the starting insulatinglayer 10, and a second patternedconductive layer 20 on another side of the starting insulatinglayer 10. According to the first embodiment as shown inFIGS. 9 d and 9 e, providing the first patterned conductive layer includes patterning the initialconductive layer 12 by way of etching, and providing the second patterned conductive layer includes providing a secondconductive layer 24 onto a side of the starting insulatinglayer 10 opposite the side including the initialconductive layer 12, and then patterning the secondconductive layer 24, such as, for example, by way of etching. Preferably, the secondconductive layer 24 is provided by laminating the secondconductive layer 24 onto the starting insulatinglayer 10. According to the second embodiment as shown inFIGS. 10 d and 10 e, providing the first patternedconductive layer 19 includes removing, such as, for example, by way of etching, the initialconductive layer 12 after filling the first set of viaopenings 14, and then providing the first patternedconductive layer 19 and the second patternedconductive layer 20 by using a semi-additive process. Removal of the initialconductive layer 12 may be preferably effected using a quick-etch process as would be recognized by one skilled in the art. A semi-additive process is a well known process according to which, for example, a desmear treatment may be performed as necessary to roughen the surfaces of the starting insulatinglayer 10, and thereafter electroless plating may be performed onto the starting insulatinglayer 10 to form an electroless plating film (not shown), such as a electroless copper plating film, on the starting insulatinglayer 10. Then, a photoresist may be deposited on the electroless plating film, which photoresist may then be exposed to light and developed, whereby a resist pattern may be formed while leaving, on the starting insulatinglayer 10, a non-mask region corresponding to the pattern of the first and/or second patterned conductive layer. By means of electroplating, the electroless plating film may be used as a seed layer to stack an electroplated film in the non-mask regions. The resist pattern may then be removed by etching, and thereafter the electroless plating film which was till then covered with the resist pattern, may be removed by etching. In this way, the first and second patternedconductive layers FIG. 10 e. - Referring next to
FIGS. 9 f and 10 f, method embodiments include providing a supplemental insulatinglayer 26 onto the first patternedconductive layer 19. In some embodiments, as shown inFIGS. 9 f and 10 f, an additional supplemental insulatinglayer 28 may be provided onto the second patternedconductive layer 20 as shown. A supplemental insulating layer according to embodiments may include the same material as the one used for the starting insulating layer as noted above. According to an embodiment, provision of a supplemental insulating layer according to embodiments may include laminating the supplemental insulating layer onto a corresponding patterned conductive layer. - Referring next to
FIGS. 9 g and 10 g, method embodiments include providing a second set ofconductive vias 30 through the first supplemental insulatinglayer 26, and providing a supplemental patternedconductive layer 36 onto an exposedside 32 of the supplemental insulatinglayer 26, where the second set ofconductive vias 30 contact the first patternedconductive layer 19 on one side thereof, and the supplemental patternedconductive layer 36 at another side thereof. Providing the second set ofconductive vias 30 may include laser drilling a second set of viaopenings 34 through the supplemental insulatinglayer 26, the second set of via openings extending to the first patterned conductive layer. Thereafter, the second set of viaopenings 34 may be filled with a conductive material such as copper, silver and/or nickel, in order to provide the second set ofconductive vias 30. Laser drilling may be accomplished for example in the same manner as described above in relation toFIGS. 9 b and 10 b, and the filling of the conductive material into the second set of via openings may further be accomplished, for the embodiment ofFIG. 9 g, for example in the same manner as described above with respect toFIG. 9 c (by way of fast electroless plating), and for the embodiment ofFIG. 10 g, for example in the same manner as described above with respect toFIG. 10 c (by way of selective fast electroless plating). Provision of the supplemental patternedconductive layer 36 may be accomplished, for the embodiment ofFIG. 9 g, for example in the same manner as described above with respect toFIG. 9 e (by way of lamination of a conductive layer followed by etching of the same), and for the embodiment ofFIG. 10 g, for example in the same manner as described above with respect toFIG. 10 e (by using a semi-additive process). - Optionally, referring still to
FIGS. 9 g and 10 g, according to a method embodiment, the supplemental insulatinglayer 26 is a first supplemental insulating layer, and the method embodiment includes providing a second supplemental insulatinglayer 28 onto the second patternedconductive layer 20, providing a third set ofconductive vias 38, and providing a second supplemental patternedconductive layer 40 onto an exposed side 41 of the second supplemental insulatinglayer 28. According to the latter method embodiment, the third set ofconductive vias 38 contacts the second supplemental patternedconductive layer 28 at one side thereof, and the second patternedconductive layer 20 at another side thereof. Provision of the second supplemental insulatinglayer 28 may be effected according to an embodiment in the same manner as described for the first supplemental insulatinglayer 26 above with respect toFIGS. 9 f and 10 f. In addition, the provision of the third set ofconductive vias 38 may be accomplished, for the embodiment ofFIG. 9 g, for example in the same manner as described above for the first set ofconductive vias 18 with respect toFIG. 9 c (fast electroless plating), and for the embodiment ofFIG. 10 g, for example in the same manner as described for the first set ofconductive vias 18 above with respect toFIG. 10 c (by way of selective fast electroless plating). - According to embodiments, the laser drilling of via openings results in laser drilled via openings which may exhibit, as shown in
FIGS. 9 h and 10 h, a conical configuration, and further in eventual conductive vias which may extend sequentially in each given layer of a substrate core structure, as opposed to extending through a total thickness of the substrate core structure as in the case of prior art printed through holes. The above layer-by-layer or sequentially disposed configuration of conductive vias according to embodiments allows the provision of staggered vias as shown. - Although the substrate core structure structures shown in
FIGS. 9 h and 10 h, respectively, show only two supplemental insulating layers, three sets of conductive vias, and four sets of patterned conductive layers, it is noted that embodiments are not so limited, and include within their ambit the provision of as many supplemental insulating layers, corresponding sets of conductive vias, and corresponding sets of patterned conductive layers as necessary in order to arrive at a desired substrate core structure structure. The provision of the various elements noted above, including the supplemental insulating layers, sets of conductive vias, and sets of patterned conductive layers may be effected as noted above either with respect to the first embodiment as shown inFIGS. 9 a-9 h, or with respect to the second embodiment as shown inFIGS. 10 a-10 h. In addition, although the second embodiment is described in relation to a preference of providing an initialconductive layer 12 onto the starting insulatinglayer 10, the second embodiment is not so limited, and includes the shown process flow inFIGS. 10 a-10 h without the initialconductive layer 12. - Referring now to
FIGS. 9 h and 10 h, a method embodiment may include subjecting a combination of the starting insulatinglayer 10, the first set ofconductive vias 18, the first patternedconductive layer 19, the second patternedconductive layer 20, the one or more supplemental insulatinglayers conductive vias 30 and 38), and the one or more supplemental patternedconductive layers - Advantageously, embodiments provide a method to enable building multilayer substrate core structures using laser drilled via openings optionally metallized by fast electroless metal plating. Embodiments address a new multilayer substrate core structures and a method of building the same in which the costly plated through hole structure is replaced with the low cost laser drilled microvias. Depending on the need for patterning fineness, two different method embodiments are proposed, as described above in relation to
FIGS. 9 a-9 i on the one hand, and toFIGS. 10 a-10 i on the other hand. The first method embodiment as described by way of example in relation toFIGS. 9 a-9 i correspond to subtractive patterning for thick conductive layers such as thick copper (for example copper having a thickness between about 50 and about 70 microns) and for moderate line and space features (for example, line and space features above about 30 microns). The second method embodiment as described by way of example in relation toFIGS. 10 a-10 i corresponds to a semi additive patterning (SAP) process for thin conductive layers such as thin copper (e.g., a copper conductive layer having a thickness of less than about 2 microns) for fine line and space features (for example, line and space features less than about 30 microns). Embodiments effectively address among other things the problems of: (1) high cost prior art substrate core structures which use mechanical drilling technology by replacing the costly mechanically drilled plated through holes with low cost laser drilled microvias; (2) the need to laser drill through conductive layers such as copper by achieving low cost, shorter processing times, and high reliability of a laser drilled via core structure that obviates the need to laser drill through any of the conductive layers. An embodiment provides a lower cost method of fabrication than prior art methods by not only replacing the prior art plated through hole regime with laser drilled microvias, but also by reducing the core dielectric material thickness (by virtue of the generally reduced via dimensions and line and space features possible according to embodiments). In addition, laser drilling according to embodiments allows for higher starting insulating layer connection density as compared with prior art structures, owing to small via sizes and pitches, thus allowing for smaller sized vias and smaller pitches, in this way leading to an improved design and to scalable miniaturization at low cost. Laser drilling features high alignment accuracy (15 um POR), and through-put (up to about 2000 vias/sec), a wide range of possible via sizes (such as between about 50 microns and about 300 microns), and low cost (about 2 cents per one thousand vias). The combination of high alignment accuracy and small via size make possible via pitches as low as about 150 microns, those pitches being much less than typically plated through hole pitches of about 400 microns. Moreover, embodiments lead to substrate core structure substrate structures having potentially smaller form factors (by virtue of potentially smaller pitches, pad sizes, via dimensions), and a potentially smaller z-height (by virtue of potentially finer routing through the thickness of the insulating layers, which may lead to thinner insulating layers and/or the use of a smaller amount of insulating layers). Embodiments further make possible flexible core routing, to the extent that embodiments are not limited to vias which extend straight through the thickness of the totality of the insulating layers (as in the case of plated through holes of the prior art), but rather make possible a large number of possibilities with respect to through core routing configurations because the vias are provided in each of the insulating layers separately. The above advantageously leads to an improved substrate core structure design and potential performance benefits as compared with the prior art. In addition, via filling according to an embodiment using selective fast electroless copper plating on copper pads but not on dielectric areas may be advantageously enabled by a proper choice of catalysts so that only the copper area is seeded with the catalyst. While conventional electroless plating speeds, such as electroless copper plating speeds, can be slow (about 4 to about 5 microns/hour), high speed or fast electroless plating solutions, such as fast electroless copper plating solutions, can allow plating at a speed as high as 2 microns per hour. Additionally, according to an embodiment, the use of a hot press advantageously allows the formation of a reliable metallurgical bond between the vias (whether copper, nickel or silver) and the pad, such as a copper pad. - Referring to
FIG. 11 , there is illustrated one of manypossible systems 900 in which embodiments of the present invention may be used. In one embodiment, theelectronic assembly 1000 may include a substrate core structure structure, such asstructure 100 ofFIG. 9 h orstructure 200 ofFIG. 10 h.Assembly 1000 may further include a microprocessor. In an alternate embodiment, theelectronic assembly 1000 may include an application specific IC (ASIC). Integrated circuits found in chipsets (e.g., graphics, sound, and control chipsets) may also be packaged in accordance with embodiments of this invention. - For the embodiment depicted by
FIG. 11 , thesystem 900 may also include amain memory 1002, agraphics processor 1004, amass storage device 1006, and/or an input/output module 1008 coupled to each other by way of abus 1010, as shown. Examples of thememory 1002 include but are not limited to static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of themass storage device 1006 include but are not limited to a hard disk drive, a compact disk drive (CD), a digital versatile disk drive (DVD), and so forth. Examples of the input/output module 1008 include but are not limited to a keyboard, cursor control arrangements, a display, a network interface, and so forth. Examples of thebus 1010 include but are not limited to a peripheral control interface (PCI) bus, and Industry Standard Architecture (ISA) bus, and so forth. In various embodiments, the system 90 may be a wireless mobile phone, a personal digital assistant, a pocket PC, a tablet PC, a notebook PC, a desktop computer, a set-top box, a media-center PC, a DVD player, and a server. - The various embodiments described above have been presented by way of example and not by way of limitation. Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many variations thereof are possible without departing from the spirit or scope thereof.
Claims (8)
1. An assembly comprising:
a package substrate, the package substrate including
a starting insulating layer having a first side and an opposing second side, the starting insulating layer including a number of vias extending from the first side to the second side, each of the vias in the starting insulating layer including a conical shape and filled with a material including copper;
a first patterned conductive layer disposed on the first side of the starting insulating layer, the first patterned conductive layer comprised of a material including copper, at least one of the vias in the starting insulating layer contacting the first patterned conductive layer;
a second patterned conductive layer disposed on the second side of the starting insulating layer, the second patterned conductive layer comprised of a material including copper, at least one of the vias in the starting insulating layer contacting the second patterned conductive layer;
a first insulating layer disposed on the first patterned conductive layer and exposed portions of the first side of the starting insulating layer, the first insulating layer including a first set of vias, each via of the first set having a conical shape and filled with a material including copper;
a third patterned conductive layer disposed on the first insulating layer, the third patterned conductive layer comprised of a material including copper, wherein at least one via of the first set contacts the first and third patterned conductive layers;
a second insulating layer disposed on the second patterned conductive layer and exposed portions of the second side of the starting insulating layer, the second insulating layer including a second set of vias, each via of the second set having a conical shape and filled with a material including copper; and
a fourth patterned conductive layer disposed on the second insulating layer, the fourth patterned conductive layer comprised of a material including copper, wherein at least one via of the second set contacts the second and fourth patterned conductive layers; and
an integrated circuit (IC) device coupled with the package substrate.
2. The assembly of claim 1 , wherein at least one via in the starting insulating layer, at least one via of the first set, and at least one via of the second set are aligned.
3. The assembly of claim 1 , wherein at least one of the vias in the starting insulating layer includes a diameter in a range between about 50 and 300 microns.
4. The assembly of claim 1 , wherein a pitch of the vias in the starting insulating layer is in a range of about 150 microns or greater.
5. The assembly of claim 1 , wherein the IC device includes a processing system.
6. The assembly of claim 5 , further comprising a memory device coupled with the package substrate.
7. The assembly of claim 1 , wherein the conical shape included in each via in the starting insulating layer is formed by laser drilling.
8. The assembly of claim 7 , wherein the vias in the starting insulating layer are formed from a first direction.
Priority Applications (1)
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US12/941,899 US20110058340A1 (en) | 2007-06-28 | 2010-11-08 | Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method |
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US11/769,852 US8877565B2 (en) | 2007-06-28 | 2007-06-28 | Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method |
US12/941,899 US20110058340A1 (en) | 2007-06-28 | 2010-11-08 | Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method |
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US12/941,899 Abandoned US20110058340A1 (en) | 2007-06-28 | 2010-11-08 | Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method |
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US (2) | US8877565B2 (en) |
JP (2) | JP5595269B2 (en) |
KR (1) | KR101134714B1 (en) |
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TW (1) | TWI417011B (en) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180308792A1 (en) * | 2015-09-25 | 2018-10-25 | Vivek Raghunathan | Thin electronic package elements using laser spallation |
US20190037693A1 (en) * | 2017-07-27 | 2019-01-31 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of fabricating the same |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4992428B2 (en) * | 2004-09-24 | 2012-08-08 | イビデン株式会社 | Plating method and plating apparatus |
US8440916B2 (en) * | 2007-06-28 | 2013-05-14 | Intel Corporation | Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method |
US8877565B2 (en) * | 2007-06-28 | 2014-11-04 | Intel Corporation | Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method |
US20090224410A1 (en) * | 2008-03-07 | 2009-09-10 | Advanced Inquiry Systems, Inc. | Wafer translator having a silicon core fabricated with printed circuit board manufacturing techniques |
US7791174B2 (en) * | 2008-03-07 | 2010-09-07 | Advanced Inquiry Systems, Inc. | Wafer translator having a silicon core isolated from signal paths by a ground plane |
US8389862B2 (en) | 2008-10-07 | 2013-03-05 | Mc10, Inc. | Extremely stretchable electronics |
US8886334B2 (en) * | 2008-10-07 | 2014-11-11 | Mc10, Inc. | Systems, methods, and devices using stretchable or flexible electronics for medical applications |
US9123614B2 (en) | 2008-10-07 | 2015-09-01 | Mc10, Inc. | Methods and applications of non-planar imaging arrays |
JP5646492B2 (en) | 2008-10-07 | 2014-12-24 | エムシー10 インコーポレイテッドMc10,Inc. | Stretchable integrated circuit and device with sensor array |
US8097926B2 (en) | 2008-10-07 | 2012-01-17 | Mc10, Inc. | Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy |
US20110218756A1 (en) * | 2009-10-01 | 2011-09-08 | Mc10, Inc. | Methods and apparatus for conformal sensing of force and/or acceleration at a person's head |
US9723122B2 (en) | 2009-10-01 | 2017-08-01 | Mc10, Inc. | Protective cases with integrated electronics |
US8035218B2 (en) * | 2009-11-03 | 2011-10-11 | Intel Corporation | Microelectronic package and method of manufacturing same |
US8207453B2 (en) * | 2009-12-17 | 2012-06-26 | Intel Corporation | Glass core substrate for integrated circuit devices and methods of making the same |
US9420707B2 (en) * | 2009-12-17 | 2016-08-16 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
US8127979B1 (en) | 2010-09-25 | 2012-03-06 | Intel Corporation | Electrolytic depositon and via filling in coreless substrate processing |
US8552564B2 (en) | 2010-12-09 | 2013-10-08 | Intel Corporation | Hybrid-core through holes and vias |
EP2712491B1 (en) | 2011-05-27 | 2019-12-04 | Mc10, Inc. | Flexible electronic structure |
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WO2013133827A1 (en) | 2012-03-07 | 2013-09-12 | Intel Corporation | Glass clad microelectronic substrate |
US9226402B2 (en) | 2012-06-11 | 2015-12-29 | Mc10, Inc. | Strain isolation structures for stretchable electronics |
JP2015521894A (en) | 2012-07-05 | 2015-08-03 | エムシー10 インコーポレイテッドMc10,Inc. | Catheter device including flow sensing |
US9295842B2 (en) | 2012-07-05 | 2016-03-29 | Mc10, Inc. | Catheter or guidewire device including flow sensing and use thereof |
US9001520B2 (en) | 2012-09-24 | 2015-04-07 | Intel Corporation | Microelectronic structures having laminated or embedded glass routing structures for high density packaging |
JP2016500869A (en) | 2012-10-09 | 2016-01-14 | エムシー10 インコーポレイテッドMc10,Inc. | Conformal electronic circuit integrated with clothing |
US9171794B2 (en) | 2012-10-09 | 2015-10-27 | Mc10, Inc. | Embedding thin chips in polymer |
US20140123487A1 (en) * | 2012-11-08 | 2014-05-08 | Boardtek Electronics Corporation | Printed circuit board manufacturing method |
US9661760B2 (en) * | 2012-11-08 | 2017-05-23 | Boardtek Electronics Corporation | Printed circuit board and manufacturing method thereof |
US9706647B2 (en) | 2013-05-14 | 2017-07-11 | Mc10, Inc. | Conformal electronics including nested serpentine interconnects |
US9372123B2 (en) | 2013-08-05 | 2016-06-21 | Mc10, Inc. | Flexible temperature sensor including conformable electronics |
JP2016532468A (en) | 2013-10-07 | 2016-10-20 | エムシー10 インコーポレイテッドMc10,Inc. | Conformal sensor system for detection and analysis |
US9949691B2 (en) | 2013-11-22 | 2018-04-24 | Mc10, Inc. | Conformal sensor systems for sensing and analysis of cardiac activity |
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EP3114911B1 (en) | 2014-03-04 | 2023-05-03 | Medidata Solutions, Inc. | Multi-part flexible encapsulation housing for electronic devices |
US9899330B2 (en) | 2014-10-03 | 2018-02-20 | Mc10, Inc. | Flexible electronic circuits with embedded integrated circuit die |
US10297572B2 (en) | 2014-10-06 | 2019-05-21 | Mc10, Inc. | Discrete flexible interconnects for modules of integrated circuits |
USD781270S1 (en) | 2014-10-15 | 2017-03-14 | Mc10, Inc. | Electronic device having antenna |
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EP3258837A4 (en) | 2015-02-20 | 2018-10-10 | Mc10, Inc. | Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation |
US10398343B2 (en) | 2015-03-02 | 2019-09-03 | Mc10, Inc. | Perspiration sensor |
WO2017015000A1 (en) | 2015-07-17 | 2017-01-26 | Mc10, Inc. | Conductive stiffener, method of making a conductive stiffener, and conductive adhesive and encapsulation layers |
WO2017031129A1 (en) | 2015-08-19 | 2017-02-23 | Mc10, Inc. | Wearable heat flux devices and methods of use |
WO2017059215A1 (en) | 2015-10-01 | 2017-04-06 | Mc10, Inc. | Method and system for interacting with a virtual environment |
WO2017062508A1 (en) | 2015-10-05 | 2017-04-13 | Mc10, Inc. | Method and System for Neuromodulation and Stimulation |
WO2017147053A1 (en) | 2016-02-22 | 2017-08-31 | Mc10, Inc. | System, device, and method for coupled hub and sensor node on-body acquisition of sensor information |
US10277386B2 (en) | 2016-02-22 | 2019-04-30 | Mc10, Inc. | System, devices, and method for on-body data and power transmission |
WO2017184705A1 (en) | 2016-04-19 | 2017-10-26 | Mc10, Inc. | Method and system for measuring perspiration |
US10447347B2 (en) | 2016-08-12 | 2019-10-15 | Mc10, Inc. | Wireless charger and high speed data off-loader |
CN115088394A (en) * | 2019-12-04 | 2022-09-20 | Lg伊诺特有限公司 | Printed circuit board |
Citations (80)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4299873A (en) * | 1979-04-06 | 1981-11-10 | Hitachi, Ltd. | Multilayer circuit board |
US5231751A (en) * | 1991-10-29 | 1993-08-03 | International Business Machines Corporation | Process for thin film interconnect |
US5543182A (en) * | 1993-03-18 | 1996-08-06 | Atotech Usa, Inc. | Self-accelerating and replenishing non-formaldehyde immersion coating method |
US5710071A (en) * | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US5780143A (en) * | 1995-03-01 | 1998-07-14 | Tokuyama Corporation | Circuit board |
US5826330A (en) * | 1995-12-28 | 1998-10-27 | Hitachi Aic Inc. | Method of manufacturing multilayer printed wiring board |
US6121553A (en) * | 1997-03-03 | 2000-09-19 | Hitachi Chemical Company, Ltd. | Circuit boards using heat resistant resin for adhesive layers |
US6165892A (en) * | 1998-07-31 | 2000-12-26 | Kulicke & Soffa Holdings, Inc. | Method of planarizing thin film layers deposited over a common circuit base |
US6165820A (en) * | 1994-12-22 | 2000-12-26 | Pace; Benedict G. | Package for electronic devices |
US6211485B1 (en) * | 1996-06-05 | 2001-04-03 | Larry W. Burgess | Blind via laser drilling system |
US6242282B1 (en) * | 1999-10-04 | 2001-06-05 | General Electric Company | Circuit chip package and fabrication method |
US6254971B1 (en) * | 1996-06-07 | 2001-07-03 | Asahi Kasei Kabushiki Kaisha | Resin-having metal foil for multilayered wiring board, process for producing the same, multilayered wiring board, and electronic device |
US6310391B1 (en) * | 1998-06-23 | 2001-10-30 | Nitto Denko Corporation | Mounted structure of circuit board and multi-layer circuit board therefor |
US6320140B1 (en) * | 1996-06-14 | 2001-11-20 | Ibiden Co., Ltd. | One-sided circuit board for multi-layer printed wiring board, multi-layer printed wiring board, and method of its production |
US6353999B1 (en) * | 1999-03-09 | 2002-03-12 | Unimicron Taiwan Corp. | Method of making mechanical-laser structure |
US6424282B1 (en) * | 2001-03-09 | 2002-07-23 | Sony Corporation | Method and apparatus for noise compensation in digital to analog converters |
US20020100608A1 (en) * | 1999-05-27 | 2002-08-01 | Hoya Corporation | Multilayer printed wiring board and a process of producing same |
US20020108776A1 (en) * | 2001-02-13 | 2002-08-15 | Fujitsu Limited | Multilayer printed circuit board and method of making the same |
US20020117743A1 (en) * | 2000-12-27 | 2002-08-29 | Matsushita Electric Industrial Co., Ltd. | Component built-in module and method for producing the same |
US20030001287A1 (en) * | 2001-06-27 | 2003-01-02 | Intel Corporation | Flexible tape electronics packaging |
US6585811B2 (en) * | 1999-01-15 | 2003-07-01 | Imec Vzw | Method for depositing copper or a copper alloy |
US6590165B1 (en) * | 1997-02-03 | 2003-07-08 | Ibiden Co., Ltd. | Printed wiring board having throughole and annular lands |
US20030136577A1 (en) * | 2002-01-24 | 2003-07-24 | Fujitsu Limited | Circuit board and method for fabricating the same, and electronic device |
US20030135994A1 (en) * | 2002-01-18 | 2003-07-24 | Fujitsu Limited | Printed circuit board and manufacturing method therefor |
US6613413B1 (en) * | 1999-04-26 | 2003-09-02 | International Business Machines Corporation | Porous power and ground planes for reduced PCB delamination and better reliability |
US6631558B2 (en) * | 1996-06-05 | 2003-10-14 | Laservia Corporation | Blind via laser drilling system |
US20030222340A1 (en) * | 2002-05-30 | 2003-12-04 | Koji Kondo | Enhancement of current-carrying capacity of a multilayer circuit board |
US20040031147A1 (en) * | 2001-07-02 | 2004-02-19 | Toshiyuki Kawashima | Method for manufacturing multilayer wiring board |
US20040080052A1 (en) * | 2002-10-24 | 2004-04-29 | Advanced Semiconductor Engineering, Inc. | Circuit substrate and fabrication method thereof |
US6739040B1 (en) * | 1999-10-28 | 2004-05-25 | Ajinomoto Co., Inc. | Method of manufacturing multilayered printed wiring board using adhesive film |
US20040212030A1 (en) * | 2003-04-22 | 2004-10-28 | Ibiden Co., Ltd. | Substrate for mounting IC chip, multilayered printed circuit board, and device for optical communication |
US20040227227A1 (en) * | 2003-05-15 | 2004-11-18 | Fujitsu Limited | Aerosol deposition process |
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
US20050098868A1 (en) * | 2003-11-12 | 2005-05-12 | Advanced Semiconductor Engineering, Inc. | Multi-chips module assembly package |
US20050136646A1 (en) * | 2003-12-18 | 2005-06-23 | Endicott Interconnect Technologies, Inc. | Method of providing printed circuit board with conductive holes and board resulting therefrom |
US20050142033A1 (en) * | 2003-11-04 | 2005-06-30 | Meso Scale Technologies, Llc. | Modular assay plates, reader systems and methods for test measurements |
US6930987B1 (en) * | 1999-06-29 | 2005-08-16 | Sony Corporation | Communication device communication method, and communication terminal device |
US20050185382A1 (en) * | 2002-10-29 | 2005-08-25 | Kiyoshi Ooi | Substrate for carrying a semiconductor chip and a manufacturing method thereof |
US20050191770A1 (en) * | 2004-02-27 | 2005-09-01 | Schieck Brian S. | Flip chip semiconductor die internal signal access system and method |
US20050218502A1 (en) * | 2004-03-31 | 2005-10-06 | Shinko Electric Industries Co., Ltd. | Capacitor-mounted wiring board and method of manufacturing the same |
US20050217893A1 (en) * | 2004-03-30 | 2005-10-06 | Setsuo Noguchi | Printed circuit board and manufacturing method thereof |
US20050218451A1 (en) * | 2004-03-31 | 2005-10-06 | Casio Computer Co., Ltd. | Semiconductor device incorporating semiconductor constructing body and method of fabricating the same |
US20050236177A1 (en) * | 2002-08-09 | 2005-10-27 | Ibiden Co., Ltd | Multilayer printed wiring board |
US20060001166A1 (en) * | 2004-06-30 | 2006-01-05 | Yusuke Igarashi | Circuit device and manufacturing method thereof |
US20060057340A1 (en) * | 2002-05-31 | 2006-03-16 | Tatsuta Electric Wire & Cable Co., | Conductive paste multilayered board including the conductive paste and process for producing the same |
US20060060956A1 (en) * | 2004-09-22 | 2006-03-23 | Tanikella Ravindra V | Materials, structures and methods for microelectronic packaging |
US20060125072A1 (en) * | 2004-12-14 | 2006-06-15 | Casio Computer Co., Ltd. | Semiconductor device having laminated semiconductor constructions and a manufacturing method thereof |
US20060158865A1 (en) * | 2002-08-23 | 2006-07-20 | Tadahiro Ohmi | Circuit board, electronic device employing circuit board, and mehtod of producing circuit board |
US20060178007A1 (en) * | 2005-02-04 | 2006-08-10 | Hiroki Nakamura | Method of forming copper wiring layer |
US20060185141A1 (en) * | 2002-12-11 | 2006-08-24 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board and manufacture method thereof |
US20060220167A1 (en) * | 2005-03-31 | 2006-10-05 | Intel Corporation | IC package with prefabricated film capacitor |
US20060226537A1 (en) * | 2004-12-06 | 2006-10-12 | International Business Machines Corporation | Multilayer circuit board and method of manufacturing the same |
WO2007010758A1 (en) * | 2005-07-15 | 2007-01-25 | Matsushita Electric Industrial Co., Ltd. | Wiring board, wiring material, copper-clad laminate, and wiring board fabrication method |
US20070023202A1 (en) * | 2005-07-29 | 2007-02-01 | Sanyo Electric Co., Ltd. | Circuit board and circuit apparatus using the same |
US20070029106A1 (en) * | 2003-04-07 | 2007-02-08 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US7178234B2 (en) * | 1999-10-26 | 2007-02-20 | Ibiden Co., Ltd. | Method of manufacturing multi-layer printed circuit board |
US20070044999A1 (en) * | 2005-08-30 | 2007-03-01 | Kiyoshi Shibata | Circuit board and circuit apparatus using the same |
US20070048447A1 (en) * | 2005-08-31 | 2007-03-01 | Alan Lee | System and method for forming patterned copper lines through electroless copper plating |
US20070096328A1 (en) * | 2005-07-07 | 2007-05-03 | Ibiden Co., Ltd. | Multilayered printed wiring board |
US7230188B1 (en) * | 1998-09-14 | 2007-06-12 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
US20070132098A1 (en) * | 2002-07-18 | 2007-06-14 | Takeshi Sano | Elastic conductive resin, and electronic device including elastic conductive bumps made of the elastic conductive resin |
US20070148420A1 (en) * | 2005-12-28 | 2007-06-28 | Intel Corporation | Method of making a substrate using laser assisted metallization and patterning with electroless plating without electrolytic plating |
US20070181994A1 (en) * | 2004-03-03 | 2007-08-09 | Shinko Electric Industries Co., Ltd. | Circuit board manufacturing method and circuit board |
US20070200211A1 (en) * | 2006-02-15 | 2007-08-30 | Shinko Electric Industries Co., Ltd. | Multilayer wiring substrate and method of connecting the same |
US20070273047A1 (en) * | 2004-12-15 | 2007-11-29 | Ibiden Co., Ltd | Printed wiring board and manufacturing method thereof |
US20070281471A1 (en) * | 2006-06-01 | 2007-12-06 | Dror Hurwitz | Advanced Multilayered Coreless Support Structures and their Fabrication |
US20080052904A1 (en) * | 2004-07-28 | 2008-03-06 | Reinhard Schneider | Method Of Manufacturing An Electronic Circuit Assembly |
US7348857B1 (en) * | 2005-02-28 | 2008-03-25 | Marvell Semiconductor Israel Ltd. | Monitoring and compensating for real time local circuit speed in an integrated circuit |
US7371974B2 (en) * | 2001-03-14 | 2008-05-13 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US20080121417A1 (en) * | 2006-11-07 | 2008-05-29 | Unimicron Technology Corp. | Package substrate having embedded capacitor |
US20080247704A1 (en) * | 2007-04-04 | 2008-10-09 | Ibiden Co., Ltd | Package substrate and device for optical communication |
US20080264681A1 (en) * | 2004-10-14 | 2008-10-30 | Ibiden Co., Ltd. | Printed Wiring Board and Method for Manufacturing Printed Wiring Board |
US20080285910A1 (en) * | 2007-05-18 | 2008-11-20 | Ibiden Co., Ltd. | Photoelectric circuit board and device for optical communication |
US20080289866A1 (en) * | 2004-12-28 | 2008-11-27 | Ngk Spark Plug Co., Ltd. | Wiring Board and Wiring Board Manufacturing Method |
US20090002958A1 (en) * | 2007-06-28 | 2009-01-01 | Yonggang Li | Method of Forming a Substrate Core Structure Using Microvia Laser Drilling and Conductive Layer Pre-Patterning And Substrate Core Structure Formed According to the Method |
US20090001550A1 (en) * | 2007-06-28 | 2009-01-01 | Yonggang Li | Method of Forming a Multilayer Substrate Core Structure Using Sequential Microvia Laser Drilling And Substrate Core Structure Formed According to the Method |
US20090091014A1 (en) * | 2003-01-22 | 2009-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Device Having a Flexible Printed Circuit |
US7683458B2 (en) * | 2004-09-02 | 2010-03-23 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
US7696613B2 (en) * | 2005-09-07 | 2010-04-13 | Shinko Electric Industries Co., Ltd. | Multilayered wiring substrate including wiring layers and insulating layers and method of manufacturing the same |
US7764987B2 (en) * | 2004-09-02 | 2010-07-27 | Biotronik Crm Patent Ag | Signal processing apparatus for physiological signals |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6432657A (en) | 1987-07-29 | 1989-02-02 | Hitachi Chemical Co Ltd | High heat-dissipating semiconductor element loader |
JP2001193743A (en) | 1999-11-02 | 2001-07-17 | Nsk Ltd | Rolling bearing |
TW468050B (en) | 2000-06-07 | 2001-12-11 | Macronix Int Co Ltd | Peak detector |
US6664483B2 (en) * | 2001-05-15 | 2003-12-16 | Intel Corporation | Electronic package with high density interconnect and associated methods |
JP2003069226A (en) | 2001-08-23 | 2003-03-07 | Toppan Printing Co Ltd | Board for semiconductor device and its manufacturing method |
JP4153328B2 (en) | 2003-02-25 | 2008-09-24 | 日本シイエムケイ株式会社 | Manufacturing method of multilayer printed wiring board |
JP2005005417A (en) | 2003-06-11 | 2005-01-06 | Shinko Seisakusho:Kk | Multilayer printed wiring board and its manufacturing method |
JP2005123397A (en) | 2003-10-16 | 2005-05-12 | Mitsubishi Electric Corp | Method for manufacturing multilayer printed wiring board |
JP2007081157A (en) * | 2005-09-14 | 2007-03-29 | Shinko Electric Ind Co Ltd | Multilevel wiring substrate and its manufacturing method |
KR100722599B1 (en) | 2005-09-26 | 2007-05-28 | 삼성전기주식회사 | All layer inner via hall printed circuit board and the manufacturing method that utilize the fill plating |
KR101232139B1 (en) | 2005-12-13 | 2013-02-12 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device |
US7674987B2 (en) | 2007-03-29 | 2010-03-09 | Ibiden Co., Ltd. | Multilayer printed circuit board |
-
2007
- 2007-06-28 US US11/769,852 patent/US8877565B2/en active Active
-
2008
- 2008-06-23 WO PCT/US2008/067847 patent/WO2009006065A1/en active Application Filing
- 2008-06-23 JP JP2010515011A patent/JP5595269B2/en active Active
- 2008-06-23 CN CN200880022291A patent/CN101690436A/en active Pending
- 2008-06-23 KR KR1020097027069A patent/KR101134714B1/en active IP Right Grant
- 2008-06-25 TW TW097123727A patent/TWI417011B/en active
-
2010
- 2010-11-08 US US12/941,899 patent/US20110058340A1/en not_active Abandoned
-
2014
- 2014-06-10 JP JP2014119461A patent/JP2014195117A/en active Pending
Patent Citations (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4299873A (en) * | 1979-04-06 | 1981-11-10 | Hitachi, Ltd. | Multilayer circuit board |
US5231751A (en) * | 1991-10-29 | 1993-08-03 | International Business Machines Corporation | Process for thin film interconnect |
US5543182A (en) * | 1993-03-18 | 1996-08-06 | Atotech Usa, Inc. | Self-accelerating and replenishing non-formaldehyde immersion coating method |
US6165820A (en) * | 1994-12-22 | 2000-12-26 | Pace; Benedict G. | Package for electronic devices |
US5780143A (en) * | 1995-03-01 | 1998-07-14 | Tokuyama Corporation | Circuit board |
US5710071A (en) * | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US5826330A (en) * | 1995-12-28 | 1998-10-27 | Hitachi Aic Inc. | Method of manufacturing multilayer printed wiring board |
US6631558B2 (en) * | 1996-06-05 | 2003-10-14 | Laservia Corporation | Blind via laser drilling system |
US6211485B1 (en) * | 1996-06-05 | 2001-04-03 | Larry W. Burgess | Blind via laser drilling system |
US6254971B1 (en) * | 1996-06-07 | 2001-07-03 | Asahi Kasei Kabushiki Kaisha | Resin-having metal foil for multilayered wiring board, process for producing the same, multilayered wiring board, and electronic device |
US6320140B1 (en) * | 1996-06-14 | 2001-11-20 | Ibiden Co., Ltd. | One-sided circuit board for multi-layer printed wiring board, multi-layer printed wiring board, and method of its production |
US6590165B1 (en) * | 1997-02-03 | 2003-07-08 | Ibiden Co., Ltd. | Printed wiring board having throughole and annular lands |
US6121553A (en) * | 1997-03-03 | 2000-09-19 | Hitachi Chemical Company, Ltd. | Circuit boards using heat resistant resin for adhesive layers |
US6310391B1 (en) * | 1998-06-23 | 2001-10-30 | Nitto Denko Corporation | Mounted structure of circuit board and multi-layer circuit board therefor |
US6165892A (en) * | 1998-07-31 | 2000-12-26 | Kulicke & Soffa Holdings, Inc. | Method of planarizing thin film layers deposited over a common circuit base |
US7230188B1 (en) * | 1998-09-14 | 2007-06-12 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
US6585811B2 (en) * | 1999-01-15 | 2003-07-01 | Imec Vzw | Method for depositing copper or a copper alloy |
US6353999B1 (en) * | 1999-03-09 | 2002-03-12 | Unimicron Taiwan Corp. | Method of making mechanical-laser structure |
US6613413B1 (en) * | 1999-04-26 | 2003-09-02 | International Business Machines Corporation | Porous power and ground planes for reduced PCB delamination and better reliability |
US20020100608A1 (en) * | 1999-05-27 | 2002-08-01 | Hoya Corporation | Multilayer printed wiring board and a process of producing same |
US6930987B1 (en) * | 1999-06-29 | 2005-08-16 | Sony Corporation | Communication device communication method, and communication terminal device |
US6242282B1 (en) * | 1999-10-04 | 2001-06-05 | General Electric Company | Circuit chip package and fabrication method |
US7178234B2 (en) * | 1999-10-26 | 2007-02-20 | Ibiden Co., Ltd. | Method of manufacturing multi-layer printed circuit board |
US6739040B1 (en) * | 1999-10-28 | 2004-05-25 | Ajinomoto Co., Inc. | Method of manufacturing multilayered printed wiring board using adhesive film |
US20020117743A1 (en) * | 2000-12-27 | 2002-08-29 | Matsushita Electric Industrial Co., Ltd. | Component built-in module and method for producing the same |
US7198996B2 (en) * | 2000-12-27 | 2007-04-03 | Matsushita Electric Industrial Co., Ltd. | Component built-in module and method for producing the same |
US20020108776A1 (en) * | 2001-02-13 | 2002-08-15 | Fujitsu Limited | Multilayer printed circuit board and method of making the same |
US6424282B1 (en) * | 2001-03-09 | 2002-07-23 | Sony Corporation | Method and apparatus for noise compensation in digital to analog converters |
US7371974B2 (en) * | 2001-03-14 | 2008-05-13 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US20030001287A1 (en) * | 2001-06-27 | 2003-01-02 | Intel Corporation | Flexible tape electronics packaging |
US20040031147A1 (en) * | 2001-07-02 | 2004-02-19 | Toshiyuki Kawashima | Method for manufacturing multilayer wiring board |
US20030135994A1 (en) * | 2002-01-18 | 2003-07-24 | Fujitsu Limited | Printed circuit board and manufacturing method therefor |
US20030136577A1 (en) * | 2002-01-24 | 2003-07-24 | Fujitsu Limited | Circuit board and method for fabricating the same, and electronic device |
US20030222340A1 (en) * | 2002-05-30 | 2003-12-04 | Koji Kondo | Enhancement of current-carrying capacity of a multilayer circuit board |
US20060057340A1 (en) * | 2002-05-31 | 2006-03-16 | Tatsuta Electric Wire & Cable Co., | Conductive paste multilayered board including the conductive paste and process for producing the same |
US20070132098A1 (en) * | 2002-07-18 | 2007-06-14 | Takeshi Sano | Elastic conductive resin, and electronic device including elastic conductive bumps made of the elastic conductive resin |
US20050236177A1 (en) * | 2002-08-09 | 2005-10-27 | Ibiden Co., Ltd | Multilayer printed wiring board |
US20060158865A1 (en) * | 2002-08-23 | 2006-07-20 | Tadahiro Ohmi | Circuit board, electronic device employing circuit board, and mehtod of producing circuit board |
US20040080052A1 (en) * | 2002-10-24 | 2004-04-29 | Advanced Semiconductor Engineering, Inc. | Circuit substrate and fabrication method thereof |
US20050185382A1 (en) * | 2002-10-29 | 2005-08-25 | Kiyoshi Ooi | Substrate for carrying a semiconductor chip and a manufacturing method thereof |
US20060185141A1 (en) * | 2002-12-11 | 2006-08-24 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board and manufacture method thereof |
US20090091014A1 (en) * | 2003-01-22 | 2009-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Device Having a Flexible Printed Circuit |
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
US20070029106A1 (en) * | 2003-04-07 | 2007-02-08 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US20040212030A1 (en) * | 2003-04-22 | 2004-10-28 | Ibiden Co., Ltd. | Substrate for mounting IC chip, multilayered printed circuit board, and device for optical communication |
US20040227227A1 (en) * | 2003-05-15 | 2004-11-18 | Fujitsu Limited | Aerosol deposition process |
US20050142033A1 (en) * | 2003-11-04 | 2005-06-30 | Meso Scale Technologies, Llc. | Modular assay plates, reader systems and methods for test measurements |
US20050098868A1 (en) * | 2003-11-12 | 2005-05-12 | Advanced Semiconductor Engineering, Inc. | Multi-chips module assembly package |
US7211289B2 (en) * | 2003-12-18 | 2007-05-01 | Endicott Interconnect Technologies, Inc. | Method of making multilayered printed circuit board with filled conductive holes |
US20050136646A1 (en) * | 2003-12-18 | 2005-06-23 | Endicott Interconnect Technologies, Inc. | Method of providing printed circuit board with conductive holes and board resulting therefrom |
US20060183316A1 (en) * | 2003-12-18 | 2006-08-17 | Endicott Interconnect Technologies, Inc. | Method of providing printed circuit board with conductive holes and board resulting therefrom |
US20050191770A1 (en) * | 2004-02-27 | 2005-09-01 | Schieck Brian S. | Flip chip semiconductor die internal signal access system and method |
US20070181994A1 (en) * | 2004-03-03 | 2007-08-09 | Shinko Electric Industries Co., Ltd. | Circuit board manufacturing method and circuit board |
US20070074895A1 (en) * | 2004-03-30 | 2007-04-05 | Nec Tokin Corporation | Printed circuit board and manufacturing method thereof |
US20050217893A1 (en) * | 2004-03-30 | 2005-10-06 | Setsuo Noguchi | Printed circuit board and manufacturing method thereof |
US20050218502A1 (en) * | 2004-03-31 | 2005-10-06 | Shinko Electric Industries Co., Ltd. | Capacitor-mounted wiring board and method of manufacturing the same |
US20050218451A1 (en) * | 2004-03-31 | 2005-10-06 | Casio Computer Co., Ltd. | Semiconductor device incorporating semiconductor constructing body and method of fabricating the same |
US20060001166A1 (en) * | 2004-06-30 | 2006-01-05 | Yusuke Igarashi | Circuit device and manufacturing method thereof |
US20080052904A1 (en) * | 2004-07-28 | 2008-03-06 | Reinhard Schneider | Method Of Manufacturing An Electronic Circuit Assembly |
US7764987B2 (en) * | 2004-09-02 | 2010-07-27 | Biotronik Crm Patent Ag | Signal processing apparatus for physiological signals |
US7683458B2 (en) * | 2004-09-02 | 2010-03-23 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
US20060060956A1 (en) * | 2004-09-22 | 2006-03-23 | Tanikella Ravindra V | Materials, structures and methods for microelectronic packaging |
US20080264681A1 (en) * | 2004-10-14 | 2008-10-30 | Ibiden Co., Ltd. | Printed Wiring Board and Method for Manufacturing Printed Wiring Board |
US20060226537A1 (en) * | 2004-12-06 | 2006-10-12 | International Business Machines Corporation | Multilayer circuit board and method of manufacturing the same |
US20060125072A1 (en) * | 2004-12-14 | 2006-06-15 | Casio Computer Co., Ltd. | Semiconductor device having laminated semiconductor constructions and a manufacturing method thereof |
US20070273047A1 (en) * | 2004-12-15 | 2007-11-29 | Ibiden Co., Ltd | Printed wiring board and manufacturing method thereof |
US20080289866A1 (en) * | 2004-12-28 | 2008-11-27 | Ngk Spark Plug Co., Ltd. | Wiring Board and Wiring Board Manufacturing Method |
US20060178007A1 (en) * | 2005-02-04 | 2006-08-10 | Hiroki Nakamura | Method of forming copper wiring layer |
US7348857B1 (en) * | 2005-02-28 | 2008-03-25 | Marvell Semiconductor Israel Ltd. | Monitoring and compensating for real time local circuit speed in an integrated circuit |
US20060220167A1 (en) * | 2005-03-31 | 2006-10-05 | Intel Corporation | IC package with prefabricated film capacitor |
US20070096328A1 (en) * | 2005-07-07 | 2007-05-03 | Ibiden Co., Ltd. | Multilayered printed wiring board |
WO2007010758A1 (en) * | 2005-07-15 | 2007-01-25 | Matsushita Electric Industrial Co., Ltd. | Wiring board, wiring material, copper-clad laminate, and wiring board fabrication method |
US20100032202A1 (en) * | 2005-07-15 | 2010-02-11 | Hideki Higashitani | Wiring substrate, wiring material, copper-clad laminate, and method of manufacturing the wiring substrate |
US20070023202A1 (en) * | 2005-07-29 | 2007-02-01 | Sanyo Electric Co., Ltd. | Circuit board and circuit apparatus using the same |
US20070044999A1 (en) * | 2005-08-30 | 2007-03-01 | Kiyoshi Shibata | Circuit board and circuit apparatus using the same |
US20070048447A1 (en) * | 2005-08-31 | 2007-03-01 | Alan Lee | System and method for forming patterned copper lines through electroless copper plating |
US7696613B2 (en) * | 2005-09-07 | 2010-04-13 | Shinko Electric Industries Co., Ltd. | Multilayered wiring substrate including wiring layers and insulating layers and method of manufacturing the same |
US20070148420A1 (en) * | 2005-12-28 | 2007-06-28 | Intel Corporation | Method of making a substrate using laser assisted metallization and patterning with electroless plating without electrolytic plating |
US20070200211A1 (en) * | 2006-02-15 | 2007-08-30 | Shinko Electric Industries Co., Ltd. | Multilayer wiring substrate and method of connecting the same |
US20070281471A1 (en) * | 2006-06-01 | 2007-12-06 | Dror Hurwitz | Advanced Multilayered Coreless Support Structures and their Fabrication |
US20080121417A1 (en) * | 2006-11-07 | 2008-05-29 | Unimicron Technology Corp. | Package substrate having embedded capacitor |
US20080247704A1 (en) * | 2007-04-04 | 2008-10-09 | Ibiden Co., Ltd | Package substrate and device for optical communication |
US20080285910A1 (en) * | 2007-05-18 | 2008-11-20 | Ibiden Co., Ltd. | Photoelectric circuit board and device for optical communication |
US20090002958A1 (en) * | 2007-06-28 | 2009-01-01 | Yonggang Li | Method of Forming a Substrate Core Structure Using Microvia Laser Drilling and Conductive Layer Pre-Patterning And Substrate Core Structure Formed According to the Method |
US20090001550A1 (en) * | 2007-06-28 | 2009-01-01 | Yonggang Li | Method of Forming a Multilayer Substrate Core Structure Using Sequential Microvia Laser Drilling And Substrate Core Structure Formed According to the Method |
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US10672701B2 (en) * | 2015-09-25 | 2020-06-02 | Intel Corporation | Thin electronic package elements using laser spallation |
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JP2010532100A (en) | 2010-09-30 |
US8877565B2 (en) | 2014-11-04 |
KR101134714B1 (en) | 2012-04-13 |
JP2014195117A (en) | 2014-10-09 |
TWI417011B (en) | 2013-11-21 |
CN101690436A (en) | 2010-03-31 |
TW200920202A (en) | 2009-05-01 |
US20090001550A1 (en) | 2009-01-01 |
WO2009006065A1 (en) | 2009-01-08 |
KR20100017926A (en) | 2010-02-16 |
JP5595269B2 (en) | 2014-09-24 |
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