US20110062572A1 - Self-aligned silicon carrier for optical device supporting wafer scale methods - Google Patents
Self-aligned silicon carrier for optical device supporting wafer scale methods Download PDFInfo
- Publication number
- US20110062572A1 US20110062572A1 US12/558,824 US55882409A US2011062572A1 US 20110062572 A1 US20110062572 A1 US 20110062572A1 US 55882409 A US55882409 A US 55882409A US 2011062572 A1 US2011062572 A1 US 2011062572A1
- Authority
- US
- United States
- Prior art keywords
- optical
- silicon substrate
- carrier
- die
- dies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/423—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using guiding surfaces for the alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/023—Mount members, e.g. sub-mount members
- H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
- H01S5/02326—Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02375—Positioning of the laser chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0225—Out-coupling of light
- H01S5/02251—Out-coupling of light using optical fibres
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0225—Out-coupling of light
- H01S5/02255—Out-coupling of light using beam deflecting elements
Definitions
- the present invention relates to the field of optical devices.
- the invention relates to the design of a self-aligned silicon carrier for optical devices which supports wafer scale methods.
- optical dies such as a vertical-cavity surface-emitting laser (VCSEL). But in all cases they require four connections: the optical, the electrical, the thermal and the mechanical. Different applications require different approaches on how to balance these four connections.
- VCSEL vertical-cavity surface-emitting laser
- an optical die When an optical device is produced, an optical die is mounted on and connected to a carrier.
- the mounting of an optical die to a carrier and coupling of light to optical fibres are both time consuming steps requiring micromechanical piece parts. Consequently, these steps are high cost steps in the production of an optical device.
- FIG. 1 illustrates an optical device comprising a transparent glass carrier 101 with a metalized pattern 102 for electrical connection and pads for epi down attachment of an optical die 103 .
- the light 104 passes through the glass substrate 101 .
- the position of the optical die 103 with respect to the metal pattern of the carrier is determined by self-alignment. For example, surface tension in liquid phase solder joints 105 could be used.
- FIG. 2 illustrates an optical assembly comprising of an optical die 103 attached to a silicon carrier 106 with a groove 107 for fibre alignment. At the end of the groove there is a metalized mirror 108 reflecting the light 90 degrees (45 deg mirror) from/to optical die 103 to fibre end face 109 .
- One way to address the cost problem is to apply wafer scale methods to produce an optical device.
- a wafer scale method a number of integrated circuits can be attached at the same time on a common slice of wafer. Once the fabrication process is complete, the wafer is divided into the individual devices.
- each optical device needs to be tested prior to shipping. From a cost perspective, it is beneficial if the optical devices can be tested at the wafer scale stage (ie: before the wafer is divided into individual devices).
- Embodiments of the present invention provide a self-aligned carrier design for an optical device supporting wafer scale methods for the assembly, the burn in and the HF electronic and optical testing.
- Embodiments of the present invention provide the advantage of micromechanical structure “through holes” for fiber alignment to an external optical connection provided by a silicon carrier that also takes advantage of optical transparency normally provided by a glass carrier.
- Embodiments of the invention exhibit “optical transparency” afforded by glass substrates in a silicon substrate, thereby also providing alignment micromechanical structures.
- a number of optical dies are soldered to the silicon carrier substrate. According to embodiments of the present invention, this is achieved by solder pads deposited onto the surface of the optical die such that self alignment is achieved by surface tension in liquid phase solder bumps using gaseous flux. Still on wafer level, the optical dies are subjected to test and burn in, the substrate is then diced to separate carriers (including dies) to produce an optical device. Using such a wafer scale assembly permits a cost effective manufacturing method.
- ICs can be assembled in parallel.
- the optical die on silicon can be effectively tested (with ICs) and approved/rejected on silicon wafer level before dicing the silicon carrier into separate optical devices.
- the wafer scale method offers parallel assembly, handling and test which is cost effective.
- Embodiments of the invention provide a simple, easily manufacturable, passively aligned method of coupling an optical device to a fiber or fiber array. Passive and self correcting alignment methods of the optical device provide for an efficient and simple device to be added onto already existing components thus making its incorporation into the manufacturing process a desirable goal.
- the invention provides a method for manufacturing an optical device, the method comprising: providing a silicon substrate; attaching a number of optical dies on the silicon substrate by self-alignment of solder bumps to form an optical device carrier assembly; dry etching a number of corresponding through holes in the silicon substrate to permit the passage of light therethrough; filling the volume between the optical die and the silicon substrate with a transparent polymer; and dicing the optical device carrier assembly to form individual optical devices.
- the invention provides a method for manufacturing an optical device, the method comprising: providing a silicon substrate; attaching a number of optical dies on the silicon substrate to form an optical device carrier assembly; providing a corresponding number of through holes in the silicon substrate to permit the passage of light therethrough; and dicing the optical device carrier assembly to form individual optical devices.
- the step of attaching a number of optical dies comprises using self-alignment of solder bumps using gaseous flux.
- the through holes are dry etched into the silicon substrate.
- the method may also comprise the step of filling the volume between the optical die and silicon substrate with a transparent polymer, and the transparent polymer may be silicone rubber or epoxy.
- the method further comprises testing and burn in of the optical dies prior to the dicing step.
- the method further comprises providing the optical dies with a polymer mass to assist the heat transfer to the silicon substrate.
- the method may comprise providing guide holes in the silicon substrate to permit passive alignment of the optical carrier to an external optical element.
- the method may comprise providing a metal pattern on the silicon substrate and solder bumps on an epi side of each optical die, and wherein the step of mounting the optical dies to the substrate includes mating together the metal pattern and the solder bumps.
- the invention provides an optical carrier of an optical device, the optical carrier comprising: a silicon substrate, an optical die mounted to the silicon substrate; and at least one through hole in the silicon substrate to permit the passage of light though the silicon substrate.
- the silicon substrate may comprise guide holes to permit passive alignment of the optical carrier to an external optical element.
- the silicon substrate may include an metal pattern and the optical die has an epi side having solder bumps, the metal pattern and the solder bumps mating together to mount the optical die to the silicon substrate.
- the optical die may be mounted to the silicon substrate and aligned by surface tension in liquid phase solder.
- the optical carrier may comprise a transparent polymer fill between the optical die and the silicon substrate.
- the transparent polymer may be silicone rubber or epoxy.
- the optical carrier may comprise a polymer mass on the optical die to permit heat transfer to the silicon substrate.
- optical die surface tension in solder bumps
- high precision etched through holes for guide pin based alignment of the optical fiber connection facilitates optical coupling and excludes high cost micro machined piece parts.
- the wafer scale method itself offers parallel assembly, handling and test which is cost effective
- Embodiments of the invention disclosed provide a simple, easily manufacturable, passively aligned method of coupling an optoelectronic device to a fiber or fiber array with most steps integrated at the wafer level.
- the passive and self correcting feature of the alignment method provides for an efficient and simple component to be added onto already existing components thus making its incorporation into the manufacturing process a desirable goal.
- FIGS. 1 and 2 each illustrate an optical device as known in the art
- FIGS. 3 a and 3 b illustrate a silicon micromechanical carrier in accordance with the teachings of the present invention
- FIGS. 4 a and 4 b illustrate the assembly of an optical die to the silicon carrier of the present invention. More specifically, FIG. 4 b shows a cross-section with through holes for light passage and mechanical alignment to external optical connection;
- FIGS. 5 a and 5 b illustrate a mechanical protection, an optical and thermal connection of an optical carrier in accordance with the teachings of this invention
- FIGS. 6 a , 6 b and 6 c illustrate alternative embodiments of the present invention in accordance with the teachings of this invention; More specifically, FIG. 6 a is a side view, 6 b is a top view and FIG. 6 c shows a version including an IC chip set for transmitting and receiving of signals;
- FIGS. 7 a and 7 b illustrate an alternative embodiment of the present invention in accordance with the teachings of this invention also including a commercially available array lens element with mechanical interface for optical fiber connection;
- FIG. 8 is a flow chart of the fabrication steps for an optical carrier in accordance with the teachings of this invention.
- Embodiments of the invention provide a carrier design assembly of an optical device.
- the carrier comprises a silicon micromechanical substrate.
- the silicon substrate is provided with a set of through holes that permit light to pass and serves as micromechanical structures for passive alignment to an external optical connection.
- silicon offers excellent properties as carrier for optical die and electrical circuits.
- the properties include high definition micromechanical structuring by dry etching; high definition metal patterning by a combination of metal deposition and lithography (electrodes) and electroplating (solder bumps); high accuracy between mechanical structures and the metal pattern (approx. 1 micron); good thermal properties, ie: thermal conductivity; good HF properties; and batch handling and parallel processing supporting low piece part cost.
- a silicon substrate in accordance with the teachings of this invention includes a metal pattern including pads 201 for connecting an optical die (not shown in this figure) to the silicon substrate 200 periphery.
- the metal pattern includes pads for optical die attachment 201 and pads with solder bumps 202 for connecting the silicon substrate 200 externally (for example a printed circuit board—not shown).
- solder bumps 202 for connecting the silicon substrate 200 externally (for example a printed circuit board—not shown).
- solder bumps for connecting the silicon substrate 200 externally (for example a printed circuit board—not shown).
- an ASIC can be placed in this path and be connected by solder bumps.
- the silicon substrate 200 includes electrical pattern and connections (solder pads) compatible with standard well-established flip-chip ASIC assembly method.
- the substrate 200 also includes guide holes 203 for passive alignment to facilitate mechanical matching to a fibre holding fixture.
- Guide holes 203 are defined with micron range accuracy for passive alignment of an optical system. These holes are used together with a mating structure to position a lens or a light-guiding device.
- An example of such a suitable mating structure is guide pins.
- Through-holes 204 are provided to let light pass through the silicon substrate 200 .
- the epi-side of the optical die 103 faces the silicon metal pattern.
- the positional matching of the optical die 103 and the silicon pads are a result of self-alignment to pads 201 by surface tension in liquid phase solder.
- These bumps are deposited onto the surface of the optical die 103 .
- the light is emitted directly against the surface of silicon substrate 200 , and permits passage of light through the opening 204 in the silicon substrate.
- FIGS. 4 a and 4 b the assembly geometry of the optical die 103 to silicon substrate 200 to form a carrier assembly in accordance with the teachings of this invention is illustrated.
- the optical die 103 is attached onto the silicon substrate 200 and the light 104 is passing through holes 204 in the silicon substrate. Due to high precision wafer patterning and self-alignment, the relative positional accuracy between the active area of the optical die 103 and the silicon guide holes 203 is very good.
- the present inventors have been able to achieve self-alignments of better than 5 microns.
- the passive optical connection is made by an optical element (lenses or a fibre fixture—not shown) with mating pins that fits to the silicon substrate guide holes 203 .
- the mechanical protection and thermal connection of the carrier design in accordance with the teachings of this invention are shown.
- the through-hole 204 and the volume between the optical die and the silicon substrate 200 is filled with a transparent polymer 205 .
- suitable polymers include silicone rubber or epoxy 205 .
- this arrangement offers a light path which is from optical die 103 to fibre tip 400 , completely filled with a transparent polymer 205 . This is beneficial in applications where there is risk of contamination or condensed water on refractive surfaces.
- the fiber coupling fixture is equipped with guide holes matching the guide holes on the silicon substrate. The two parts are aligned by guide pins (not shown).
- a thick lump or mass of polymer 206 is provided to deal with high thermal resistance at the metal pads on the optical die.
- the polymer mass 206 permits heat transfer to the silicon substrate 200 .
- the polymer mass top 206 is dispensed onto the optical die 103 .
- the heat is spread through the mass 206 top down to the silicon substrate 200 . This is normally not needed for a flip chip attached ASIC since the bond surfaces serves as numerous thermal paths securing acceptable heat dissipation. Besides from establishing a thermal path to the outside, the mass 206 top also mechanically protects the chip.
- FIG. 8 illustrates a broad flow chart of steps in a method 300 of manufacturing an optical device in accordance with these teachings.
- steps 310 a and 310 b the silicon wafer substrate is metallized and patterned with solder bumps (step 310 a ) and the guide pin holes and through holes are dry etched (step 310 b ).
- step 320 at a wafer scale method, the optical die is attached by soldering. Also at a wafer scale, in step 330 , underfill is dispensed and cured.
- step 340 also a wafer scale, the units undergo burn in and testing.
- approved optical dies or units are diced into separate optical devices.
- alignment between optical dies, integrated circuits and the silicon carrier is done by self alignment based on surface tension force in liquid solder bumps assisted by gaseous flux at specific temperatures to mount the dies.
- eutectic AuSn @+280 deg C. and eutectic AgSn @+220 degC. respectively.
- FIGS. 6 a , 6 b and 6 c illustrate alternative embodiments of the invention in accordance with the teachings of this invention.
- FIGS. 6 a (side view) and 6 b (top view) show an array type design including two optical dies, one 4-channel transmitter 601 and one 4-channel receiver 602 .
- FIG. 6 c shows basically the same, but with electronics added, one transmitter 701 and one receiver 702 ASIC.
- FIG. 7 illustrates the assembly of FIG. 6 c with a standard type array lens 800 attachment on top side and the reverse side connected to a PCB 900 .
Abstract
Description
- The present invention relates to the field of optical devices. In particular, the invention relates to the design of a self-aligned silicon carrier for optical devices which supports wafer scale methods.
- There are numerous methods to produce an optical device including optical dies, such as a vertical-cavity surface-emitting laser (VCSEL). But in all cases they require four connections: the optical, the electrical, the thermal and the mechanical. Different applications require different approaches on how to balance these four connections.
- When an optical device is produced, an optical die is mounted on and connected to a carrier. The mounting of an optical die to a carrier and coupling of light to optical fibres are both time consuming steps requiring micromechanical piece parts. Consequently, these steps are high cost steps in the production of an optical device.
-
FIG. 1 illustrates an optical device comprising atransparent glass carrier 101 with ametalized pattern 102 for electrical connection and pads for epi down attachment of anoptical die 103. Thelight 104 passes through theglass substrate 101. The position of theoptical die 103 with respect to the metal pattern of the carrier is determined by self-alignment. For example, surface tension in liquidphase solder joints 105 could be used. -
FIG. 2 illustrates an optical assembly comprising of anoptical die 103 attached to asilicon carrier 106 with agroove 107 for fibre alignment. At the end of the groove there is ametalized mirror 108 reflecting the light 90 degrees (45 deg mirror) from/tooptical die 103 tofibre end face 109. - One way to address the cost problem is to apply wafer scale methods to produce an optical device. Using a wafer scale method, a number of integrated circuits can be attached at the same time on a common slice of wafer. Once the fabrication process is complete, the wafer is divided into the individual devices.
- However, each optical device needs to be tested prior to shipping. From a cost perspective, it is beneficial if the optical devices can be tested at the wafer scale stage (ie: before the wafer is divided into individual devices).
- Embodiments of the present invention provide a self-aligned carrier design for an optical device supporting wafer scale methods for the assembly, the burn in and the HF electronic and optical testing. Embodiments of the present invention provide the advantage of micromechanical structure “through holes” for fiber alignment to an external optical connection provided by a silicon carrier that also takes advantage of optical transparency normally provided by a glass carrier. Embodiments of the invention exhibit “optical transparency” afforded by glass substrates in a silicon substrate, thereby also providing alignment micromechanical structures.
- To effectively take advantage of a wafer scale assembly method, a number of optical dies are soldered to the silicon carrier substrate. According to embodiments of the present invention, this is achieved by solder pads deposited onto the surface of the optical die such that self alignment is achieved by surface tension in liquid phase solder bumps using gaseous flux. Still on wafer level, the optical dies are subjected to test and burn in, the substrate is then diced to separate carriers (including dies) to produce an optical device. Using such a wafer scale assembly permits a cost effective manufacturing method.
- In an alternative embodiment, ICs can be assembled in parallel. The optical die on silicon can be effectively tested (with ICs) and approved/rejected on silicon wafer level before dicing the silicon carrier into separate optical devices. The wafer scale method offers parallel assembly, handling and test which is cost effective.
- Embodiments of the invention provide a simple, easily manufacturable, passively aligned method of coupling an optical device to a fiber or fiber array. Passive and self correcting alignment methods of the optical device provide for an efficient and simple device to be added onto already existing components thus making its incorporation into the manufacturing process a desirable goal.
- Thus, according to one aspect, the invention provides a method for manufacturing an optical device, the method comprising: providing a silicon substrate; attaching a number of optical dies on the silicon substrate by self-alignment of solder bumps to form an optical device carrier assembly; dry etching a number of corresponding through holes in the silicon substrate to permit the passage of light therethrough; filling the volume between the optical die and the silicon substrate with a transparent polymer; and dicing the optical device carrier assembly to form individual optical devices.
- In another aspect, the invention provides a method for manufacturing an optical device, the method comprising: providing a silicon substrate; attaching a number of optical dies on the silicon substrate to form an optical device carrier assembly; providing a corresponding number of through holes in the silicon substrate to permit the passage of light therethrough; and dicing the optical device carrier assembly to form individual optical devices.
- In one aspect, the step of attaching a number of optical dies comprises using self-alignment of solder bumps using gaseous flux. In one aspect, the through holes are dry etched into the silicon substrate. The method may also comprise the step of filling the volume between the optical die and silicon substrate with a transparent polymer, and the transparent polymer may be silicone rubber or epoxy.
- In one aspect, the method further comprises testing and burn in of the optical dies prior to the dicing step. In one aspect, the method further comprises providing the optical dies with a polymer mass to assist the heat transfer to the silicon substrate. In one aspect, the method may comprise providing guide holes in the silicon substrate to permit passive alignment of the optical carrier to an external optical element. In one aspect, the method may comprise providing a metal pattern on the silicon substrate and solder bumps on an epi side of each optical die, and wherein the step of mounting the optical dies to the substrate includes mating together the metal pattern and the solder bumps.
- In another aspect, the invention provides an optical carrier of an optical device, the optical carrier comprising: a silicon substrate, an optical die mounted to the silicon substrate; and at least one through hole in the silicon substrate to permit the passage of light though the silicon substrate. The silicon substrate may comprise guide holes to permit passive alignment of the optical carrier to an external optical element. The silicon substrate may include an metal pattern and the optical die has an epi side having solder bumps, the metal pattern and the solder bumps mating together to mount the optical die to the silicon substrate. The optical die may be mounted to the silicon substrate and aligned by surface tension in liquid phase solder.
- In one aspect, the optical carrier may comprise a transparent polymer fill between the optical die and the silicon substrate. The transparent polymer may be silicone rubber or epoxy. The optical carrier may comprise a polymer mass on the optical die to permit heat transfer to the silicon substrate.
- By the self alignment of optical die (surface tension in solder bumps) in combination with high precision etched through holes for guide pin based alignment of the optical fiber connection facilitates optical coupling and excludes high cost micro machined piece parts. The wafer scale method itself, offers parallel assembly, handling and test which is cost effective
- Embodiments of the invention disclosed provide a simple, easily manufacturable, passively aligned method of coupling an optoelectronic device to a fiber or fiber array with most steps integrated at the wafer level. The passive and self correcting feature of the alignment method provides for an efficient and simple component to be added onto already existing components thus making its incorporation into the manufacturing process a desirable goal.
- Other aspects and advantages of embodiments of the invention will be readily apparent to those ordinarily skilled in the art upon a review of the following description.
- Embodiments of the invention will now be described in conjunction with the accompanying drawings, wherein:
-
FIGS. 1 and 2 each illustrate an optical device as known in the art; -
FIGS. 3 a and 3 b illustrate a silicon micromechanical carrier in accordance with the teachings of the present invention; -
FIGS. 4 a and 4 b illustrate the assembly of an optical die to the silicon carrier of the present invention. More specifically,FIG. 4 b shows a cross-section with through holes for light passage and mechanical alignment to external optical connection; -
FIGS. 5 a and 5 b illustrate a mechanical protection, an optical and thermal connection of an optical carrier in accordance with the teachings of this invention; -
FIGS. 6 a, 6 b and 6 c illustrate alternative embodiments of the present invention in accordance with the teachings of this invention; More specifically,FIG. 6 a is a side view, 6 b is a top view andFIG. 6 c shows a version including an IC chip set for transmitting and receiving of signals; -
FIGS. 7 a and 7 b illustrate an alternative embodiment of the present invention in accordance with the teachings of this invention also including a commercially available array lens element with mechanical interface for optical fiber connection; and -
FIG. 8 is a flow chart of the fabrication steps for an optical carrier in accordance with the teachings of this invention. - This invention will now be described in detail with respect to certain specific representative embodiments thereof, the materials, apparatus and process steps being understood as examples that are intended to be illustrative only. In particular, the invention is not intended to be limited to the methods, materials, conditions, process parameters, apparatus and the like specifically recited herein.
- Embodiments of the invention provide a carrier design assembly of an optical device. In accordance with the teachings of this invention, the carrier comprises a silicon micromechanical substrate. The silicon substrate is provided with a set of through holes that permit light to pass and serves as micromechanical structures for passive alignment to an external optical connection.
- Generally silicon offers excellent properties as carrier for optical die and electrical circuits. The properties include high definition micromechanical structuring by dry etching; high definition metal patterning by a combination of metal deposition and lithography (electrodes) and electroplating (solder bumps); high accuracy between mechanical structures and the metal pattern (approx. 1 micron); good thermal properties, ie: thermal conductivity; good HF properties; and batch handling and parallel processing supporting low piece part cost.
- Referring to
FIGS. 3 a and 3 b, a silicon substrate in accordance with the teachings of this invention includes a metalpattern including pads 201 for connecting an optical die (not shown in this figure) to thesilicon substrate 200 periphery. The metal pattern includes pads foroptical die attachment 201 and pads withsolder bumps 202 for connecting thesilicon substrate 200 externally (for example a printed circuit board—not shown). It should be noted that an ASIC can be placed in this path and be connected by solder bumps. Thesilicon substrate 200 includes electrical pattern and connections (solder pads) compatible with standard well-established flip-chip ASIC assembly method. - The
substrate 200 also includes guide holes 203 for passive alignment to facilitate mechanical matching to a fibre holding fixture. Guide holes 203 are defined with micron range accuracy for passive alignment of an optical system. These holes are used together with a mating structure to position a lens or a light-guiding device. An example of such a suitable mating structure is guide pins. - Through-
holes 204 are provided to let light pass through thesilicon substrate 200. To obtain high positional accuracy between optical die 103 (seen inFIG. 4 ) and the metal pattern on thesilicon substrate 200, the epi-side of theoptical die 103 faces the silicon metal pattern. The positional matching of theoptical die 103 and the silicon pads are a result of self-alignment topads 201 by surface tension in liquid phase solder. These bumps are deposited onto the surface of theoptical die 103. As a consequence of this geometry the light is emitted directly against the surface ofsilicon substrate 200, and permits passage of light through theopening 204 in the silicon substrate. - Referring to
FIGS. 4 a and 4 b, the assembly geometry of theoptical die 103 tosilicon substrate 200 to form a carrier assembly in accordance with the teachings of this invention is illustrated. Theoptical die 103 is attached onto thesilicon substrate 200 and the light 104 is passing throughholes 204 in the silicon substrate. Due to high precision wafer patterning and self-alignment, the relative positional accuracy between the active area of theoptical die 103 and the silicon guide holes 203 is very good. The present inventors have been able to achieve self-alignments of better than 5 microns. The passive optical connection is made by an optical element (lenses or a fibre fixture—not shown) with mating pins that fits to the silicon substrate guide holes 203. - Referring to
FIGS. 5 a and 5 b, the mechanical protection and thermal connection of the carrier design in accordance with the teachings of this invention are shown. To protect the sensitive epi side of theoptical die 103, the through-hole 204 and the volume between the optical die and thesilicon substrate 200 is filled with atransparent polymer 205. Examples of suitable polymers include silicone rubber orepoxy 205. - In combination with a fiber-
coupling fixture 300 according to known methods, this arrangement offers a light path which is fromoptical die 103 tofibre tip 400, completely filled with atransparent polymer 205. This is beneficial in applications where there is risk of contamination or condensed water on refractive surfaces. The fiber coupling fixture is equipped with guide holes matching the guide holes on the silicon substrate. The two parts are aligned by guide pins (not shown). - A thick lump or mass of
polymer 206 is provided to deal with high thermal resistance at the metal pads on the optical die. Thepolymer mass 206 permits heat transfer to thesilicon substrate 200. Thepolymer mass top 206 is dispensed onto theoptical die 103. The heat is spread through the mass 206 top down to thesilicon substrate 200. This is normally not needed for a flip chip attached ASIC since the bond surfaces serves as numerous thermal paths securing acceptable heat dissipation. Besides from establishing a thermal path to the outside, themass 206 top also mechanically protects the chip. -
FIG. 8 illustrates a broad flow chart of steps in amethod 300 of manufacturing an optical device in accordance with these teachings. Insteps step 320, at a wafer scale method, the optical die is attached by soldering. Also at a wafer scale, instep 330, underfill is dispensed and cured. Instep 340, also a wafer scale, the units undergo burn in and testing. Instep 350, approved optical dies or units are diced into separate optical devices. - In a preferred embodiment of the method, alignment between optical dies, integrated circuits and the silicon carrier is done by self alignment based on surface tension force in liquid solder bumps assisted by gaseous flux at specific temperatures to mount the dies. For example, eutectic AuSn @+280 deg C. and eutectic AgSn @+220 degC. respectively.
-
FIGS. 6 a, 6 b and 6 c illustrate alternative embodiments of the invention in accordance with the teachings of this invention.FIGS. 6 a (side view) and 6 b (top view) show an array type design including two optical dies, one 4-channel transmitter 601 and one 4-channel receiver 602.FIG. 6 c shows basically the same, but with electronics added, onetransmitter 701 and onereceiver 702 ASIC.FIG. 7 illustrates the assembly ofFIG. 6 c with a standardtype array lens 800 attachment on top side and the reverse side connected to aPCB 900. - Numerous modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/558,824 US8232142B2 (en) | 2009-09-14 | 2009-09-14 | Self-aligned silicon carrier for optical device supporting wafer scale methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/558,824 US8232142B2 (en) | 2009-09-14 | 2009-09-14 | Self-aligned silicon carrier for optical device supporting wafer scale methods |
Publications (2)
Publication Number | Publication Date |
---|---|
US20110062572A1 true US20110062572A1 (en) | 2011-03-17 |
US8232142B2 US8232142B2 (en) | 2012-07-31 |
Family
ID=43729679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/558,824 Expired - Fee Related US8232142B2 (en) | 2009-09-14 | 2009-09-14 | Self-aligned silicon carrier for optical device supporting wafer scale methods |
Country Status (1)
Country | Link |
---|---|
US (1) | US8232142B2 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8538215B2 (en) | 2010-05-20 | 2013-09-17 | Analog Devices, Inc. | Optical package and related methods |
US8842951B2 (en) | 2012-03-02 | 2014-09-23 | Analog Devices, Inc. | Systems and methods for passive alignment of opto-electronic components |
US8946879B2 (en) | 2012-07-27 | 2015-02-03 | Analog Devices, Inc. | Packages and methods for 3D integration including two stacked dies with a portion of one die extending into a hole of the other die |
US9533878B2 (en) | 2014-12-11 | 2017-01-03 | Analog Devices, Inc. | Low stress compact device packages |
US9590129B2 (en) | 2014-11-19 | 2017-03-07 | Analog Devices Global | Optical sensor module |
US9716193B2 (en) | 2012-05-02 | 2017-07-25 | Analog Devices, Inc. | Integrated optical sensor module |
US9731959B2 (en) | 2014-09-25 | 2017-08-15 | Analog Devices, Inc. | Integrated device packages having a MEMS die sealed in a cavity by a processor die and method of manufacturing the same |
US10712197B2 (en) | 2018-01-11 | 2020-07-14 | Analog Devices Global Unlimited Company | Optical sensor package |
US10884551B2 (en) | 2013-05-16 | 2021-01-05 | Analog Devices, Inc. | Integrated gesture sensor module |
US11296005B2 (en) | 2019-09-24 | 2022-04-05 | Analog Devices, Inc. | Integrated device package including thermally conductive element and method of manufacturing same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9335494B2 (en) | 2014-05-15 | 2016-05-10 | Tyco Electronics Corporation | Optoelectronics structures |
US9651749B1 (en) * | 2016-03-31 | 2017-05-16 | Tyco Electronics Svenska Holdings Ab | Interposer with opaque substrate |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6571466B1 (en) * | 2000-03-27 | 2003-06-03 | Amkor Technology, Inc. | Flip chip image sensor package fabrication method |
US6825065B2 (en) * | 2001-11-29 | 2004-11-30 | Electronics And Telecommunications Research Institute | Method for optical module packaging of flip chip bonding |
US7264995B2 (en) * | 2004-10-08 | 2007-09-04 | Epworks Co., Ltd. | Method for manufacturing wafer level chip scale package using redistribution substrate |
US7371602B2 (en) * | 2005-03-02 | 2008-05-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US20080224248A1 (en) * | 2007-03-15 | 2008-09-18 | Advanced Chip Engineering Technology Inc. | Image sensor module having build-in package cavity and the method of the same |
US7498647B2 (en) * | 2004-06-10 | 2009-03-03 | Micron Technology, Inc. | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
US7583834B2 (en) * | 2005-03-04 | 2009-09-01 | Eastman Kodak Company | Laser etched fiducials in roll-roll display |
US7638813B2 (en) * | 2002-08-29 | 2009-12-29 | Micron Technology, Inc. | Methods of fabrication for flip-chip image sensor packages |
US7723146B2 (en) * | 2006-01-04 | 2010-05-25 | Stats Chippac Ltd. | Integrated circuit package system with image sensor system |
-
2009
- 2009-09-14 US US12/558,824 patent/US8232142B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6571466B1 (en) * | 2000-03-27 | 2003-06-03 | Amkor Technology, Inc. | Flip chip image sensor package fabrication method |
US6825065B2 (en) * | 2001-11-29 | 2004-11-30 | Electronics And Telecommunications Research Institute | Method for optical module packaging of flip chip bonding |
US7638813B2 (en) * | 2002-08-29 | 2009-12-29 | Micron Technology, Inc. | Methods of fabrication for flip-chip image sensor packages |
US7498647B2 (en) * | 2004-06-10 | 2009-03-03 | Micron Technology, Inc. | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
US7264995B2 (en) * | 2004-10-08 | 2007-09-04 | Epworks Co., Ltd. | Method for manufacturing wafer level chip scale package using redistribution substrate |
US7371602B2 (en) * | 2005-03-02 | 2008-05-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US7583834B2 (en) * | 2005-03-04 | 2009-09-01 | Eastman Kodak Company | Laser etched fiducials in roll-roll display |
US7723146B2 (en) * | 2006-01-04 | 2010-05-25 | Stats Chippac Ltd. | Integrated circuit package system with image sensor system |
US20080224248A1 (en) * | 2007-03-15 | 2008-09-18 | Advanced Chip Engineering Technology Inc. | Image sensor module having build-in package cavity and the method of the same |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8538215B2 (en) | 2010-05-20 | 2013-09-17 | Analog Devices, Inc. | Optical package and related methods |
US8842951B2 (en) | 2012-03-02 | 2014-09-23 | Analog Devices, Inc. | Systems and methods for passive alignment of opto-electronic components |
US9348088B2 (en) | 2012-03-02 | 2016-05-24 | Analog Devices, Inc. | Systems and methods for passive alignment of opto-electronic components |
US9716193B2 (en) | 2012-05-02 | 2017-07-25 | Analog Devices, Inc. | Integrated optical sensor module |
US8946879B2 (en) | 2012-07-27 | 2015-02-03 | Analog Devices, Inc. | Packages and methods for 3D integration including two stacked dies with a portion of one die extending into a hole of the other die |
US10884551B2 (en) | 2013-05-16 | 2021-01-05 | Analog Devices, Inc. | Integrated gesture sensor module |
US9731959B2 (en) | 2014-09-25 | 2017-08-15 | Analog Devices, Inc. | Integrated device packages having a MEMS die sealed in a cavity by a processor die and method of manufacturing the same |
US9590129B2 (en) | 2014-11-19 | 2017-03-07 | Analog Devices Global | Optical sensor module |
US9533878B2 (en) | 2014-12-11 | 2017-01-03 | Analog Devices, Inc. | Low stress compact device packages |
US10712197B2 (en) | 2018-01-11 | 2020-07-14 | Analog Devices Global Unlimited Company | Optical sensor package |
US11296005B2 (en) | 2019-09-24 | 2022-04-05 | Analog Devices, Inc. | Integrated device package including thermally conductive element and method of manufacturing same |
Also Published As
Publication number | Publication date |
---|---|
US8232142B2 (en) | 2012-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8232142B2 (en) | Self-aligned silicon carrier for optical device supporting wafer scale methods | |
US7978940B2 (en) | Self-aligned carrier assembly for optical device supporting wafer scale methods | |
US7703993B1 (en) | Wafer level optoelectronic package with fiber side insertion | |
US10082633B2 (en) | Wafer-level integrated opto-electronic module | |
US9465176B2 (en) | Small form factor transceiver compatible with solder processing | |
US7118294B2 (en) | Optical semiconductor module and its manufacturing method | |
JP5270917B2 (en) | Optical assembly having optoelectronic device alignment function | |
US9151916B2 (en) | Compact optical package made with planar structures | |
EP2810112A1 (en) | Apparatus for use in optoelectronics | |
JP2017516152A (en) | Removable optical connector for optoelectronic devices | |
JP2006148128A (en) | Optical rotating system for optoelectronic module | |
US9739958B2 (en) | Wafer level packaged optical subassembly and transceiver module having same | |
WO2004070428A2 (en) | Method and apparatus for parallel optical transceiver module assembly | |
GB2416941A (en) | Passive alignment and coupling of an optical fibre with an optoelectonic device using a dual lens arrangement | |
KR100957338B1 (en) | Passively aligned fiber optical engine for parallel optics interconnect devices | |
Ambrosy et al. | Silicon motherboards for multichannel optical modules | |
US7253388B2 (en) | Assembly with self-alignment features to position a cover on a substrate that supports a micro component | |
US6403948B1 (en) | Photo-detecting module having a fiber optic groove on rear surface of integrated circuit device | |
JP6500336B2 (en) | Optical waveguide type module device and manufacturing method | |
WO2013155263A1 (en) | Small form factor transceiver compatible with solder processing | |
US6948860B1 (en) | Optical subassembly for optoelectronic devices | |
US7021835B1 (en) | Alignment of optical components in an optical subassembly | |
Dahlgren et al. | Non-imaging optical concentrators for low-cost optical interconnect | |
JP5919632B2 (en) | Manufacturing method of parts for photoelectric conversion module | |
WO2004088380A2 (en) | Package for optoelectronic device on wafer level and associated methods |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ZARLINK SEMICONDUCTOR AB, SWEDEN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STEIJER, ODD ROBERT;ANDERSSON, HANS MAGNUS EMIL;REEL/FRAME:023692/0567 Effective date: 20091026 |
|
AS | Assignment |
Owner name: GOLDCUP 5514 AB UNAT TYCO ELECTRONICS SVENSKA HOLD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZARLINK SEMICONDUCTOR INC;ZARLINK SEMICONDUCTOR AB;REEL/FRAME:026272/0772 Effective date: 20100514 Owner name: TYCO ELECTRONICS SERVICES GMBH, SWITZERLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ZARLINK SEMICONDUCTOR INC;ZARLINK SEMICONDUCTOR AB;REEL/FRAME:026272/0772 Effective date: 20100514 |
|
AS | Assignment |
Owner name: TYCO ELECTRONICS SERVICES GMBH, SWITZERLAND Free format text: CORRECTIVE ASSIGNMENT TO REMOVE SECOND ASSIGNEE PREVIOUSLY RECORDED ON REEL 026272, FRAME 0772;ASSIGNORS:ZARLINK SEMICONDUCTOR INC.;ZARLINK SEMICONDUCTOR AB;REEL/FRAME:026619/0271 Effective date: 20100514 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20200731 |