US20110136335A1 - Semiconductor Device with Improved Contacts - Google Patents
Semiconductor Device with Improved Contacts Download PDFInfo
- Publication number
- US20110136335A1 US20110136335A1 US13/008,158 US201113008158A US2011136335A1 US 20110136335 A1 US20110136335 A1 US 20110136335A1 US 201113008158 A US201113008158 A US 201113008158A US 2011136335 A1 US2011136335 A1 US 2011136335A1
- Authority
- US
- United States
- Prior art keywords
- layer
- copper
- nickel
- solder
- alloy layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- 239000004065 semiconductor Substances 0.000 title claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 85
- 239000010949 copper Substances 0.000 claims abstract description 51
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 38
- 229910052802 copper Inorganic materials 0.000 claims abstract description 35
- 229910000679 solder Inorganic materials 0.000 claims abstract description 35
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 32
- 239000000956 alloy Substances 0.000 claims abstract description 32
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 20
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910000765 intermetallic Inorganic materials 0.000 claims abstract description 10
- 229910018471 Cu6Sn5 Inorganic materials 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 17
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 229910052718 tin Inorganic materials 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 10
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000012360 testing method Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 38
- 239000011135 tin Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910000510 noble metal Inorganic materials 0.000 description 3
- 230000032683 aging Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- KSAVQLQVUXSOCR-UHFFFAOYSA-M sodium lauroyl sarcosinate Chemical compound [Na+].CCCCCCCCCCCC(=O)N(C)CC([O-])=O KSAVQLQVUXSOCR-UHFFFAOYSA-M 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000004083 survival effect Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
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Abstract
A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.
Description
- This application is a continuation of application Ser. No. 11/745,821 filed May 8, 2007 which is a continuation of application Ser. No. 11/201,717 filed Aug. 11, 2005, now U.S. Pat. No. 7,233,074 issued Jun. 19, 2007, the contents of which are herein incorporated by reference in there entireties.
- The present invention is related in general to the field of metallurgical systems with application to electronic systems and semiconductor devices, and more specifically to the structure of semiconductor devices with copper-metallized contact pads and their reliability under accelerated stress tests.
- Among the semiconductor device packages for surface mount assembly, ball grid array (BGA) packages enjoy an ever increasing popularity. They can be used in many customer products and lend themselves to the ongoing trend of miniaturization. The solder elements, distributed over the whole package area, offer high numbers of input/output terminals. In addition, the solder elements offer the opportunity of board attach technology at very low failure rate (“6 sigma processing”).
- Recently, however, there are challenging requirements affecting BGA packages. To name just a few: More and more, the solder elements are required to be free of lead (for environmental reasons); this requirement causes metallurgical challenges. The contact pads have copper as its base metal; this choice creates metallurgical interface challenges for the solder elements. The ever decreasing feature size of the package components creates new hurdles to pass the accelerated stress tests at acceptable survival rates; for instance, accelerated life tests at elevated temperatures and in moist environment become more challenging. Device products containing BGA packages are spreading into more and more customer applications; often, these applications create more stringent or even altogether new acceptance tests. As a recent example, wireless phone applications brought about the requirement to withstand phone drop tests in order to demonstrate that the solder joints of the BGA packages remain reliable after the test.
- Applicant recognizes a need for a flexible, yet low-cost and robust methodology to fabricate devices with solder joints, especially semiconductor packages, so that the joints bestow application-specific mechanical and thermal reliability to the devices and the devices will pass product-specific tests.
- One embodiment of the invention is a device with a solder joint made of a contact pad of certain area and an alloy layer metallurgically attached to the contact pad across the pad area. The surface of the contact pad has copper. The alloy layer includes copper/tin alloys and copper/nickel/tin alloys over the contact area. The copper/tin alloys include Cu6Sn5 intermetallic compound. The copper/nickel/tin alloys include (Ni,Cu)6Sn5 intermetallic compound. A solder element including tin is metallurgically attached to the alloy layer across the pad area.
- The first alloys, dominated by copper/tin alloys, help to improve the drop test performance to the best level achieved by solder joints with copper pads. The second alloys, dominated by nickel-containing alloys, help to improve the life test performance by slowing the aging conditions.
- A preferred method of forming the desired number, distribution, and thickness of the alloy regions in the above-described embodiment is to deposit a thin nickel layer of pre-determined thickness over the copper contact pad, to attach a tin-containing solder element to the nickel layer, and to reflow the solder according to a selected time-temperature profile.
- In another embodiment of the invention, the alloy layer may include gold or palladium.
- The technical advantages represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
-
FIG. 1 illustrates a schematic cross section of a semiconductor device of the ball grid array (BGA) type having solder elements for external connections. -
FIG. 2 is a schematic cross section of portion “A” (FIG. 1 ) of the substrate showing the detail of a contact pad before solder element attachment. -
FIG. 3 is a schematic cross section of portion “A” (FIG. 1 ) of the substrate showing the detail of a contact pad after reflow of the solder element. -
FIG. 4 is a schematic cross section of portion “B” (FIG. 3 ) of a solder joint. -
FIG. 5 illustrates an example of a time-temperature profile for a copper contact with a thin nickel layer to reflow tin solder and create copper/tin and nickel/tin, nickel/copper/tin alloy regions. -
FIG. 1 illustrates schematically a representative of the large family of ball grid array (BGA) semiconductor devices.Semiconductor chip 101 is assembled onsubstrate 102 by usingchip attach material 103 for mechanical attachment andbonding wires 104 for electrical connections. The assembly is encapsulated, typically inmolding compound 105. -
Substrate 102 has one or more patterned metal layers for internal interconnection (not shown inFIG. 1 ), especially to create connecting lines between the wirestitch bond sites 106 and thecontact pads 107 for external connections. The metal layers are separated by insulating layers.Solder elements 108 are attached to thecontact pads 107. The reliability of this solder attachment under various test and use conditions deserves special consideration. - Portion “A” of the device is shown in more detail in
FIGS. 2 and 3 .FIG. 2 illustrates a device contact pad before the reflow ofsolder element 208, andFIG. 3 after the reflow process. InFIG. 2 ,substrate 102 has aninsulating surface layer 201, which is often referred to as a solder mask. A window ofwidth 202 has been opened insolder mask 201, which exposes a portion of the interconnectingmetallization 210 of the substrate and thus defines the contact area.Metallization 210 is made of copper, and the area of the exposed copper is determined by thewidth 202 of the solder mask window. - A
layer 211 of nickel is deposited over the area of the exposed copper; in addition, alayer 212 of a noble metal such as gold or palladium is deposited over the nickel layer. The thickness of the nickel layer in this embodiment is between about 0.01 and 0.3 μm; a preferred thickness range is 0.12±0.04 μm. The thickness of the gold layer is between about 0.1 and 1.0 μm; a preferred thickness range is 0.5±0.25 μm. -
Solder reflow element 208 contains tin; in addition, it may contain one or more of the metals selected from a group consisting of lead, silver, bismuth, indium, zinc, copper, nickel and antimony. For the nickel layer thickness in this embodiment, the amount of tin, and other reflow metals, inreflow element 208 is much larger than the amount of nickel. - As
FIG. 2 shows,substrate 102 has one ormore pads 220 on the substrate surface opposite to thecontact pad 202; these pads serve as bond pads for theconnection wires 230 to the semiconductor chip bond pads. Sincewire 230 is preferably made of gold andpad 220 preferably is intended forgold wire stitches 231,pad 220 is preferably made of a stack of layers includingcopper layer 221,nickel layer 222, andgold layer 223. -
FIG. 3 illustrates the device contact pad after the reflow of thesolder element 208. 210 is the copper line with the contact pad exposed by the window ofwidth 202 insolder resist 201.Width 202 defines the copper contact area. - Metallurgically attached to the copper, across the area, is an
alloy layer 301, which includes tin, copper and nickel. Region “B” ofFIG. 3 is enlarged inFIG. 4 . In order to achieve the best reliability performance, the alloy should consume the entire deposited nickel layer in the contact area. Metallurgically attached toalloy layer 301 isreflow element 308 with tin as its main component. - In
FIG. 4 , on an insulating portion ofsubstrate 102 is a portion of thecopper layer 210 in the copper contact area. Metallurgically attached tocopper layer 210 isalloy layer 301, and metallurgically attached toalloy layer 301 is a portion ofreflow element 308, containing mainly tin. -
Alloy layer 301 comprises copper/tin alloys and copper/nickel/tin alloys. The copper/tin alloys comprise a high percentage of Cu6Sn5 intermetallic compound, frequently in scallop-type outline. The nickel/copper/tin alloys comprise a high percentage of (Ni, Cu)6Sn5 intermetallic compound, frequently with crystallites spalled off into the alloy layer. - In embodiments, which have gold as a component of the alloys, the alloys comprise a high percentage of (Cu, Ni, Au)6Sn5 intermetallic compound. With the latter intermetallic compound, the thickness of the alloy layer is preferably between 2.0 and 3.0 μm.
- The nickel-containing alloys have consumed all available nickel from the original nickel layer so that no fraction of the nickel layer is left after the alloy formation (reflow) process.
- A pre-determined ratio between copper/tin alloys and nickel/copper/tin alloys can be manufactured by selecting the values of two parameters: the thickness of the nickel layer and the time-temperature profile of the reflow process. An example of a preferred time-
temperature sequence 501 for a nickel layer in the 0.1±0.05 μm thickness range is reproduced inFIG. 5 (temperature measured in ° C., time in minutes). As can be seen, the profile has apre-heat range 501 between about 130 and 170° C. of about 1 to 2 min, and ahigh temperature range 502 above about 230° C. of about ¼to ¾min. - Quantitative investigations by the inventor have shown that copper/tin alloys help to improve the drop test performance of the assembled device to the best level achieved by solder joints with copper pads. On the other hand, nickel-containing alloys, obtained from a starting nickel layer thickness of approximately 0.1 μm, improve the life test performance of the finished device characteristics by slowing the aging conditions so much that the device characteristics remain approximately constant over the expected device life span.
- In other embodiments of the invention, the
alloy layer 301 together with the reflowedtin solder element 308 may include dissolved noble metals such as gold or palladium. The noble metal, shown inFIG. 2 as a deposited layer, is dissolved in the process step of reflowing. - While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, even thinner nickel layers may be employed—just enough nickel to shield the copper from oxidation. It is therefore intended that the appended claims encompass any such modification.
Claims (14)
1. A method of fabricating a semiconductor device, comprising:
depositing a nickel layer on a copper contact pad on a surface of a substrate to which a semiconductor chip is affixed;
depositing a tin-containing solder layer on the nickel layer;
dissolving the entire nickel layer at an elevated temperature forming an alloy layer; and
the alloy layer contacting the copper contact pad on one side and the solder layer on the opposite side.
2. The method of claim 1 , further comprising depositing a gold layer between the nickel layer and the solder layer.
3. The method of claim 2 , further comprising dissolving the gold layer into the alloy layer.
4. The method of claim 1 , further comprising depositing a palladium layer between the nickel layer and the solder layer.
5. The method of claim 4 , further comprising dissolving the palladium layer into the alloy layer.
6. The method of claim 1 , in which the alloy layer includes copper/tin alloys and copper/nickel/tin alloys.
7. The method of claim 6 , in which the copper/nickel/tin alloys include (Cu, Ni, Au)6Sn5 intermetallic compound.
8. The method of claim 6 , in which the copper/tin alloys include Cu6Sn5 intermetallic compound.
9. The method of claim 1 , in which the substrate includes a solder mask window over the copper contact pad, defining a substrate contact.
10. The method of claim 9 , in which the alloy layer is confined to the substrate contact.
11. The method of claim 1 , in which the alloy layer is disposed on a first substrate surface opposite a second substrate surface on which the semiconductor chip is affixed.
12. The method of claim 11 , in which the second substrate surface is free of solder material.
13. The method of claim 11 , in which the semiconductor chip is affixed to the second substrate surface via bond wires.
14. The method of claim 13 , in which the bond wires include gold.
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US13/008,158 US20110136335A1 (en) | 2005-08-11 | 2011-01-18 | Semiconductor Device with Improved Contacts |
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US13/008,158 US20110136335A1 (en) | 2005-08-11 | 2011-01-18 | Semiconductor Device with Improved Contacts |
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US13/008,158 Abandoned US20110136335A1 (en) | 2005-08-11 | 2011-01-18 | Semiconductor Device with Improved Contacts |
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US7233074B2 (en) * | 2005-08-11 | 2007-06-19 | Texas Instruments Incorporated | Semiconductor device with improved contacts |
JP2007287712A (en) * | 2006-04-12 | 2007-11-01 | Oki Electric Ind Co Ltd | Semiconductor device, packaging structure thereof, and manufacturing method of semiconductor device and packaging structure |
WO2009051181A1 (en) * | 2007-10-19 | 2009-04-23 | Nihon Superior Sha Co., Ltd. | Lead-free solder alloy |
US7847399B2 (en) * | 2007-12-07 | 2010-12-07 | Texas Instruments Incorporated | Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles |
US8592995B2 (en) * | 2009-07-02 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump |
JP2011044624A (en) * | 2009-08-24 | 2011-03-03 | Hitachi Ltd | Semiconductor device, and on-vehicle ac generator |
US8679591B2 (en) * | 2009-11-17 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing voids in a copper-tin interface and structure formed thereby |
US8698306B2 (en) | 2010-05-20 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate contact opening |
JP6046406B2 (en) * | 2011-07-26 | 2016-12-14 | ローム アンド ハース エレクトロニック マテリアルズ エルエルシーRohm and Haas Electronic Materials LLC | High temperature resistant silver coated substrate |
JP2013093538A (en) * | 2011-10-04 | 2013-05-16 | Ngk Spark Plug Co Ltd | Wiring board and manufacturing method of the same |
JP6028449B2 (en) * | 2011-10-05 | 2016-11-16 | 富士通株式会社 | Semiconductor device, electronic device, and manufacturing method of semiconductor device |
KR101359733B1 (en) * | 2011-12-16 | 2014-02-11 | 성균관대학교산학협력단 | Bump including diffusion barrier bi-layer for the 3d integration applications and manufacturing method thereof |
US9627344B2 (en) | 2013-04-04 | 2017-04-18 | Rohm Co., Ltd. | Semiconductor device |
KR101514529B1 (en) * | 2013-07-09 | 2015-04-22 | 삼성전기주식회사 | Printed circuit board and manufacturing method thereof |
US9941146B2 (en) * | 2015-07-15 | 2018-04-10 | Chip Solutions, LLC | Semiconductor device and method |
CN107195605A (en) * | 2017-05-18 | 2017-09-22 | 上海交通大学 | Cuprum-nickel-stannum micro bump using thin nickel dam as barrier layer and preparation method thereof |
KR20190085590A (en) * | 2018-01-11 | 2019-07-19 | 삼성전자주식회사 | Semiconductor device, semiconductor package including the semiconductor device, and method of fabricating the semiconductor device |
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- 2006-08-09 CN CNB2006800282088A patent/CN100565859C/en active Active
- 2006-08-09 WO PCT/US2006/031023 patent/WO2007021736A2/en active Application Filing
- 2006-08-09 KR KR1020087005819A patent/KR100969400B1/en active IP Right Grant
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Also Published As
Publication number | Publication date |
---|---|
US20070035023A1 (en) | 2007-02-15 |
CN101233613A (en) | 2008-07-30 |
US7233074B2 (en) | 2007-06-19 |
TWI314354B (en) | 2009-09-01 |
EP1922755A2 (en) | 2008-05-21 |
EP1922755A4 (en) | 2018-05-02 |
US7893544B2 (en) | 2011-02-22 |
JP2009505404A (en) | 2009-02-05 |
TW200713534A (en) | 2007-04-01 |
KR100969400B1 (en) | 2010-07-14 |
KR20080038213A (en) | 2008-05-02 |
WO2007021736A3 (en) | 2007-05-24 |
US20070284740A1 (en) | 2007-12-13 |
WO2007021736A2 (en) | 2007-02-22 |
CN100565859C (en) | 2009-12-02 |
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