US20110156145A1 - Fabrication of channel wraparound gate structure for field-effect transistor - Google Patents
Fabrication of channel wraparound gate structure for field-effect transistor Download PDFInfo
- Publication number
- US20110156145A1 US20110156145A1 US13/042,973 US201113042973A US2011156145A1 US 20110156145 A1 US20110156145 A1 US 20110156145A1 US 201113042973 A US201113042973 A US 201113042973A US 2011156145 A1 US2011156145 A1 US 2011156145A1
- Authority
- US
- United States
- Prior art keywords
- gate
- disposed
- semiconductor body
- insulation material
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000005669 field effect Effects 0.000 title abstract description 6
- 238000004519 manufacturing process Methods 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 9
- 239000011800 void material Substances 0.000 claims description 5
- 239000012774 insulation material Substances 0.000 claims 26
- 238000000034 method Methods 0.000 abstract description 13
- 238000005468 ion implantation Methods 0.000 abstract description 11
- 238000000231 atomic layer deposition Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 25
- 229910052710 silicon Inorganic materials 0.000 description 20
- 239000010703 silicon Substances 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 238000002513 implantation Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 239000012286 potassium permanganate Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 150000001298 alcohols Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/926—Dummy metallization
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/957—Making metal-insulator-metal device
Definitions
- the invention is in the field of Field-Effect Transistors.
- CMOS complementary metal-oxide-semiconductor
- Examples of transistors having reduced bodies along with tri-gate structures are shown in US 2004/0036127.
- Other small transistors are delta-doped transistors formed in lightly doped or undoped epitaxial layers grown on a heavily doped substrate. See, for instance, “Metal Gate Transistor with Epitaxial Source and Drain Regions,” application Ser. No. 10/955,669, filed Sep. 29, 2004, assigned to the assignee of the present application.
- Off-state current reduces the switching efficiency and robs system power. This is particularly significant in planar CMOS transistors, where substrate leakage paths account for most of the current flow in the off state. While three-dimensional structures such as tri-gates and fin-FETs are more scalable, since they have more effective electrostatic control, there still remains a leakage path in the channel.
- FIG. 1 is a cross-sectional, elevation view of a silicon-on-insulator (SOT) substrate.
- SOT silicon-on-insulator
- FIG. 2 is a perspective view of the structure of FIG. 1 , after the formation of a silicon body, sometimes referred to as a fin.
- FIG. 3 illustrates the structure of FIG. 2 , after a dummy gate is fabricated and during a first ion implantation step.
- FIG. 4 illustrates the structure of FIG. 3 , after spacers are fabricated and during a second ion implantation step.
- FIG. 5 illustrates the structure of FIG. 4 , after forming a dielectric layer and after the removal of the dummy gate.
- FIG. 6 is a cross-sectional, elevation view of the structure of FIG. 5 through section line 6 - 6 of FIG. 5 .
- FIG. 7 illustrates the structure of FIG. 6 during an ion implantation step.
- FIG. 8 illustrates the structure of FIG. 7 after an etching step which removes the BOX under the channel region. This view is generally through section line- 8 - 8 of FIG. 5 .
- FIG. 9 is an enlarged view of the region beneath the gate after the formation of a gate dielectric layer and a gate metal.
- FIG. 10 is a cross-sectional, elevation view taken through the same plane as FIG. 6 , this view illustrates the formation of the gate encircling the entire channel region of a semiconductor body.
- CMOS field-effect transistors A process for fabricating CMOS field-effect transistors and the resultant transistors are described.
- numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as cleaning steps, are not described in detail, in order to not unnecessarily obscure the present invention.
- the fabrication of a single transistor is described. As will be appreciated in the typical integrated circuit, both n and p channel transistors are fabricated.
- transistors are fabricated on a buried oxide layer (BOX) 20 which is disposed on a silicon substrate 21 shown in FIG. 1 .
- Transistor bodies are fabricated from a monocrystalline, silicon layer 24 disposed on BOX 20 .
- This silicon-on-insulation (SOT) substrate is well-known in the semiconductor industry.
- the SOI substrate is fabricated by bonding the oxide layer 20 and silicon layer 24 onto the substrate 21 , and then planarizing the layer 24 until it is relatively thin.
- Other techniques are known for forming an SOI substrate including, for instance, the implantation of oxygen into a silicon substrate to form a buried oxide layer.
- Other semiconductor materials, other than silicon, may also be used such as gallium arsenide.
- the BOX is seeded through ion implantation beneath the channel region of a transistor to make the oxide more readily etchable than the overlying silicon body.
- An electrically inactive species is implemented so as to not alter the electrical characteristics of the semiconductor body.
- a gate insulator and gate are formed entirely around the channel.
- the layer 24 may be selectively ion implanted with a p type dopant in regions where n channel transistors are to be fabricated, and with an n type dopant in those regions where p channel devices are to be fabricated. This is used to provide the relatively light doping typically found in the channel regions of MOS devices fabricated in a CMOS integrated circuit.
- a protective oxide is disposed on the silicon layer 24 followed by the deposition of a silicon nitride layer (both not shown).
- the nitride layer acts as a hard mask to define silicon bodies such as the silicon body 25 of FIG. 2 .
- the body 25 may have a height and width of 20-30 nm.
- An oxide (not shown) which subsequently acts as an etchant stop is formed over body 25 .
- a polysilicon layer is formed over the structure of FIG. 2 and etched to define a dummy gate 30 which extends over the body 25 as seen in FIG. 3 .
- the region of the body 25 below the dummy gate 30 is the channel region in this replacement gate process.
- phosphorous or arsenic may be implanted into the body 25 for an n channel transistor, or boron for a p channel transistor in alignment with the dummy gate, as illustrated by the ion implantation 26 . This ion implantation defines the tip or extension source and drain regions frequently used in CMOS transistors.
- a layer of silicon nitride is conformally deposited over the structure of FIG. 3 to fabricate the spacers 38 shown in FIG. 4 .
- Ordinary, well-known, anisotropic etching is used to fabricate the spacers.
- a carbon-doped nitride, doped with 5-13% carbon concentration is used for the spacers.
- the main part of the source and drain regions are formed through ion implantation 35 shown in FIG. 4 .
- arsenic or phosphorous is used with an implant dose of up to 1 ⁇ 10 19 -1 ⁇ 10 20 atoms/cm 3 .
- a similar dose range of boron may be used for a p channel transistor.
- the silicon body 25 Following the implantation of the main source and drain region, the silicon body 25 , to the extent that it extends beyond the spacers 38 , receives a silicide or salicide layer 39 as is often done on exposed silicon in field-effect transistors.
- An annealing step to activate the source and drain dopant is used, also commonly used cleaning steps common in the fabrication of a field-effect transistor are not shown.
- a dielectric layer 40 is now conformally deposited over the structure of FIG. 4 , as shown in FIG. 5 .
- This may comprise a silicon dioxide layer which will become an interlayer dielectric (ILD) in an integrated circuit or a low-k ILD may be used. Alternatively, a sacrificial dielectric layer may be used.
- the layer 40 typically has the mechanical strength to withstand a planarization process such as chemical mechanical polishing (CMP) so that it may be polished level with the top of the spacers 38 .
- CMP chemical mechanical polishing
- FIG. 6 After the deposition and planarization of the dielectric layer 40 , a wet etch is used to remove the dummy polysilicon gate 30 , leaving the opening 45 , as shown in FIG. 5 . (A dummy gate oxide (not shown) may also be removed.)
- the cross-sectional view of FIG. 6 taken through section line 6 - 6 of FIG. 5 , also shows the body 25 . This view is a better reference for the ion implantation of FIG. 7 .
- the wafer having the structure of FIG. 6 is now ion implanted at an angle of ⁇ ° relative to the normal of the wafer with the wafer at two different angles of rotation. These angles of rotation are in the plane of the wafer and are referred to below as the wafer rotation angle.
- the angle between the normal to the wafer and the ion beam is referred to below as the ion implantation angle ⁇ .
- the wafer is ion implanted at the angle ⁇ with the wafer rotated to an angle of 90°.
- implantation occurs again at the angle ⁇ with the wafer rotated to an angle of 270°.
- the implanted ions are implanted into the dielectric 40 , in the exposed portions of the BOX 20 , as well as under the channel region of the body 25 and in the channel region of body 25 .
- ⁇ may be in the range of 30°-60°, the angle is selected so as to insure that the ions are implanted into all the BOX 20 under the body 25 .
- Ions seeded into the upper portion of BOX 20 shown as region 20 a , cause BOX 20 to be more readily etched and to provide better selectivity between the region 20 a versus the body 25 and the non-implanted regions of BOX 20 .
- the ions alter the crystalline nature of BOX 20 , in effect, amorphizing or modifying the structure making it less resistant to selected chemistry without making body 25 or non-implanted regions of the BOX 20 more readily etched.
- the implanted region 20 a is etched more readily in the presence of the wet etchant compared to the body 25 or unexposed portions of the BOX 20 , allowing the implanted portion of the BOX 20 (region 20 a ), including beneath the body 25 to be removed without substantially affecting the dimensions of the body 25 .
- pre-etch implantation may be found in US2004/0118805. Wet etchant discrimination ratio of 6-1 between implanted silicon dioxide and non-implanted silicon dioxide are achievable.
- Ions selected for the implantation shown in FIG. 7 are electrically inactive in the BOX 20 and the semiconductor body 25 .
- silicon can be implanted where the body 25 is a silicon body, to disrupt the structure of the silicon dioxide without altering the electrical properties of the body 25 .
- the additional silicon ions implanted in body 25 are re-crystallized and have substantially no impact on the transistor characteristics.
- electrically inactive species such as nitrogen or halogens (fluorine, chlorine, etc.) may be implanted to create structural alteration with the resultant modification of the wet etch rate without adversely effecting the electrical behavior of the transistor. These species remain in the silicon without altering the electrical characteristics of the transistor which is subsequently formed.
- Relatively low implantation energies and dose levels are adequate to sufficiently seed the BOX 20 beneath the body 25 to allow removal of the oxide below the body.
- energy levels for implanting silicon in the range of 0.5-2.0 KeV, to a dose of 1 ⁇ 10 18 atoms/cm 2 are sufficient for a silicon body having dimensions of approximately 20 ⁇ 20 nm.
- a wet etch is used to remove the region 20 a including the region 20 a under the body 25 .
- Many wet chemical etchants are known to be effective and controllable on such thin film materials. As would be apparent to one skilled in the art, they may be appropriately matched with substrate and thin film materials, such as those above, to provide desirable selective etching.
- Suitable etchants include but are not limited to phosphoric acid (H 3 PO 4 ), hydrofluoric acid (HF), buffered HF, hydrochloric acid (HCl), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), ammonium hydroxide (NH 4 OH), alcohols, potassium permanganate (KMnO 4 ), ammonium fluoride (NH 4 F), and others, as would be listed in known wet chemical etching references such as Thin Film Processes , Academic Press (1978), edited by John L. Vossen and Werner Kern. Mixtures of these and other etchant chemicals are also conventionally used.
- the wet etchant of the region 20 a of layer 20 defines a trench aligned with the opening 45 which extends beneath the body 25 .
- This trench is best seen in FIG. 8 as trench 50 . Note, this view is taken through the section lines 8 - 8 of FIG. 5 . In this view the source and drain regions 55 are visible.
- the trench 50 is encircled with the circle 60 , and enlarged in FIG. 9 , as will be subsequently discussed.
- a gate dielectric 62 may now be formed on exposed surfaces which includes the sides, top and bottom of the body 25 .
- the gate dielectric has a high dielectric constant (k), such as a metal oxide dielectric, for instance, HfO 2 or ZrO 2 or other high k dielectrics, such as PZT or BST.
- the gate dielectric may be formed by any well-known technique such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Alternately, the gate dielectric may be a grown dielectric.
- the gate dielectric 62 may be a silicon dioxide film grown with a wet or dry oxidation process to a thickness between 5-50 ⁇ .
- a gate electrode (metal) layer 63 is formed over the gate dielectric layer 62 .
- the gate electrode layer 62 may be formed by blanket deposition of a suitable gate electrode material.
- a gate electrode material comprises a metal film such as tungsten, tantalum, titanium and/or nitrides and alloys thereof.
- n channel transistors a work function in the range of 3.9 to 4.6 eV may be used.
- p channel transistors a work function of 4.6 to 5.2 eV may be used. Accordingly, for substrates with both n channel and p channel transistors, two separate metal deposition processes may need to be used. Only approximately 100 ⁇ of the metal needs to be formed through ALD to set the work function. The remainder of the gate may be formed of polysilicon.
- the formation of the gate beneath the body 25 may not be as well defined as the gate on the sides and top of the body 25 .
- a void 64 may occur.
- Such a void will not affect the performance of the transistor.
- some of the BOX 20 (not shown) may remain directly under the body 25 in the trench 50 . This oxide, which is subsequently covered with both the high-k dielectric 62 and the metal 63 , will not meaningfully impact transistor performance.
- the above described method may also be used on other three dimensional (3D) semiconductor bodies such as semiconducting carbon nanotubes, Group 3-5 nanowires and silicon nanowires.
- the surface upon which the 3D semiconductor nanostructure rests is ion implanted to alter its etching rate to make it more etchable than the nanostructure.
- ALD is then used to form a dielectric and gate entirely around the semiconductor body for one embodiment.
Abstract
A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
Description
- This application is a continuation of U.S. patent application Ser. No. 11/240,440, filed Sep. 29, 2005, the entire contents of which are hereby incorporated by reference herein.
- The invention is in the field of Field-Effect Transistors.
- The continuing trend in the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors is to scale the transistors. Examples of transistors having reduced bodies along with tri-gate structures are shown in US 2004/0036127. Other small transistors are delta-doped transistors formed in lightly doped or undoped epitaxial layers grown on a heavily doped substrate. See, for instance, “Metal Gate Transistor with Epitaxial Source and Drain Regions,” application Ser. No. 10/955,669, filed Sep. 29, 2004, assigned to the assignee of the present application.
- The ability to continue scaling CMOS transistors to even smaller geometries is hindered by the off-state leakage current. Off-state current reduces the switching efficiency and robs system power. This is particularly significant in planar CMOS transistors, where substrate leakage paths account for most of the current flow in the off state. While three-dimensional structures such as tri-gates and fin-FETs are more scalable, since they have more effective electrostatic control, there still remains a leakage path in the channel.
- One structure for providing a more completely wrapped around gate is described in “Nonplanar Semiconductor Device with Partially or Fully Wrapped Around Gate Electrode and Methods of Fabrication,” U.S. patent application Ser. No. 10/607,769, filed Jun. 27, 2003.
-
FIG. 1 is a cross-sectional, elevation view of a silicon-on-insulator (SOT) substrate. -
FIG. 2 is a perspective view of the structure ofFIG. 1 , after the formation of a silicon body, sometimes referred to as a fin. -
FIG. 3 illustrates the structure ofFIG. 2 , after a dummy gate is fabricated and during a first ion implantation step. -
FIG. 4 illustrates the structure ofFIG. 3 , after spacers are fabricated and during a second ion implantation step. -
FIG. 5 illustrates the structure ofFIG. 4 , after forming a dielectric layer and after the removal of the dummy gate. -
FIG. 6 is a cross-sectional, elevation view of the structure ofFIG. 5 through section line 6-6 ofFIG. 5 . -
FIG. 7 illustrates the structure ofFIG. 6 during an ion implantation step. -
FIG. 8 illustrates the structure ofFIG. 7 after an etching step which removes the BOX under the channel region. This view is generally through section line-8-8 ofFIG. 5 . -
FIG. 9 is an enlarged view of the region beneath the gate after the formation of a gate dielectric layer and a gate metal. -
FIG. 10 is a cross-sectional, elevation view taken through the same plane asFIG. 6 , this view illustrates the formation of the gate encircling the entire channel region of a semiconductor body. - A process for fabricating CMOS field-effect transistors and the resultant transistors are described. In the following description, numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as cleaning steps, are not described in detail, in order to not unnecessarily obscure the present invention. Also, in the description below, the fabrication of a single transistor is described. As will be appreciated in the typical integrated circuit, both n and p channel transistors are fabricated.
- In one embodiment, transistors are fabricated on a buried oxide layer (BOX) 20 which is disposed on a
silicon substrate 21 shown inFIG. 1 . Transistor bodies are fabricated from a monocrystalline,silicon layer 24 disposed onBOX 20. This silicon-on-insulation (SOT) substrate is well-known in the semiconductor industry. By way of example, the SOI substrate is fabricated by bonding theoxide layer 20 andsilicon layer 24 onto thesubstrate 21, and then planarizing thelayer 24 until it is relatively thin. Other techniques are known for forming an SOI substrate including, for instance, the implantation of oxygen into a silicon substrate to form a buried oxide layer. Other semiconductor materials, other than silicon, may also be used such as gallium arsenide. - As will be seen, the BOX is seeded through ion implantation beneath the channel region of a transistor to make the oxide more readily etchable than the overlying silicon body. An electrically inactive species is implemented so as to not alter the electrical characteristics of the semiconductor body. Then, after removal of the BOX beneath the channel, a gate insulator and gate are formed entirely around the channel. Referring to
FIG. 1 , thelayer 24 may be selectively ion implanted with a p type dopant in regions where n channel transistors are to be fabricated, and with an n type dopant in those regions where p channel devices are to be fabricated. This is used to provide the relatively light doping typically found in the channel regions of MOS devices fabricated in a CMOS integrated circuit. - A protective oxide is disposed on the
silicon layer 24 followed by the deposition of a silicon nitride layer (both not shown). The nitride layer acts as a hard mask to define silicon bodies such as thesilicon body 25 ofFIG. 2 . By way of example, thebody 25 may have a height and width of 20-30 nm. - An oxide (not shown) which subsequently acts as an etchant stop is formed over
body 25. A polysilicon layer is formed over the structure ofFIG. 2 and etched to define adummy gate 30 which extends over thebody 25 as seen inFIG. 3 . The region of thebody 25 below thedummy gate 30, as will be seen, is the channel region in this replacement gate process. Once thedummy gate 30 has been defined, phosphorous or arsenic may be implanted into thebody 25 for an n channel transistor, or boron for a p channel transistor in alignment with the dummy gate, as illustrated by theion implantation 26. This ion implantation defines the tip or extension source and drain regions frequently used in CMOS transistors. - Now, a layer of silicon nitride is conformally deposited over the structure of
FIG. 3 to fabricate thespacers 38 shown inFIG. 4 . Ordinary, well-known, anisotropic etching is used to fabricate the spacers. In one embodiment, a carbon-doped nitride, doped with 5-13% carbon concentration is used for the spacers. After the spacer formation, the main part of the source and drain regions are formed throughion implantation 35 shown inFIG. 4 . For the n channel transistor, arsenic or phosphorous is used with an implant dose of up to 1×1019-1×1020 atoms/cm3. A similar dose range of boron may be used for a p channel transistor. - Following the implantation of the main source and drain region, the
silicon body 25, to the extent that it extends beyond thespacers 38, receives a silicide orsalicide layer 39 as is often done on exposed silicon in field-effect transistors. - An annealing step to activate the source and drain dopant is used, also commonly used cleaning steps common in the fabrication of a field-effect transistor are not shown.
- A
dielectric layer 40 is now conformally deposited over the structure ofFIG. 4 , as shown inFIG. 5 . This may comprise a silicon dioxide layer which will become an interlayer dielectric (ILD) in an integrated circuit or a low-k ILD may be used. Alternatively, a sacrificial dielectric layer may be used. In any event, thelayer 40 typically has the mechanical strength to withstand a planarization process such as chemical mechanical polishing (CMP) so that it may be polished level with the top of thespacers 38. - After the deposition and planarization of the
dielectric layer 40, a wet etch is used to remove thedummy polysilicon gate 30, leaving theopening 45, as shown inFIG. 5 . (A dummy gate oxide (not shown) may also be removed.) The cross-sectional view ofFIG. 6 , taken through section line 6-6 ofFIG. 5 , also shows thebody 25. This view is a better reference for the ion implantation ofFIG. 7 . - Referring to
FIG. 7 , the wafer having the structure ofFIG. 6 is now ion implanted at an angle of θ° relative to the normal of the wafer with the wafer at two different angles of rotation. These angles of rotation are in the plane of the wafer and are referred to below as the wafer rotation angle. The angle between the normal to the wafer and the ion beam is referred to below as the ion implantation angle θ. First, for instance, the wafer is ion implanted at the angle θ with the wafer rotated to an angle of 90°. Then, implantation occurs again at the angle θ with the wafer rotated to an angle of 270°. The wafer rotation angles of 90° and 270°, shown inFIG. 2 are perpendicular to thebody 25. Since 90° and 270° are 180° apart, the net effect is the same as implanting at ±θ, as shown inFIG. 7 . The implanted ions are implanted into the dielectric 40, in the exposed portions of theBOX 20, as well as under the channel region of thebody 25 and in the channel region ofbody 25. θ may be in the range of 30°-60°, the angle is selected so as to insure that the ions are implanted into all theBOX 20 under thebody 25. - Ions seeded into the upper portion of
BOX 20, shown asregion 20 a,cause BOX 20 to be more readily etched and to provide better selectivity between theregion 20 a versus thebody 25 and the non-implanted regions ofBOX 20. The ions alter the crystalline nature ofBOX 20, in effect, amorphizing or modifying the structure making it less resistant to selected chemistry without makingbody 25 or non-implanted regions of theBOX 20 more readily etched. More specifically, by selecting suitable ions and a suitable wet etchant, the implantedregion 20 a is etched more readily in the presence of the wet etchant compared to thebody 25 or unexposed portions of theBOX 20, allowing the implanted portion of the BOX 20 (region 20 a), including beneath thebody 25 to be removed without substantially affecting the dimensions of thebody 25. A discussion of pre-etch implantation may be found in US2004/0118805. Wet etchant discrimination ratio of 6-1 between implanted silicon dioxide and non-implanted silicon dioxide are achievable. - Ions selected for the implantation shown in
FIG. 7 are electrically inactive in theBOX 20 and thesemiconductor body 25. For example, silicon can be implanted where thebody 25 is a silicon body, to disrupt the structure of the silicon dioxide without altering the electrical properties of thebody 25. In subsequent annealing, the additional silicon ions implanted inbody 25 are re-crystallized and have substantially no impact on the transistor characteristics. Further, electrically inactive species such as nitrogen or halogens (fluorine, chlorine, etc.) may be implanted to create structural alteration with the resultant modification of the wet etch rate without adversely effecting the electrical behavior of the transistor. These species remain in the silicon without altering the electrical characteristics of the transistor which is subsequently formed. Relatively low implantation energies and dose levels are adequate to sufficiently seed theBOX 20 beneath thebody 25 to allow removal of the oxide below the body. For example, energy levels for implanting silicon in the range of 0.5-2.0 KeV, to a dose of 1×1018 atoms/cm2 are sufficient for a silicon body having dimensions of approximately 20×20 nm. - Following the implantation, a wet etch is used to remove the
region 20 a including theregion 20 a under thebody 25. Many wet chemical etchants are known to be effective and controllable on such thin film materials. As would be apparent to one skilled in the art, they may be appropriately matched with substrate and thin film materials, such as those above, to provide desirable selective etching. Suitable etchants include but are not limited to phosphoric acid (H3PO4), hydrofluoric acid (HF), buffered HF, hydrochloric acid (HCl), nitric acid (HNO3), acetic acid (CH3COOH), ammonium hydroxide (NH4OH), alcohols, potassium permanganate (KMnO4), ammonium fluoride (NH4F), and others, as would be listed in known wet chemical etching references such as Thin Film Processes, Academic Press (1978), edited by John L. Vossen and Werner Kern. Mixtures of these and other etchant chemicals are also conventionally used. - The wet etchant of the
region 20 a oflayer 20 defines a trench aligned with theopening 45 which extends beneath thebody 25. This trench is best seen inFIG. 8 as trench 50. Note, this view is taken through the section lines 8-8 ofFIG. 5 . In this view the source and drain regions 55 are visible. The trench 50 is encircled with the circle 60, and enlarged inFIG. 9 , as will be subsequently discussed. - A
gate dielectric 62 may now be formed on exposed surfaces which includes the sides, top and bottom of thebody 25. The gate dielectric has a high dielectric constant (k), such as a metal oxide dielectric, for instance, HfO2 or ZrO2 or other high k dielectrics, such as PZT or BST. The gate dielectric may be formed by any well-known technique such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Alternately, the gate dielectric may be a grown dielectric. For instance, thegate dielectric 62, may be a silicon dioxide film grown with a wet or dry oxidation process to a thickness between 5-50 Å. - Following this a gate electrode (metal)
layer 63 is formed over thegate dielectric layer 62. Thegate electrode layer 62 may be formed by blanket deposition of a suitable gate electrode material. In one embodiment, a gate electrode material comprises a metal film such as tungsten, tantalum, titanium and/or nitrides and alloys thereof. For the n channel transistors, a work function in the range of 3.9 to 4.6 eV may be used. For the p channel transistors, a work function of 4.6 to 5.2 eV may be used. Accordingly, for substrates with both n channel and p channel transistors, two separate metal deposition processes may need to be used. Only approximately 100 Å of the metal needs to be formed through ALD to set the work function. The remainder of the gate may be formed of polysilicon. - Standard processing is now used to complete the transistor of
FIG. 10 . - The formation of the gate beneath the
body 25 may not be as well defined as the gate on the sides and top of thebody 25. For instance, as shown inFIG. 9 , a void 64 may occur. Such a void, however, will not affect the performance of the transistor. Moreover, some of the BOX 20 (not shown) may remain directly under thebody 25 in the trench 50. This oxide, which is subsequently covered with both the high-k dielectric 62 and themetal 63, will not meaningfully impact transistor performance. - The above described method may also be used on other three dimensional (3D) semiconductor bodies such as semiconducting carbon nanotubes, Group 3-5 nanowires and silicon nanowires. The surface upon which the 3D semiconductor nanostructure rests is ion implanted to alter its etching rate to make it more etchable than the nanostructure.
- Thus, a method has been described for forming a gate entirely around a silicon body in a replacement gate process. Ion implantation damages the insulation beneath the semiconductor body in the channel region allowing it to be more readily etched. ALD is then used to form a dielectric and gate entirely around the semiconductor body for one embodiment.
Claims (20)
1. A transistor structure, comprising:
a semiconductor body disposed on a substrate;
source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions; and
a gate stack comprising a gate insulation material and a conductive gate material, the gate stack completely surrounding the channel region of the semiconductor body, wherein a portion of the gate stack between the semiconductor body and the substrate comprises a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.
2. The transistor structure defined by claim 1 , wherein the semiconductor body is disposed on an insulator layer of the substrate.
3. The transistor structure defined by claim 2 , wherein the portion of the gate stack between the semiconductor body and the substrate is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity.
4. The transistor structure defined by claim 3 , wherein the portion of the gate stack between the semiconductor body and the substrate only partially fills the cavity to provide a void in the layer of the conductive gate material of the portion of the gate stack between the semiconductor body and the substrate.
5. The transistor structure defined by claim 3 , wherein the portion of the gate stack between the semiconductor body and the substrate completely fills the cavity.
6. The transistor structure defined by claim 1 , wherein the gate insulation material comprises a high-k dielectric layer.
7. The transistor structure defined by claim 1 , wherein the conductive gate material comprises a metal and has a work function between 3.9 to 5.2 eV.
8. A transistor structure, comprising:
a semiconductor body disposed on a substrate and having a top surface, a bottom surface, a first side surface and a second side surface;
source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions;
a first gate electrode disposed on the top surface of the semiconductor body and comprising a gate insulation material and a conductive gate material;
a second gate electrode disposed on the first side surface of the semiconductor body and comprising the gate insulation material and the conductive gate material;
a third gate electrode disposed on the second side surface of the semiconductor body and comprising the gate insulation material and the conductive gate material; and
a fourth gate electrode disposed on the bottom surface of the semiconductor body and comprising the gate insulation material and the conductive gate material, the fourth gate electrode comprising a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.
9. The transistor structure defined by claim 8 , wherein the semiconductor body is disposed on an insulator layer of the substrate.
10. The transistor structure defined by claim 9 , wherein the fourth gate electrode is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity.
11. The transistor structure defined by claim 10 , wherein the fourth gate electrode only partially fills the cavity to provide a void in the layer of the conductive gate material of the fourth gate electrode.
12. The transistor structure defined by claim 10 , wherein the fourth gate electrode completely fills the cavity.
13. The transistor structure defined by claim 8 , wherein the gate insulation material comprises a high-k dielectric layer.
14. The transistor structure defined by claim 8 , wherein the conductive gate material comprises a metal and has a work function between 3.9 to 5.2 eV.
15. A transistor structure, comprising:
a semiconductor body disposed on a substrate and having a top surface, a bottom surface, and a pair of side surfaces;
source and drain regions disposed in the semiconductor body and defining a channel region in the semiconductor body, between the source and drain regions; and
a gate stack comprising a gate insulation material and a conductive gate material, the gate stack disposed on the entire top surface, the entire side surfaces, and at least a portion of the bottom surface of the semiconductor body, wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body comprises a top layer of the gate insulation material disposed above a layer of the conductive gate material which is disposed above a bottom layer of the gate insulation material.
16. The transistor structure defined by claim 15 , wherein the semiconductor body is disposed on an insulator layer of the substrate.
17. The transistor structure defined by claim 16 , wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body is disposed in a cavity disposed in the insulator layer of the substrate, and wherein the top layer of the gate insulation material is disposed on the top of the cavity, adjacent the semiconductor body, the bottom layer of the gate insulation material is disposed on the bottom of the cavity, and the top and bottom layers of the gate insulation material are joined by gate insulation material disposed along sides of the cavity.
18. The transistor structure defined by claim 17 , wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body only partially fills the cavity to provide a void in the conductive gate material of the portion of the gate stack disposed on the bottom surface of the semiconductor body.
19. The transistor structure defined by claim 17 , wherein the portion of the gate stack disposed on the bottom surface of the semiconductor body completely fills the cavity.
20. The transistor structure defined by claim 16 , wherein a portion of the insulator layer of the substrate is disposed between a portion of the portion of the gate stack disposed on the bottom surface of the semiconductor body.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/042,973 US20110156145A1 (en) | 2004-09-29 | 2011-03-08 | Fabrication of channel wraparound gate structure for field-effect transistor |
US15/197,563 US20160308014A1 (en) | 2004-09-29 | 2016-06-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/955,669 US7332439B2 (en) | 2004-09-29 | 2004-09-29 | Metal gate transistors with epitaxial source and drain regions |
US11/240,440 US7915167B2 (en) | 2004-09-29 | 2005-09-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
US13/042,973 US20110156145A1 (en) | 2004-09-29 | 2011-03-08 | Fabrication of channel wraparound gate structure for field-effect transistor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/240,440 Continuation US7915167B2 (en) | 2004-09-29 | 2005-09-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/197,563 Continuation US20160308014A1 (en) | 2004-09-29 | 2016-06-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110156145A1 true US20110156145A1 (en) | 2011-06-30 |
Family
ID=35788956
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/955,669 Active 2025-12-18 US7332439B2 (en) | 2004-09-29 | 2004-09-29 | Metal gate transistors with epitaxial source and drain regions |
US11/240,440 Expired - Fee Related US7915167B2 (en) | 2004-09-29 | 2005-09-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
US12/011,439 Expired - Fee Related US8344452B2 (en) | 2004-09-29 | 2008-01-24 | Metal gate transistors with raised source and drain regions formed on heavily doped substrate |
US13/042,973 Abandoned US20110156145A1 (en) | 2004-09-29 | 2011-03-08 | Fabrication of channel wraparound gate structure for field-effect transistor |
US15/197,563 Abandoned US20160308014A1 (en) | 2004-09-29 | 2016-06-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/955,669 Active 2025-12-18 US7332439B2 (en) | 2004-09-29 | 2004-09-29 | Metal gate transistors with epitaxial source and drain regions |
US11/240,440 Expired - Fee Related US7915167B2 (en) | 2004-09-29 | 2005-09-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
US12/011,439 Expired - Fee Related US8344452B2 (en) | 2004-09-29 | 2008-01-24 | Metal gate transistors with raised source and drain regions formed on heavily doped substrate |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/197,563 Abandoned US20160308014A1 (en) | 2004-09-29 | 2016-06-29 | Fabrication of channel wraparound gate structure for field-effect transistor |
Country Status (6)
Country | Link |
---|---|
US (5) | US7332439B2 (en) |
KR (1) | KR100867781B1 (en) |
CN (2) | CN103560150B (en) |
DE (1) | DE112005002302B4 (en) |
TW (1) | TWI272681B (en) |
WO (1) | WO2006039597A2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110767804A (en) * | 2019-11-19 | 2020-02-07 | 北京元芯碳基集成电路研究院 | Carbon nanotube device and manufacturing method thereof |
US10714598B2 (en) * | 2017-06-30 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor device |
US11538940B2 (en) * | 2015-03-27 | 2022-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
DE102017126544B4 (en) | 2017-06-30 | 2023-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | PROCESSES FOR MANUFACTURING SEMICONDUCTOR DEVICES |
Families Citing this family (130)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2002306436A1 (en) * | 2001-02-12 | 2002-10-15 | Asm America, Inc. | Improved process for deposition of semiconductor films |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7456476B2 (en) * | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7268058B2 (en) * | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
US7154118B2 (en) * | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
WO2005116304A2 (en) * | 2004-04-23 | 2005-12-08 | Asm America, Inc. | In situ doped epitaxial films |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7422946B2 (en) * | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7611943B2 (en) * | 2004-10-20 | 2009-11-03 | Texas Instruments Incorporated | Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
JP4369359B2 (en) | 2004-12-28 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device |
US7438760B2 (en) * | 2005-02-04 | 2008-10-21 | Asm America, Inc. | Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) * | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7402875B2 (en) * | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US20070090408A1 (en) * | 2005-09-29 | 2007-04-26 | Amlan Majumdar | Narrow-body multiple-gate FET with dominant body transistor for high performance |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8101485B2 (en) | 2005-12-16 | 2012-01-24 | Intel Corporation | Replacement gates to enhance transistor strain |
WO2007078802A2 (en) * | 2005-12-22 | 2007-07-12 | Asm America, Inc. | Epitaxial deposition of doped semiconductor materials |
US20070152266A1 (en) * | 2005-12-29 | 2007-07-05 | Intel Corporation | Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers |
US7425500B2 (en) * | 2006-03-31 | 2008-09-16 | Intel Corporation | Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors |
US7449373B2 (en) * | 2006-03-31 | 2008-11-11 | Intel Corporation | Method of ion implanting for tri-gate devices |
US7422960B2 (en) * | 2006-05-17 | 2008-09-09 | Micron Technology, Inc. | Method of forming gate arrays on a partial SOI substrate |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US7537994B2 (en) | 2006-08-28 | 2009-05-26 | Micron Technology, Inc. | Methods of forming semiconductor devices, assemblies and constructions |
US20080054361A1 (en) * | 2006-08-30 | 2008-03-06 | Infineon Technologies Ag | Method and apparatus for reducing flicker noise in a semiconductor device |
US7999251B2 (en) * | 2006-09-11 | 2011-08-16 | International Business Machines Corporation | Nanowire MOSFET with doped epitaxial contacts for source and drain |
JP5380827B2 (en) | 2006-12-11 | 2014-01-08 | ソニー株式会社 | Manufacturing method of semiconductor device |
US20090170270A1 (en) * | 2007-12-27 | 2009-07-02 | Texas Instruments Incorporated | Integration schemes to avoid faceted sige |
US7786518B2 (en) * | 2007-12-27 | 2010-08-31 | Texas Instruments Incorporated | Growth of unfaceted SiGe in MOS transistor fabrication |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US20100078728A1 (en) * | 2008-08-28 | 2010-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Raise s/d for gate-last ild0 gap filling |
US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
US20110079861A1 (en) * | 2009-09-30 | 2011-04-07 | Lucian Shifren | Advanced Transistors with Threshold Voltage Set Dopant Structures |
US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
US8367528B2 (en) * | 2009-11-17 | 2013-02-05 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
KR101634748B1 (en) | 2009-12-08 | 2016-07-11 | 삼성전자주식회사 | method for manufacturing MOS transistor and forming method of integrated circuit using the sime |
US8399314B2 (en) * | 2010-03-25 | 2013-03-19 | International Business Machines Corporation | p-FET with a strained nanowire channel and embedded SiGe source and drain stressors |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
CN102222692B (en) * | 2010-04-14 | 2013-06-12 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
CN102376572A (en) * | 2010-08-10 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor device |
US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
US11469271B2 (en) * | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US8778767B2 (en) | 2010-11-18 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and fabrication methods thereof |
US11508605B2 (en) * | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
DE102011004322B4 (en) * | 2011-02-17 | 2012-12-06 | Globalfoundries Dresden Module One Llc & Co. Kg | A method of manufacturing a semiconductor device having self-aligned contact elements and an exchange gate electrode structure |
US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
US8574990B2 (en) | 2011-02-24 | 2013-11-05 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gate |
US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8802524B2 (en) | 2011-03-22 | 2014-08-12 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gates |
US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
US8835266B2 (en) | 2011-04-13 | 2014-09-16 | International Business Machines Corporation | Method and structure for compound semiconductor contact |
US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
CN102891175B (en) * | 2011-07-19 | 2016-03-16 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and manufacture method thereof |
US9263566B2 (en) | 2011-07-19 | 2016-02-16 | Semiconductor Manufacturing International (Beijing) Corporation | Semiconductor device and manufacturing method thereof |
CN102891178A (en) * | 2011-07-19 | 2013-01-23 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and manufacturing method thereof |
CN102891177B (en) * | 2011-07-19 | 2016-03-02 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and manufacture method thereof |
US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
US20130032876A1 (en) | 2011-08-01 | 2013-02-07 | International Business Machines Corporation | Replacement Gate ETSOI with Sharp Junction |
US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
KR101891373B1 (en) | 2011-08-05 | 2018-08-24 | 엠아이이 후지쯔 세미컨덕터 리미티드 | Semiconductor devices having fin structures and fabrication methods thereof |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
US9847225B2 (en) * | 2011-11-15 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing the same |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
US9607987B2 (en) | 2011-12-21 | 2017-03-28 | Intel Corporation | Methods for forming fins for metal oxide semiconductor device structures |
US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
JP2013138201A (en) * | 2011-12-23 | 2013-07-11 | Imec | Method for manufacturing field-effect semiconductor device following replacement gate process |
US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
CN103187290B (en) * | 2011-12-31 | 2015-10-21 | 中芯国际集成电路制造(北京)有限公司 | Fin type field-effect transistor and manufacture method thereof |
US8735258B2 (en) * | 2012-01-05 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit resistor fabrication with dummy gate removal |
US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
US20140004677A1 (en) * | 2012-06-29 | 2014-01-02 | GlobalFoundries, Inc. | High-k Seal for Protection of Replacement Gates |
CN103578987B (en) | 2012-07-19 | 2016-08-24 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
US9431068B2 (en) | 2012-10-31 | 2016-08-30 | Mie Fujitsu Semiconductor Limited | Dynamic random access memory (DRAM) with low variation transistor peripheral circuits |
US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
US8994415B1 (en) | 2013-03-01 | 2015-03-31 | Suvolta, Inc. | Multiple VDD clock buffer |
US8988153B1 (en) | 2013-03-09 | 2015-03-24 | Suvolta, Inc. | Ring oscillator with NMOS or PMOS variation insensitivity |
US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
US9449967B1 (en) | 2013-03-15 | 2016-09-20 | Fujitsu Semiconductor Limited | Transistor array structure |
US9112495B1 (en) | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
US9412842B2 (en) | 2013-07-03 | 2016-08-09 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device |
US9263455B2 (en) | 2013-07-23 | 2016-02-16 | Micron Technology, Inc. | Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines |
US8976575B1 (en) | 2013-08-29 | 2015-03-10 | Suvolta, Inc. | SRAM performance monitor |
US9543410B2 (en) * | 2014-02-14 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and formation thereof |
US9112032B1 (en) * | 2014-06-16 | 2015-08-18 | Globalfoundries Inc. | Methods of forming replacement gate structures on semiconductor devices |
US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
JP6631950B2 (en) * | 2014-12-11 | 2020-01-15 | パナソニックIpマネジメント株式会社 | Nitride semiconductor device and method of manufacturing nitride semiconductor device |
US9496338B2 (en) | 2015-03-17 | 2016-11-15 | International Business Machines Corporation | Wire-last gate-all-around nanowire FET |
KR102290685B1 (en) | 2015-06-04 | 2021-08-17 | 삼성전자주식회사 | Semiconductor device |
US9972513B2 (en) * | 2016-03-07 | 2018-05-15 | Shibaura Mechatronics Corporation | Device and method for treating a substrate with hydrofluoric and nitric acid |
JP6903446B2 (en) * | 2016-03-07 | 2021-07-14 | 芝浦メカトロニクス株式会社 | Substrate processing equipment and substrate processing method |
US9768278B1 (en) * | 2016-09-06 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of Fin loss in the formation of FinFETS |
US11127590B2 (en) * | 2016-12-05 | 2021-09-21 | The Regents Of The University Of California | Method for ALD deposition on inert surfaces via Al2O3 nanoparticles |
CN108231594B (en) * | 2017-12-21 | 2020-10-02 | 上海集成电路研发中心有限公司 | Manufacturing method of FinFET device |
JP2021192396A (en) * | 2018-09-14 | 2021-12-16 | キオクシア株式会社 | Integrated circuit device and manufacturing method for integrated circuit device |
US11165032B2 (en) * | 2019-09-05 | 2021-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor using carbon nanotubes |
WO2023140840A1 (en) * | 2022-01-20 | 2023-07-27 | Applied Materials, Inc. | Methods for near surface work function engineering |
Citations (93)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4905063A (en) * | 1988-06-21 | 1990-02-27 | American Telephone And Telegraph Company, At&T Bell Laboratories | Floating gate memories |
US4907048A (en) * | 1987-11-23 | 1990-03-06 | Xerox Corporation | Double implanted LDD transistor self-aligned with gate |
US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
US4994873A (en) * | 1988-10-17 | 1991-02-19 | Motorola, Inc. | Local interconnect for stacked polysilicon device |
US4996574A (en) * | 1988-07-01 | 1991-02-26 | Fujitsu Limited | MIS transistor structure for increasing conductance between source and drain regions |
US5179037A (en) * | 1991-12-24 | 1993-01-12 | Texas Instruments Incorporated | Integration of lateral and vertical quantum well transistors in the same epitaxial stack |
US5278102A (en) * | 1990-08-18 | 1994-01-11 | Fujitsu Limited | SOI device and a fabrication process thereof |
US5391506A (en) * | 1992-01-31 | 1995-02-21 | Kawasaki Steel Corporation | Manufacturing method for semiconductor devices with source/drain formed in substrate projection. |
US5482877A (en) * | 1993-02-17 | 1996-01-09 | Samsung Electronics Co., Ltd. | Method for making a semiconductor device having a silicon-on-insulator structure |
US5495115A (en) * | 1993-08-06 | 1996-02-27 | Hitachi, Ltd. | Semiconductor crystalline laminate structure, forming method of the same, and semiconductor device employing the same |
US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
US5595941A (en) * | 1994-06-01 | 1997-01-21 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fine patterns |
US5716879A (en) * | 1994-12-15 | 1998-02-10 | Goldstar Electron Company, Ltd. | Method of making a thin film transistor |
US5856225A (en) * | 1997-11-24 | 1999-01-05 | Chartered Semiconductor Manufacturing Ltd | Creation of a self-aligned, ion implanted channel region, after source and drain formation |
US5859456A (en) * | 1994-11-02 | 1999-01-12 | Texas Instruments Incorporated | Multiple transistor integrated circuit with thick copper interconnect |
US5880015A (en) * | 1991-04-30 | 1999-03-09 | Sgs-Thomson Microelectronics, Inc. | Method of producing stepped wall interconnects and gates |
US5883564A (en) * | 1994-04-18 | 1999-03-16 | General Motors Corporation | Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer |
US5888309A (en) * | 1997-12-29 | 1999-03-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma |
US5889304A (en) * | 1996-06-28 | 1999-03-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US6013926A (en) * | 1996-11-20 | 2000-01-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with refractory metal element |
US6018176A (en) * | 1995-05-26 | 2000-01-25 | Samsung Electronics Co., Ltd. | Vertical transistor and memory cell |
US6031249A (en) * | 1996-07-11 | 2000-02-29 | Semiconductor Energy Laboratory Co., Ltd. | CMOS semiconductor device having boron doped channel |
US6174820B1 (en) * | 1999-02-16 | 2001-01-16 | Sandia Corporation | Use of silicon oxynitride as a sacrificial material for microelectromechanical devices |
US6190975B1 (en) * | 1996-09-17 | 2001-02-20 | Matsushita Electric Industrial Co., Ltd. | Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layer |
US6200865B1 (en) * | 1998-12-04 | 2001-03-13 | Advanced Micro Devices, Inc. | Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate |
US6335251B2 (en) * | 1998-05-29 | 2002-01-01 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US6358800B1 (en) * | 2000-09-18 | 2002-03-19 | Vanguard International Semiconductor Corporation | Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit |
US6359311B1 (en) * | 2001-01-17 | 2002-03-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same |
US6362111B1 (en) * | 1998-12-09 | 2002-03-26 | Texas Instruments Incorporated | Tunable gate linewidth reduction process |
US20020037619A1 (en) * | 2000-09-22 | 2002-03-28 | Kohei Sugihara | Semiconductor device and method of producing the same |
US20020036290A1 (en) * | 2000-09-28 | 2002-03-28 | Kabushiki Kaisha Toshiba | Semiconductor device having MIS field effect transistors or three-dimensional structure |
US6506692B2 (en) * | 2001-05-30 | 2003-01-14 | Intel Corporation | Method of making a semiconductor device using a silicon carbide hard mask |
US20030036290A1 (en) * | 2001-08-17 | 2003-02-20 | United Microelectronics Corp. | Method for improving the coating capability of low-k dielectric layer |
US6526996B1 (en) * | 2000-06-12 | 2003-03-04 | Promos Technologies, Inc. | Dry clean method instead of traditional wet clean after metal etch |
US20030042542A1 (en) * | 1996-04-26 | 2003-03-06 | Shigeto Maegawa | Semiconductor device having a thin film transistor and manufacturing method thereof |
US6534807B2 (en) * | 2001-08-13 | 2003-03-18 | International Business Machines Corporation | Local interconnect junction on insulator (JOI) structure |
US6537885B1 (en) * | 2002-05-09 | 2003-03-25 | Infineon Technologies Ag | Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer |
US6537862B2 (en) * | 2001-05-23 | 2003-03-25 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device having a GAA type transistor |
US6537901B2 (en) * | 2000-12-29 | 2003-03-25 | Hynix Semiconductor Inc. | Method of manufacturing a transistor in a semiconductor device |
US20030057486A1 (en) * | 2001-09-27 | 2003-03-27 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US20030057477A1 (en) * | 1999-06-18 | 2003-03-27 | Hergenrother John Michael | CMOS integrated circuit having vertical transistors and a process for fabricating same |
US6680240B1 (en) * | 2002-06-25 | 2004-01-20 | Advanced Micro Devices, Inc. | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
US20040016968A1 (en) * | 2002-04-08 | 2004-01-29 | Stmicroelectronics S.A. | Surround-gate semiconductor device encapsulated in an insulating medium |
US6686231B1 (en) * | 2002-12-06 | 2004-02-03 | Advanced Micro Devices, Inc. | Damascene gate process with sacrificial oxide in semiconductor devices |
US20040029393A1 (en) * | 2002-08-12 | 2004-02-12 | Applied Materials, Inc. | Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer |
US20040029345A1 (en) * | 2000-06-09 | 2004-02-12 | Simon Deleonibus | Damascene architecture electronics storage and method for making same |
US20040031979A1 (en) * | 2002-06-07 | 2004-02-19 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20040033639A1 (en) * | 2001-05-07 | 2004-02-19 | Applied Materials, Inc. | Integrated method for release and passivation of MEMS structures |
US6696366B1 (en) * | 1998-08-17 | 2004-02-24 | Lam Research Corporation | Technique for etching a low capacitance dielectric layer |
US20040038436A1 (en) * | 2002-08-09 | 2004-02-26 | Hitachi, Ltd. | Method of manufacturing a semiconductor integrated circuit device |
US20040036118A1 (en) * | 2002-08-26 | 2004-02-26 | International Business Machines Corporation | Concurrent Fin-FET and thick-body device fabrication |
US20040036126A1 (en) * | 2002-08-23 | 2004-02-26 | Chau Robert S. | Tri-gate devices and methods of fabrication |
US20040038533A1 (en) * | 1999-04-09 | 2004-02-26 | Chunlin Liang | Isolated junction structure and method of manufacture |
US6705571B2 (en) * | 2002-07-22 | 2004-03-16 | Northrop Grumman Corporation | System and method for loading stores on an aircraft |
US6706571B1 (en) * | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
US6709982B1 (en) * | 2002-11-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Double spacer FinFET formation |
US6713396B2 (en) * | 2002-04-29 | 2004-03-30 | Hewlett-Packard Development Company, L.P. | Method of fabricating high density sub-lithographic features on a substrate |
US6838322B2 (en) * | 2003-05-01 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a double-gated semiconductor device |
US6844238B2 (en) * | 2003-03-26 | 2005-01-18 | Taiwan Semiconductor Manufacturing Co., Ltd | Multiple-gate transistors with improved gate control |
US20050020020A1 (en) * | 2002-07-16 | 2005-01-27 | Nadine Collaert | Integrated semiconductor fin device and a method for manufacturing such device |
US20050019993A1 (en) * | 2003-07-24 | 2005-01-27 | Deok-Hyung Lee | Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage |
US6849556B2 (en) * | 2002-09-27 | 2005-02-01 | Oki Electric Industry Co., Ltd. | Etching method, gate etching method, and method of manufacturing semiconductor devices |
US6849884B2 (en) * | 2002-03-19 | 2005-02-01 | International Business Machines Corporation | Strained Fin FETs structure and method |
US20050023633A1 (en) * | 2003-08-01 | 2005-02-03 | Yee-Chia Yeo | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US6852559B2 (en) * | 2002-12-06 | 2005-02-08 | Hynix Semiconductor Inc. | Transistor of semiconductor device, and method for manufacturing the same |
US6855606B2 (en) * | 2003-02-20 | 2005-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-rod devices |
US6855990B2 (en) * | 2002-11-26 | 2005-02-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained-channel multiple-gate transistor |
US20050035415A1 (en) * | 2003-08-13 | 2005-02-17 | Yee-Chia Yeo | Multiple-gate transistors formed on bulk substrates |
US20050040444A1 (en) * | 2003-08-22 | 2005-02-24 | International Business Machines Corporation | Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates |
US20050040429A1 (en) * | 2003-04-17 | 2005-02-24 | Uppal Parvez N. | Gaas substrate with sb buffering for high in devices |
US6864540B1 (en) * | 2004-05-21 | 2005-03-08 | International Business Machines Corp. | High performance FET with elevated source/drain region |
US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US6867460B1 (en) * | 2003-11-05 | 2005-03-15 | International Business Machines Corporation | FinFET SRAM cell with chevron FinFET logic |
US20050059214A1 (en) * | 2003-09-16 | 2005-03-17 | International Business Machines Corporation | Method and structure of vertical strained silicon devices |
US6869868B2 (en) * | 2002-12-13 | 2005-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a MOSFET device with metal containing gate structures |
US20050062082A1 (en) * | 2003-09-22 | 2005-03-24 | Ernst Bucher | Field-effect transistors with weakly coupled layered inorganic semiconductors |
US20060014338A1 (en) * | 2004-06-30 | 2006-01-19 | International Business Machines Corporation | Method and structure for strained finfet devices |
US6998301B1 (en) * | 2003-09-03 | 2006-02-14 | Advanced Micro Devices, Inc. | Method for forming a tri-gate MOSFET |
US6998318B2 (en) * | 2002-07-26 | 2006-02-14 | Dongbuanam Semiconductor Inc. | Method for forming short-channel transistors |
US20060040054A1 (en) * | 2004-08-18 | 2006-02-23 | Pearlstein Ronald M | Passivating ALD reactor chamber internal surfaces to prevent residue buildup |
US20070001219A1 (en) * | 2005-06-30 | 2007-01-04 | Marko Radosavljevic | Block contact architectures for nanoscale channel transistors |
US7163898B2 (en) * | 2002-07-31 | 2007-01-16 | Stmicroelectronics S.R.L. | Method for manufacturing semiconductor integrated circuit structures |
US20070023795A1 (en) * | 2005-07-15 | 2007-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US20070029624A1 (en) * | 2005-08-03 | 2007-02-08 | International Business Machines Corporation | Fin-type field effect transistor |
US7183137B2 (en) * | 2003-12-01 | 2007-02-27 | Taiwan Semiconductor Manufacturing Company | Method for dicing semiconductor wafers |
US7273785B2 (en) * | 2002-09-05 | 2007-09-25 | International Business Machines Corporation | Method to control device threshold of SOI MOSFET's |
US20080017934A1 (en) * | 2006-05-18 | 2008-01-24 | Samsung Electronic Co., Ltd. | Wire-type semiconductor devices and methods of fabricating the same |
US20080017890A1 (en) * | 2006-06-30 | 2008-01-24 | Sandisk 3D Llc | Highly dense monolithic three dimensional memory array and method for forming |
US7323710B2 (en) * | 2003-07-23 | 2008-01-29 | Samsung Electronics Co., Ltd. | Fin field effect transistors having multi-layer fin patterns |
US7329913B2 (en) * | 2003-12-30 | 2008-02-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US7479421B2 (en) * | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US7655989B2 (en) * | 2006-11-30 | 2010-02-02 | International Business Machines Corporation | Triple gate and double gate finFETs with different vertical dimension fins |
Family Cites Families (201)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4198250A (en) * | 1979-02-05 | 1980-04-15 | Intel Corporation | Shadow masking process for forming source and drain regions for field-effect transistors and like regions |
JPS58201363A (en) * | 1982-05-20 | 1983-11-24 | Sanyo Electric Co Ltd | Formation of gate electrode |
GB2156149A (en) | 1984-03-14 | 1985-10-02 | Philips Electronic Associated | Dielectrically-isolated integrated circuit manufacture |
US4487652A (en) | 1984-03-30 | 1984-12-11 | Motorola, Inc. | Slope etch of polyimide |
US5514885A (en) * | 1986-10-09 | 1996-05-07 | Myrick; James J. | SOI methods and apparatus |
US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
US5346834A (en) | 1988-11-21 | 1994-09-13 | Hitachi, Ltd. | Method for manufacturing a semiconductor device and a semiconductor memory device |
KR930003790B1 (en) * | 1990-07-02 | 1993-05-10 | 삼성전자 주식회사 | Dielectric meterial |
JP3061406B2 (en) * | 1990-09-28 | 2000-07-10 | 株式会社東芝 | Semiconductor device |
JP3202223B2 (en) | 1990-11-27 | 2001-08-27 | 日本電気株式会社 | Method for manufacturing transistor |
US5521859A (en) * | 1991-03-20 | 1996-05-28 | Fujitsu Limited | Semiconductor memory device having thin film transistor and method of producing the same |
US5292670A (en) | 1991-06-10 | 1994-03-08 | Texas Instruments Incorporated | Sidewall doping technique for SOI transistors |
JPH05243572A (en) * | 1992-02-27 | 1993-09-21 | Fujitsu Ltd | Semiconductor device |
US5405454A (en) | 1992-03-19 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Electrically insulated silicon structure and producing method therefor |
JP2572003B2 (en) | 1992-03-30 | 1997-01-16 | 三星電子株式会社 | Method of manufacturing thin film transistor having three-dimensional multi-channel structure |
JPH0793441B2 (en) | 1992-04-24 | 1995-10-09 | ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド | Thin film transistor and manufacturing method thereof |
JPH06310547A (en) * | 1993-02-25 | 1994-11-04 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
EP0623963A1 (en) | 1993-05-06 | 1994-11-09 | Siemens Aktiengesellschaft | MOSFET on SOI substrate |
US5739544A (en) * | 1993-05-26 | 1998-04-14 | Matsushita Electric Industrial Co., Ltd. | Quantization functional device utilizing a resonance tunneling effect and method for producing the same |
US6730549B1 (en) * | 1993-06-25 | 2004-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for its preparation |
JP3460863B2 (en) | 1993-09-17 | 2003-10-27 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
JP3361922B2 (en) | 1994-09-13 | 2003-01-07 | 株式会社東芝 | Semiconductor device |
JP3378414B2 (en) | 1994-09-14 | 2003-02-17 | 株式会社東芝 | Semiconductor device |
US5602049A (en) | 1994-10-04 | 1997-02-11 | United Microelectronics Corporation | Method of fabricating a buried structure SRAM cell |
JPH08125152A (en) * | 1994-10-28 | 1996-05-17 | Canon Inc | Semiconductor device, correlation operating unit empolying it, ad converter, da converter, and signal processing system |
GB2295488B (en) | 1994-11-24 | 1996-11-20 | Toshiba Cambridge Res Center | Semiconductor device |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
JPH08204191A (en) * | 1995-01-20 | 1996-08-09 | Sony Corp | Field-effect transistor and its manufacture |
JP3303601B2 (en) | 1995-05-19 | 2002-07-22 | 日産自動車株式会社 | Groove type semiconductor device |
US5627097A (en) * | 1995-07-03 | 1997-05-06 | Motorola, Inc. | Method for making CMOS device having reduced parasitic capacitance |
US5658806A (en) | 1995-10-26 | 1997-08-19 | National Science Council | Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration |
US5814895A (en) | 1995-12-22 | 1998-09-29 | Sony Corporation | Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate |
KR100205442B1 (en) | 1995-12-26 | 1999-07-01 | 구본준 | Thin film transistor and method of fabricating the same |
US5817560A (en) * | 1996-09-12 | 1998-10-06 | Advanced Micro Devices, Inc. | Ultra short trench transistors and process for making same |
US6163053A (en) | 1996-11-06 | 2000-12-19 | Ricoh Company, Ltd. | Semiconductor device having opposite-polarity region under channel |
US5827769A (en) | 1996-11-20 | 1998-10-27 | Intel Corporation | Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode |
US5908313A (en) * | 1996-12-31 | 1999-06-01 | Intel Corporation | Method of forming a transistor |
JP4086926B2 (en) | 1997-01-29 | 2008-05-14 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
US5929526A (en) * | 1997-06-05 | 1999-07-27 | Micron Technology, Inc. | Removal of metal cusp for improved contact fill |
JPH118390A (en) | 1997-06-18 | 1999-01-12 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
US6251763B1 (en) * | 1997-06-30 | 2001-06-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
JPH1140811A (en) * | 1997-07-22 | 1999-02-12 | Hitachi Ltd | Semiconductor device and manufacture thereof |
US5952701A (en) | 1997-08-18 | 1999-09-14 | National Semiconductor Corporation | Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value |
US6232233B1 (en) * | 1997-09-30 | 2001-05-15 | Siemens Aktiengesellschaft | Methods for performing planarization and recess etches and apparatus therefor |
US6066869A (en) * | 1997-10-06 | 2000-05-23 | Micron Technology, Inc. | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
US5976767A (en) | 1997-10-09 | 1999-11-02 | Micron Technology, Inc. | Ammonium hydroxide etch of photoresist masked silicon |
US6120846A (en) | 1997-12-23 | 2000-09-19 | Advanced Technology Materials, Inc. | Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition |
US6117741A (en) | 1998-01-09 | 2000-09-12 | Texas Instruments Incorporated | Method of forming a transistor having an improved sidewall gate structure |
US6294416B1 (en) | 1998-01-23 | 2001-09-25 | Texas Instruments-Acer Incorporated | Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts |
US6097065A (en) * | 1998-03-30 | 2000-08-01 | Micron Technology, Inc. | Circuits and methods for dual-gated transistors |
US6087208A (en) | 1998-03-31 | 2000-07-11 | Advanced Micro Devices, Inc. | Method for increasing gate capacitance by using both high and low dielectric gate material |
US6215190B1 (en) | 1998-05-12 | 2001-04-10 | International Business Machines Corporation | Borderless contact to diffusion with respect to gate conductor and methods for fabricating |
US20010040907A1 (en) | 1998-06-12 | 2001-11-15 | Utpal Kumar Chakrabarti | Optical device including carbon-doped contact layers |
US6165880A (en) | 1998-06-15 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits |
US6153485A (en) | 1998-11-09 | 2000-11-28 | Chartered Semiconductor Manufacturing Ltd. | Salicide formation on narrow poly lines by pulling back of spacer |
TW449919B (en) * | 1998-12-18 | 2001-08-11 | Koninkl Philips Electronics Nv | A method of manufacturing a semiconductor device |
US6380558B1 (en) | 1998-12-29 | 2002-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
US6093621A (en) | 1999-04-05 | 2000-07-25 | Vanguard International Semiconductor Corp. | Method of forming shallow trench isolation |
US6459123B1 (en) | 1999-04-30 | 2002-10-01 | Infineon Technologies Richmond, Lp | Double gated transistor |
JP2001015704A (en) | 1999-06-29 | 2001-01-19 | Hitachi Ltd | Semiconductor integrated circuit |
US6218309B1 (en) * | 1999-06-30 | 2001-04-17 | Lam Research Corporation | Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features |
US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
TW432594B (en) | 1999-07-31 | 2001-05-01 | Taiwan Semiconductor Mfg | Manufacturing method for shallow trench isolation |
FR2799305B1 (en) | 1999-10-05 | 2004-06-18 | St Microelectronics Sa | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH ENVELOPING GRID AND DEVICE OBTAINED |
US6252284B1 (en) * | 1999-12-09 | 2001-06-26 | International Business Machines Corporation | Planarized silicon fin device |
US6303479B1 (en) * | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
JP4194237B2 (en) | 1999-12-28 | 2008-12-10 | 株式会社リコー | Voltage generation circuit and reference voltage source circuit using field effect transistor |
US6214679B1 (en) | 1999-12-30 | 2001-04-10 | Intel Corporation | Cobalt salicidation method on a silicon germanium film |
KR20020001839A (en) * | 2000-02-23 | 2002-01-09 | 와다 다다시 | Method and apparatus for polishing outer peripheral chamfered part of wafer |
US6483156B1 (en) | 2000-03-16 | 2002-11-19 | International Business Machines Corporation | Double planar gated SOI MOSFET structure |
FR2806832B1 (en) | 2000-03-22 | 2002-10-25 | Commissariat Energie Atomique | METAL SOURCE AND DRAIN MOS TRANSISTOR, AND METHOD FOR MANUFACTURING SUCH A TRANSISTOR |
US6391782B1 (en) * | 2000-06-20 | 2002-05-21 | Advanced Micro Devices, Inc. | Process for forming multiple active lines and gate-all-around MOSFET |
KR100545706B1 (en) | 2000-06-28 | 2006-01-24 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
EP1299914B1 (en) | 2000-07-04 | 2008-04-02 | Qimonda AG | Field effect transistor |
JP2002047034A (en) * | 2000-07-31 | 2002-02-12 | Shinetsu Quartz Prod Co Ltd | Quarts glass jig for process device utilizing plasma |
US6403981B1 (en) * | 2000-08-07 | 2002-06-11 | Advanced Micro Devices, Inc. | Double gate transistor having a silicon/germanium channel region |
US6562665B1 (en) * | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
US7163864B1 (en) | 2000-10-18 | 2007-01-16 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US6413802B1 (en) | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
US6716684B1 (en) * | 2000-11-13 | 2004-04-06 | Advanced Micro Devices, Inc. | Method of making a self-aligned triple gate silicon-on-insulator device |
US6472258B1 (en) | 2000-11-13 | 2002-10-29 | International Business Machines Corporation | Double gate trench transistor |
US6396108B1 (en) * | 2000-11-13 | 2002-05-28 | Advanced Micro Devices, Inc. | Self-aligned double gate silicon-on-insulator (SOI) device |
KR100767950B1 (en) | 2000-11-22 | 2007-10-18 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and method for fabricating the same |
US6552401B1 (en) | 2000-11-27 | 2003-04-22 | Micron Technology | Use of gate electrode workfunction to improve DRAM refresh |
US6413877B1 (en) | 2000-12-22 | 2002-07-02 | Lam Research Corporation | Method of preventing damage to organo-silicate-glass materials during resist stripping |
JP2002198368A (en) | 2000-12-26 | 2002-07-12 | Nec Corp | Method for fabricating semiconductor device |
US6524920B1 (en) | 2001-02-09 | 2003-02-25 | Advanced Micro Devices, Inc. | Low temperature process for a transistor with elevated source and drain |
US6475890B1 (en) | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
US6475869B1 (en) | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
FR2822293B1 (en) | 2001-03-13 | 2007-03-23 | Nat Inst Of Advanced Ind Scien | FIELD EFFECT TRANSISTOR AND DOUBLE GRID, INTEGRATED CIRCUIT COMPRISING THIS TRANSISTOR, AND METHOD OF MANUFACTURING THE SAME |
US6444513B1 (en) * | 2001-03-19 | 2002-09-03 | Advanced Micro Devices, Inc. | Metal gate stack with etch stop layer having implanted metal species |
US6787402B1 (en) | 2001-04-27 | 2004-09-07 | Advanced Micro Devices, Inc. | Double-gate vertical MOSFET transistor and fabrication method |
SG112804A1 (en) | 2001-05-10 | 2005-07-28 | Inst Of Microelectronics | Sloped trench etching process |
US6635923B2 (en) * | 2001-05-24 | 2003-10-21 | International Business Machines Corporation | Damascene double-gate MOSFET with vertical channel regions |
US6952040B2 (en) | 2001-06-29 | 2005-10-04 | Intel Corporation | Transistor structure and method of fabrication |
JP2003017508A (en) | 2001-07-05 | 2003-01-17 | Nec Corp | Field effect transistor |
US6492212B1 (en) * | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
JP2003142484A (en) * | 2001-10-31 | 2003-05-16 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
US20030085194A1 (en) * | 2001-11-07 | 2003-05-08 | Hopkins Dean A. | Method for fabricating close spaced mirror arrays |
US6509282B1 (en) * | 2001-11-26 | 2003-01-21 | Advanced Micro Devices, Inc. | Silicon-starved PECVD method for metal gate electrode dielectric spacer |
US7385262B2 (en) * | 2001-11-27 | 2008-06-10 | The Board Of Trustees Of The Leland Stanford Junior University | Band-structure modulation of nano-structures in an electric field |
US6657259B2 (en) | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
US6967351B2 (en) | 2001-12-04 | 2005-11-22 | International Business Machines Corporation | Finfet SRAM cell using low mobility plane for cell stability and method for forming |
US6610576B2 (en) | 2001-12-13 | 2003-08-26 | International Business Machines Corporation | Method for forming asymmetric dual gate transistor |
US6583469B1 (en) * | 2002-01-28 | 2003-06-24 | International Business Machines Corporation | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same |
KR100442089B1 (en) | 2002-01-29 | 2004-07-27 | 삼성전자주식회사 | Method of forming mos transistor having notched gate |
KR100458288B1 (en) | 2002-01-30 | 2004-11-26 | 한국과학기술원 | Double-Gate FinFET |
US20030151077A1 (en) | 2002-02-13 | 2003-08-14 | Leo Mathew | Method of forming a vertical double gate semiconductor device and structure thereof |
JP3782021B2 (en) | 2002-02-22 | 2006-06-07 | 株式会社東芝 | Semiconductor device, semiconductor device manufacturing method, and semiconductor substrate manufacturing method |
US6605498B1 (en) | 2002-03-29 | 2003-08-12 | Intel Corporation | Semiconductor transistor having a backfilled channel material |
KR100410574B1 (en) * | 2002-05-18 | 2003-12-18 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by decaborane doping |
US6642090B1 (en) | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
US7078284B2 (en) * | 2002-06-20 | 2006-07-18 | Micron Technology, Inc. | Method for forming a notched gate |
US7105891B2 (en) | 2002-07-15 | 2006-09-12 | Texas Instruments Incorporated | Gate structure and method |
US6919238B2 (en) | 2002-07-29 | 2005-07-19 | Intel Corporation | Silicon on insulator (SOI) transistor and methods of fabrication |
US6921702B2 (en) | 2002-07-30 | 2005-07-26 | Micron Technology Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
US6777761B2 (en) * | 2002-08-06 | 2004-08-17 | International Business Machines Corporation | Semiconductor chip using both polysilicon and metal gate devices |
US6833556B2 (en) | 2002-08-12 | 2004-12-21 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
US6770516B2 (en) | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
US6794313B1 (en) | 2002-09-20 | 2004-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Oxidation process to improve polysilicon sidewall roughness |
CN1189923C (en) | 2002-09-27 | 2005-02-16 | 上海华虹(集团)有限公司 | Structure of grid medium with high dielectric and its preparation method |
US6800910B2 (en) | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
KR100481209B1 (en) * | 2002-10-01 | 2005-04-08 | 삼성전자주식회사 | MOS Transistor having multiple channels and method of manufacturing the same |
US6833588B2 (en) | 2002-10-22 | 2004-12-21 | Advanced Micro Devices, Inc. | Semiconductor device having a U-shaped gate structure |
US6706581B1 (en) * | 2002-10-29 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
DE10250902B4 (en) * | 2002-10-31 | 2009-06-18 | Advanced Micro Devices, Inc., Sunnyvale | A method of removing structural elements using an improved ablation process in the manufacture of a semiconductor device |
US6611029B1 (en) | 2002-11-08 | 2003-08-26 | Advanced Micro Devices, Inc. | Double gate semiconductor device having separate gates |
US6787439B2 (en) | 2002-11-08 | 2004-09-07 | Advanced Micro Devices, Inc. | Method using planarizing gate material to improve gate critical dimension in semiconductor devices |
US6821834B2 (en) | 2002-12-04 | 2004-11-23 | Yoshiyuki Ando | Ion implantation methods and transistor cell layout for fin type transistors |
US6645797B1 (en) | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
US6794718B2 (en) | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
EP1581968B1 (en) | 2002-12-20 | 2010-05-12 | International Business Machines Corporation | Integrated antifuse structure for finfet and cmos devices |
KR100486609B1 (en) * | 2002-12-30 | 2005-05-03 | 주식회사 하이닉스반도체 | Method for fabricating pMOSFET having Ultra Shallow Super-Steep-Retrograde epi-channel formed by Multiple channel doping |
US6780694B2 (en) | 2003-01-08 | 2004-08-24 | International Business Machines Corporation | MOS transistor |
US6803631B2 (en) * | 2003-01-23 | 2004-10-12 | Advanced Micro Devices, Inc. | Strained channel finfet |
US6762483B1 (en) | 2003-01-23 | 2004-07-13 | Advanced Micro Devices, Inc. | Narrow fin FinFET |
US6885055B2 (en) * | 2003-02-04 | 2005-04-26 | Lee Jong-Ho | Double-gate FinFET device and fabricating method thereof |
WO2004073044A2 (en) | 2003-02-13 | 2004-08-26 | Massachusetts Institute Of Technology | Finfet device and method to make same |
US6746900B1 (en) * | 2003-02-19 | 2004-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a semiconductor device having high-K gate dielectric material |
US6800885B1 (en) | 2003-03-12 | 2004-10-05 | Advance Micro Devices, Inc. | Asymmetrical double gate or all-around gate MOSFET devices and methods for making same |
US6787854B1 (en) | 2003-03-12 | 2004-09-07 | Advanced Micro Devices, Inc. | Method for forming a fin in a finFET device |
US6716690B1 (en) * | 2003-03-12 | 2004-04-06 | Advanced Micro Devices, Inc. | Uniformly doped source/drain junction in a double-gate MOSFET |
JP4563652B2 (en) * | 2003-03-13 | 2010-10-13 | シャープ株式会社 | MEMORY FUNCTIONAL BODY, PARTICLE FORMING METHOD, MEMORY ELEMENT, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE |
US20040191980A1 (en) | 2003-03-27 | 2004-09-30 | Rafael Rios | Multi-corner FET for better immunity from short channel effects |
US6790733B1 (en) | 2003-03-28 | 2004-09-14 | International Business Machines Corporation | Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer |
US6764884B1 (en) | 2003-04-03 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
TWI231994B (en) | 2003-04-04 | 2005-05-01 | Univ Nat Taiwan | Strained Si FinFET |
US7442415B2 (en) | 2003-04-11 | 2008-10-28 | Sharp Laboratories Of America, Inc. | Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films |
TW200506093A (en) | 2003-04-21 | 2005-02-16 | Aviza Tech Inc | System and method for forming multi-component films |
WO2004097943A1 (en) * | 2003-04-28 | 2004-11-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing same |
US7074656B2 (en) | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
JP3976703B2 (en) | 2003-04-30 | 2007-09-19 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
US6909147B2 (en) | 2003-05-05 | 2005-06-21 | International Business Machines Corporation | Multi-height FinFETS |
US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US20040262683A1 (en) | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US6960517B2 (en) | 2003-06-30 | 2005-11-01 | Intel Corporation | N-gate transistor |
US6921982B2 (en) | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
EP1519420A2 (en) * | 2003-09-25 | 2005-03-30 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | Multiple gate semiconductor device and method for forming same |
US6835618B1 (en) | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
US6787406B1 (en) | 2003-08-12 | 2004-09-07 | Advanced Micro Devices, Inc. | Systems and methods for forming dense n-channel and p-channel fins using shadow implanting |
KR100496891B1 (en) | 2003-08-14 | 2005-06-23 | 삼성전자주식회사 | Silicon fin for finfet and method for fabricating the same |
US6970373B2 (en) | 2003-10-02 | 2005-11-29 | Intel Corporation | Method and apparatus for improving stability of a 6T CMOS SRAM cell |
EP1683193A1 (en) * | 2003-10-22 | 2006-07-26 | Spinnaker Semiconductor, Inc. | Dynamic schottky barrier mosfet device and method of manufacture |
US7060576B2 (en) * | 2003-10-24 | 2006-06-13 | Intel Corporation | Epitaxially deposited source/drain |
US7138320B2 (en) | 2003-10-31 | 2006-11-21 | Advanced Micro Devices, Inc. | Advanced technique for forming a transistor having raised drain and source regions |
US6831310B1 (en) | 2003-11-10 | 2004-12-14 | Freescale Semiconductor, Inc. | Integrated circuit having multiple memory types and method of formation |
US6885072B1 (en) | 2003-11-18 | 2005-04-26 | Applied Intellectual Properties Co., Ltd. | Nonvolatile memory with undercut trapping structure |
US7075150B2 (en) | 2003-12-02 | 2006-07-11 | International Business Machines Corporation | Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique |
US7018551B2 (en) * | 2003-12-09 | 2006-03-28 | International Business Machines Corporation | Pull-back method of forming fins in FinFets |
US7388258B2 (en) * | 2003-12-10 | 2008-06-17 | International Business Machines Corporation | Sectional field effect devices |
US7247578B2 (en) | 2003-12-30 | 2007-07-24 | Intel Corporation | Method of varying etch selectivities of a film |
US7705345B2 (en) | 2004-01-07 | 2010-04-27 | International Business Machines Corporation | High performance strained silicon FinFETs device and method for forming same |
US7056794B2 (en) * | 2004-01-09 | 2006-06-06 | International Business Machines Corporation | FET gate structure with metal gate electrode and silicide contact |
US7385247B2 (en) | 2004-01-17 | 2008-06-10 | Samsung Electronics Co., Ltd. | At least penta-sided-channel type of FinFET transistor |
JP2005209782A (en) | 2004-01-21 | 2005-08-04 | Toshiba Corp | Semiconductor device |
US7250645B1 (en) | 2004-01-22 | 2007-07-31 | Advanced Micro Devices, Inc. | Reversed T-shaped FinFET |
EP1566844A3 (en) | 2004-02-20 | 2006-04-05 | Samsung Electronics Co., Ltd. | Multi-gate transistor and method for manufacturing the same |
US7060539B2 (en) | 2004-03-01 | 2006-06-13 | International Business Machines Corporation | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby |
US6921691B1 (en) | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
US7141480B2 (en) | 2004-03-26 | 2006-11-28 | Texas Instruments Incorporated | Tri-gate low power device and method for manufacturing the same |
US8450806B2 (en) | 2004-03-31 | 2013-05-28 | International Business Machines Corporation | Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US20050224797A1 (en) | 2004-04-01 | 2005-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS fabricated on different crystallographic orientation substrates |
US20050230763A1 (en) | 2004-04-15 | 2005-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a microelectronic device with electrode perturbing sill |
KR100634372B1 (en) | 2004-06-04 | 2006-10-16 | 삼성전자주식회사 | Semiconductor devices and methods for forming the same |
US7132360B2 (en) | 2004-06-10 | 2006-11-07 | Freescale Semiconductor, Inc. | Method for treating a semiconductor surface to form a metal-containing layer |
US7291886B2 (en) | 2004-06-21 | 2007-11-06 | International Business Machines Corporation | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs |
US7084025B2 (en) * | 2004-07-07 | 2006-08-01 | Chartered Semiconductor Manufacturing Ltd | Selective oxide trimming to improve metal T-gate transistor |
DE102004042169B4 (en) * | 2004-08-31 | 2009-08-20 | Advanced Micro Devices, Inc., Sunnyvale | Technique for increasing the filling capacity in an electrochemical deposition process by rounding the edges and trenches |
US7250367B2 (en) | 2004-09-01 | 2007-07-31 | Micron Technology, Inc. | Deposition methods using heteroleptic precursors |
US7071064B2 (en) | 2004-09-23 | 2006-07-04 | Intel Corporation | U-gate transistors and methods of fabrication |
US20060289931A1 (en) * | 2004-09-26 | 2006-12-28 | Samsung Electronics Co., Ltd. | Recessed gate structures including blocking members, methods of forming the same, semiconductor devices having the recessed gate structures and methods of forming the semiconductor devices |
US20060086977A1 (en) * | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7875547B2 (en) | 2005-01-12 | 2011-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact hole structures and contact structures and fabrication methods thereof |
US7071047B1 (en) * | 2005-01-28 | 2006-07-04 | International Business Machines Corporation | Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions |
US7238564B2 (en) | 2005-03-10 | 2007-07-03 | Taiwan Semiconductor Manufacturing Company | Method of forming a shallow trench isolation structure |
US7858481B2 (en) * | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US8513066B2 (en) * | 2005-10-25 | 2013-08-20 | Freescale Semiconductor, Inc. | Method of making an inverted-T channel transistor |
JP2007180310A (en) * | 2005-12-28 | 2007-07-12 | Toshiba Corp | Semiconductor device |
-
2004
- 2004-09-29 US US10/955,669 patent/US7332439B2/en active Active
-
2005
- 2005-09-29 CN CN201310419494.2A patent/CN103560150B/en not_active Expired - Fee Related
- 2005-09-29 DE DE112005002302T patent/DE112005002302B4/en active Active
- 2005-09-29 TW TW094133997A patent/TWI272681B/en not_active IP Right Cessation
- 2005-09-29 WO PCT/US2005/035377 patent/WO2006039597A2/en active Application Filing
- 2005-09-29 CN CNA2005800324531A patent/CN101027763A/en active Pending
- 2005-09-29 KR KR1020077007071A patent/KR100867781B1/en active IP Right Grant
- 2005-09-29 US US11/240,440 patent/US7915167B2/en not_active Expired - Fee Related
-
2008
- 2008-01-24 US US12/011,439 patent/US8344452B2/en not_active Expired - Fee Related
-
2011
- 2011-03-08 US US13/042,973 patent/US20110156145A1/en not_active Abandoned
-
2016
- 2016-06-29 US US15/197,563 patent/US20160308014A1/en not_active Abandoned
Patent Citations (100)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4907048A (en) * | 1987-11-23 | 1990-03-06 | Xerox Corporation | Double implanted LDD transistor self-aligned with gate |
US4905063A (en) * | 1988-06-21 | 1990-02-27 | American Telephone And Telegraph Company, At&T Bell Laboratories | Floating gate memories |
US4996574A (en) * | 1988-07-01 | 1991-02-26 | Fujitsu Limited | MIS transistor structure for increasing conductance between source and drain regions |
US4994873A (en) * | 1988-10-17 | 1991-02-19 | Motorola, Inc. | Local interconnect for stacked polysilicon device |
US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
US5278102A (en) * | 1990-08-18 | 1994-01-11 | Fujitsu Limited | SOI device and a fabrication process thereof |
US5880015A (en) * | 1991-04-30 | 1999-03-09 | Sgs-Thomson Microelectronics, Inc. | Method of producing stepped wall interconnects and gates |
US5179037A (en) * | 1991-12-24 | 1993-01-12 | Texas Instruments Incorporated | Integration of lateral and vertical quantum well transistors in the same epitaxial stack |
US5391506A (en) * | 1992-01-31 | 1995-02-21 | Kawasaki Steel Corporation | Manufacturing method for semiconductor devices with source/drain formed in substrate projection. |
US5482877A (en) * | 1993-02-17 | 1996-01-09 | Samsung Electronics Co., Ltd. | Method for making a semiconductor device having a silicon-on-insulator structure |
US5495115A (en) * | 1993-08-06 | 1996-02-27 | Hitachi, Ltd. | Semiconductor crystalline laminate structure, forming method of the same, and semiconductor device employing the same |
US5883564A (en) * | 1994-04-18 | 1999-03-16 | General Motors Corporation | Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer |
US5595941A (en) * | 1994-06-01 | 1997-01-21 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fine patterns |
US5859456A (en) * | 1994-11-02 | 1999-01-12 | Texas Instruments Incorporated | Multiple transistor integrated circuit with thick copper interconnect |
US5716879A (en) * | 1994-12-15 | 1998-02-10 | Goldstar Electron Company, Ltd. | Method of making a thin film transistor |
US6018176A (en) * | 1995-05-26 | 2000-01-25 | Samsung Electronics Co., Ltd. | Vertical transistor and memory cell |
US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
US6693324B2 (en) * | 1996-04-26 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a thin film transistor and manufacturing method thereof |
US20030042542A1 (en) * | 1996-04-26 | 2003-03-06 | Shigeto Maegawa | Semiconductor device having a thin film transistor and manufacturing method thereof |
US5889304A (en) * | 1996-06-28 | 1999-03-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US6031249A (en) * | 1996-07-11 | 2000-02-29 | Semiconductor Energy Laboratory Co., Ltd. | CMOS semiconductor device having boron doped channel |
US6190975B1 (en) * | 1996-09-17 | 2001-02-20 | Matsushita Electric Industrial Co., Ltd. | Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layer |
US6013926A (en) * | 1996-11-20 | 2000-01-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with refractory metal element |
US5856225A (en) * | 1997-11-24 | 1999-01-05 | Chartered Semiconductor Manufacturing Ltd | Creation of a self-aligned, ion implanted channel region, after source and drain formation |
US5888309A (en) * | 1997-12-29 | 1999-03-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma |
US6335251B2 (en) * | 1998-05-29 | 2002-01-01 | Kabushiki Kaisha Toshiba | Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor |
US6696366B1 (en) * | 1998-08-17 | 2004-02-24 | Lam Research Corporation | Technique for etching a low capacitance dielectric layer |
US6200865B1 (en) * | 1998-12-04 | 2001-03-13 | Advanced Micro Devices, Inc. | Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate |
US6362111B1 (en) * | 1998-12-09 | 2002-03-26 | Texas Instruments Incorporated | Tunable gate linewidth reduction process |
US6174820B1 (en) * | 1999-02-16 | 2001-01-16 | Sandia Corporation | Use of silicon oxynitride as a sacrificial material for microelectromechanical devices |
US20040038533A1 (en) * | 1999-04-09 | 2004-02-26 | Chunlin Liang | Isolated junction structure and method of manufacture |
US20030057477A1 (en) * | 1999-06-18 | 2003-03-27 | Hergenrother John Michael | CMOS integrated circuit having vertical transistors and a process for fabricating same |
US20040029345A1 (en) * | 2000-06-09 | 2004-02-12 | Simon Deleonibus | Damascene architecture electronics storage and method for making same |
US6526996B1 (en) * | 2000-06-12 | 2003-03-04 | Promos Technologies, Inc. | Dry clean method instead of traditional wet clean after metal etch |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US6358800B1 (en) * | 2000-09-18 | 2002-03-19 | Vanguard International Semiconductor Corporation | Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit |
US20020037619A1 (en) * | 2000-09-22 | 2002-03-28 | Kohei Sugihara | Semiconductor device and method of producing the same |
US20020036290A1 (en) * | 2000-09-28 | 2002-03-28 | Kabushiki Kaisha Toshiba | Semiconductor device having MIS field effect transistors or three-dimensional structure |
US6525403B2 (en) * | 2000-09-28 | 2003-02-25 | Kabushiki Kaisha Toshiba | Semiconductor device having MIS field effect transistors or three-dimensional structure |
US6537901B2 (en) * | 2000-12-29 | 2003-03-25 | Hynix Semiconductor Inc. | Method of manufacturing a transistor in a semiconductor device |
US6359311B1 (en) * | 2001-01-17 | 2002-03-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same |
US20040033639A1 (en) * | 2001-05-07 | 2004-02-19 | Applied Materials, Inc. | Integrated method for release and passivation of MEMS structures |
US6537862B2 (en) * | 2001-05-23 | 2003-03-25 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device having a GAA type transistor |
US6506692B2 (en) * | 2001-05-30 | 2003-01-14 | Intel Corporation | Method of making a semiconductor device using a silicon carbide hard mask |
US6534807B2 (en) * | 2001-08-13 | 2003-03-18 | International Business Machines Corporation | Local interconnect junction on insulator (JOI) structure |
US20030036290A1 (en) * | 2001-08-17 | 2003-02-20 | United Microelectronics Corp. | Method for improving the coating capability of low-k dielectric layer |
US20030057486A1 (en) * | 2001-09-27 | 2003-03-27 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US6689650B2 (en) * | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US6849884B2 (en) * | 2002-03-19 | 2005-02-01 | International Business Machines Corporation | Strained Fin FETs structure and method |
US20040016968A1 (en) * | 2002-04-08 | 2004-01-29 | Stmicroelectronics S.A. | Surround-gate semiconductor device encapsulated in an insulating medium |
US6713396B2 (en) * | 2002-04-29 | 2004-03-30 | Hewlett-Packard Development Company, L.P. | Method of fabricating high density sub-lithographic features on a substrate |
US6537885B1 (en) * | 2002-05-09 | 2003-03-25 | Infineon Technologies Ag | Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer |
US20040031979A1 (en) * | 2002-06-07 | 2004-02-19 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US6680240B1 (en) * | 2002-06-25 | 2004-01-20 | Advanced Micro Devices, Inc. | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
US20050020020A1 (en) * | 2002-07-16 | 2005-01-27 | Nadine Collaert | Integrated semiconductor fin device and a method for manufacturing such device |
US6705571B2 (en) * | 2002-07-22 | 2004-03-16 | Northrop Grumman Corporation | System and method for loading stores on an aircraft |
US6998318B2 (en) * | 2002-07-26 | 2006-02-14 | Dongbuanam Semiconductor Inc. | Method for forming short-channel transistors |
US7163898B2 (en) * | 2002-07-31 | 2007-01-16 | Stmicroelectronics S.R.L. | Method for manufacturing semiconductor integrated circuit structures |
US20040038436A1 (en) * | 2002-08-09 | 2004-02-26 | Hitachi, Ltd. | Method of manufacturing a semiconductor integrated circuit device |
US20040029393A1 (en) * | 2002-08-12 | 2004-02-12 | Applied Materials, Inc. | Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer |
US20040036127A1 (en) * | 2002-08-23 | 2004-02-26 | Chau Robert S. | Tri-gate devices and methods of fabrication |
US20040036126A1 (en) * | 2002-08-23 | 2004-02-26 | Chau Robert S. | Tri-gate devices and methods of fabrication |
US6858478B2 (en) * | 2002-08-23 | 2005-02-22 | Intel Corporation | Tri-gate devices and methods of fabrication |
US7163851B2 (en) * | 2002-08-26 | 2007-01-16 | International Business Machines Corporation | Concurrent Fin-FET and thick-body device fabrication |
US20040036118A1 (en) * | 2002-08-26 | 2004-02-26 | International Business Machines Corporation | Concurrent Fin-FET and thick-body device fabrication |
US7273785B2 (en) * | 2002-09-05 | 2007-09-25 | International Business Machines Corporation | Method to control device threshold of SOI MOSFET's |
US6849556B2 (en) * | 2002-09-27 | 2005-02-01 | Oki Electric Industry Co., Ltd. | Etching method, gate etching method, and method of manufacturing semiconductor devices |
US6706571B1 (en) * | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
US6709982B1 (en) * | 2002-11-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Double spacer FinFET formation |
US6855990B2 (en) * | 2002-11-26 | 2005-02-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained-channel multiple-gate transistor |
US6852559B2 (en) * | 2002-12-06 | 2005-02-08 | Hynix Semiconductor Inc. | Transistor of semiconductor device, and method for manufacturing the same |
US6686231B1 (en) * | 2002-12-06 | 2004-02-03 | Advanced Micro Devices, Inc. | Damascene gate process with sacrificial oxide in semiconductor devices |
US6869868B2 (en) * | 2002-12-13 | 2005-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a MOSFET device with metal containing gate structures |
US6855606B2 (en) * | 2003-02-20 | 2005-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-rod devices |
US6844238B2 (en) * | 2003-03-26 | 2005-01-18 | Taiwan Semiconductor Manufacturing Co., Ltd | Multiple-gate transistors with improved gate control |
US20050040429A1 (en) * | 2003-04-17 | 2005-02-24 | Uppal Parvez N. | Gaas substrate with sb buffering for high in devices |
US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US6838322B2 (en) * | 2003-05-01 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a double-gated semiconductor device |
US7323710B2 (en) * | 2003-07-23 | 2008-01-29 | Samsung Electronics Co., Ltd. | Fin field effect transistors having multi-layer fin patterns |
US20050019993A1 (en) * | 2003-07-24 | 2005-01-27 | Deok-Hyung Lee | Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage |
US20050023633A1 (en) * | 2003-08-01 | 2005-02-03 | Yee-Chia Yeo | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US7172943B2 (en) * | 2003-08-13 | 2007-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-gate transistors formed on bulk substrates |
US20050035415A1 (en) * | 2003-08-13 | 2005-02-17 | Yee-Chia Yeo | Multiple-gate transistors formed on bulk substrates |
US20050040444A1 (en) * | 2003-08-22 | 2005-02-24 | International Business Machines Corporation | Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates |
US6998301B1 (en) * | 2003-09-03 | 2006-02-14 | Advanced Micro Devices, Inc. | Method for forming a tri-gate MOSFET |
US20050059214A1 (en) * | 2003-09-16 | 2005-03-17 | International Business Machines Corporation | Method and structure of vertical strained silicon devices |
US20050062082A1 (en) * | 2003-09-22 | 2005-03-24 | Ernst Bucher | Field-effect transistors with weakly coupled layered inorganic semiconductors |
US6867460B1 (en) * | 2003-11-05 | 2005-03-15 | International Business Machines Corporation | FinFET SRAM cell with chevron FinFET logic |
US7183137B2 (en) * | 2003-12-01 | 2007-02-27 | Taiwan Semiconductor Manufacturing Company | Method for dicing semiconductor wafers |
US7329913B2 (en) * | 2003-12-30 | 2008-02-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US6864540B1 (en) * | 2004-05-21 | 2005-03-08 | International Business Machines Corp. | High performance FET with elevated source/drain region |
US20060014338A1 (en) * | 2004-06-30 | 2006-01-19 | International Business Machines Corporation | Method and structure for strained finfet devices |
US20060040054A1 (en) * | 2004-08-18 | 2006-02-23 | Pearlstein Ronald M | Passivating ALD reactor chamber internal surfaces to prevent residue buildup |
US20070001219A1 (en) * | 2005-06-30 | 2007-01-04 | Marko Radosavljevic | Block contact architectures for nanoscale channel transistors |
US20070023795A1 (en) * | 2005-07-15 | 2007-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US20070029624A1 (en) * | 2005-08-03 | 2007-02-08 | International Business Machines Corporation | Fin-type field effect transistor |
US7479421B2 (en) * | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20080017934A1 (en) * | 2006-05-18 | 2008-01-24 | Samsung Electronic Co., Ltd. | Wire-type semiconductor devices and methods of fabricating the same |
US20080017890A1 (en) * | 2006-06-30 | 2008-01-24 | Sandisk 3D Llc | Highly dense monolithic three dimensional memory array and method for forming |
US7655989B2 (en) * | 2006-11-30 | 2010-02-02 | International Business Machines Corporation | Triple gate and double gate finFETs with different vertical dimension fins |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11538940B2 (en) * | 2015-03-27 | 2022-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
US10714598B2 (en) * | 2017-06-30 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor device |
US11043580B2 (en) | 2017-06-30 | 2021-06-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor devices |
US11677012B2 (en) | 2017-06-30 | 2023-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor devices |
DE102017126544B4 (en) | 2017-06-30 | 2023-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | PROCESSES FOR MANUFACTURING SEMICONDUCTOR DEVICES |
CN110767804A (en) * | 2019-11-19 | 2020-02-07 | 北京元芯碳基集成电路研究院 | Carbon nanotube device and manufacturing method thereof |
CN110767804B (en) * | 2019-11-19 | 2020-11-06 | 北京元芯碳基集成电路研究院 | Carbon nanotube device and manufacturing method thereof |
WO2021098546A1 (en) * | 2019-11-19 | 2021-05-27 | 北京元芯碳基集成电路研究院 | Carbon nanotube device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
DE112005002302B4 (en) | 2009-07-23 |
KR100867781B1 (en) | 2008-11-10 |
US20060068591A1 (en) | 2006-03-30 |
WO2006039597A2 (en) | 2006-04-13 |
CN103560150B (en) | 2017-01-11 |
TW200618125A (en) | 2006-06-01 |
TWI272681B (en) | 2007-02-01 |
US20080142840A1 (en) | 2008-06-19 |
US7915167B2 (en) | 2011-03-29 |
KR20070052329A (en) | 2007-05-21 |
US20060068590A1 (en) | 2006-03-30 |
CN103560150A (en) | 2014-02-05 |
CN101027763A (en) | 2007-08-29 |
WO2006039597A3 (en) | 2006-07-13 |
US20160308014A1 (en) | 2016-10-20 |
US8344452B2 (en) | 2013-01-01 |
US7332439B2 (en) | 2008-02-19 |
DE112005002302T5 (en) | 2007-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7915167B2 (en) | Fabrication of channel wraparound gate structure for field-effect transistor | |
USRE45944E1 (en) | Structure for a multiple-gate FET device and a method for its fabrication | |
US7915682B2 (en) | Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures | |
TWI570915B (en) | Semiconductor device and method for fabricating fin fet device | |
US9041009B2 (en) | Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device | |
US9040369B2 (en) | Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric | |
JP4069063B2 (en) | Method for forming a semiconductor transistor device | |
US7176522B2 (en) | Semiconductor device having high drive current and method of manufacturing thereof | |
US7321155B2 (en) | Offset spacer formation for strained channel CMOS transistor | |
US7618853B2 (en) | Field effect transistors with dielectric source drain halo regions and reduced miller capacitance | |
US10134864B2 (en) | Nanowire semiconductor device including lateral-etch barrier region | |
US20070063277A1 (en) | Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current | |
US20130260519A1 (en) | Strained structure of semiconductor device | |
US20210233997A1 (en) | Semiconductor Device and Method | |
US11901235B2 (en) | Ion implantation for nano-FET | |
US11348921B2 (en) | Semiconductor structure and method of manufacturing the same | |
JP2007519217A (en) | Semiconductor device and manufacturing method thereof | |
US20230131688A1 (en) | Nanosheet channel formation method and structure | |
KR102584048B1 (en) | Semiconductor device structure with uneven gate profile | |
US20230369428A1 (en) | Under epitaxy isolation structure | |
TW202410163A (en) | Nanostructure field-effect transistor and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION |
|
AS | Assignment |
Owner name: TAHOE RESEARCH, LTD., IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:061827/0686 Effective date: 20220718 |