US20110187487A1 - Inductor formed on a semiconductor substrate - Google Patents
Inductor formed on a semiconductor substrate Download PDFInfo
- Publication number
- US20110187487A1 US20110187487A1 US13/086,500 US201113086500A US2011187487A1 US 20110187487 A1 US20110187487 A1 US 20110187487A1 US 201113086500 A US201113086500 A US 201113086500A US 2011187487 A1 US2011187487 A1 US 2011187487A1
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- US
- United States
- Prior art keywords
- inductor
- slots
- insulator
- single metal
- coil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
Abstract
An inductor formed on a semiconductor substrate, comprising a coil formed with at least a single metal layer having a plurality of slots and an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the insulator layer does not cover the top surface of the single metal layer.
Description
- This application is a divisional of an application Ser. No. 11/468,789, filed on Aug. 31, 2006, now allowed for issuance as a patent. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of Invention
- The present invention relates to an inductor fabricated on a semiconductor substrate. More particularly, the present invention relates to an inductor formed with insulator slots inside.
- 2. Description of Related Art
- Inductor is widely used for radio frequency (RF) application. The application covers a very broad spectrum. Some applications, such as personal handy-phone system (PHS), require an inductor to work with frequencies below 1 GHz. Accordingly, the maximum quality factor (abbreviated as Q hereinafter) of the inductor has to move into the sub-GHz range.
- For an inductor to have acceptable inductance and maximum quality factor below 1 GHz, a conventional solution is stacking metal layers in parallel. However, this solution increases sidewall capacitance coupling and consequently degrades the broadband performance of the quality factor. Another solution is widening the coil of the inductor, but an over-wide coil tends to violate chemical-mechanical polishing (CMP) rules. In addition, although widening the coil lowers the resistance and improves the maximum quality factor, it also significantly accentuates the variation in the fabrication process.
- The maximum quality factor of an inductor should be as high as possible. Therefore it is desirable to have an inductor which works properly with a frequency less than 1 GHz and is without the drawbacks of conventional solutions.
- The present invention is to provide an inductor formed on a semiconductor substrate. The inductor provided by the present invention can be widened without violating CMP rules. In addition, the inductor provided by the present invention features acceptable inductance and maximum quality factor comparable to that of conventional inductors under a lower operation frequency (for example, a sub-GHz frequency). This inductor also alleviates the variation in the fabrication process.
- For the purposes mentioned above, an inductor formed on a semiconductor substrate is provided in an embodiment of the present invention. The inductor comprises a single metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.
- In this embodiment, the insulator slot may be formed using silicon oxide. The insulator layer may comprise a row of insulator slots arranged along the coil of the inductor.
- For the purposes mentioned above, an inductor formed on a semiconductor substrate is provided in another embodiment of the present invention. The inductor comprises a plurality of metal layers and an insulator layer. The metal layers constitute the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers.
- In this embodiment, the insulator slot may be formed using silicon oxide. The insulator layer may comprise a row of insulator slots arranged along the coil of the inductor.
- In this embodiment, each insulator slot may be encompassed in the same one of the metal layers. Alternatively, the insulator layer may comprise a plurality of insulator slots, and the insulator slots may be distributed in each one of the metal layers.
- In this embodiment, the metal layers may be connected in parallel to constitute the coil of the inductor. Alternatively, the metal layers may be connected in series to constitute the coil of the inductor.
- For the purposes mentioned above, an inductor formed on a semiconductor substrate is provided in another embodiment of the present invention. The inductor comprises a coil formed with at least a single metal layer having a plurality of slots and an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the insulator layer does not cover the top surface of the single metal layer.
- For the purposes mentioned above, an inductor formed on a semiconductor substrate is provided in another embodiment of the present invention. The inductor comprises a coil formed with at least a single metal layer having a plurality of slots and an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the insulator layer does not cover the top and the bottom surface of the single metal layer.
- For the purposes mentioned above, an inductor formed on a semiconductor substrate is provided in another embodiment of the present invention. The inductor comprises a coil formed with at least one single metal layer having a plurality of slots and an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the top surface of the insulator layer and the single metal layer is substantially coplanar.
- In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIG. 1 is a schematic diagram showing a conventional inductor formed on a semiconductor substrate. -
FIGS. 2A and 2B are schematic diagrams showing an inductor according to an embodiment of the present invention. -
FIGS. 3A and 3B are schematic diagrams showing an inductor according to an embodiment of the present invention. -
FIGS. 4A and 4B are schematic diagrams showing an inductor according to an embodiment of the present invention. -
FIGS. 5A and 5B are schematic diagrams showing an inductor according to an embodiment of the present invention. -
FIG. 6 ,FIG. 7 andFIG. 8 are schematic diagrams showing inductors according to various embodiments of the present invention. -
FIG. 9 is a plot of inductance versus frequency of a conventional inductor and an inductor according to an embodiment of the present invention. -
FIG. 10 is a plot of quality factor versus frequency of a conventional inductor and an inductor according to an embodiment of the present invention. - Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1 illustrates aconventional inductor 100 fabricated on a semiconductor substrate (not shown).Inductor 100 is formed purely with metal, without any insulator material. In contrast,FIG. 2A illustrates aninductor 200 according to an embodiment of the present invention.Inductor 200 is a metallic inductor with insulator slots embedded inside, which is also formed on a semiconductor substrate (not shown).Inductor 200 comprises a single metal layer and an insulator layer. The metal layer constitutes the coil of theinductor 200. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.FIG. 2B is an enlarged view of the lower left corner ofinductor 200. There is a row of insulator slots arranged along the entire length of the coil ofinductor 200. For example, each ofinsulator slots insulator slot 201 is a slim rectangular in shape, whileinsulator slot 202 is L-shaped. The insulator slots may be formed using silicon oxide (for example, SiO2). - In the scope of the present invention, the insulator slots are not limited to a single-row arrangement. Insulator slots may be arranged into multiple rows. The insulator slots of different rows may be placed in parallel with one another or be placed in an alternate fashion. There is no limitation to the relative positions of the insulator slots. There is also no limitation to the number of rows. For example,
FIG. 3A illustrates aninductor 300 according to another embodiment of the present invention. There are two rows along the coil ofinductor 300.FIG. 3B is en enlarged view of the lower left corner ofinductor 300. As can be seen, one of the rows includes theexemplary insulator slots 301 and the other row includes theexemplary insulator slots 302. Similarly,FIGS. 4A and 4B illustrate aninductor 400 with three rows of insulator slots according to another embodiment of the present invention.FIGS. 5A and 5B illustrate aninductor 500 with four rows of insulator slots according to yet another embodiment of the present invention. - The arrangement of insulator slots is quite flexible in the scope of the present invention. Each insulator slot may be formed in arbitrary size and shape. The number and arrangement of insulator slots are also arbitrary. For example, insulator slots may be distributed either evenly or unevenly in the coil the inductor. In other words, insulator slots may be distributed either symmetrically or asymmetrically in the coil the inductor.
FIG. 6 is an example of uneven distribution. Insulator slots are embedded only insections inductor 600. However, it is preferred that insulator slots have an even and symmetrical distribution in the inductor coil. Furthermore, there is no limit regarding the position of an insulator slot relative to the boundary surface of the inductor. An insulator slot may be at arbitrary distance from any boundary surface of the containing metal layer. An insulator slot may be completely embedded in the metal layer, in other words, surrounded in every direction by the metal layer. Alternatively, an insulator slot may be partially embedded in the metal layer. In such a case, an insulator slot may emerge from one or more boundary surfaces of the metal layer. - In the above embodiments, each inductor comprises a single metal layer. The present invention also provides inductors comprising multiple metal layers. The metal layers constitute the coil of such an inductor.
FIG. 7 illustrates aninductor 700 according to an embodiment of the present invention. As shown inFIG. 7 ,inductor 700 may comprise three, four or five metal layers. The metal layers (for example, 701) are stacked in parallel and are connected by vias (for example, 702). In contrast,FIG. 8 illustrates anotherinductor 800 according to another embodiment of the present invention. Three metal layers 801-803 are connected in series byvias inductor 800. - For simplicity, insulator slots are not shown in
FIG. 7 andFIG. 8 . In fact, each ofinductors - As discussed above, there is no limitation regarding the sizes, shapes, positions, number, arrangement, distribution and other characteristics of the insulator slots. The only restriction is that the inductor has to comply with CMP rules and the maximum quality factor of the inductor has to be in the desired low frequency range (for example, below 1 GHz).
-
FIG. 9 andFIG. 10 illustrate the effect of an embodiment of the present invention.FIG. 9 is a plot of inductance versus frequency ofinductor 100 inFIG. 1 andinductor 600 inFIG. 6 .Curve 901 inFIG. 9 is the plot ofinductor 100, whilecurve 902 is the plot ofinductor 600.FIG. 10 is a plot of quality factor versus frequency ofinductor 100 andinductor 600.Curve 1001 inFIG. 10 is the plot ofinductor 100, whilecurve 1002 is the plot ofinductor 600.Inductor 100 is formed using metal only, with a coil width of 10 micrometers and an inner diameter of approximately 200 micrometers.Inductor 600 is formed using metal and insulator slots, with a coil width of 20 micrometers and an inner diameter of approximately 200 micrometers. As shown inFIG. 10 , this embodiment of the present invention moves the maximum quality factor from the conventional operation frequency of 2.488 GHz to the desired lower frequency of 0.981 GHz. Furthermore, the maximum quality factor ofinductor 600 does not decay too much from that ofinductor 100. - In addition to inductor structures as discussed in the embodiments above, the present invention also provides a method for forming an inductor on a semiconductor substrate. In fact, the method is for forming inductors in the embodiments above. The major steps of the method are forming one or more metal layer on the semiconductor substrate, and then forming an insulator layer on the semiconductor substrate. The metal layers constitute the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in one the metal layers. The technical details of the method are the same as those of the inductor structures discussed in the previous embodiments so they are not repeated here.
- Thanks to the insulator slots, the coil of the inductor provided by the present invention can be widened without violating CMP rules. In addition, the inductor provided by the present invention features acceptable inductance and maximum quality factor comparable to that of conventional inductors under a lower operation frequency (for example, a sub-GHz frequency).
- The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.
Claims (20)
1. An inductor formed on a semiconductor substrate, comprising:
a coil formed with at least a single metal layer having a plurality of slots; and
an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the insulator layer does not cover the top surface of the single metal layer.
2. The inductor of claim 1 , wherein the insulator layer is formed using silicon oxide.
3. The inductor of claim 1 , wherein the slots are arranged in at least a row.
4. The inductor of claim 1 , wherein the slots insulator slots have an even and symmetrical distribution in the inductor coil.
5. The inductor of claim 1 , wherein the coil comprises a plurality of the single metal layers stacked and connected in parallel.
6. The inductor of claim 1 , wherein the coil comprises a plurality of the single metal layers connected in series.
7. The inductor of claim 1 , wherein one of the slots shapes as a slim rectangular or is in L-shaped.
8. An inductor formed on a semiconductor substrate, comprising:
a coil formed with at least a single metal layer having a plurality of slots; and
an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the insulator layer does not cover the top and the bottom surface of the single metal layer.
9. The inductor of claim 8 , wherein the insulator layer is formed using silicon oxide.
10. The inductor of claim 8 , wherein the slots are arranged in at least a row.
11. The inductor of claim 8 , wherein the slots insulator slots have an even and symmetrical distribution in the inductor coil.
12. The inductor of claim 8 , wherein the coil comprises a plurality of the single metal layers stacked and connected in parallel.
13. The inductor of claim 8 , wherein the coil comprises a plurality of the single metal layers connected in series.
14. An inductor formed on a semiconductor substrate, comprising:
a coil formed with at least one single metal layer having a plurality of slots; and
an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the top surface of the insulator layer and the single metal layer is substantially coplanar.
15. The inductor of claim 14 , wherein the insulator layer is formed using silicon oxide.
16. The inductor of claim 14 , wherein the slots are arranged in at least a row.
17. The inductor of claim 14 , wherein the slots insulator slots have an even and symmetrical distribution in the inductor coil.
18. The inductor of claim 14 , wherein the coil comprises a plurality of the single metal layers stacked and connected in parallel.
19. The inductor of claim 14 , wherein the coil comprises a plurality of the single metal layers connected in series.
20. The inductor of claim 14 , wherein one of the slots shapes as a slim rectangular or is in L-shaped.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/086,500 US20110187487A1 (en) | 2006-08-31 | 2011-04-14 | Inductor formed on a semiconductor substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/468,789 US7948055B2 (en) | 2006-08-31 | 2006-08-31 | Inductor formed on semiconductor substrate |
US13/086,500 US20110187487A1 (en) | 2006-08-31 | 2011-04-14 | Inductor formed on a semiconductor substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/468,789 Continuation US7948055B2 (en) | 2006-08-31 | 2006-08-31 | Inductor formed on semiconductor substrate |
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US20110187487A1 true US20110187487A1 (en) | 2011-08-04 |
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US11/468,789 Active 2027-03-26 US7948055B2 (en) | 2006-08-31 | 2006-08-31 | Inductor formed on semiconductor substrate |
US12/191,307 Abandoned US20080299738A1 (en) | 2006-08-31 | 2008-08-14 | Method for forming inductor on semiconductor substrate |
US13/086,500 Abandoned US20110187487A1 (en) | 2006-08-31 | 2011-04-14 | Inductor formed on a semiconductor substrate |
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US11/468,789 Active 2027-03-26 US7948055B2 (en) | 2006-08-31 | 2006-08-31 | Inductor formed on semiconductor substrate |
US12/191,307 Abandoned US20080299738A1 (en) | 2006-08-31 | 2008-08-14 | Method for forming inductor on semiconductor substrate |
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US9449749B2 (en) | 2013-05-28 | 2016-09-20 | Tdk Corporation | Signal handling apparatus for radio frequency circuits |
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US8860544B2 (en) * | 2007-06-26 | 2014-10-14 | Mediatek Inc. | Integrated inductor |
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-
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9324490B2 (en) | 2013-05-28 | 2016-04-26 | Tdk Corporation | Apparatus and methods for vector inductors |
US9449749B2 (en) | 2013-05-28 | 2016-09-20 | Tdk Corporation | Signal handling apparatus for radio frequency circuits |
US9570222B2 (en) | 2013-05-28 | 2017-02-14 | Tdk Corporation | Vector inductor having multiple mutually coupled metalization layers providing high quality factor |
US9735752B2 (en) * | 2014-12-03 | 2017-08-15 | Tdk Corporation | Apparatus and methods for tunable filters |
Also Published As
Publication number | Publication date |
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US7948055B2 (en) | 2011-05-24 |
US20080299738A1 (en) | 2008-12-04 |
US20080122028A1 (en) | 2008-05-29 |
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AS | Assignment |
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, TSUN-LAI;OU, JUN-HONG;CHEN, JUI-FANG;AND OTHERS;REEL/FRAME:026124/0700 Effective date: 20060822 |
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STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |