US20120039123A1 - Multiple level programming in a non-volatile memory device - Google Patents

Multiple level programming in a non-volatile memory device Download PDF

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US20120039123A1
US20120039123A1 US13/279,717 US201113279717A US2012039123A1 US 20120039123 A1 US20120039123 A1 US 20120039123A1 US 201113279717 A US201113279717 A US 201113279717A US 2012039123 A1 US2012039123 A1 US 2012039123A1
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memory
memory cells
programming
threshold voltage
program
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Hagop A. Nazarian
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Round Rock Research LLC
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Round Rock Research LLC
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Definitions

  • the present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices.
  • RAM random-access memory
  • ROM read only memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • flash memory flash memory
  • Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
  • BIOS basic input/output system
  • MLC multi-level cell
  • FIG. 1 shows a simplified diagram of one embodiment for a NAND flash memory array of the present invention.
  • FIG. 2 shows a diagram of one embodiment of a method of the present invention for multiple level, first page programming of a memory block.
  • FIG. 3 shows a diagram of one embodiment of a method of the present invention for multiple level, second page programming of a memory block.
  • FIG. 4 shows a diagram of an alternate embodiment of a method of the present invention for multiple level, first page programming of a memory block.
  • FIG. 5 shows a diagram of the alternate embodiment of a method of the present invention for multiple level, second page programming of a memory block.
  • FIG. 6 shows a block diagram of one embodiment of an electronic system of the present invention.
  • FIG. 1 illustrates a simplified diagram of one embodiment for a NAND flash memory array of the present invention.
  • This memory is for purposes of illustration only as the present invention is not limited to NAND flash but can be used for other non-volatile memory technologies such as electrically erasable programmable read only memory (EEPROM).
  • EEPROM electrically erasable programmable read only memory
  • the memory array of FIG. 1 does not show all of the elements typically required in a memory array. For example, only two bitlines are shown (BL 1 and BL 2 ) when the number of bitlines required actually depends upon the memory density. The bitlines are subsequently referred to as (BL 1 -BLN).
  • the array is comprised of an array of floating gate cells 101 arranged in series strings 104 , 105 .
  • Each of the floating gate cells 101 are coupled drain to source in each series string 104 , 105 .
  • a word line (WL 0 -WL 31 ) that spans across multiple series strings 104 , 105 is coupled to the control gates of every floating gate cell in a row in order to control their operation.
  • the bitlines (BL 1 -BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.
  • the word lines select the individual floating gate memory cells in the series string 104 , 105 to be written to or read from and operate the remaining floating gate memory cells in each series string 104 , 105 in a pass through mode.
  • Each series string 104 , 105 of floating gate memory cells is coupled to a source line 106 by a source select gate 116 , 117 and to an individual bitline (BL 1 -BLN) by a drain select gate 112 , 113 .
  • the source select gates 116 , 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates.
  • the drain select gates 112 , 113 are controlled by a drain select gate control line SG(D) 114 .
  • Each cell can be programmed as a single bit per cell (i.e., single level cell-SBC) or MLC.
  • Each cell's threshold voltage (V t ) determines the data that is stored in the cell. For example, in a single bit per cell, a V t of 1V might indicate a programmed cell while a V t of ⁇ 1V might indicate an erased cell.
  • the multilevel cells have more then two V t windows that each indicates a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
  • a cell may be assigned four different voltage V t distributions.
  • the width of the distribution is ⁇ 200 mV.
  • a separation of 0.3V to 0.5V is assigned between each VT distribution range as well. This separation zone between the V t distributions is to insure that the multi V t distributions do not overlap causing logic errors.
  • the voltage stored on the cell is sensed to be within the 01 high V t distribution, then the cell is storing a 01. If the voltage is within the 00 second highest distribution, the cell is storing a 00. This continues for as many ranges that are used for the cell.
  • the embodiments of the present invention are not limited to two bits per cell. Some embodiments may store more than two bits per cell, depending on the quantity of different voltage ranges that can be differentiated on the cell.
  • the selected word line for the flash memory cell to be programmed is applied with a train of high voltage programming pulses. These high voltage programming pulses typically start at 16 v and increment in 0.5V increments. A 10V non-incrementing, high voltage pulse is applied on the unselected WLs.
  • the channel of the inhibited cell is decoupled from the BL by applying ⁇ 1.3 v on the BL.
  • the channel area of these devices will rise with the WL pulse based on the coupling coefficient of the memory cell so that the differential voltage between the WL and the channel will not be sufficient to program the cell.
  • the channel is grounded to 0 v through the BL.
  • the large potential formed between the channel, and the WL will cause the cell to program and the V t of the device will increase as higher programming pulses are applied.
  • a verification phase is performed.
  • the selected WL is lowered to 0V, the unselected WLs are lowered to 5V, and the states of the selected cells are sensed. If the cell is programmed to have a V t level such that the 0 v on the WL cannot make the device to conduct, the device is considered to be programmed. Otherwise the cell is considered to be still erased and the programming pulse height is increased by 0.5V and applied to the selected WL again. This process is repeated until all selected cells that need to be programmed are all programmed.
  • a typical memory block is comprised of 64 logical pages.
  • the 64 pages are formed with 32 physical WLs.
  • Each WL contains 2 logical pages.
  • the second page on the same WL will experience disturb condition even though it is inhibited. Therefore pages with shared WLs can experience programming disturb.
  • the programming disturb caused on the shared WL will shift the V t distribution of cells that are previously programmed in the second page that is on the same WL and make their distribution wider.
  • the prior art method of programming a multi-level cell may be a practical programming method but, from the programming disturb point of view, it is not an optimum method.
  • the higher voltages needed to program the higher V t distributions will disturb the already programmed lower V t distribution due to the higher voltage. By reversing this sequence, the disturb of the lower V t distribution will be minimized.
  • FIG. 2 illustrates a diagram of one embodiment of a method of the present invention for multiple level, first page programming of a memory block. This diagram shows that the page begins in a known erased state 200 .
  • the erased state 200 is indicated by a logical “11” since both bits of the multi-bit cell are in a “1” state when erased.
  • the erased state may be indicated by the logical “0” state in other memory devices.
  • the embodiment of FIG. 2 starts with the programming of the highest threshold voltage distribution and programs in decreasing order of threshold voltage distribution. Statistically, this places the highest voltage on the word line prior to all the lower multi-level distributions being programmed and, therefore, minimizing the chance to cause disturb conditions with the other cells on the same word line that are planned to be programmed to lower V t distributions.
  • the diagram of FIG. 2 also shows the disturb created in the erased state 200 during the programming of the first page.
  • the disturb is shown as the movement 230 of the V t state along the V t axis.
  • This movement 230 can be substantial since the largest word line voltage has just been experienced.
  • usually the separation zone between the “11” and “10” states is larger than other states in order to make sure that the “11” state exposure to disturb is accounted for.
  • “11” states will see the largest distribution shift since it is the lowest V t , and is exposed to the largest number of inhibit pulses.
  • FIG. 3 illustrates a second page of programming in accordance with the embodiment of FIG. 2 .
  • This figure shows that cells that are to be programmed to the “10” state 201 are programmed last with a second page of incrementing programming voltage pulses 300 .
  • Incrementing programming pulses, and a verification pulse following each programming pulse will program the “10” state.
  • the maximum applied voltage to program will not reach as high as the previous higher V t distribution needed. This puts the lowest programming voltage on the word line after the first two states have already been programmed. While a slight amount of disturb 301 and 302 in the previously programmed states is going to be present, it is substantially less than that experienced with the prior art programming methods where the lower V t distributions are set before setting the highest V t distribution.
  • the bits that are mapped to the states 200 - 203 shown in FIGS. 2 and 3 are for purposes of illustration only.
  • the present invention is not limited to having the state with the highest V t being a logical “01”.
  • a “10” state might have the highest threshold voltage.
  • FIG. 4 illustrates an alternate embodiment of the method of the present invention for programming multiple level, non-volatile memory cells.
  • incrementing programming pulses and a single level verification pulse following each programming pulse will program 400 the “01” state.
  • This embodiment similarly programs the highest threshold voltage first to reduce the amount of disturb experienced by other cells sharing a word line.
  • a programming pulse at the highest programming voltage is generated to program the “01” state to the appropriate cells coupled to the word line.
  • FIG. 5 shows the second page of programming for the embodiment of FIG. 4 .
  • This page of programming generates programming pulses to program 500 , 501 the “00” and “10” states.
  • Two verification pulses follow each programming pulse where two different levels are applied (i.e., 2V pulse for “01” and 1.3V pulse for “00”) to the WL.
  • the V t distributions in decreasing order of their threshold voltages, the least amount of program disturb is achieved to the previously programmed states within the same page and the previously programmed pages on the same WL.
  • FIGS. 2-5 are for purposes of illustration only.
  • the programming of non-volatile memory cells by programming in decreasing order of threshold voltages can be accomplished in various ways that have not been shown.
  • FIG. 6 illustrates a functional block diagram of a memory device 600 that can incorporate the flash memory array and programming method embodiments of the present invention.
  • the memory device 600 is coupled to a processor 610 .
  • the processor 610 may be a microprocessor or some other type of controlling circuitry.
  • the memory device 600 and the processor 610 form part of an electronic system 620 .
  • the memory device 600 has been simplified to focus on features of the memory that are helpful in understanding the present invention.
  • the memory device includes an array of flash memory cells 630 as described above with reference to FIGS. 2 and 3 .
  • the memory array 630 is arranged in banks of rows and columns.
  • the control gates of each row of memory cells is coupled with a word line while the drain and source connections of the memory cells are coupled to bitlines.
  • the connections of the cells to the bitlines determines whether the array is a NAND architecture or a NOR architecture.
  • An address buffer circuit 640 is provided to latch address signals provided on address input connections A 0 -Ax 642 . Address signals are received and decoded by a row decoder 644 and a column decoder 646 to access the memory array 630 . It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 630 . That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
  • the memory device 600 reads data in the memory array 630 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 650 .
  • the sense/buffer circuitry in one embodiment, is coupled to read and latch a row of data from the memory array 630 .
  • Data input and output buffer circuitry 660 is included for bi-directional data communication over a plurality of data connections 662 with the processor 610 .
  • Write circuitry 655 is provided to write data to the memory array.
  • Control circuitry 670 decodes signals provided on control connections 672 from the processor 610 . These signals are used to control the operations on the memory array 630 , including data read, data write (program), and erase operations.
  • the control circuitry 670 may be a state machine, a sequencer, or some other type of controller. In one embodiment, the control circuitry 670 is responsible for executing the embodiments of the programming method of the present invention.
  • the flash memory device illustrated in FIG. 6 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.
  • the embodiments of the present invention improve margins between MLC levels while maintaining programming throughput. This is accomplished by programming the higher V t distribution first then the lower distributions. This reduces the number of word line programming voltages in order to minimize the program disturb of other cells on the word line.
  • one embodiment maps the logical “11” to the erased state and the logical “01” state to have the highest threshold voltage, thus requiring the highest programming voltage.
  • the logical “00” state is mapped to the 3 rd highest threshold voltage and the logical “10” state to the 2nd highest threshold voltage. Therefore, one embodiment of the present invention would first program a first page by programming cells on a word line with the “01,” state together with the logical “00” state.
  • a second page, comprising the logical “10” state can then be programmed. Since the lowest programming voltage is used last, the program disturb experienced by the first page is minimized.

Abstract

The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of divisional U.S. application Ser. No. 12/125,147, which was filed on May 22, 2008, which is scheduled to issue as U.S. Pat. No. 8,045,392 on Oct. 25, 2011, which is a divisional of U.S. application Ser. No. 11/454,737, which was filed on Jun. 16, 2006 and issued as U.S. Pat. No. 7,388,779 on Jun. 17, 2008, which is a divisional of U.S. application Ser. No. 11/065,986, which was filed on Feb. 25, 2005, which issued as U.S. Pat. No. 7,221,592 on May 22, 2007 the disclosure of which are hereby incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices.
  • Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
  • Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
  • As the performance and complexity of electronic systems increase, the requirement for additional memory also increases. However, in order to continue to reduce the costs of a system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit.
  • One way to increase memory density is to use multi-level cell (MLC) non-volatile memory. This method stores two or more data bits in each memory cell. One problem with MLC is that subsequent programming of additional data can cause a program disturb condition that can program bits that are not desired to be programmed. This is caused by placing a large programming voltage on a word line that is shared by cells that have already been programmed.
  • The above-mentioned problems with the flash memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
  • For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to program MLC non-volatile memory cells while reducing program disturb.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a simplified diagram of one embodiment for a NAND flash memory array of the present invention.
  • FIG. 2 shows a diagram of one embodiment of a method of the present invention for multiple level, first page programming of a memory block.
  • FIG. 3 shows a diagram of one embodiment of a method of the present invention for multiple level, second page programming of a memory block.
  • FIG. 4 shows a diagram of an alternate embodiment of a method of the present invention for multiple level, first page programming of a memory block.
  • FIG. 5 shows a diagram of the alternate embodiment of a method of the present invention for multiple level, second page programming of a memory block.
  • FIG. 6 shows a block diagram of one embodiment of an electronic system of the present invention.
    •  DETAILED DESCRIPTION
  • In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.
  • FIG. 1 illustrates a simplified diagram of one embodiment for a NAND flash memory array of the present invention. This memory is for purposes of illustration only as the present invention is not limited to NAND flash but can be used for other non-volatile memory technologies such as electrically erasable programmable read only memory (EEPROM).
  • The memory array of FIG. 1, for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only two bitlines are shown (BL1 and BL2) when the number of bitlines required actually depends upon the memory density. The bitlines are subsequently referred to as (BL1-BLN).
  • The array is comprised of an array of floating gate cells 101 arranged in series strings 104, 105. Each of the floating gate cells 101 are coupled drain to source in each series string 104, 105. A word line (WL0-WL31) that spans across multiple series strings 104, 105 is coupled to the control gates of every floating gate cell in a row in order to control their operation. The bitlines (BL1-BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.
  • In operation, the word lines (WL0-WL31) select the individual floating gate memory cells in the series string 104, 105 to be written to or read from and operate the remaining floating gate memory cells in each series string 104, 105 in a pass through mode. Each series string 104, 105 of floating gate memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bitline (BL1-BLN) by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.
  • Each cell can be programmed as a single bit per cell (i.e., single level cell-SBC) or MLC. Each cell's threshold voltage (Vt) determines the data that is stored in the cell. For example, in a single bit per cell, a Vt of 1V might indicate a programmed cell while a Vt of −1V might indicate an erased cell. The multilevel cells have more then two Vt windows that each indicates a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
  • For example, a cell may be assigned four different voltage Vt distributions. The width of the distribution is ˜200 mV. Typically, a separation of 0.3V to 0.5V is assigned between each VT distribution range as well. This separation zone between the Vt distributions is to insure that the multi Vt distributions do not overlap causing logic errors. During verification, if the voltage stored on the cell is sensed to be within the 01 high Vt distribution, then the cell is storing a 01. If the voltage is within the 00 second highest distribution, the cell is storing a 00. This continues for as many ranges that are used for the cell.
  • The embodiments of the present invention are not limited to two bits per cell. Some embodiments may store more than two bits per cell, depending on the quantity of different voltage ranges that can be differentiated on the cell.
  • During a typical programming operation, the selected word line for the flash memory cell to be programmed is applied with a train of high voltage programming pulses. These high voltage programming pulses typically start at 16 v and increment in 0.5V increments. A 10V non-incrementing, high voltage pulse is applied on the unselected WLs.
  • To inhibit selected cells from programming on the selected WL, the channel of the inhibited cell is decoupled from the BL by applying ˜1.3 v on the BL. The channel area of these devices will rise with the WL pulse based on the coupling coefficient of the memory cell so that the differential voltage between the WL and the channel will not be sufficient to program the cell.
  • To program selected cells on the selected WL, the channel is grounded to 0 v through the BL. The large potential formed between the channel, and the WL will cause the cell to program and the Vt of the device will increase as higher programming pulses are applied.
  • Between every programming pulse a verification phase is performed. During verification, the selected WL is lowered to 0V, the unselected WLs are lowered to 5V, and the states of the selected cells are sensed. If the cell is programmed to have a Vt level such that the 0 v on the WL cannot make the device to conduct, the device is considered to be programmed. Otherwise the cell is considered to be still erased and the programming pulse height is increased by 0.5V and applied to the selected WL again. This process is repeated until all selected cells that need to be programmed are all programmed.
  • A typical memory block is comprised of 64 logical pages. The 64 pages are formed with 32 physical WLs. Each WL contains 2 logical pages. For example, there are 4 Kbit cells on a WL. 2 Kbit is dedicated for one page that shares the same WL with another 2 Kbit page. If every cell is used in a multi Vt distribution level mode then a WL will hold 4 pages of 2 Kbit per page. When one of these pages is being programmed the second page on the same WL will experience disturb condition even though it is inhibited. Therefore pages with shared WLs can experience programming disturb. The programming disturb caused on the shared WL will shift the Vt distribution of cells that are previously programmed in the second page that is on the same WL and make their distribution wider. For non-volatile memory devices that use two levels per cell this may not be a major problem since the separation zone between the two distributions is large enough to prevent the distributions from overlapping due to disturb. However, for multi level cell (MLC) operation where a single cell is used to represent 2 bits or 4 levels per physical single cell, the separation zone is reduced and reducing disturb becomes extremely important in order to prevent Vt distributions from overlapping or shifting.
  • Prior art, multi page programming algorithms follow a special programming sequence in order to minimize the disturb condition due to cell-to-cell floating gate coupling issues. The sequence in which the prior art Vt distribution is programmed is based on the cell-to-cell coupling issues. This is an important factor to consider in minimizing the cell-to-cell floating gate coupling to the Vt distribution. However, it is also important to consider minimizing the number of the highest voltage pulses being applied to the WL to program all pages on the same WL in order to minimize the shared WL disturb condition.
  • The prior art method of programming a multi-level cell, starting from the low Vt distribution state to the highest Vt distribution, may be a practical programming method but, from the programming disturb point of view, it is not an optimum method. After programming the lower Vt distribution, the higher voltages needed to program the higher Vt distributions will disturb the already programmed lower Vt distribution due to the higher voltage. By reversing this sequence, the disturb of the lower Vt distribution will be minimized.
  • FIG. 2 illustrates a diagram of one embodiment of a method of the present invention for multiple level, first page programming of a memory block. This diagram shows that the page begins in a known erased state 200. In this embodiment, the erased state 200 is indicated by a logical “11” since both bits of the multi-bit cell are in a “1” state when erased. The erased state may be indicated by the logical “0” state in other memory devices.
  • When a programming operation is performed, the embodiment of FIG. 2 starts with the programming of the highest threshold voltage distribution and programs in decreasing order of threshold voltage distribution. Statistically, this places the highest voltage on the word line prior to all the lower multi-level distributions being programmed and, therefore, minimizing the chance to cause disturb conditions with the other cells on the same word line that are planned to be programmed to lower Vt distributions.
  • As an example of operation, all of the cells in a page that have to be programmed with bits “01” are programmed first since this state 203 is the highest Vt. The next lowest state is a logical “00” so cells with this state 202 would be programmed next. These programming operations can be accomplished with consecutive programming and verification pulses where two verification pulses with two different levels are applied (i.e., 2V for 01, and 1.3V for 00) between every increasing programming pulse.
  • The diagram of FIG. 2 also shows the disturb created in the erased state 200 during the programming of the first page. The disturb is shown as the movement 230 of the Vt state along the Vt axis. This movement 230 can be substantial since the largest word line voltage has just been experienced. However, usually the separation zone between the “11” and “10” states is larger than other states in order to make sure that the “11” state exposure to disturb is accounted for. “11” states will see the largest distribution shift since it is the lowest Vt, and is exposed to the largest number of inhibit pulses.
  • FIG. 3 illustrates a second page of programming in accordance with the embodiment of FIG. 2. This figure shows that cells that are to be programmed to the “10” state 201 are programmed last with a second page of incrementing programming voltage pulses 300. Incrementing programming pulses, and a verification pulse following each programming pulse, will program the “10” state. Statistically, since this is the 3rd lowest Vt distribution, the maximum applied voltage to program will not reach as high as the previous higher Vt distribution needed. This puts the lowest programming voltage on the word line after the first two states have already been programmed. While a slight amount of disturb 301 and 302 in the previously programmed states is going to be present, it is substantially less than that experienced with the prior art programming methods where the lower Vt distributions are set before setting the highest Vt distribution.
  • The bits that are mapped to the states 200-203 shown in FIGS. 2 and 3 are for purposes of illustration only. The present invention is not limited to having the state with the highest Vt being a logical “01”. For example, in an alternate embodiment, a “10” state might have the highest threshold voltage.
  • FIG. 4 illustrates an alternate embodiment of the method of the present invention for programming multiple level, non-volatile memory cells. In this method, incrementing programming pulses and a single level verification pulse following each programming pulse will program 400 the “01” state. Statistically, since “01” requires the highest Vt distribution the highest voltage on the WL will be applied before programming the lower Vt distributions. This embodiment similarly programs the highest threshold voltage first to reduce the amount of disturb experienced by other cells sharing a word line. In the embodiment of FIG. 4, a programming pulse at the highest programming voltage is generated to program the “01” state to the appropriate cells coupled to the word line.
  • FIG. 5 shows the second page of programming for the embodiment of FIG. 4. This page of programming generates programming pulses to program 500, 501 the “00” and “10” states. Two verification pulses follow each programming pulse where two different levels are applied (i.e., 2V pulse for “01” and 1.3V pulse for “00”) to the WL. By programming 500, 501 the Vt distributions in decreasing order of their threshold voltages, the least amount of program disturb is achieved to the previously programmed states within the same page and the previously programmed pages on the same WL.
  • The above-described embodiments of FIGS. 2-5 are for purposes of illustration only. The programming of non-volatile memory cells by programming in decreasing order of threshold voltages can be accomplished in various ways that have not been shown.
  • FIG. 6 illustrates a functional block diagram of a memory device 600 that can incorporate the flash memory array and programming method embodiments of the present invention. The memory device 600 is coupled to a processor 610. The processor 610 may be a microprocessor or some other type of controlling circuitry. The memory device 600 and the processor 610 form part of an electronic system 620. The memory device 600 has been simplified to focus on features of the memory that are helpful in understanding the present invention.
  • The memory device includes an array of flash memory cells 630 as described above with reference to FIGS. 2 and 3. The memory array 630 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a word line while the drain and source connections of the memory cells are coupled to bitlines. As is well known in the art, the connections of the cells to the bitlines determines whether the array is a NAND architecture or a NOR architecture.
  • An address buffer circuit 640 is provided to latch address signals provided on address input connections A0-Ax 642. Address signals are received and decoded by a row decoder 644 and a column decoder 646 to access the memory array 630. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 630. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
  • The memory device 600 reads data in the memory array 630 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 650. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 630. Data input and output buffer circuitry 660 is included for bi-directional data communication over a plurality of data connections 662 with the processor 610. Write circuitry 655 is provided to write data to the memory array.
  • Control circuitry 670 decodes signals provided on control connections 672 from the processor 610. These signals are used to control the operations on the memory array 630, including data read, data write (program), and erase operations. The control circuitry 670 may be a state machine, a sequencer, or some other type of controller. In one embodiment, the control circuitry 670 is responsible for executing the embodiments of the programming method of the present invention.
  • The flash memory device illustrated in FIG. 6 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.
  • In summary, the embodiments of the present invention improve margins between MLC levels while maintaining programming throughput. This is accomplished by programming the higher Vt distribution first then the lower distributions. This reduces the number of word line programming voltages in order to minimize the program disturb of other cells on the word line.
  • For example, one embodiment maps the logical “11” to the erased state and the logical “01” state to have the highest threshold voltage, thus requiring the highest programming voltage. The logical “00” state is mapped to the 3 rd highest threshold voltage and the logical “10” state to the 2nd highest threshold voltage. Therefore, one embodiment of the present invention would first program a first page by programming cells on a word line with the “01,” state together with the logical “00” state. A second page, comprising the logical “10” state, can then be programmed. Since the lowest programming voltage is used last, the program disturb experienced by the first page is minimized.
  • Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims (11)

1.-20. (canceled)
21. An electronic system comprising:
a processor for generating control signals that are transmitted on control connections; and
a memory device, coupled to the processor, for operating in response to the control signals, the memory device comprising:
a memory array comprising a plurality of word lines that are each coupled to a plurality of multiple level memory cells the memory array adapted to receive data as controlled by the control signals; and
a control circuit that receives control signals from the processor and is coupled to program the memory array, the control circuit configured to initially program a first page, with two highest distributions, and subsequently program a second page with lower distributions.
22. The system of claim 21 wherein the memory device is a NAND flash memory device.
23. The system of claim 21 wherein the memory signals comprise programming and verification commands.
24. The system of claim 21 wherein each distribution represents a programmable state for the plurality of memory cells.
25. The system of claim 24 wherein the control circuit is configured to program memory cells on the first page in descending order of distributions that begin at the highest distribution.
26. The system of claim 24 wherein each state is comprised of two bits.
27. The system of claim 21 wherein each of the plurality of memory cells is programmable within four different distributions in response to at least one programming pulse.
28. The system of claim 21 wherein the control circuit programs the first and second pages by control of generation of a series of incrementing programming pulses.
29. The system of claim 28 wherein the control circuit is further configured to control generation of a verify pulse between each programming pulse.
30. The system of claim 21 wherein the control circuit is further configured to program:
a first set of memory cells of the plurality of memory cells of a word line, each memory cell having a plurality of programmable states wherein each state is represented by a threshold voltage distribution, a second set of memory cells of the word line, and remaining memory cells of the word line wherein the first set of memory cells are programmed to a first threshold voltage distribution, the second set of memory cells are programmed to a second threshold voltage distribution and further wherein the first threshold voltage distribution is greater than the second threshold voltage distribution and the remaining memory cells of the word line are programmed in a decreasing order of threshold voltage distributions.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140089561A1 (en) * 2012-09-26 2014-03-27 Kiran Pangal Techniques Associated with Protecting System Critical Data Written to Non-Volatile Memory

Families Citing this family (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7221592B2 (en) * 2005-02-25 2007-05-22 Micron Technology, Inc. Multiple level programming in a non-volatile memory device
CN103258572B (en) 2006-05-12 2016-12-07 苹果公司 Distortion estimation in storage device and elimination
WO2007132456A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Memory device with adaptive capacity
WO2007132452A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Reducing programming error in memory devices
WO2007132457A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US8060806B2 (en) 2006-08-27 2011-11-15 Anobit Technologies Ltd. Estimation of non-linear distortion in memory devices
WO2008053472A2 (en) 2006-10-30 2008-05-08 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
CN101601094B (en) 2006-10-30 2013-03-27 苹果公司 Reading memory cells using multiple thresholds
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US7511996B2 (en) 2006-11-30 2009-03-31 Mosaid Technologies Incorporated Flash memory program inhibit scheme
US8151163B2 (en) 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
KR100801035B1 (en) * 2006-12-14 2008-02-04 삼성전자주식회사 Method of programming multi-level cells, page buffer block and non-volatile memory device including the same
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7619918B2 (en) * 2006-12-29 2009-11-17 Intel Corporation Apparatus, method, and system for flash memory
KR100818717B1 (en) * 2007-01-18 2008-04-02 삼성전자주식회사 Nonvolatile semi-conductor memory device and program method of the nonvolatile semi-conductor memory device
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
US20080189473A1 (en) * 2007-02-07 2008-08-07 Micron Technology, Inc Mlc selected multi-program for system management
US7738291B2 (en) * 2007-03-12 2010-06-15 Micron Technology, Inc. Memory page boosting method, device and system
CN101715595A (en) 2007-03-12 2010-05-26 爱诺彼得技术有限责任公司 Adaptive estimation of memory cell read thresholds
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
US20080266651A1 (en) * 2007-04-24 2008-10-30 Katsuhiko Murakami Optical apparatus, multilayer-film reflective mirror, exposure apparatus, and device
US7577029B2 (en) * 2007-05-04 2009-08-18 Mosaid Technologies Incorporated Multi-level cell access buffer with dual function
WO2008139441A2 (en) 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
KR100836800B1 (en) * 2007-05-30 2008-06-10 삼성전자주식회사 Memory data reading device and method using the same
US7580292B2 (en) * 2007-06-14 2009-08-25 Macronix International Co., Ltd. Method for programming a multilevel memory
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
WO2009050703A2 (en) 2007-10-19 2009-04-23 Anobit Technologies Data storage in analog memory cell arrays having erase failures
WO2009063450A2 (en) 2007-11-13 2009-05-22 Anobit Technologies Optimized selection of memory units in multi-unit memory devices
US7633798B2 (en) * 2007-11-21 2009-12-15 Micron Technology, Inc. M+N bit programming and M+L bit read for M bit memory cells
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
KR101448851B1 (en) * 2008-02-26 2014-10-13 삼성전자주식회사 Programming method of Non-volatile memory device
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US7843725B2 (en) 2008-06-11 2010-11-30 Micron Technology, Inc. M+L bit read column architecture for M bit memory cells
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US7852671B2 (en) 2008-10-30 2010-12-14 Micron Technology, Inc. Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array
US8261159B1 (en) 2008-10-30 2012-09-04 Apple, Inc. Data scrambling schemes for memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
KR101518033B1 (en) * 2008-11-18 2015-05-06 삼성전자주식회사 Multi-level non-volatile semiconductor device, memory system having the same and Operating method there-of
KR101518039B1 (en) 2008-12-08 2015-05-07 삼성전자주식회사 Nonvolatile memory device and write method thereof
US8397131B1 (en) 2008-12-31 2013-03-12 Apple Inc. Efficient readout schemes for analog memory cell devices
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
KR101534274B1 (en) * 2009-02-25 2015-07-06 삼성전자주식회사 Memory system and write method thereof
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US20100332922A1 (en) * 2009-06-30 2010-12-30 Mediatek Inc. Method for managing device and solid state disk drive utilizing the same
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US8537623B2 (en) * 2011-07-07 2013-09-17 Micron Technology, Inc. Devices and methods of programming memory cells
CN102436849B (en) * 2011-12-02 2015-03-11 南京大学 Operation method for realizing multiple-valued/multibit storage of partial capture-type flash memory
KR102125376B1 (en) 2013-07-01 2020-06-23 삼성전자주식회사 Storage device and writing method thereof
US11004525B1 (en) * 2020-02-20 2021-05-11 Sandisk Technologies Llc Modulation of programming voltage during cycling
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory
TW202331726A (en) * 2022-01-21 2023-08-01 聯華電子股份有限公司 Method of programming mlc memory device and related mlc memory device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6058042A (en) * 1997-12-26 2000-05-02 Sony Corporation Semiconductor nonvolatile memory device and method of data programming the same
US6859397B2 (en) * 2003-03-05 2005-02-22 Sandisk Corporation Source side self boosting technique for non-volatile memory
US7110300B2 (en) * 2003-02-20 2006-09-19 Stmicroelectronics S.R.L. Method of programming a multi-level, electrically programmable non-volatile semiconductor memory
US7450433B2 (en) * 2004-12-29 2008-11-11 Sandisk Corporation Word line compensation in non-volatile memory erase operations
US7492643B2 (en) * 2004-03-16 2009-02-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US8045392B2 (en) * 2005-02-25 2011-10-25 Round Rock Research, Llc Multiple level programming in a non-volatile memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3740212B2 (en) * 1996-05-01 2006-02-01 株式会社ルネサステクノロジ Nonvolatile semiconductor memory device
US6181604B1 (en) * 1999-07-22 2001-01-30 Macronix International Co., Ltd. Method for fast programming of EPROMS and multi-level flash EPROMS
US6147910A (en) * 1999-08-31 2000-11-14 Macronix International Co., Ltd. Parallel read and verify for floating gate memory device
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs
KR100465064B1 (en) * 2002-05-17 2005-01-06 주식회사 하이닉스반도체 Program word line voltage generation circuit of flash memory device
US7020017B2 (en) * 2004-04-06 2006-03-28 Sandisk Corporation Variable programming of non-volatile memory
KR100632940B1 (en) * 2004-05-06 2006-10-12 삼성전자주식회사 Non-volatile semiconductor memory device capable of changing program cycle time
KR100632942B1 (en) * 2004-05-17 2006-10-12 삼성전자주식회사 Program method of non-volatile memory device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6058042A (en) * 1997-12-26 2000-05-02 Sony Corporation Semiconductor nonvolatile memory device and method of data programming the same
US7110300B2 (en) * 2003-02-20 2006-09-19 Stmicroelectronics S.R.L. Method of programming a multi-level, electrically programmable non-volatile semiconductor memory
US6859397B2 (en) * 2003-03-05 2005-02-22 Sandisk Corporation Source side self boosting technique for non-volatile memory
US7492643B2 (en) * 2004-03-16 2009-02-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US7450433B2 (en) * 2004-12-29 2008-11-11 Sandisk Corporation Word line compensation in non-volatile memory erase operations
US8045392B2 (en) * 2005-02-25 2011-10-25 Round Rock Research, Llc Multiple level programming in a non-volatile memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140089561A1 (en) * 2012-09-26 2014-03-27 Kiran Pangal Techniques Associated with Protecting System Critical Data Written to Non-Volatile Memory
WO2014051775A1 (en) 2012-09-26 2014-04-03 Intel Corporation Techniques associated with protecting system critical data written to non-volatile memory
EP2901292A4 (en) * 2012-09-26 2016-04-13 Intel Corp Techniques associated with protecting system critical data written to non-volatile memory

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US20080219055A1 (en) 2008-09-11
US7221592B2 (en) 2007-05-22

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