US20120049347A1 - Semiconductor structure having conductive vias and method for manufacturing the same - Google Patents
Semiconductor structure having conductive vias and method for manufacturing the same Download PDFInfo
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- US20120049347A1 US20120049347A1 US13/103,059 US201113103059A US2012049347A1 US 20120049347 A1 US20120049347 A1 US 20120049347A1 US 201113103059 A US201113103059 A US 201113103059A US 2012049347 A1 US2012049347 A1 US 2012049347A1
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Abstract
Description
- This application claims the benefit of Taiwan application Serial No. 99129126, filed Aug. 30, 2010, the subject matter of which is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to the field of semiconductor packaging, and, more particularly, to thermal management of stacked-chip packages.
- 2. Description of Related Art
- In stacked-chip packaging, multiple integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This increases stack density, making the package structure smaller, and often reduces the length of the path that signals must traverse between chips. Thus, stacked-chip packaging tends to increase the speed of signal transmission between or among chips. Additionally, stacked-chip packaging allows chips having different functions to be integrated in a single package structure. Use of through silicon vias (TSV) has been a key technology in realizing stacked-chip packaging integration due to the ability to provide short vertical conductive paths between chips.
- However, thermal management of 3-D designs has been challenging. To maintain normal operation of the chip, the chip must be maintained within a limited operation temperature range. Operating temperatures in excess of the limited operation temperature range results in chip performance drop, reduced reliability or damage. Existing stacked-chip packages usually include a heat sink, which is bonded to a lower chip using adhesives and that covers the upper chips of the package.
- In current chip processing the surface of the chip is covered with a protective layer, which has a low thermal conductivity and therefore hinders conducting of the heat from the chip interior, where it is produced, to the surrounding environment. Even if the heat sink is disposed on the lower chip of the stacked-chip package structure, the protective layer likewise hinders thermal conductance between the lower chip and the heat sink, thus affecting operation and reliability of the stacked-chip package structure.
- One aspect of the disclosure relates to a semiconductor structure that includes a first chip; a redistribution layer disposed on a first surface of the first chip, the redistribution layer including at least one thermal via contacting the first surface of the first chip; a second chip coupled to the first surface of the first chip; and a heat sink thermally coupled to the at least one thermal via and the second chip.
- Another aspect of the disclosure relates to a semiconductor structure that includes a first chip having an active surface and a back surface opposite to the active surface, the first chip having a plurality of through silicon vias; a first wiring layer disposed on the active surface of the first chip, the first wiring layer comprising a first interconnect, the first interconnect connected to one end of each of the through silicon vias; a second wiring layer disposed on the back surface of the first chip, the second wiring layer comprising a second interconnect and at least one thermal via, the second interconnect connected to the other end of each of the through silicon vias, the at least one thermal via electrically insulated from the second interconnect and contacting the back surface of the first chip; a plurality of bump pads disposed on the second wiring layer, each of the bump pads connected to the second interconnect; and a heat dissipation layer disposed on the second wiring layer in an area where the bump pads are not located, the heat dissipation layer connected to the thermal via.
- Another aspect of the disclosure relates to manufacturing methods. In one embodiment, a manufacturing method includes providing a semiconductor wafer, the semiconductor wafer having an active surface, the semiconductor wafer having a plurality through silicon vias, a first wiring layer formed on the active surface of the semiconductor structure, the first wiring layer comprising a first interconnect, the first interconnect connected to one end of each of the through silicon vias; thinning the semiconductor wafer from a back surface of the semiconductor wafer opposite to the active surface to expose the other end of each of the through silicon vias and a back surface of the semiconductor wafer; forming a second wiring layer on the back surface of the semiconductor wafer, the second wiring layer comprising a second interconnect and a thermal via, the second interconnect connected to the other end of each of the through silicon vias, the thermal via electrically insulated from the second interconnects and contacting the back surface of the semiconductor structure; and forming a plurality of bump pads and a heat dissipation layer, each of the bump pads connected to the second interconnect, the heat dissipation layer connected to the thermal via.
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FIG. 1 illustrates a semiconductor structure according to one embodiment of the present invention; -
FIGS. 2A-2K illustrate a method for manufacturing a semiconductor structure according to one embodiment of present invention; and - FIGS. 2H′ and 2I′ illustrate substitute steps of the process as shown in
FIGS. 2A-2K according to one embodiment of present invention. - Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.
- Referring to
FIG. 1 , there is shown asemiconductor structure 100 according to one embodiment of the present invention. Thesemiconductor structure 100 includes afirst chip 110 having a plurality of through silicon vias (TSV) 112 in the semiconductor substrate thereof. It is to be appreciated that although silicon is the preferred semiconductor substrate material, the invention applies to any semiconductor material used in semiconductor chip fabrication, such as germanium, silicon germanium, gallium arsenide, or other III-V and II-IV compounds and the term is used generically throughout the disclosure regardless of the semiconductor material. - TSV fabrication can be placed into two main categories: “Via-First” processing and “Via-Last” processing. Via-First processing means that the through silicon vias are formed early in the manufacturing process, before the “back-end-of-line” (BEOL) processing. For Via-Last processing, the through silicon vias are fabricated after the BEOL processing.
- For Via-First, since the through silicon vias are buried inside the substrate material before the BEOL processing, the wafer requires an additional thinning process to expose the vias on the wafer back surface and an additional passivation step to isolate the substrate material from an electrical redistribution layer on the back surface.
- A
first wiring layer 120 or redistribution layer, commonly referred to as “RDL” is disposed on anactive surface 110 a of thefirst chip 110. The various wiring layers or RDL disclosed below are typically include one or more layers of dielectric or passivation material and one or more layers of conductive material for routing, and under bump metallurgy. Thefirst wiring layer 120 includes afirst interconnect 122. Thefirst interconnect 122 may, for example, be an interconnect formed during the back end of line of the wafer process. Thefirst interconnect 122 is, for example, connected betweenend 112 a of each of the throughsilicon vias 112 and asecond bump 184 disposed at a bottom side of thefirst chip 110. In addition, other active or passive elements (not shown) may exist in thefirst chip 110 and, therefore, thefirst interconnect 122 may be also connected with these active or passive elements. - A
second wiring layer 130 or RDL is disposed at aback side 110 b of thefirst chip 110. Thesecond wiring layer 130 includes asecond interconnect 132 and a plurality ofthermal vias 134. Thesecond interconnect 132 is connected to theother end 112 b of each of the throughsilicon vias 112. As shown, thethermal vias 134 are electrically insulated from thesecond interconnect 132 and contacts theback side 110 b of thefirst chip 110. Here, thethermal vias 134 are mainly used for thermal conduction. - A plurality of
bump pads 142 is disposed on thesecond wiring layer 130. Eachbump pad 142 is connected to thesecond interconnect 132. In addition, aheat dissipation layer 144 is disposed on thesecond wiring layer 130 in the area where thebump pads 142 are not located. Theheat dissipation layer 144 is connected to thethermal vias 134. - A
second chip 150 is disposed above thefirst chip 110 and is connected with thebump pads 142 via a plurality offirst bumps 182, such that thesecond chip 150 is electrically connected to the throughsilicon vias 112 of thefirst chip 110 via thefirst bumps 182, thebump pads 142 and thesecond interconnect 132. In order to protect thefirst bumps 182, afirst underfill 162 is filled between thesecond chip 150 and thesecond wiring layer 130 to enclose thefirst bumps 182. Thesecond chip 150 may also have an RDL formed on the active surface to facilitate patterning of the bumps. - As shown in
FIG. 1 , the foregoing structure may be disposed on acarrier substrate 170. Thecarrier substrate 170 may, for example, be a common printed circuit board, a ceramic substrate, a metal substrate, or another suitable type of carrier substrate for supporting thefirst chip 110. A plurality ofsecond bumps 184 is disposed between thefirst wiring layer 120 and thecarrier substrate 170 to electrically connect thefirst wiring layer 120 to thecarrier substrate 170. In order to protect thesecond bumps 184, asecond underfill 164 may be filled between thefirst wiring layer 120 and thecarrier substrate 170 to enclose thesecond bumps 184. In addition, a plurality ofsolder balls 186 may be disposed on a bottom of thecarrier substrate 170 as a path along which theentire semiconductor structure 100 is connected to an external circuit. - A
heat sink 190 may be disposed on thefirst chip 110 to enhance heat dissipation efficiency. Theheat sink 190 covers thesecond chip 150 and is coupled to theheat dissipation layer 144 on thefirst chip 110, such that heat generated by thefirst chip 110 andsecond chip 150 during operation can be dissipated to the surrounding environment by theheat sink 190. In order to position theheat sink 190 and enhance the efficiency of thermal conduction between theheat sink 190 and thefirst chip 110/second chip 150, a first thermally conductive adhesive 192 may be disposed between theheat sink 190 and theheat dissipation layer 144, and a second thermally conductive adhesive 194 may be disposed between theheat sink 190 and thesecond chip 150. - In the present embodiment, the
second wiring layer 130 is provided with thethermal vias 134, such that a large part of the heat generated by thefirst chip 110 can be transferred to a thermal conductive path comprising thethermal vias 134, theheat dissipation layer 144, and theheat sink 190, without being hindered by the dielectric material, having a lower thermal conductance, in thesecond wiring layer 130. As a result of adding the thermal conductive path, thesemiconductor structure 100 of the present embodiment has improved heat dissipation efficiency and operation reliability in comparison with existing structures. - In addition, in the present embodiment, the
heat dissipation layer 144 and thebump pads 142 may be fabricated using the same or similar materials. For example, the surface layer of thebump pad 142 can be a nickel-gold stack layer 140 b, which has good wettability. Likewise, theheat dissipation layer 144 also can have this nickel-gold stack layer 140 b as its surface layer, thus improving the solderability between theheat sink 190 and theheat dissipation layer 144. - Furthermore, in the present embodiment, a thermal path which includes the
heat sink 190, theheat dissipation layer 144 and thethermal vias 134 can also form a ground path through additional TSV's in the first chip 110 (not shown) so as to electrically interconnect with thesubstrate 170 and a ground plane external to thestructure 100 thereby forming an electromagnetic interference shield and preventing external electromagnetic fields from interfering with electrical performance of thefirst chip 110 and thesecond chip 150. - Referring to
FIG. 2A , asemiconductor wafer 110′ is first provided. Thesemiconductor wafer 110′ is used to form thefirst chip 110 ofFIG. 1 after a subsequent dicing process. Thesemiconductor wafer 110′ includes anactive surface 110 a, and the plurality of throughsilicon vias 112 formed in an interior thereof. In addition, theactive surface 110 a of thesemiconductor wafer 110′ includes thefirst wiring layer 120. Thefirst wiring layer 120 includes a first interconnect (e.g., back-end-of-line interconnect) 122, and thefirst interconnect 122 is connected to one end of each of the throughsilicon vias 112. - As shown in
FIG. 2B , thesemiconductor wafer 110′ is thinned from a back side of thesemiconductor wafer 110′ opposite to theactive surface 110 a so as to expose theother end 112 b of each of the throughsilicon vias 112 and theback surface 110 b of thesemiconductor wafer 110′. - As shown in
FIG. 2C , asecond wiring layer 130 is then formed on theback surface 110 b of thesemiconductor wafer 110′. Thesecond wiring layer 130 includes therein asecond interconnect 132 and thethermal vias 134. Thesecond interconnect 132 is connected to theother end 112 b of each of the throughsilicon vias 112. Thethermal vias 134 are electrically insulated from thesecond interconnect 132 and contact theback surface 110 b of thesemiconductor wafer 110′. Here, thesecond wiring layer 130 may be a stack of a single ormultiple metal layers 130 a and adielectric layer 130 b. Theuppermost dielectric layer 130 b has a plurality ofopenings 139 to expose thesecond interconnect 132 and thethermal vias 134. - As shown in
FIG. 2D , aplating seed layer 140 is then formed over the entire area of thesecond wiring layer 130. Theplating seed layer 140 is electrically connected to thesecond interconnect 132 and thethermal vias 134 through theopenings 139. As shown inFIG. 2E , amask 210 is then formed over theplating seed layer 140 to define a plurality ofpad regions 212 and aheat dissipation region 214 on theplating seed layer 140. Thepad regions 212 are positioned in correspondence with thesecond interconnect 132, and theheat dissipation region 214 is positioned in correspondence with thethermal vias 134. - In
FIG. 2F , a plating process is performed on theplating seed layer 140 to form a plurality ofbump pads 142 within thepad regions 212 and, at the same time, form aheat dissipation layer 144 within theheat dissipation region 214. Eachbump pad 142 is connected to thesecond interconnect 132, and theheat dissipation layer 144 is connected to thethermal vias 134. In the plating process, in order to increase the solderability between thebump pads 142 and the subsequently bondedsecond bumps 184 and the solderability between theheat dissipation layer 144 and the subsequently bondedheat sink 190, acopper layer 140 and the nickel-gold stack layer 140 b may be formed by plating. A gold layer is used as the surface layer of the plated structure, which has good wettability, thus increasing the yield of the subsequent soldering process. - As shown in
FIG. 2G , themask 210 and the portion of theplating seed layer 140 covered by themask 210 are then removed. The structure shown inFIG. 2G is a semi-finished product of thesemiconductor structure 100, which may be shipped in the form of wafers or individual chips after a sawing process. - The following description explains a subsequent process of stacking chips on the semi-product in the form of a wafer after the step of
FIG. 2G . - As shown in
FIG. 2H , multiple second chips 150 (only one shown inFIG. 2H ) are flip-chip bonded to thesemiconductor wafer 110′. Each of thesecond chip 150 is connected to a corresponding one of thebump pads 142 through a correspondingfirst bump 182. Additionally, in the present embodiment, thefirst underfill 162 is optionally applied between thesecond chips 150 and thesecond wiring layer 130, with thefirst underfill 162 enclosing the first bumps 182. The step of fillingunderfill 162 may be performed before or after thesecond chips 150 are flip-chip bonded to thesemiconductor wafer 110′. That is, thefirst underfill 162 may be formed on thesecond wiring layer 130 before each of thesecond chips 150 is bonded to thesemiconductor wafer 110′, or may be filled between thesecond chips 150 and thesecond wiring layer 130, after each of thesecond chips 150 is bonded to thesemiconductor wafer 110′. - As shown in
FIG. 2I , after thesecond chips 150 are flip-chip bonded to thesemiconductor wafer 110′, thesemiconductor wafer 110′ is sawed into a plurality of individualfirst chips 110. - As shown in
FIG. 2J , thefirst chip 110 is flip-chip bonded to thecarrier substrate 170. The throughsilicon vias 112 of thefirst chip 110 are electrically connected to thecarrier substrate 170 via the second bumps 184. Additionally, in the present embodiment, thesecond underfill 164 may also be filled between thefirst chip 110 and thecarrier substrate 170 to enclose the second bumps 184. Thesecond underfill 164 may be pre-formed on thecarrier substrate 170 before thefirst chip 110 is bonded to thecarrier substrate 170, or filled between thefirst chip 110 and thecarrier substrate 170 after thefirst chip 110 is bonded to thecarrier substrate 170. - FIG. 2H′ and 2I′ depicts a subsequent process of sawing the semi-finished product in the form of individual chips, and then stacking the individual chip on a carrier substrate.
- As shown in FIG. 2H′, the
semiconductor wafer 110′ is sawed into a plurality of the individualfirst chips 110. As shown in FIG. 2I′, after thesemiconductor wafer 110′ is sawed, one of the individualfirst chips 110 is flip-chip bonded to thecarrier substrate 170. Then, as shown in 2J, thesecond chip 150 is flip-chip bonded to the individualfirst chip 110. - In addition, as shown in
FIG. 2K , theheat sink 190 may be disposed on thefirst chip 110, substantially completing the fabrication of thesemiconductor structure 100. Theheat sink 190 covers thesecond chip 150 and is thermally coupled to theheat dissipation layer 144. - While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present invention which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.
Claims (20)
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