US20120074504A1 - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- US20120074504A1 US20120074504A1 US13/289,111 US201113289111A US2012074504A1 US 20120074504 A1 US20120074504 A1 US 20120074504A1 US 201113289111 A US201113289111 A US 201113289111A US 2012074504 A1 US2012074504 A1 US 2012074504A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title description 14
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- -1 silicate nitride Chemical class 0.000 claims description 14
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 11
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 11
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 11
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 4
- 150000004645 aluminates Chemical class 0.000 claims description 4
- 239000000463 material Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 2
- 238000005389 semiconductor device fabrication Methods 0.000 abstract description 2
- 125000006850 spacer group Chemical group 0.000 description 11
- 238000002955 isolation Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 229910052735 hafnium Inorganic materials 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 150000001638 boron Chemical class 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 150000003017 phosphorus Chemical class 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- AYHOQSGNVUZKJA-UHFFFAOYSA-N [B+3].[B+3].[B+3].[B+3].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-] Chemical compound [B+3].[B+3].[B+3].[B+3].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-] AYHOQSGNVUZKJA-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- the present invention relates to a semiconductor device and a method of fabricating the same.
- a gate insulating film decreases as downsizing of MOSFETs advances, and this poses the problem that a gate leakage current increases.
- a high-k film having a relative dielectric constant higher than that of a silicon oxide (SiO 2 ) film is used as a gate insulating film.
- An example of this high-k film is a hafnium silicate nitride (HfSiON) film.
- a complementary MOS transistor (to be referred to as a CMOSFET hereinafter) including a PMOSFET and NMOSFET is to be formed, however, if this hafnium silicate nitride (HfSiON) film is used as a gate insulating film, the gate threshold voltage of the PMOSFET fluctuates more than that of the NMOSFET.
- a CMOSFET complementary MOS transistor
- HfSiON hafnium silicate nitride
- a reference related to a CMOSFET using a high-k gate insulating film is as follows.
- a semiconductor device fabrication method comprising:
- first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate;
- first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film;
- first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces of the second gate electrode and the second gate insulating film, thereby forming an interface insulating film in an interface between the second gate electrode and the second gate insulating film.
- a semiconductor device comprising:
- first gate electrode sidewall insulating film formed on side surfaces of said first gate electrode and said first gate insulating film via an insulating film
- an N-channel transistor having a first source region and a first drain region formed on two sides of a first channel region formed in a surface portion of said P-type semiconductor region below said first gate electrode;
- a P-channel transistor having a second source region and a second drain region formed on two sides of a second channel region formed in a surface portion of said N-type semiconductor region below said second gate electrode.
- FIG. 1 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating a CMOSFET according to an embodiment of the present invention
- FIG. 2 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
- FIG. 3 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
- FIG. 4 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
- FIG. 5 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
- FIG. 6 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
- FIG. 7 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
- FIG. 8 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
- FIG. 9 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET.
- FIG. 10 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
- FIG. 11 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOSFET.
- FIG. 12 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOS FET.
- FIGS. 1 to 10 illustrate a method of fabricating a CMOSFET according to an embodiment of the present invention.
- a resist mask having a desired pattern is formed on a semiconductor substrate 10 by photolithography, and used as a mask to ion-implant boron (B), gallium (G), indium (In), or the like.
- a resist mask having a desired pattern is formed on the semiconductor substrate 10 , and used as a mask to ion-implant phosphorus (P), arsenic (As), antimony (Sb), or the like. Annealing is then performed to form a P-type semiconductor region 20 and N-type semiconductor region 30 as shown in FIG. 1 . Subsequently, as shown in FIG. 2 , an element isolation insulating film 40 is formed in a desired region on the semiconductor substrate 10 .
- an insulating film made of, e.g., a hafnium silicate nitride (HfSiON) film is formed on the surface of the semiconductor substrate 10 .
- this insulating film is not limited to the hafnium silicate nitride film. That is, it is possible to use various types of high-k films having relative dielectric constants higher than that of a silicon oxide (SiO 2 ) film.
- Examples are a hafnium oxide (HfOx) film, a zirconium oxide (ZrOx) film, a silicate film of a hafnium oxide film, an aluminate film of a hafnium oxide film, a silicate film of a zirconium oxide film, an aluminate film of a zirconium oxide film, a silicate nitride film of a hafnium oxide film, an aluminate nitride film of a hafnium oxide film, a silicate nitride film of a zirconium oxide film, and an aluminate nitride film of a zirconium oxide film.
- HfOx hafnium oxide
- ZrOx zirconium oxide
- a silicate film of a hafnium oxide film an aluminate film of a hafnium oxide film
- a silicate film of a zirconium oxide film an a
- Polysilicon is deposited on this insulating film by CVD or the like to form a polysilicon film.
- a polysilicon germanium film may also be formed by depositing polysilicon germanium on the insulating film.
- the polysilicon film and hafnium silicate nitride (HfSiON) film are sequentially patterned by lithography and RIE, thereby forming a gate electrode 70 and gate insulating film 50 on the P-type semiconductor region 20 , and a gate electrode 80 and gate insulating film 60 on the N-type semiconductor region 30 .
- a silicon nitride (SiN) film 90 about 2 nm thick is formed on the entire surface.
- the silicon nitride (SiN) film 90 is removed by RIE except for the silicon nitride (SiN) film 90 formed on the side surfaces of the gate electrode 70 and gate insulating film 50 , and on the side surfaces of the gate electrode 80 and gate insulating film 60 .
- offset spacers 100 A and 100 B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50
- offset spacers 110 A and 110 B are formed on the side surfaces of the gate electrode 80 and gate insulating film 60 .
- an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20 , and annealing is so performed as to diffuse this phosphorus (P), thereby forming a shallow-junction, lightly doped source extension region 120 A and drain extension region 120 B.
- P phosphorus
- a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region 30 , and annealing is so performed as to diffuse this boron (B), thereby forming a shallow-junction, lightly doped source extension region 130 A and drain extension region 130 B.
- the semiconductor substrate 10 , gate electrodes 70 and 80 , and offset spacers 100 and 110 are coated with a photoresist, and the photoresist is exposed and developed to form a resist mask 140 having a pattern which opens over the N-type semiconductor region 30 , thereby covering the P-type semiconductor region 20 with the resist mask 140 .
- the resist mask 140 is used as a mask to etch away the offset spacers 110 A and 110 B formed in the N-type semiconductor region 30 .
- the offset spacers 110 A and 110 B may also be removed after they are changed into an oxynitride film or oxide film by radical oxidation or thermal oxidation.
- the source extension region 130 A and drain extension region 130 B may also be formed after the offset spacers 110 A and 110 B are removed.
- a silicon oxide (SiO 2 ) film made of, e.g., a TEOS (tetraethoxysilane) film is formed on the entire surface of the semiconductor substrate 10 .
- this silicon oxide (SiO 2 ) film is etched by RIE to form gate electrode side walls 150 A and 150 B on the side surfaces of the offset spacers 100 A and 100 B, and gate electrode side walls 160 A and 160 B on the side surfaces of the gate electrode 80 and gate insulating film 60 .
- the gate electrode side walls 160 A and 160 B act on the interface between the gate electrode 80 and gate insulating film 60 formed on the N-type semiconductor region 30 , thereby forming a low-k interface insulating film (interface layer) 170 made of a silicon oxide (SiO 2 ) film about 2 to 3 nm thick in the interface between the gate electrode 80 and gate insulating film 60 .
- interface layer silicon oxide
- the offset spacers 100 A and 100 B are already formed on the side surfaces of the gate electrode 70 and gate insulating film 50 formed on the P-type semiconductor region 20 . Therefore, even when the gate electrode side walls 150 A and 150 B are formed, they do not act on the interface between the gate electrode 70 and gate insulating film 50 , so almost no interface insulating film forms.
- a silicon oxide film made of a TEOS film is used as the gate electrode side walls 150 and 160 in this embodiment, it is also possible to use any of various silicon oxide films such as HTO (High Temperature Oxide), BPSG (Borophosphosilicate Glass), PSG (Phosphosilicate Glass), and BSG (Boron-Silicate Glass).
- an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20 , and annealing is so performed as to diffuse this phosphorus (P), thereby forming a source region 180 A and drain region 180 B.
- P phosphorus
- a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region 30 , and annealing is so performed as to diffuse this boron (B), thereby forming a source region 190 A and drain region 190 B.
- silicides 200 A to 200 C for reducing the parasitic resistance on the surface of the gate electrode 70 and in the surface portions of the source region 180 A and drain region 180 B, and form silicides 210 A to 210 C on the surface of the gate electrode 80 and in the surface portions of the source region 190 A and drain region 190 B.
- a metal film made of, e.g., cobalt (Co), nickel (Ni), or platinum (Pt) is formed by sputtering
- annealing is performed to form silicides 200 A to 200 C for reducing the parasitic resistance on the surface of the gate electrode 70 and in the surface portions of the source region 180 A and drain region 180 B, and form silicides 210 A to 210 C on the surface of the gate electrode 80 and in the surface portions of the source region 190 A and drain region 190 B.
- an interlayer dielectric film (not shown) is formed, and a wiring step is performed by forming contact plugs (not shown) in this interlayer dielectric film, thereby forming a CMOSFET 240 including an NMOSFET 220 and PMOSFET 230 .
- the element isolation insulating film 40 is formed in the surface portion of the semiconductor substrate 10 .
- the gate electrode 70 is formed via the gate insulating film 50 formed on the surface of the semiconductor substrate 10 .
- the gate electrode side walls 150 A and 150 B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50 via the offset spacers 100 A and 100 B about 2 nm thick. Also, a channel region 250 is formed near the surface of the
- the source extension region 120 A and drain extension region 120 B are formed on the two ends of the channel region 250 .
- the source region 180 A is formed between the source extension region 120 A and an element isolation insulating film (not shown).
- the drain region 180 B is formed between the drain extension region 120 B and element isolation insulating film 40 .
- silicides 200 A to 200 C for reducing the parasitic resistance are formed on the surface of the gate electrode 70 and on the surfaces of the source region 180 A and drain region 180 B.
- the gate electrode 80 is formed near the central portion of the N-type semiconductor region 30 via the gate insulating film 60 formed on the surface of the semiconductor substrate 10 , and the interface insulating film 170 made of a silicon oxide (SiO 2 ) film about 2 to 3 nm thick.
- the gate electrode side walls 160 A and 160 B are formed on the side surfaces of the gate electrode 80 , interface insulating film 170 , and gate insulating film 60 . Also, a channel region 260 is formed near the surface of the semiconductor substrate 10 below the gate electrode 80 .
- the source extension region 130 A and drain extension region 130 B are formed on the two ends of the channel region 260 .
- the source region 190 A is formed between the source extension region 130 A and element isolation insulating film 40 .
- the drain region 190 B is formed between the drain extension region 130 B and an element isolation insulating film (not shown).
- the silicides 210 A to 210 C for reducing the parasitic resistance are formed on the surface of the gate electrode 80 and on the surfaces of the source region 190 A and drain region 190 B.
- FIGS. 11 and 12 illustrate the current-voltage characteristics of the NMOSFET and PMOSFET forming the CMOSFET.
- the abscissa indicates the gate voltage applied to the gate electrode
- the ordinate indicates the drain current (the driving current flowing through the channel region).
- the gate threshold voltage of the PMOSFET changes by about 0.6 V in the negative direction, but that of the NMOSFET changes only by about 0.2 V in the positive direction, compared to the case in which a silicon oxide (SiO 2 ) film is used as the gate insulating film.
- the driving current flowing through the channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET.
- the offset spacers 100 A and 100 B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50 only in the NMOSFET 220 , and no offset spacers are formed in the PMOSFET 230 , thereby forming the interface insulating film 170 in the interface between the gate electrode 80 and gate insulating film 60 in the PMOSFET 230 .
- Negative fixed electric charge is generated in the interface insulating film 170 .
- the gate threshold voltage of the PMOSFET 230 changes by about 0.16 V in the positive direction ( FIG. 12 ), compared to the case in which no interface insulating film is formed.
- the driving current largely increases, and this improves the drivability of the PMOSFET 230 , compared to the case in which no interface insulating film is formed. Consequently, the difference in drivability between the NMOSFET 220 and PMOSFET 230 can be reduced.
- the semiconductor device and the method of fabricating the same according to the above embodiment can improve the drivability of a PMOSFET in a CMOSFET using a high-k gate insulating film.
- the above embodiment is merely an example and does not limit the present invention.
Abstract
A semiconductor device fabrication method includes forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate; forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; forming a first insulating film; forming a second insulating film; forming a mask having a pattern corresponding to the P-type semiconductor region; etching away the second insulating film by using the mask; removing the mask; and forming a first gate electrode sidewall insulating film and forming a second gate electrode sidewall insulating film.
Description
- This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2005-281537, filed on Sep. 28, 2005, the entire contents of which are incorporated herein by reference.
- The present invention relates to a semiconductor device and a method of fabricating the same.
- Recently, the film thickness of a gate insulating film decreases as downsizing of MOSFETs advances, and this poses the problem that a gate leakage current increases. To suppress this gate leakage current, therefore, it is proposed to use a high-k film having a relative dielectric constant higher than that of a silicon oxide (SiO2) film as a gate insulating film. An example of this high-k film is a hafnium silicate nitride (HfSiON) film.
- When a complementary MOS transistor (to be referred to as a CMOSFET hereinafter) including a PMOSFET and NMOSFET is to be formed, however, if this hafnium silicate nitride (HfSiON) film is used as a gate insulating film, the gate threshold voltage of the PMOSFET fluctuates more than that of the NMOSFET.
- In this case, a driving current flowing through a channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET.
- A reference related to a CMOSFET using a high-k gate insulating film is as follows.
- Japanese Patent Laid-Open No. 2004-289061
- According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:
- forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate;
- forming a first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film;
- forming a mask having a pattern corresponding to the P-type semiconductor region;
- etching away the second insulating film by using the mask;
- removing the mask; and
- forming a first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces of the second gate electrode and the second gate insulating film, thereby forming an interface insulating film in an interface between the second gate electrode and the second gate insulating film.
- According to one aspect of the invention, there is provided a semiconductor device comprising:
- a first gate insulating film formed on a P-type semiconductor region in a surface portion of a semiconductor substrate;
- a first gate electrode formed on said first gate insulating film;
- a first gate electrode sidewall insulating film formed on side surfaces of said first gate electrode and said first gate insulating film via an insulating film;
- an N-channel transistor having a first source region and a first drain region formed on two sides of a first channel region formed in a surface portion of said P-type semiconductor region below said first gate electrode;
- a second gate insulating film formed on an N-type semiconductor region in the surface portion of said semiconductor substrate;
- a second gate electrode formed on said second gate insulating film via an interface insulating film;
- a second gate electrode sidewall insulating film formed on side surfaces of said second gate electrode, said interface insulating film, and said second gate insulating film; and
- a P-channel transistor having a second source region and a second drain region formed on two sides of a second channel region formed in a surface portion of said N-type semiconductor region below said second gate electrode.
-
FIG. 1 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating a CMOSFET according to an embodiment of the present invention; -
FIG. 2 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 3 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 4 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 5 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 6 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 7 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 8 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 9 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 10 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET; -
FIG. 11 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOSFET; and -
FIG. 12 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOS FET. - An embodiment of the present invention will be described below with reference to the accompanying drawings.
-
FIGS. 1 to 10 illustrate a method of fabricating a CMOSFET according to an embodiment of the present invention. First, a resist mask having a desired pattern is formed on asemiconductor substrate 10 by photolithography, and used as a mask to ion-implant boron (B), gallium (G), indium (In), or the like. - Similarly, a resist mask having a desired pattern is formed on the
semiconductor substrate 10, and used as a mask to ion-implant phosphorus (P), arsenic (As), antimony (Sb), or the like. Annealing is then performed to form a P-type semiconductor region 20 and N-type semiconductor region 30 as shown inFIG. 1 . Subsequently, as shown inFIG. 2 , an element isolationinsulating film 40 is formed in a desired region on thesemiconductor substrate 10. - After that, an insulating film made of, e.g., a hafnium silicate nitride (HfSiON) film is formed on the surface of the
semiconductor substrate 10. Note that this insulating film is not limited to the hafnium silicate nitride film. That is, it is possible to use various types of high-k films having relative dielectric constants higher than that of a silicon oxide (SiO2) film. Examples are a hafnium oxide (HfOx) film, a zirconium oxide (ZrOx) film, a silicate film of a hafnium oxide film, an aluminate film of a hafnium oxide film, a silicate film of a zirconium oxide film, an aluminate film of a zirconium oxide film, a silicate nitride film of a hafnium oxide film, an aluminate nitride film of a hafnium oxide film, a silicate nitride film of a zirconium oxide film, and an aluminate nitride film of a zirconium oxide film. - Polysilicon is deposited on this insulating film by CVD or the like to form a polysilicon film. In this case, a polysilicon germanium film may also be formed by depositing polysilicon germanium on the insulating film.
- As shown in
FIG. 3 , the polysilicon film and hafnium silicate nitride (HfSiON) film are sequentially patterned by lithography and RIE, thereby forming agate electrode 70 and gateinsulating film 50 on the P-type semiconductor region 20, and agate electrode 80 andgate insulating film 60 on the N-type semiconductor region 30. - As shown in
FIG. 4 , a silicon nitride (SiN) film 90 about 2 nm thick is formed on the entire surface. As shown inFIG. 5 , the silicon nitride (SiN) film 90 is removed by RIE except for the silicon nitride (SiN) film 90 formed on the side surfaces of thegate electrode 70 and gateinsulating film 50, and on the side surfaces of thegate electrode 80 and gateinsulating film 60. In this manner,offset spacers gate electrode 70 andgate insulating film 50, andoffset spacers gate electrode 80 and gateinsulating film 60. - As shown in
FIG. 6 , an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20, and annealing is so performed as to diffuse this phosphorus (P), thereby forming a shallow-junction, lightly dopedsource extension region 120A anddrain extension region 120B. - Also, a P-type dopant such as boron (B) is ion-implanted into the N-
type semiconductor region 30, and annealing is so performed as to diffuse this boron (B), thereby forming a shallow-junction, lightly dopedsource extension region 130A anddrain extension region 130B. - As shown in
FIG. 7 , thesemiconductor substrate 10,gate electrodes resist mask 140 having a pattern which opens over the N-type semiconductor region 30, thereby covering the P-type semiconductor region 20 with theresist mask 140. - The
resist mask 140 is used as a mask to etch away theoffset spacers type semiconductor region 30. - Note that wet etching using hydrofluoric acid (HF) may also be performed instead of RIE. In this case, the
offset spacers source extension region 130A anddrain extension region 130B may also be formed after the offsetspacers - As shown in
FIG. 8 , after the resist mask 90 is removed, a silicon oxide (SiO2) film made of, e.g., a TEOS (tetraethoxysilane) film is formed on the entire surface of thesemiconductor substrate 10. As shown inFIG. 9 , this silicon oxide (SiO2) film is etched by RIE to form gateelectrode side walls spacers electrode side walls gate electrode 80 andgate insulating film 60. - In this state, the gate
electrode side walls gate electrode 80 andgate insulating film 60 formed on the N-type semiconductor region 30, thereby forming a low-k interface insulating film (interface layer) 170 made of a silicon oxide (SiO2) film about 2 to 3 nm thick in the interface between thegate electrode 80 andgate insulating film 60. - On the other hand, the offset
spacers gate electrode 70 andgate insulating film 50 formed on the P-type semiconductor region 20. Therefore, even when the gateelectrode side walls gate electrode 70 andgate insulating film 50, so almost no interface insulating film forms. - Although a silicon oxide film made of a TEOS film is used as the gate electrode side walls 150 and 160 in this embodiment, it is also possible to use any of various silicon oxide films such as HTO (High Temperature Oxide), BPSG (Borophosphosilicate Glass), PSG (Phosphosilicate Glass), and BSG (Boron-Silicate Glass).
- As shown in
FIG. 10 , an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20, and annealing is so performed as to diffuse this phosphorus (P), thereby forming asource region 180A and drainregion 180B. - Also, a P-type dopant such as boron (B) is ion-implanted into the N-
type semiconductor region 30, and annealing is so performed as to diffuse this boron (B), thereby forming asource region 190A and drainregion 190B. - After a metal film made of, e.g., cobalt (Co), nickel (Ni), or platinum (Pt) is formed by sputtering, annealing is performed to form
silicides 200A to 200C for reducing the parasitic resistance on the surface of thegate electrode 70 and in the surface portions of thesource region 180A and drainregion 180B, and formsilicides 210A to 210C on the surface of thegate electrode 80 and in the surface portions of thesource region 190A and drainregion 190B. - Subsequently, an interlayer dielectric film (not shown) is formed, and a wiring step is performed by forming contact plugs (not shown) in this interlayer dielectric film, thereby forming a
CMOSFET 240 including anNMOSFET 220 andPMOSFET 230. - In the
CMOSFET 240 fabricated by the above method, as shown inFIG. 10 , the elementisolation insulating film 40 is formed in the surface portion of thesemiconductor substrate 10. - Near the central portion of the P-
type semiconductor region 20 isolated by the elementisolation insulating film 40, thegate electrode 70 is formed via thegate insulating film 50 formed on the surface of thesemiconductor substrate 10. - The gate
electrode side walls gate electrode 70 andgate insulating film 50 via the offsetspacers channel region 250 is formed near the surface of the -
semiconductor substrate 10 below thegate electrode 70. Thesource extension region 120A anddrain extension region 120B are formed on the two ends of thechannel region 250. - The
source region 180A is formed between thesource extension region 120A and an element isolation insulating film (not shown). Thedrain region 180B is formed between thedrain extension region 120B and elementisolation insulating film 40. - In addition, the
silicides 200A to 200C for reducing the parasitic resistance are formed on the surface of thegate electrode 70 and on the surfaces of thesource region 180A and drainregion 180B. - On the other hand, the
gate electrode 80 is formed near the central portion of the N-type semiconductor region 30 via thegate insulating film 60 formed on the surface of thesemiconductor substrate 10, and theinterface insulating film 170 made of a silicon oxide (SiO2) film about 2 to 3 nm thick. - The gate
electrode side walls gate electrode 80,interface insulating film 170, andgate insulating film 60. Also, achannel region 260 is formed near the surface of thesemiconductor substrate 10 below thegate electrode 80. - The
source extension region 130A anddrain extension region 130B are formed on the two ends of thechannel region 260. - The
source region 190A is formed between thesource extension region 130A and elementisolation insulating film 40. - The
drain region 190B is formed between thedrain extension region 130B and an element isolation insulating film (not shown). - In addition, the
silicides 210A to 210C for reducing the parasitic resistance are formed on the surface of thegate electrode 80 and on the surfaces of thesource region 190A and drainregion 190B. -
FIGS. 11 and 12 illustrate the current-voltage characteristics of the NMOSFET and PMOSFET forming the CMOSFET. In each ofFIGS. 11 and 12 , the abscissa indicates the gate voltage applied to the gate electrode, and the ordinate indicates the drain current (the driving current flowing through the channel region). - As shown in
FIG. 11 , when a hafnium silicate nitride (HfSiON) film is used as the gate insulating film, the gate threshold voltage of the PMOSFET changes by about 0.6 V in the negative direction, but that of the NMOSFET changes only by about 0.2 V in the positive direction, compared to the case in which a silicon oxide (SiO2) film is used as the gate insulating film. - As described above, the driving current flowing through the channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET.
- In this embodiment, therefore, the offset
spacers gate electrode 70 andgate insulating film 50 only in theNMOSFET 220, and no offset spacers are formed in thePMOSFET 230, thereby forming theinterface insulating film 170 in the interface between thegate electrode 80 andgate insulating film 60 in thePMOSFET 230. - Negative fixed electric charge is generated in the
interface insulating film 170. When theinterface insulating film 170 is formed, therefore, the gate threshold voltage of thePMOSFET 230 changes by about 0.16 V in the positive direction (FIG. 12 ), compared to the case in which no interface insulating film is formed. - As described above, when the
interface insulating film 170 is formed, the driving current largely increases, and this improves the drivability of thePMOSFET 230, compared to the case in which no interface insulating film is formed. Consequently, the difference in drivability between theNMOSFET 220 and PMOSFET 230 can be reduced. - Accordingly, the semiconductor device and the method of fabricating the same according to the above embodiment can improve the drivability of a PMOSFET in a CMOSFET using a high-k gate insulating film.
- Note that the above embodiment is merely an example and does not limit the present invention. For example, it is also possible to form an N-type semiconductor region in the surface portion of a P-type semiconductor substrate, and a P-type semiconductor region in the surface portion of an N-type semiconductor substrate, instead of forming the P-
type semiconductor region 20 and N-type semiconductor region 30 in the surface portion of thesemiconductor substrate 10.
Claims (6)
1.-13. (canceled)
14. A semiconductor device comprising:
a first gate insulating film formed on a P-type semiconductor region in a surface portion of a semiconductor substrate;
a first gate electrode formed on said first gate insulating film;
a first gate electrode sidewall insulating film formed on side surfaces of said first gate electrode and said first gate insulating film via an insulating film;
an N-channel transistor having a first source region and a first drain region formed on two sides of a first channel region formed in a surface portion of said P-type semiconductor region below said first gate electrode;
a second gate insulating film formed on an N-type semiconductor region in the surface portion of said semiconductor substrate;
a second gate electrode formed on said second gate insulating film via an interface insulating film;
a second gate electrode sidewall insulating film formed on side surfaces of said second gate electrode, said interface insulating film, and said second gate insulating film; and
a P-channel transistor having a second source region and a second drain region formed on two sides of a second channel region formed in a surface portion of said N-type semiconductor region below said second gate electrode.
15. A device according to claim 14 , wherein each of said first gate insulating film and said second gate insulating film is made of a material selected from the group consisting of a hafnium oxide film, a zirconium oxide film, a silicate film of a hafnium oxide film, an aluminate film of a hafnium oxide film, a silicate film of a zirconium oxide film, an aluminate film of a zirconium oxide film, a silicate nitride film of a hafnium oxide film, an aluminate nitride film of a hafnium oxide film, a silicate nitride film of a zirconium oxide film, and an aluminate nitride film of a zirconium oxide film.
16. A device according to claim 14 , wherein said interface insulating film is made of a silicon oxide film, and has a film thickness of 2 to 3 nm.
17. A device according to claim 14 , wherein said insulating film is made of a silicon nitride film, and has a film thickness of about 2 nm.
18. A method according to claim 14 , wherein said first gate electrode sidewall insulating film and said second gate electrode sidewall insulating film are made of a same material.
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JP2005-281537 | 2005-09-28 | ||
US11/377,686 US8076193B2 (en) | 2005-09-28 | 2006-03-17 | CMOS device fabrication method with PMOS interface insulating film formed concurrently with sidewall insulating film |
US13/289,111 US20120074504A1 (en) | 2005-09-28 | 2011-11-04 | Semiconductor device and method of fabricating the same |
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US9202906B2 (en) | 2013-03-14 | 2015-12-01 | Northrop Grumman Systems Corporation | Superlattice crenelated gate field effect transistor |
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JP5527080B2 (en) * | 2010-07-22 | 2014-06-18 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US8772118B2 (en) * | 2011-07-08 | 2014-07-08 | Texas Instruments Incorporated | Offset screen for shallow source/drain extension implants, and processes and integrated circuits |
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US6504214B1 (en) * | 2002-01-11 | 2003-01-07 | Advanced Micro Devices, Inc. | MOSFET device having high-K dielectric layer |
US6696327B1 (en) * | 2003-03-18 | 2004-02-24 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US20050067704A1 (en) * | 2003-09-26 | 2005-03-31 | Akio Kaneko | Semiconductor device and method of manufacturing the same |
US7344934B2 (en) * | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
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JPH09205151A (en) * | 1996-01-26 | 1997-08-05 | Sony Corp | Manufacture of complementary semiconductor device |
US6187645B1 (en) | 1999-01-19 | 2001-02-13 | United Microelectronics Corp. | Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation |
JP4524995B2 (en) | 2003-03-25 | 2010-08-18 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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US6504214B1 (en) * | 2002-01-11 | 2003-01-07 | Advanced Micro Devices, Inc. | MOSFET device having high-K dielectric layer |
US6696327B1 (en) * | 2003-03-18 | 2004-02-24 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US20050067704A1 (en) * | 2003-09-26 | 2005-03-31 | Akio Kaneko | Semiconductor device and method of manufacturing the same |
US7344934B2 (en) * | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
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JP2007095887A (en) | 2007-04-12 |
US8076193B2 (en) | 2011-12-13 |
JP5072209B2 (en) | 2012-11-14 |
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