US20120211805A1 - Cavity structures for mems devices - Google Patents
Cavity structures for mems devices Download PDFInfo
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- US20120211805A1 US20120211805A1 US13/032,334 US201113032334A US2012211805A1 US 20120211805 A1 US20120211805 A1 US 20120211805A1 US 201113032334 A US201113032334 A US 201113032334A US 2012211805 A1 US2012211805 A1 US 2012211805A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/008—MEMS characterised by an electronic circuit specially adapted for controlling or driving the same
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0264—Pressure sensors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2203/00—Basic microelectromechanical structures
- B81B2203/03—Static structures
- B81B2203/0315—Cavities
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
- B81B2207/015—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being integrated on the same substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
- B81C1/00158—Diaphragms, membranes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0714—Forming the micromechanical structure with a CMOS process
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0757—Topology for facilitating the monolithic integration
- B81C2203/0771—Stacking the electronic processing unit and the micromechanical structure
Definitions
- the invention relates generally to microelectromechanical systems (MEMS) devices and more particularly to MEMS devices and electrical devices on a single wafer.
- MEMS microelectromechanical systems
- MEMS devices such as sensors
- related electrical devices such as an application-specific integrated circuit (ASIC)
- ASIC application-specific integrated circuit
- MEMS first processes have been developed for integrating MEMS and electrical devices on a single chip. Such processes, however, still present drawbacks and disadvantages, leaving room for improvement.
- Embodiments are directed to monolithic integrated MEMS sensor devices and electrical devices and method related thereto.
- a method comprises forming a microelectromechanical system (MEMS) device on a substrate by forming a sacrificial layer on the substrate, depositing a first silicon layer on the sacrificial layer, the first silicon layer comprising at least one release aperture, forming a cavity in the sacrificial layer via the at least one release aperture, and sealing the cavity by depositing a second silicon layer; and forming an electrical device on the substrate.
- MEMS microelectromechanical system
- a monolithic integrated sensor device comprises a microelectromechanical system (MEMS) sensor formed on a substrate, the MEMS sensor comprising a cavity formed in a sacrificial layer via at least one release aperture and sealed by a silicon layer; and an electrical device formed on the substrate.
- MEMS microelectromechanical system
- a method comprises obtaining a silicon substrate; forming an implanted layer on the silicon substrate; patterning a monocrystalline sacrificial layer on the implanted layer; depositing a first silicon layer on the sacrificial layer, the first silicon layer having at least one release aperture; etching the sacrificial layer through the release aperture to form a cavity; and sealing the cavity by depositing a second silicon layer on the first silicon layer.
- FIGS. 1A-1E depict stages in the fabrication of a capacitive MEMS device integrated with an electrical device according to an embodiment.
- FIGS. 2A-2D depict stages in the fabrication of a capacitive MEMS device integrated with an electrical device according to an embodiment.
- FIG. 3 depicts a piezoresistive MEMS device integrated with an electrical device according to an embodiment.
- FIGS. 4A-4G depict stages in the fabrication of a capacitive MEMS device integrated with an electrical device according to an embodiment.
- FIG. 5 depicts a piezoresistive MEMS device integrated with an electrical device according to an embodiment.
- Embodiments relate to MEMS devices, particularly MEMS devices integrated with related electrical devices on a single wafer.
- Embodiments utilize a modular process flow concept as part of a MEMS-first approach, enabling use of a novel cavity sealing process. The impact and potential detrimental effects on the electrical devices by the MEMS processing are thereby reduced or eliminated.
- a highly flexible solution is provided that enables implementation of a variety of measurement principles, including capacitive and piezoresistive. A variety of sensor applications can therefore be addressed with improved performance and quality while remaining cost-effective.
- FIG. 1 depicts stages in the fabrication of a capacitive MEMS device 100 with a local sacrificial layer, such as oxide.
- FIG. 1A depicts a silicon substrate 102 having an implanted layer 104 .
- substrate 102 is a p-type substrate
- layer 104 is an n-type implanted layer, forming a pn-junction.
- a patterned sacrificial layer 106 is formed on layer 104 .
- sacrificial layer 106 comprises oxide.
- a silicon layer 108 has been deposited, for example by epitaxial growth in an embodiment.
- Silicon layer 108 comprises release apertures 110 through which a cavity 112 is formed by sacrificial layer etching.
- cavity 112 is about 50 nanometers (nm) to about 100 nm high (with respect to the orientation of the drawing on the page).
- An optional cavity passivation layer 114 such as silicon oxide or silicon nitride, is deposited and etched back to assist with later cavity sealing.
- a silicon layer 116 deposited by epitaxial growth seals cavity 112 .
- Optional cavity passivation layer 114 if implemented in embodiments, can help to avoid silicon growth in cavity 112 under certain process conditions.
- the result is a polycrystalline silicon sealed membrane 116 on top of cavity 112 , with remaining sacrificial layer 108 and a monocrystalline silicon 118 on the other areas of the surface of substrate 102 .
- FIG. 1D because of the monocrystalline silicon formed next to membrane structure 116 , electrical devices such as a MOS transistor 120 can be processed in common CMOS or BICMOS processes on the same wafer 102 . Lateral electrical isolation can be achieved by isolation trenches 122 , and electrical contact to top and bottom electrodes can be carried out by contacts structures 124 .
- a common wafer finishing process with intermetal oxide 126 , electrical contacts 128 and metallization 130 can be applied.
- a capacitive sensor device 136 such as a pressure sensor in an embodiment, is formed next to electrical devices, such as transistor 120 , on the same wafer 102 .
- sensor device 136 can comprise another sensor technology, such as a piezoresistive sensor, and transistor 120 can comprise some other electrical device. While FIG. 1 is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices if necessary or desired in specific applications.
- FIG. 2 depicts stages in the fabrication of a capacitive MEMS device 200 with a local monocrystalline sacrificial layer, such as silicon germanium (SiGe) or doped silicon in embodiments.
- a silicon substrate 202 has an implanted layer 204 .
- substrate 202 is a p-type substrate, and layer 204 n-type, such that a vertical pn-junction is formed.
- a monocrystalline sacrificial layer 206 is patterned on layer 104 .
- Sacrificial layer 206 can comprise SiGe or doped silicon with a different dopant type or doping concentration than the silicon material 204 interfacing layer 206 .
- sacrificial layer 206 permits formation of a monocrystalline layer 208 by epitaxial growth next to and on top of sacrificial layer 206 .
- release apertures 210 a portion sacrificial layer 206 is removed to form cavity 212 .
- cavity 212 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page).
- cavity 212 and release apertures 210 are filled with a filling material 214 , such as oxide, for isolation and removed from the wafer surface.
- a filling material 214 such as oxide
- release apertures 216 formed over remaining sacrificial layer 206 a cavity 218 is formed by another sacrificial layer etch.
- An optional cavity passivation layer 220 such a silicon oxide or silicon nitride, is deposited and etched back on the wafer surface to assist with later cavity sealing.
- Cavity passivation layer 220 can help to avoid silicon growth inside cavity 218 under certain process conditions. The result is a monocrystalline silicon sealed membrane 224 on top of cavity 218 and a monocrystalline silicon 226 on other areas of the wafer surface.
- electrical devices like a MOS transistor 228 can be formed on the same wafer 202 in common CMOS or BICMOS processes. Lateral electrical isolation can be provided by isolation trenches 230 , with electrical contact to the bottom and top electrodes of the capacitive sensor device provided by contact structures 232 .
- a common wafer finishing process with intermetal oxide 234 , electrical contacts 236 and metallization 238 can be applied.
- a capacitive sensor device 244 such as a pressure sensor, has been formed with an electrical device, such as transistor 228 , on the same wafer 202 .
- sensor device 244 can comprise another sensor technology and transistor 228 can comprise some other electrical device.
- FIG. 2 like FIG. 1 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices if necessary or desired in specific applications.
- FIG. 3 depicts a piezoresistive MEMS device 300 with a monocrystalline sacrificial layer, such as silicon germanium (SiGe) or doped silicon in embodiments.
- a monocrystalline sacrificial layer need not be patterned because isolation is not needed in this piezoresistive sensing embodiment as it was in the aforementioned capacitive sensing embodiments.
- Device 300 comprises a silicon substrate 302 with an implanted layer 304 .
- substrate 302 is a p-type substrate
- layer 304 is an n-type implanted layer.
- a monocrystalline sacrificial layer 306 is formed on layer 304 .
- Sacrificial layer 306 can comprise, for example, SiGe or doped silicon having a different dopant type and/or concentration than the silicon material at the interface of layers 304 and 306 .
- Monocrystalline sacrificial layer 306 enables formation of a monocrystalline layer 308 on layer 306 by epitaxial growth.
- a cavity 312 can be formed by sacrificial etch, such as is described in DE19700290, which is incorporated herein by reference in its entirety.
- cavity 312 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page).
- An optional cavity passivation layer 314 such as silicon oxide or silicon nitride or some other suitable material, is deposited and etched back on the wafer surface to assist with later cavity sealing.
- Implantation of piezoresistors 318 on monocrystalline membrane 316 provides a piezoresistive sensor device 320 .
- the monocrystalline silicon 316 enables electrical devices such as a MOS transistor 322 to be processed in common CMOS or BICMOS processing concepts on the same wafer 302 .
- a piezoresistive sensor device 334 such as a pressure sensor, has been formed next an electrical device, such as a transistor 322 , on the same wafer 302 .
- sensor device 334 can comprise another sensor technology and transistor 322 can comprise some other electrical device.
- FIG. 3 like FIGS. 1 and 2 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices and/or both capacitive and piezoresistive sensor devices on the same wafer if necessary or desired in specific applications.
- FIG. 4 depicts stages in the fabrication of a capacitive MEMS device 400 formed on a silicon on insulator (SOI) substrate. While SOI can be more expensive than other technologies, it can provide a simplified process flow in embodiments.
- SOI silicon on insulator
- an SOI substrate comprises a silicon substrate 402 , a box oxide layer 404 and a thin silicon device layer 406 .
- layer 406 is about 100 nm to about 400 nm thick.
- a doped layer 408 below box oxide layer 404 is formed by high-energy implantation.
- Layer 408 thus can form a bottom electrode for MEMS devices.
- a monocrystalline silicon layer 410 is formed by epitaxial growth.
- a cavity 412 is formed by sacrificial layer etch through release apertures 414 .
- cavity 412 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page).
- An optional cavity passivation layer 416 such as silicon oxide, silicon nitride or some other suitable material, is deposited and etched back on the wafer surface and can later assist with cavity sealing.
- a silicon layer 418 is deposited by epitaxial growth and seals cavity 412 .
- Cavity passivation layer 416 can help to prevent silicon growth inside cavity 412 under certain process conditions. What results is a monocrystalline silicon sealed membrane 418 on top of cavity 412 with a monocrystalline silicon ( 418 ) also on all other areas of the wafer surface.
- a MOS transistor 420 or another electrical device is formed in common CMOS or BICMOS processing on the same wafer 402 , enabled by the monocrystalline silicon 418 .
- Lateral electrical isolation between the MEMS device and transistor 420 can be accomplished by isolation trenches 422 .
- Electrical contact with the top and bottom electrodes of the sensor device can be established by contact structures 424 .
- a common wafer finishing process with intermetal oxide 426 , electrical contacts 428 and metallization 430 can be applied.
- a capacitive sensor device 436 such as a pressure sensor, is created beside and on the same wafer as electrical devices, such as transistor 420 .
- sensor device 436 can comprise another sensor technology, and transistor 420 can comprise some other electrical device.
- FIG. 4 like FIGS. 1-3 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices on the same wafer if necessary or desired in specific applications.
- FIG. 5 depicts stages a piezoresistive MEMS device 500 formed on a SOI substrate. While SOI can be more expensive than other technologies, it can provide a simplified process flow in embodiments.
- An SOI substrate 502 has a box oxide layer 504 and a silicon device layer 506 formed thereon. In embodiments, layer 506 is about 100 nm to about 400 nm thick.
- a monocrystalline silicon layer 508 is formed on layer 504 by epitaxial growth. Through release apertures 510 , a cavity 512 is formed by sacrificial layer etch. In embodiments, cavity 512 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page).
- An optional cavity passivation layer 514 such as silicon oxide, silicon nitride or some other suitable material, is deposited and etched back on the wafer surface to assist with later cavity sealing.
- a silicon layer 516 is then deposited by epitaxial growth, sealing cavity 512 .
- Cavity passivation layer 514 can help to avoid silicon growth inside cavity 512 under certain process conditions. The result is thus a monocrystalline silicon sealed membrane 516 on cavity 512 , with monocrystalline silicon on all other areas of the wafer surface.
- Implantation of piezoresistors 518 on the monocrystalline membrane 516 forms a piezoresistive sensor device 520 .
- Monocrystalline layer 516 enables electrical devices, such as a MOS transistor 522 , to be processed in common CMOS or BICMOS on the same wafer 502 .
- a piezoresistive sensor device 520 such as a pressure sensor, is formed next to an electrical device, such as transistor 522 or some other device, on the same wafer 502 .
- sensor device 520 can comprise another sensor technology
- transistor 522 can comprise some other electrical device.
- FIG. 5 like FIGS. 1-4 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices and/or both capacitive and piezoresistive sensor devices on the same wafer if necessary or desired in specific applications.
- Embodiments thereby provide cost-efficient, flexible solutions for monolithic integration of MEMS structures in modern CMOS and BICMOS technologies. Negative interactions between MEMS and electrical processing steps are avoided, at least in part by utilizing a novel cavity sealing process.
- the smaller dimensions of the cavity that can be implemented in embodiments also improve the robustness of the device, reducing the risk of over-stress.
- advantages in test stages of manufacturing can also be provided in embodiments by enabling use of an applied voltage rather than a physical pressure or acceleration load, thereby reducing test complexity and efforts. This is enabled at least in part by the narrower cavity. High flexibility for a variety of sensing principles, such as capacitive and piezoresistive, is provided based on the same MEMS technology platform.
Abstract
Embodiments relate to MEMS devices, particularly MEMS devices integrated with related electrical devices on a single wafer. Embodiments utilize a modular process flow concept as part of a MEMS-first approach, enabling use of a novel cavity sealing process. The impact and potential detrimental effects on the electrical devices by the MEMS processing are thereby reduced or eliminated. At the same time, a highly flexible solution is provided that enables implementation of a variety of measurement principles, including capacitive and piezoresistive. A variety of sensor applications can therefore be addressed with improved performance and quality while remaining cost-effective.
Description
- The invention relates generally to microelectromechanical systems (MEMS) devices and more particularly to MEMS devices and electrical devices on a single wafer.
- MEMS devices, such as sensors, and related electrical devices, such as an application-specific integrated circuit (ASIC), are typically implemented on separate chips because the fabrication processes for each are incompatible with the other. For example, in modern CMOS technologies it can be critical to avoid high temperatures in order to preserve doping profiles, whereas high temperature steps may be necessary in steps of the electrical device fabrication. There are many disadvantages associated with two-chip solutions, including more complex and expensive packaging and the inability to implement applications requiring processing of very small signals.
- More recently, so-called “MEMS first” processes have been developed for integrating MEMS and electrical devices on a single chip. Such processes, however, still present drawbacks and disadvantages, leaving room for improvement.
- Therefore, there is a need for improved systems and methods that enable MEMS and electrical devices to be implemented on a single wafer.
- Embodiments are directed to monolithic integrated MEMS sensor devices and electrical devices and method related thereto.
- In an embodiment, a method comprises forming a microelectromechanical system (MEMS) device on a substrate by forming a sacrificial layer on the substrate, depositing a first silicon layer on the sacrificial layer, the first silicon layer comprising at least one release aperture, forming a cavity in the sacrificial layer via the at least one release aperture, and sealing the cavity by depositing a second silicon layer; and forming an electrical device on the substrate.
- In an embodiment, a monolithic integrated sensor device comprises a microelectromechanical system (MEMS) sensor formed on a substrate, the MEMS sensor comprising a cavity formed in a sacrificial layer via at least one release aperture and sealed by a silicon layer; and an electrical device formed on the substrate.
- In an embodiment, a method comprises obtaining a silicon substrate; forming an implanted layer on the silicon substrate; patterning a monocrystalline sacrificial layer on the implanted layer; depositing a first silicon layer on the sacrificial layer, the first silicon layer having at least one release aperture; etching the sacrificial layer through the release aperture to form a cavity; and sealing the cavity by depositing a second silicon layer on the first silicon layer.
- The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
-
FIGS. 1A-1E depict stages in the fabrication of a capacitive MEMS device integrated with an electrical device according to an embodiment. -
FIGS. 2A-2D depict stages in the fabrication of a capacitive MEMS device integrated with an electrical device according to an embodiment. -
FIG. 3 depicts a piezoresistive MEMS device integrated with an electrical device according to an embodiment. -
FIGS. 4A-4G depict stages in the fabrication of a capacitive MEMS device integrated with an electrical device according to an embodiment. -
FIG. 5 depicts a piezoresistive MEMS device integrated with an electrical device according to an embodiment. - While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- Embodiments relate to MEMS devices, particularly MEMS devices integrated with related electrical devices on a single wafer. Embodiments utilize a modular process flow concept as part of a MEMS-first approach, enabling use of a novel cavity sealing process. The impact and potential detrimental effects on the electrical devices by the MEMS processing are thereby reduced or eliminated. At the same time, a highly flexible solution is provided that enables implementation of a variety of measurement principles, including capacitive and piezoresistive. A variety of sensor applications can therefore be addressed with improved performance and quality while remaining cost-effective.
-
FIG. 1 depicts stages in the fabrication of acapacitive MEMS device 100 with a local sacrificial layer, such as oxide.FIG. 1A depicts asilicon substrate 102 having an implantedlayer 104. In one embodiment,substrate 102 is a p-type substrate, andlayer 104 is an n-type implanted layer, forming a pn-junction. A patternedsacrificial layer 106 is formed onlayer 104. In one embodiment,sacrificial layer 106 comprises oxide. - In
FIG. 1B , asilicon layer 108 has been deposited, for example by epitaxial growth in an embodiment.Silicon layer 108 comprisesrelease apertures 110 through which acavity 112 is formed by sacrificial layer etching. In embodiments,cavity 112 is about 50 nanometers (nm) to about 100 nm high (with respect to the orientation of the drawing on the page). An optionalcavity passivation layer 114, such as silicon oxide or silicon nitride, is deposited and etched back to assist with later cavity sealing. - In
FIG. 1C , asilicon layer 116 deposited by epitaxialgrowth seals cavity 112. Optionalcavity passivation layer 114, if implemented in embodiments, can help to avoid silicon growth incavity 112 under certain process conditions. As depicted inFIG. 1C , the result is a polycrystalline silicon sealedmembrane 116 on top ofcavity 112, with remainingsacrificial layer 108 and amonocrystalline silicon 118 on the other areas of the surface ofsubstrate 102. - In
FIG. 1D , because of the monocrystalline silicon formed next tomembrane structure 116, electrical devices such as aMOS transistor 120 can be processed in common CMOS or BICMOS processes on thesame wafer 102. Lateral electrical isolation can be achieved byisolation trenches 122, and electrical contact to top and bottom electrodes can be carried out bycontacts structures 124. - In
FIG. 1E , a common wafer finishing process withintermetal oxide 126,electrical contacts 128 andmetallization 130 can be applied. After sensor release at 132 andpassivation 134, acapacitive sensor device 136, such as a pressure sensor in an embodiment, is formed next to electrical devices, such astransistor 120, on thesame wafer 102. In other embodiments,sensor device 136 can comprise another sensor technology, such as a piezoresistive sensor, andtransistor 120 can comprise some other electrical device. WhileFIG. 1 is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices if necessary or desired in specific applications. -
FIG. 2 depicts stages in the fabrication of acapacitive MEMS device 200 with a local monocrystalline sacrificial layer, such as silicon germanium (SiGe) or doped silicon in embodiments. InFIG. 2A , asilicon substrate 202 has an implantedlayer 204. In an embodiment,substrate 202 is a p-type substrate, and layer 204 n-type, such that a vertical pn-junction is formed. A monocrystallinesacrificial layer 206 is patterned onlayer 104.Sacrificial layer 206 can comprise SiGe or doped silicon with a different dopant type or doping concentration than thesilicon material 204interfacing layer 206. - Referring to
FIG. 2B , the monocrystalline nature ofsacrificial layer 206 permits formation of amonocrystalline layer 208 by epitaxial growth next to and on top ofsacrificial layer 206. Throughrelease apertures 210, a portionsacrificial layer 206 is removed to formcavity 212. Embodiments of this process sequence are discussed in DE 19700290, which is incorporated herein by reference in its entirety. In embodiments,cavity 212 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page). - Referring to
FIG. 2C ,cavity 212 and releaseapertures 210 are filled with a fillingmaterial 214, such as oxide, for isolation and removed from the wafer surface. Throughrelease apertures 216 formed over remainingsacrificial layer 206, acavity 218 is formed by another sacrificial layer etch. An optionalcavity passivation layer 220, such a silicon oxide or silicon nitride, is deposited and etched back on the wafer surface to assist with later cavity sealing. - Referring to
FIG. 2D , a silicon layer 222 deposted by epitaxial growth sealscavity 218.Cavity passivation layer 220 can help to avoid silicon growth insidecavity 218 under certain process conditions. The result is a monocrystalline silicon sealedmembrane 224 on top ofcavity 218 and amonocrystalline silicon 226 on other areas of the wafer surface. - Because of the
monocrystalline silicon 226, electrical devices like aMOS transistor 228 can be formed on thesame wafer 202 in common CMOS or BICMOS processes. Lateral electrical isolation can be provided byisolation trenches 230, with electrical contact to the bottom and top electrodes of the capacitive sensor device provided bycontact structures 232. - A common wafer finishing process with
intermetal oxide 234,electrical contacts 236 andmetallization 238 can be applied. Aftersensor release 240 andpassivation 242, acapacitive sensor device 244, such as a pressure sensor, has been formed with an electrical device, such astransistor 228, on thesame wafer 202. In other embodiments,sensor device 244 can comprise another sensor technology andtransistor 228 can comprise some other electrical device. WhileFIG. 2 , likeFIG. 1 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices if necessary or desired in specific applications. -
FIG. 3 depicts apiezoresistive MEMS device 300 with a monocrystalline sacrificial layer, such as silicon germanium (SiGe) or doped silicon in embodiments. In the embodiment ofFIG. 3 , in contrast with those ofFIGS. 1 and 2 , a monocrystalline sacrificial layer need not be patterned because isolation is not needed in this piezoresistive sensing embodiment as it was in the aforementioned capacitive sensing embodiments. -
Device 300 comprises asilicon substrate 302 with an implantedlayer 304. In an embodiment,substrate 302 is a p-type substrate, andlayer 304 is an n-type implanted layer. A monocrystallinesacrificial layer 306 is formed onlayer 304.Sacrificial layer 306 can comprise, for example, SiGe or doped silicon having a different dopant type and/or concentration than the silicon material at the interface oflayers - Monocrystalline
sacrificial layer 306 enables formation of amonocrystalline layer 308 onlayer 306 by epitaxial growth. Throughrelease apertures 310, acavity 312 can be formed by sacrificial etch, such as is described in DE19700290, which is incorporated herein by reference in its entirety. In embodiments,cavity 312 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page). An optionalcavity passivation layer 314, such as silicon oxide or silicon nitride or some other suitable material, is deposited and etched back on the wafer surface to assist with later cavity sealing. Asilicon layer 316 deposited by epitaxial growth sealscavity 312, withcavity passivation layer 314, if present, assisting to avoid silicon growth insidecavity 312 under certain process conditions. The result thus far is a monocrystalline silicon sealedmembrane 316 on top of acavity 312, with the monocrystalline silicon also on all other areas of the wafer surface. Implantation ofpiezoresistors 318 onmonocrystalline membrane 316 provides apiezoresistive sensor device 320. - The
monocrystalline silicon 316 enables electrical devices such as aMOS transistor 322 to be processed in common CMOS or BICMOS processing concepts on thesame wafer 302. A common wafer finishing process withintermetal oxide 324,electrical contacts 326 andmetallization 328 can be applied. Aftersensor release 330 andpassivation 332, apiezoresistive sensor device 334, such as a pressure sensor, has been formed next an electrical device, such as atransistor 322, on thesame wafer 302. In other embodiments,sensor device 334 can comprise another sensor technology andtransistor 322 can comprise some other electrical device. WhileFIG. 3 , likeFIGS. 1 and 2 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices and/or both capacitive and piezoresistive sensor devices on the same wafer if necessary or desired in specific applications. -
FIG. 4 depicts stages in the fabrication of acapacitive MEMS device 400 formed on a silicon on insulator (SOI) substrate. While SOI can be more expensive than other technologies, it can provide a simplified process flow in embodiments. - Referring to
FIG. 4A , an SOI substrate comprises asilicon substrate 402, abox oxide layer 404 and a thinsilicon device layer 406. In embodiments,layer 406 is about 100 nm to about 400 nm thick. - In
FIG. 4B , adoped layer 408 belowbox oxide layer 404 is formed by high-energy implantation.Layer 408 thus can form a bottom electrode for MEMS devices. - In
FIG. 4C , amonocrystalline silicon layer 410 is formed by epitaxial growth. - In
FIG. 4D , acavity 412 is formed by sacrificial layer etch throughrelease apertures 414. In embodiments,cavity 412 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page). An optionalcavity passivation layer 416, such as silicon oxide, silicon nitride or some other suitable material, is deposited and etched back on the wafer surface and can later assist with cavity sealing. - In
FIG. 4E , asilicon layer 418 is deposited by epitaxial growth and sealscavity 412.Cavity passivation layer 416 can help to prevent silicon growth insidecavity 412 under certain process conditions. What results is a monocrystalline silicon sealedmembrane 418 on top ofcavity 412 with a monocrystalline silicon (418) also on all other areas of the wafer surface. - In
FIG. 4F , aMOS transistor 420 or another electrical device is formed in common CMOS or BICMOS processing on thesame wafer 402, enabled by themonocrystalline silicon 418. Lateral electrical isolation between the MEMS device andtransistor 420 can be accomplished byisolation trenches 422. Electrical contact with the top and bottom electrodes of the sensor device can be established bycontact structures 424. - In
FIG. 4G , a common wafer finishing process withintermetal oxide 426,electrical contacts 428 andmetallization 430 can be applied. Aftersensor release 432 andpassivation 434, acapacitive sensor device 436, such as a pressure sensor, is created beside and on the same wafer as electrical devices, such astransistor 420. In other embodiments,sensor device 436 can comprise another sensor technology, andtransistor 420 can comprise some other electrical device. WhileFIG. 4 , likeFIGS. 1-3 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices on the same wafer if necessary or desired in specific applications. -
FIG. 5 depicts stages apiezoresistive MEMS device 500 formed on a SOI substrate. While SOI can be more expensive than other technologies, it can provide a simplified process flow in embodiments. AnSOI substrate 502 has abox oxide layer 504 and asilicon device layer 506 formed thereon. In embodiments,layer 506 is about 100 nm to about 400 nm thick. Amonocrystalline silicon layer 508 is formed onlayer 504 by epitaxial growth. Throughrelease apertures 510, acavity 512 is formed by sacrificial layer etch. In embodiments,cavity 512 is about 50 nm to about 100 nm high (with respect to the orientation of the drawing on the page). An optionalcavity passivation layer 514, such as silicon oxide, silicon nitride or some other suitable material, is deposited and etched back on the wafer surface to assist with later cavity sealing. - A
silicon layer 516 is then deposited by epitaxial growth, sealingcavity 512.Cavity passivation layer 514 can help to avoid silicon growth insidecavity 512 under certain process conditions. The result is thus a monocrystalline silicon sealedmembrane 516 oncavity 512, with monocrystalline silicon on all other areas of the wafer surface. - Implantation of
piezoresistors 518 on themonocrystalline membrane 516 forms apiezoresistive sensor device 520. -
Monocrystalline layer 516 enables electrical devices, such as aMOS transistor 522, to be processed in common CMOS or BICMOS on thesame wafer 502. A common wafer finishing process withintermetal oxide 524,electrical contacts 526 andmetallization 528 can be applied. Aftersensor release 530 andpassivation 532, apiezoresistive sensor device 520, such as a pressure sensor, is formed next to an electrical device, such astransistor 522 or some other device, on thesame wafer 502. In other embodiments,sensor device 520 can comprise another sensor technology, andtransistor 522 can comprise some other electrical device. WhileFIG. 5 , likeFIGS. 1-4 , is an example for monolithic integrated sensor technology, the concept also has the flexibility to create a discrete sensor device without electrical devices and/or both capacitive and piezoresistive sensor devices on the same wafer if necessary or desired in specific applications. - Embodiments thereby provide cost-efficient, flexible solutions for monolithic integration of MEMS structures in modern CMOS and BICMOS technologies. Negative interactions between MEMS and electrical processing steps are avoided, at least in part by utilizing a novel cavity sealing process. The smaller dimensions of the cavity that can be implemented in embodiments also improve the robustness of the device, reducing the risk of over-stress. Further, advantages in test stages of manufacturing can also be provided in embodiments by enabling use of an applied voltage rather than a physical pressure or acceleration load, thereby reducing test complexity and efforts. This is enabled at least in part by the narrower cavity. High flexibility for a variety of sensing principles, such as capacitive and piezoresistive, is provided based on the same MEMS technology platform.
- Various embodiments of systems, devices and methods have been described herein. These embodiments are given only by way of example and are not intended to limit the scope of the invention. It should be appreciated, moreover, that the various features of the embodiments that have been described may be combined in various ways to produce numerous additional embodiments. Moreover, while various materials, dimensions, shapes, configurations and locations, etc. have been described for use with disclosed embodiments, others besides those disclosed may be utilized without exceeding the scope of the invention.
- Persons of ordinary skill in the relevant arts will recognize that the invention may comprise fewer features than illustrated in any individual embodiment described above. The embodiments described herein are not meant to be an exhaustive presentation of the ways in which the various features of the invention may be combined. Accordingly, the embodiments are not mutually exclusive combinations of features; rather, the invention may comprise a combination of different individual features selected from different individual embodiments, as understood by persons of ordinary skill in the art.
- Any incorporation by reference of documents above is limited such that no subject matter is incorporated that is contrary to the explicit disclosure herein. Any incorporation by reference of documents above is further limited such that no claims included in the documents are incorporated by reference herein. Any incorporation by reference of documents above is yet further limited such that any definitions provided in the documents are not incorporated by reference herein unless expressly included herein.
- For purposes of interpreting the claims for the present invention, it is expressly intended that the provisions of
Section 112, sixth paragraph of 35 U.S.C. are not to be invoked unless the specific terms “means for” or “step for” are recited in a claim.
Claims (25)
1. A method comprising:
forming a microelectromechanical system (MEMS) device on a substrate by:
forming a sacrificial layer on the substrate,
depositing a first silicon layer on the sacrificial layer, the first silicon layer comprising at least one release aperture,
forming a cavity in the sacrificial layer via the at least one release aperture, and
sealing the cavity by depositing a second silicon layer; and
forming an electrical device on the substrate.
2. The method of claim 1 , further comprising depositing a cavity passivation layer in the cavity.
3. The method of claim 1 , wherein forming the sacrificial layer comprises patterning the sacrificial layer.
4. The method of claim 1 , wherein forming the sacrificial layer comprises forming a monocrystalline sacrificial layer.
5. The method of claim 1 , wherein forming the electrical device further comprises utilizing the monocrystalline sacrificial layer.
6. The method of claim 1 , wherein sealing the cavity further comprises depositing a second silicon layer comprises monocrystalline silicon.
7. The method of claim 1 , wherein forming a MEMS device comprises forming a sensor device.
8. The method of claim 7 , wherein forming a sensor device comprises forming at least one of a capacitive sensor device or a piezoresistive sensor device.
9. The method of claim 1 , wherein forming an electrical device comprises forming at least one transistor.
10. The method of claim 1 , wherein forming an electrical device comprises utilizing one of a CMOS or BICMOS process.
11. The method of claim 1 , wherein forming a MEMS device further comprises filling a portion of the cavity via at least one release aperture.
12. The method of claim 1 , further comprising forming an isolation trench between the MEMS device and the electrical device.
13. A monolithic integrated sensor device comprising:
a microelectromechanical system (MEMS) sensor formed on a substrate, the MEMS sensor comprising a cavity formed in a sacrificial layer via at least one release aperture and sealed by a silicon layer; and
an electrical device formed on the substrate.
14. The device of claim 13 , wherein the silicon layer comprises a monocrystalline silicon layer.
15. The device of claim 14 , wherein the monocrystalline silicon layer forms a part of the electrical device.
16. The device of claim 13 , further comprising an isolation trench formed between the MEMS sensor and the electrical device.
17. The device of claim 13 , wherein the MEMS sensor is one of a capacitive sensor or a piezoresistive sensor.
18. The device of claim 13 , wherein the electrical device comprises a transistor.
19. The device of claim 13 , further comprising a cavity passivation layer inside the cavity.
20. The device of claim 13 , wherein the silicon layer comprises a membrane.
21. A method comprising:
obtaining a silicon substrate;
forming an implanted layer on the silicon substrate;
patterning a monocrystalline sacrificial layer on the implanted layer;
depositing a first silicon layer on the sacrificial layer, the first silicon layer having at least one release aperture;
etching the sacrificial layer through the release aperture to form a cavity; and
sealing the cavity by depositing a second silicon layer on the first silicon layer.
22. The method of claim 21 , further comprising forming a microelectromechanical system (MEMS) sensor by carrying out the obtaining, forming, patterning, depositing, etching and sealing.
23. The method of claim 22 , further comprising forming a monolithic integrated sensor device by forming an electrical device on the substrate.
24. The method of claim 23 , wherein forming an electrical device further comprises utilizing the second silicon layer.
25. The method of claim 23 , wherein forming a MEMS sensor further comprises forming at least one of a capacitive MEMS sensor or a piezoresistive MEMS sensor, and wherein forming an electrical device further comprises forming a transistor.
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2012
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- 2012-02-21 DE DE102012202643.6A patent/DE102012202643B4/en not_active Expired - Fee Related
- 2012-02-21 DE DE102012025750.3A patent/DE102012025750A1/en not_active Ceased
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2014
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US20150059484A1 (en) * | 2013-01-29 | 2015-03-05 | Chad S Dawson | Microelectromechanical system devices having crack resistant membrane structures and methods for the fabrication thereof |
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US10118820B2 (en) | 2014-07-25 | 2018-11-06 | Semiconductor Manufacturing International (Shanghai) Corporation | Membrane transducer structures and methods of manufacturing same using thin-film encapsulation |
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US10556791B2 (en) * | 2016-07-19 | 2020-02-11 | King Abdulaziz City For Science And Technology | CMOS compatible capacitive absolute pressure sensors |
US20180022600A1 (en) * | 2016-07-19 | 2018-01-25 | Tariq Salim Alsaiary | Cmos compatible capacitive absolute pressure sensors |
US20180346322A1 (en) * | 2017-05-30 | 2018-12-06 | Rohm Co., Ltd. | Mems-device manufacturing method, mems device, and mems module |
US10597288B2 (en) * | 2017-05-30 | 2020-03-24 | Rohm Co., Ltd. | MEMS-device manufacturing method, MEMS device, and MEMS module |
US10903316B2 (en) | 2017-07-10 | 2021-01-26 | Globalfoundries Inc. | Radio frequency switches with air gap structures |
US10833153B2 (en) | 2017-09-13 | 2020-11-10 | Globalfoundries Inc. | Switch with local silicon on insulator (SOI) and deep trench isolation |
US11107884B2 (en) | 2018-01-22 | 2021-08-31 | Globalfoundries U.S. Inc. | Sealed cavity structures with a planar surface |
US11410872B2 (en) | 2018-11-30 | 2022-08-09 | Globalfoundries U.S. Inc. | Oxidized cavity structures within and under semiconductor devices |
US20200219760A1 (en) * | 2019-01-07 | 2020-07-09 | Globalfoundries Inc. | Cavity structures under shallow trench isolation regions |
US10923577B2 (en) * | 2019-01-07 | 2021-02-16 | Globalfoundries U.S. Inc. | Cavity structures under shallow trench isolation regions |
CN110707115A (en) * | 2019-10-14 | 2020-01-17 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof, and artificial intelligence chip and forming method thereof |
US11127816B2 (en) | 2020-02-14 | 2021-09-21 | Globalfoundries U.S. Inc. | Heterojunction bipolar transistors with one or more sealed airgap |
Also Published As
Publication number | Publication date |
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US9145292B2 (en) | 2015-09-29 |
CN102674237A (en) | 2012-09-19 |
CN102674237B (en) | 2015-12-02 |
US20140252422A1 (en) | 2014-09-11 |
DE102012202643B4 (en) | 2015-07-23 |
US20150353344A1 (en) | 2015-12-10 |
DE102012202643A1 (en) | 2012-09-13 |
DE102012025750A1 (en) | 2015-09-03 |
US9598277B2 (en) | 2017-03-21 |
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