US20120217043A1 - Method of manufacturing a printed circuit board - Google Patents
Method of manufacturing a printed circuit board Download PDFInfo
- Publication number
- US20120217043A1 US20120217043A1 US13/466,784 US201213466784A US2012217043A1 US 20120217043 A1 US20120217043 A1 US 20120217043A1 US 201213466784 A US201213466784 A US 201213466784A US 2012217043 A1 US2012217043 A1 US 2012217043A1
- Authority
- US
- United States
- Prior art keywords
- insulation layer
- layer
- printed circuit
- circuit board
- dry film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 238000009413 insulation Methods 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000000945 filler Substances 0.000 claims description 12
- 238000011049 filling Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 32
- 239000011810 insulating material Substances 0.000 description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 239000000758 substrate Substances 0.000 description 12
- 238000009713 electroplating Methods 0.000 description 7
- 239000010949 copper Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 239000012774 insulation material Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003513 alkali Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical class [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229940043430 calcium compound Drugs 0.000 description 1
- 150000001674 calcium compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002681 magnesium compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 150000003112 potassium compounds Chemical class 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0582—Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a printed circuit board having a buried pattern and a method of manufacturing the same.
- a printed circuit board serves to electrically connect electronic parts to each other, supply power and mechanically fix them thereon through a wire pattern formed on an insulation substrate made of a phenol resin, an epoxy resin or the like.
- a printed circuit board includes a one-sided printed circuit board, in which a wiring pattern is formed on only one side of an insulation substrate, a double-sided printed circuit board, in which wiring patterns are formed on both sides of an insulation substrate, and a multi-layered printed circuit board (MLB), in which wiring patterns are provided in multiple layers.
- an additive process As a method of forming a wiring pattern on a printed circuit board, an additive process, a subtractive process, a semi additive process (SAP), a modified semi additive process (MSAP) or the like is used.
- SAP semi additive process
- MSAP modified semi additive process
- FIG. 1 shows a conventional process of forming a wiring pattern using MSAP or SAP.
- a seed layer 3 is formed on an insulation substrate 1 , and then a plating resist layer 5 is formed on the seed layer 3 . Thereafter, an electroplating layer is formed on the seed layer 3 through an electroplating process. Subsequently, as shown in FIG. 1B , the plating resist layer 5 is removed from the seed layer 3 , and then, as shown in FIG. 1C , the exposed portion of the seed layer 3 is removed from the insulation substrate 1 through flash etching or quick etching to form a wiring pattern 7 .
- the electroplating layer for forming the wiring pattern is also etched, so that the lateral face of the wiring pattern 7 is greatly tapered and the width of the wiring pattern 7 is decreased, with the result that the wiring pattern 7 is short-circuited and the signal transfer characteristics of the wiring pattern 7 are weakened.
- the present invention has been made keeping in mind the above problems occurring in the prior art, and the present invention provides a printed circuit board in which a circuit pattern is buried in an insulation layer and thus an undercut phenomenon does not occur and which can realize various fine circuit patterns, and a method of manufacturing the same.
- An aspect of the present invention provides a method of manufacturing a printed circuit board having a buried pattern, including: forming a second insulation layer on a first insulation layer, the second insulation layer having openings for forming a circuit layer; and filling the openings with a conductive metal to form a circuit layer.
- the forming of the second insulation layer may include: applying a dry film on the first insulation layer; forming grooves on the dry film such that the dry film has the same pattern as the circuit layer; filling the grooves with a second insulation material; and removing the dry film.
- the first insulation layer may have higher filler content than the second insulation layer.
- the method may further include: forming a via hole passing through the first insulation layer and the second insulation layer after the forming of the second insulation layer, wherein, in the filling of the openings, the via hole as well as the openings is filled with a conductive metal.
- the dry film may be a photosensitive dry film.
- the method may further include: removing the second insulation material applied on the dry film such that an upper surface of the dry film is exposed, after the filling the grooves with the second insulation material.
- the removing of the second insulation material may be conducted by a chemical etching process or a mechanical grinding process.
- a printed circuit board having a buried pattern including: a first insulation layer; a second insulation layer which is formed on the first insulation layer and has openings for forming a circuit layer; and a circuit layer charged in the openings and made of a conductive metal, wherein an interface is formed between the first insulation layer and the second insulation layer.
- the first insulation layer may have higher filler content than the second insulation layer.
- the printed circuit board may further include: a via made of a conductive metal passing through the first insulation layer and the second insulation layer.
- FIG. 1A to 1C are sectional views showing a convention method of manufacturing a printed circuit board.
- FIGS. 2 to 8 are sectional views showing a method of manufacturing a printed circuit board having a buried pattern according to an embodiment of the present invention.
- FIGS. 2 to 8 are sectional views showing a method of manufacturing a printed circuit board having a buried pattern according to an embodiment of the present invention.
- a double-side copper clad laminate which is used as a core, is provided.
- the double-side copper clad laminate includes an insulation substrate 100 , and copper foils 110 applied on both sides of the insulation substrate 100 .
- a first insulation layer 300 is formed on each of the copper foils 110 by applying a first insulating material on each of the copper foils 110 .
- the first insulation layer is made of a polymer material, which is an electric insulator, for example, prepreg including an epoxy resin.
- the double-sided copper clad laminate is used as a core substrate, but the present invention is not limited thereto.
- One-sided, double-sided or multi-layered printed circuit board having a wiring pattern made of conductive metals may be used as a core substrate, and the first insulation layer 300 itself may also be used as a core substrate.
- a dry film 400 having the same pattern as a circuit layer 900 is formed on the first insulation layer 300 .
- the dry film 400 may be a photosensitive dry film.
- the photosensitive dry film is a material which can be patterned by selectively curing it using a mask having light shielding patterns.
- the dry film 400 formed on the first insulation layer 300 is exposed and developed using a light shielding mask such that the dry film 400 has the same pattern as the circuit layer 900 , thereby forming grooves 410 in the dry film 400 .
- the thickness of the dry film be thin in order to manufacture a high-density thin printed circuit board.
- a second insulating layer 500 is formed on the first insulating layer 300 by filling the grooves 410 formed in the dry film 400 with a second insulating material.
- the second insulating material may be the same as the first insulating material, but it is preferred that the second insulating material have lower filler content than the first insulating material in order to easily fill the groove 410 with the second insulating material. Further, it is preferred that the average particle size of the filler included in the second insulating material be smaller than that of the filler included in the first insulating material in order to easily fill the groove 410 with the second insulating material.
- the filler is a material added to an insulating material in order to impart rigidity or thermal conductivity thereto. Examples of the filler may include aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, silicon compounds, and the like.
- the second insulation layer 500 is sequentially formed after the formation of the first insulation layer 300 , an interface which can be distinguished by surface roughness is formed between the first insulation layer 300 and the second insulation layer 500 .
- the second insulating material when the second insulating material is charged in the grooves 410 formed in the dry film 400 , the upper surface of the dry film 400 may be covered with the second insulating material. In this case, in order to easily remove the dry film 400 in subsequent processes, the second insulating material applied on the upper surface of the dry film 400 must be removed.
- the removal of the second insulating material applied on the upper surface of the dry film 400 may be conducted by partially removing the second insulating material in its thickness direction through a dry etching process using plasma or a wet etching process (chemical etching process) using organic alkali or aqueous alkali solution supplied from etchant supply units 610 .
- the second insulating material applied on the upper surface of the dry film 400 may be removed through a mechanical grinding process using a buff grinder 630 .
- the second insulating material applied on the upper surface of the dry film 400 may be removed using a belt sander or a grinding brush.
- the dry film 400 applied on the first insulation layer 300 is removed using a stripper, and thus the second insulation layer 500 having openings 510 for forming a circuit layer 900 is formed on the first insulation layer 300
- a via hole 700 passing through the first insulation layer 300 and second insulation layer 500 is formed.
- the via hole 700 is formed by etching the first insulation layer 300 through the opening 510 of the second insulation layer 500 , and thus the copper foil 110 applied on the insulation substrate 100 is exposed through the via hole 700 .
- the formation of the via hole 700 may be conducted using a YAG laser drill or a CO 2 laser drill.
- a circuit layer 900 is formed by charging a conductive metal in the via hole 700 and openings 510 .
- an electroless seed layer is formed on the first insulation layer 300 and second insulation layer 500 , and then an electroplating layer is formed on the second insulation layer 500 by performing an electroplating process using the electroless seed layer as an incoming line.
- the electroless seed layer and electroplating layer may be made of a conductive metal, such as gold (Au), silver (Al), copper (Cu), nickel (Ni) or the like.
- the electroless seed layer and electroplating layer formed on the second insulation layer 500 are removed using a buffer grinder 630 , a grinding brush or a belt sander, thereby completing the circuit layer 900 including a circuit pattern 910 and a via 930 .
- the above-mentioned method of manufacturing a printed circuit board having a buried pattern according to an embodiment of the present invention is advantageous in that, since the openings 510 for forming the circuit pattern 910 is formed in the second insulating layer 500 using the dry film 400 , the width and depth of the openings are constant compared to compared to a conventional laser trenching method, and a circuit pattern having uniform height can be formed.
- the above-mentioned method is advantageous in that the method is simple compared to a conventional imprinting method or laser trenching method for forming buried patterns, and thus process costs can be reduced.
- the printed circuit board having a buried pattern includes a first insulation layer 300 , a second insulation layer 500 which is formed on the first insulation layer 300 and has openings 510 for forming a circuit layer 900 , and a circuit layer 900 made of a conductive metal charged in the openings 510 .
- the printed circuit board may further include a via 930 made of a conductive metal penetrating the first insulation layer 300 and second insulation layer 500 .
- an interface which can be distinguished by surface roughness is formed between the first insulation layer 300 and the second insulation layer 500 .
- This interface is necessarily formed because the first insulation layer 300 and the second insulation layer 500 are formed sequentially, not simultaneously.
- first insulation layer 300 and second insulation layer 500 may be made of a filler-containing epoxy resin, a glass epoxy resin, an alumina-containing epoxy or the like, but the present invention is not limited thereto. Further, the first insulation layer 300 and second insulation layer 500 may be made of the same material as each other, and may also be made of different material from each other.
- the first insulating material have higher filler content than the second insulating material. Further, it is preferred that the average particle size of the filler included in the first insulating material be larger than that of the filler included in the second insulating material.
- the printed circuit board having a buried pattern is advantageous in that, since a circuit pattern 910 and a via 930 are buried in the second insulation layer 500 , the circuit pattern 910 is not undercut, and a fine pitched circuit pattern is formed.
- the printed circuit board having a buried pattern according to an embodiment of the present invention is advantageous in that, since the height of the circuit pattern 910 buried in the second insulation layer 500 is uniform, its electric signal transfer performance is improved.
- a printed circuit board according to the present invention is advantageous in that, since a circuit pattern and a via are buried in an insulation layer, a circuit pattern is not undercut, and a fine pitched circuit pattern is formed.
- a method of manufacturing the printed circuit board according to the present invention is advantageous in that, since openings for forming circuit patterns are formed in a second insulating material using a dry film, the method is simple compared to a conventional imprinting method or laser trenching method for forming buried patterns, and thus process costs can be reduced.
Abstract
Disclosed herein is a method of manufacturing a printed circuit board having a buried pattern, including: forming a second insulation layer on a first insulation layer, the second insulation layer having openings for forming a circuit layer; and filling the openings with a conductive metal to form a circuit layer.
Description
- This application is a U.S. divisional application, filed under 37 CFR 1.53(b), claiming priority benefit of U.S. Ser. No. 12/382,057, filed in the United States on Mar. 6, 2009, now allowed, which claims earlier priority benefit to Korean Patent Application No. 10-2008-0118187, filed Nov. 26, 2008, the disclosures of which are incorporated herein by reference.
- 1. Field
- The present invention relates to a printed circuit board having a buried pattern and a method of manufacturing the same.
- 2. Description of the Related Art
- A printed circuit board (PCB) serves to electrically connect electronic parts to each other, supply power and mechanically fix them thereon through a wire pattern formed on an insulation substrate made of a phenol resin, an epoxy resin or the like. Such a printed circuit board includes a one-sided printed circuit board, in which a wiring pattern is formed on only one side of an insulation substrate, a double-sided printed circuit board, in which wiring patterns are formed on both sides of an insulation substrate, and a multi-layered printed circuit board (MLB), in which wiring patterns are provided in multiple layers.
- As a method of forming a wiring pattern on a printed circuit board, an additive process, a subtractive process, a semi additive process (SAP), a modified semi additive process (MSAP) or the like is used.
- Recently, with the advancement of the electronics industry, electronic parts are increasingly required to be highly functionalized and to be miniaturized. In response to the trend, printed circuit boards loaded with such electronic parts are also required to have a highly densified circuit pattern. Thus, methods of realizing various fine circuit patterns are developed, proposed and applied.
- In the present invention, among the methods of forming a fine circuit pattern, a method of realizing the densification of a circuit pattern by burying a circuit pattern in an insulation layer will be described.
-
FIG. 1 shows a conventional process of forming a wiring pattern using MSAP or SAP. - First, as shown in
FIG. 1A , aseed layer 3 is formed on aninsulation substrate 1, and then a platingresist layer 5 is formed on theseed layer 3. Thereafter, an electroplating layer is formed on theseed layer 3 through an electroplating process. Subsequently, as shown inFIG. 1B , theplating resist layer 5 is removed from theseed layer 3, and then, as shown inFIG. 1C , the exposed portion of theseed layer 3 is removed from theinsulation substrate 1 through flash etching or quick etching to form awiring pattern 7. - However, when the exposed portion of the
seed layer 3 is removed from theinsulation substrate 1 through flash etching or quick etching, the electroplating layer for forming the wiring pattern is also etched, so that the lateral face of thewiring pattern 7 is greatly tapered and the width of thewiring pattern 7 is decreased, with the result that thewiring pattern 7 is short-circuited and the signal transfer characteristics of thewiring pattern 7 are weakened. - Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and the present invention provides a printed circuit board in which a circuit pattern is buried in an insulation layer and thus an undercut phenomenon does not occur and which can realize various fine circuit patterns, and a method of manufacturing the same.
- An aspect of the present invention provides a method of manufacturing a printed circuit board having a buried pattern, including: forming a second insulation layer on a first insulation layer, the second insulation layer having openings for forming a circuit layer; and filling the openings with a conductive metal to form a circuit layer.
- In the method, the forming of the second insulation layer may include: applying a dry film on the first insulation layer; forming grooves on the dry film such that the dry film has the same pattern as the circuit layer; filling the grooves with a second insulation material; and removing the dry film.
- Further, the first insulation layer may have higher filler content than the second insulation layer.
- Further, the method may further include: forming a via hole passing through the first insulation layer and the second insulation layer after the forming of the second insulation layer, wherein, in the filling of the openings, the via hole as well as the openings is filled with a conductive metal.
- Further, the dry film may be a photosensitive dry film.
- Further, the method may further include: removing the second insulation material applied on the dry film such that an upper surface of the dry film is exposed, after the filling the grooves with the second insulation material.
- Furthermore, the removing of the second insulation material may be conducted by a chemical etching process or a mechanical grinding process.
- Another aspect of the present invention provides a printed circuit board having a buried pattern, including: a first insulation layer; a second insulation layer which is formed on the first insulation layer and has openings for forming a circuit layer; and a circuit layer charged in the openings and made of a conductive metal, wherein an interface is formed between the first insulation layer and the second insulation layer.
- In the printed circuit board, the first insulation layer may have higher filler content than the second insulation layer.
- Further, the printed circuit board may further include: a via made of a conductive metal passing through the first insulation layer and the second insulation layer.
- Various objects, advantages and features of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings.
- The terms and words used in the present specification and claims should not be interpreted as being limited to typical meanings or dictionary definitions, but should be interpreted as having meanings and concepts relevant to the technical scope of the present invention based on the rule according to which an inventor can appropriately define the concept of the term to describe the best method he or she knows for carrying out the invention.
- The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1A to 1C are sectional views showing a convention method of manufacturing a printed circuit board; and -
FIGS. 2 to 8 are sectional views showing a method of manufacturing a printed circuit board having a buried pattern according to an embodiment of the present invention. - Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.
- Throughout the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant descriptions thereof are omitted. In the following description, the terms “upper”, “lower” and the like are used to differentiate a certain component from other components, but the configuration of such components should not be construed to be limited by the terms.
-
FIGS. 2 to 8 are sectional views showing a method of manufacturing a printed circuit board having a buried pattern according to an embodiment of the present invention. - First, as shown in
FIG. 2 , a double-side copper clad laminate (CCL), which is used as a core, is provided. The double-side copper clad laminate (CCL) includes aninsulation substrate 100, andcopper foils 110 applied on both sides of theinsulation substrate 100. Afirst insulation layer 300 is formed on each of thecopper foils 110 by applying a first insulating material on each of thecopper foils 110. The first insulation layer is made of a polymer material, which is an electric insulator, for example, prepreg including an epoxy resin. - In an embodiment of the present invention, the double-sided copper clad laminate is used as a core substrate, but the present invention is not limited thereto. One-sided, double-sided or multi-layered printed circuit board having a wiring pattern made of conductive metals may be used as a core substrate, and the
first insulation layer 300 itself may also be used as a core substrate. - Subsequently, as shown in
FIG. 3 , adry film 400 having the same pattern as acircuit layer 900 is formed on thefirst insulation layer 300. In this case, thedry film 400 may be a photosensitive dry film. The photosensitive dry film is a material which can be patterned by selectively curing it using a mask having light shielding patterns. Thedry film 400 formed on thefirst insulation layer 300 is exposed and developed using a light shielding mask such that thedry film 400 has the same pattern as thecircuit layer 900, thereby forminggrooves 410 in thedry film 400. - In this case, since the height of a
circuit pattern 910 of thecircuit layer 900, which is to be formed later, can be adjusted, it is preferred that the thickness of the dry film be thin in order to manufacture a high-density thin printed circuit board. - Subsequently, as shown in
FIG. 4 , a secondinsulating layer 500 is formed on the first insulatinglayer 300 by filling thegrooves 410 formed in thedry film 400 with a second insulating material. The second insulating material may be the same as the first insulating material, but it is preferred that the second insulating material have lower filler content than the first insulating material in order to easily fill thegroove 410 with the second insulating material. Further, it is preferred that the average particle size of the filler included in the second insulating material be smaller than that of the filler included in the first insulating material in order to easily fill thegroove 410 with the second insulating material. The filler is a material added to an insulating material in order to impart rigidity or thermal conductivity thereto. Examples of the filler may include aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, silicon compounds, and the like. - Meanwhile, in an embodiment of the present invention, since the
second insulation layer 500 is sequentially formed after the formation of thefirst insulation layer 300, an interface which can be distinguished by surface roughness is formed between thefirst insulation layer 300 and thesecond insulation layer 500. - In this case, as shown in
FIG. 5A , when the second insulating material is charged in thegrooves 410 formed in thedry film 400, the upper surface of thedry film 400 may be covered with the second insulating material. In this case, in order to easily remove thedry film 400 in subsequent processes, the second insulating material applied on the upper surface of thedry film 400 must be removed. - As shown in
FIG. 5B , the removal of the second insulating material applied on the upper surface of thedry film 400 may be conducted by partially removing the second insulating material in its thickness direction through a dry etching process using plasma or a wet etching process (chemical etching process) using organic alkali or aqueous alkali solution supplied frometchant supply units 610. In addition, as shown inFIG. 5C , the second insulating material applied on the upper surface of thedry film 400 may be removed through a mechanical grinding process using abuff grinder 630. Moreover, although not shown, the second insulating material applied on the upper surface of thedry film 400 may be removed using a belt sander or a grinding brush. - Subsequently, as shown in
FIG. 6 , thedry film 400 applied on thefirst insulation layer 300 is removed using a stripper, and thus thesecond insulation layer 500 havingopenings 510 for forming acircuit layer 900 is formed on thefirst insulation layer 300 - Subsequently, as shown in
FIG. 7 , a viahole 700 passing through thefirst insulation layer 300 andsecond insulation layer 500 is formed. In an embodiment of the present invention, the viahole 700 is formed by etching thefirst insulation layer 300 through theopening 510 of thesecond insulation layer 500, and thus thecopper foil 110 applied on theinsulation substrate 100 is exposed through the viahole 700. The formation of the viahole 700 may be conducted using a YAG laser drill or a CO2 laser drill. - Subsequently, as shown in
FIG. 8 , acircuit layer 900 is formed by charging a conductive metal in the viahole 700 andopenings 510. In the formation of thecircuit layer 900, first, an electroless seed layer is formed on thefirst insulation layer 300 andsecond insulation layer 500, and then an electroplating layer is formed on thesecond insulation layer 500 by performing an electroplating process using the electroless seed layer as an incoming line. The electroless seed layer and electroplating layer may be made of a conductive metal, such as gold (Au), silver (Al), copper (Cu), nickel (Ni) or the like. Then, the electroless seed layer and electroplating layer formed on thesecond insulation layer 500 are removed using abuffer grinder 630, a grinding brush or a belt sander, thereby completing thecircuit layer 900 including acircuit pattern 910 and a via 930. - The above-mentioned method of manufacturing a printed circuit board having a buried pattern according to an embodiment of the present invention is advantageous in that, since the
openings 510 for forming thecircuit pattern 910 is formed in the second insulatinglayer 500 using thedry film 400, the width and depth of the openings are constant compared to compared to a conventional laser trenching method, and a circuit pattern having uniform height can be formed. - Further, the above-mentioned method is advantageous in that the method is simple compared to a conventional imprinting method or laser trenching method for forming buried patterns, and thus process costs can be reduced.
- Hereinafter, the structure of a printed circuit board having a buried pattern according to an embodiment of the present invention is described with reference to
FIG. 8 . - As shown in
FIG. 8 , the printed circuit board having a buried pattern according to an embodiment of the present invention includes afirst insulation layer 300, asecond insulation layer 500 which is formed on thefirst insulation layer 300 and hasopenings 510 for forming acircuit layer 900, and acircuit layer 900 made of a conductive metal charged in theopenings 510. The printed circuit board may further include a via 930 made of a conductive metal penetrating thefirst insulation layer 300 andsecond insulation layer 500. - In this case, an interface which can be distinguished by surface roughness is formed between the
first insulation layer 300 and thesecond insulation layer 500. This interface is necessarily formed because thefirst insulation layer 300 and thesecond insulation layer 500 are formed sequentially, not simultaneously. - Here, the
first insulation layer 300 andsecond insulation layer 500 may be made of a filler-containing epoxy resin, a glass epoxy resin, an alumina-containing epoxy or the like, but the present invention is not limited thereto. Further, thefirst insulation layer 300 andsecond insulation layer 500 may be made of the same material as each other, and may also be made of different material from each other. - In this case, it is preferred that the first insulating material have higher filler content than the second insulating material. Further, it is preferred that the average particle size of the filler included in the first insulating material be larger than that of the filler included in the second insulating material.
- The printed circuit board having a buried pattern according to an embodiment of the present invention is advantageous in that, since a
circuit pattern 910 and a via 930 are buried in thesecond insulation layer 500, thecircuit pattern 910 is not undercut, and a fine pitched circuit pattern is formed. - Further, the printed circuit board having a buried pattern according to an embodiment of the present invention is advantageous in that, since the height of the
circuit pattern 910 buried in thesecond insulation layer 500 is uniform, its electric signal transfer performance is improved. - As describe above, a printed circuit board according to the present invention is advantageous in that, since a circuit pattern and a via are buried in an insulation layer, a circuit pattern is not undercut, and a fine pitched circuit pattern is formed.
- Further, a method of manufacturing the printed circuit board according to the present invention is advantageous in that, since openings for forming circuit patterns are formed in a second insulating material using a dry film, the method is simple compared to a conventional imprinting method or laser trenching method for forming buried patterns, and thus process costs can be reduced.
- Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims (3)
1. A printed circuit board having a buried pattern, comprising:
a first insulation layer;
a second insulation layer which is formed on the first insulation layer and has openings for forming a circuit layer; and
a circuit layer charged in the openings and made of a conductive metal,
wherein an interface is formed between the first insulation layer and the second insulation layer.
2. The printed circuit board according to claim 1 , wherein the first insulation layer has higher filler content than the second insulation layer.
3. The printed circuit board according to claim 1 , further comprising:
a via made of a conductive metal passing through the first insulation layer and the second insulation layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/466,784 US20120217043A1 (en) | 2008-11-26 | 2012-05-08 | Method of manufacturing a printed circuit board |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2008-0118187 | 2008-11-26 | ||
KR1020080118187A KR101022903B1 (en) | 2008-11-26 | 2008-11-26 | A printed circuit board comprising a buried-pattern and a method of manufacturing the same |
US12/382,057 US8191249B2 (en) | 2008-11-26 | 2009-03-06 | Method of manufacturing a printed circuit board |
US13/466,784 US20120217043A1 (en) | 2008-11-26 | 2012-05-08 | Method of manufacturing a printed circuit board |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/382,057 Division US8191249B2 (en) | 2008-11-26 | 2009-03-06 | Method of manufacturing a printed circuit board |
Publications (1)
Publication Number | Publication Date |
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US20120217043A1 true US20120217043A1 (en) | 2012-08-30 |
Family
ID=42195188
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/382,057 Expired - Fee Related US8191249B2 (en) | 2008-11-26 | 2009-03-06 | Method of manufacturing a printed circuit board |
US13/466,784 Abandoned US20120217043A1 (en) | 2008-11-26 | 2012-05-08 | Method of manufacturing a printed circuit board |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US12/382,057 Expired - Fee Related US8191249B2 (en) | 2008-11-26 | 2009-03-06 | Method of manufacturing a printed circuit board |
Country Status (3)
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US (2) | US8191249B2 (en) |
JP (1) | JP2010129997A (en) |
KR (1) | KR101022903B1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US8662640B2 (en) * | 2012-01-24 | 2014-03-04 | Eastman Kodak Company | Corrosion protected flexible printed wiring member |
KR20150062558A (en) * | 2013-11-29 | 2015-06-08 | 삼성전기주식회사 | Printed circuit board and Manufacture method using thereof |
KR102171021B1 (en) | 2014-03-14 | 2020-10-28 | 삼성전자주식회사 | Method for manufacturing circuit board and semiconductor package |
Citations (3)
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US6281448B1 (en) * | 1996-12-26 | 2001-08-28 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electronic components |
US6320140B1 (en) * | 1996-06-14 | 2001-11-20 | Ibiden Co., Ltd. | One-sided circuit board for multi-layer printed wiring board, multi-layer printed wiring board, and method of its production |
US7205483B2 (en) * | 2004-03-19 | 2007-04-17 | Matsushita Electric Industrial Co., Ltd. | Flexible substrate having interlaminar junctions, and process for producing the same |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US5480048A (en) * | 1992-09-04 | 1996-01-02 | Hitachi, Ltd. | Multilayer wiring board fabricating method |
JPH08186119A (en) * | 1994-12-27 | 1996-07-16 | Sharp Corp | Manufacture of circuit board |
JP3790063B2 (en) * | 1999-03-08 | 2006-06-28 | 新光電気工業株式会社 | Multilayer wiring board, manufacturing method thereof, and semiconductor device |
JP3635219B2 (en) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | Multilayer substrate for semiconductor device and manufacturing method thereof |
JP2002111174A (en) * | 2000-09-27 | 2002-04-12 | Nitto Denko Corp | Method for manufacturing wiring circuit board |
JP4092890B2 (en) * | 2001-05-31 | 2008-05-28 | 株式会社日立製作所 | Multi-chip module |
JP3910907B2 (en) * | 2002-10-29 | 2007-04-25 | 新光電気工業株式会社 | Capacitor element and manufacturing method thereof, substrate for semiconductor device, and semiconductor device |
TWI236721B (en) * | 2004-06-29 | 2005-07-21 | Advanced Semiconductor Eng | Leadframe for leadless flip-chip package and method for manufacturing the same |
JP2006049804A (en) * | 2004-07-07 | 2006-02-16 | Shinko Electric Ind Co Ltd | Manufacturing method of wiring board |
JP2007311484A (en) * | 2006-05-17 | 2007-11-29 | Cmk Corp | Printed-wiring board, and manufacturing method therefor |
US20070281464A1 (en) | 2006-06-01 | 2007-12-06 | Shih-Ping Hsu | Multi-layer circuit board with fine pitches and fabricating method thereof |
TWI316381B (en) * | 2007-01-24 | 2009-10-21 | Phoenix Prec Technology Corp | Circuit board and fabrication method thereof |
-
2008
- 2008-11-26 KR KR1020080118187A patent/KR101022903B1/en not_active IP Right Cessation
-
2009
- 2009-03-03 JP JP2009049575A patent/JP2010129997A/en active Pending
- 2009-03-06 US US12/382,057 patent/US8191249B2/en not_active Expired - Fee Related
-
2012
- 2012-05-08 US US13/466,784 patent/US20120217043A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6320140B1 (en) * | 1996-06-14 | 2001-11-20 | Ibiden Co., Ltd. | One-sided circuit board for multi-layer printed wiring board, multi-layer printed wiring board, and method of its production |
US6281448B1 (en) * | 1996-12-26 | 2001-08-28 | Matsushita Electric Industrial Co., Ltd. | Printed circuit board and electronic components |
US7205483B2 (en) * | 2004-03-19 | 2007-04-17 | Matsushita Electric Industrial Co., Ltd. | Flexible substrate having interlaminar junctions, and process for producing the same |
Also Published As
Publication number | Publication date |
---|---|
US20100126761A1 (en) | 2010-05-27 |
US8191249B2 (en) | 2012-06-05 |
KR101022903B1 (en) | 2011-03-16 |
KR20100059417A (en) | 2010-06-04 |
JP2010129997A (en) | 2010-06-10 |
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