US20120256657A1

US20120256657A1 - Field effect transistor, and electric circuit

Info

Publication number: US20120256657A1
Application number: US13/494,349
Authority: US
Inventors: Andreas Ullmann; Walter Fix
Original assignee: PolylC GmbH and Co KG
Current assignee: PolylC GmbH and Co KG
Priority date: 2006-10-06
Filing date: 2012-06-12
Publication date: 2012-10-11
Also published as: EP2087519A1; WO2008043475A1; DE102006047388A1; EP2087519B1; US20100033213A1; EP2387076A1; KR20090076908A; US8217432B2

Abstract

The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer.

Description

This application is a continuation of application Ser. No. 12/311,620 filed Apr. 22, 2009, incorporated by reference herein in its entirety.
The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer. The invention furthermore relates to a logic component, electric circuits, and a method for producing electric circuits.
Field effect transistors having the construction mentioned above are known from WO 2004/047144 A2. On a substrate, intermeshing source and drain electrode layers are disclosed which are covered in this order with a patterned semiconductor layer and a whole-area insulator layer. A patterned gate electrode layer is situated on the insulator layer. Situated between the source electrode layer and the drain electrode layer is the so-called channel, above which the gate electrode layer, here as top gate electrode, is arranged. The field effect transistor can be produced in an inexpensive printing method.
In this case, the precise registration or positioning of the gate electrode layer relative to the source/drain electrode layers is necessary since this greatly influences the switching speed of the field effect transistor. Thus, in order to improve the registration, it has already been attempted to increase the area extent of the gate electrode layer to such a degree that the latter—as seen perpendicular to the plane of the source/drain electrode layers—completely covers, and if appropriate even projects beyond, the region covered by the source and drain electrode layers and the channel region enclosed in between. A field effect transistor of this type has a good switch-on and switch-off behavior, ultimately independently of the precise arrangement of the gate electrode layer relative to the source/drain electrode layers. However, the increased area extent of the gate electrode layer gives rise to high capacitances, so-called register capacitances, as a result of which logic components and electronic circuits formed with such a field effect transistor lose speed.
It is thus an object of the invention to provide an improved field effect transistor comprising at least one electrical functional layer patterned with the aid of a printing method. It is furthermore an object of the invention to provide an electric circuit having a small space requirement and a method for producing said electric circuit.
The object is achieved for the field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, by virtue of the fact that the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer.
The area extent of the gate electrode layer is thus made significantly smaller than the area extent of the source and drain electrode layers and of the channel region arranged in between. This results in a functional field effect transistor which has electrically a similar ON current and similarly low capacitances to those achieved by a field effect transistor with a precise positioning of the to gate electrode layer in register with respect to the source/drain electrode layers, even though an exact registration is not present. What is achieved in addition is that despite the surplus channel region, the space requirement for forming the field effect transistor can be reduced by up to 50% since the source/drain electrode layers can be made significantly smaller.
It is particularly preferred if the area extent of the gate electrode layer, with respect to the sum of the area extents of the source/drain electrode layers and of the channel region, is embodied such that it is reduced by the magnitude of the maximum register tolerance with the printing method used. Thus, register tolerances within the range of 400 to 40 μm can usually be achieved with the printing methods preferred here, such as intaglio printing, relief printing, planographic printing, template printing (screen printing or stencil printing) or pad printing. Both lateral register tolerances per perpendicular to the printing direction and longitudinal register tolerances in the printing direction should be taken into account in this case.
The reduction of the area dimension of the gate electrode layer is preferably effected by choosing the length thereof in the printing direction to be smaller than the sum of the lengths of the source/drain electrode layers and of the channel region in the printing direction. The width of the gate electrode layer perpendicular to the, printing direction can likewise be embodied in reduced fashion with respect to the sum of the widths of the source/drain electrode layers and of the channel region perpendicular to the printing direction. However, an increase in the width of the gate electrode layer perpendicular to the printing direction in accordance with the known method described above has also proved worthwhile in combination with a reduction of the length of the gate electrode layer in the printing direction.
It has proved particularly worthwhile in this case if the channel extends between the at least one source electrode layer and at least two drain electrode layers, wherein the drain electrode layers are embodied in a manner electrically insulated from one another. As a result, the leakage current of the field effect transistor—that arises In channel regions not covered/overlaid by the gate electrode layer no longer has a disturbing effect on the electrical properties of the field effect transistor.
Furthermore, it has proved to be advantageous if the at least one source electrode layer is embodied in comb-shaped fashion or in the form of parallel lines that are electrically insulated from one another. A comb-shaped configuration or one in the form of parallel lines that are electrically insulated from one another has likewise proved to be worthwhile for the at least one drain electrode layer. If a plurality of drain electrode layers are provided, then a configuration of each drain electrode layer in each case in comb-shaped form has proved to be worthwhile. A comb-shaped configuration of the at least one source electrode layer in combination with a comb-shaped configuration of the at least one drain electrode layer is particularly preferred, wherein the comb teeth of the source and drain electrode layers intermesh, such that the channel runs in meandering fashion between the at 30 least one source electrode layer and the at least one drain electrode layer. A gate electrode layer according to the invention, which is preferably embodied in a manner overlapping such comb-shaped, intermeshing source and drain electrode layers, covers the meandering channel region only partly, such that channel regions which do not contribute to the mode of operation of the field effect transistor remain unused. A positional inaccuracy of the gate electrode layer in the region of the channel region on account of the register tolerances that are unavoidable during printing is of no or virtually no significance for the electrical behavior of the field effect transistor.
It has proved to be worthwhile if the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, covers an area of 10 to 90%, in particular of 25 to 50%, of the channel.
The gate electrode layer can be embodied as a bottom gate electrode or as a top gate electrode. An embodiment as a bottom gate electrode involves forming, in particular on a carrier substrate, firstly the gate electrode layer, then the insulator layer, the semiconductor layer and the source/drain electrode layers. An embodiment as a top gate electrode involves forming, in particular on a carrier substrate, firstly the source/drain electrode layers, then the semiconductor layer, the insulator layer and the gate electrode layer.
A suitable carrier substrate on which the source electrode layer, the at least one drain electrode layer, the to semiconductor layer—preferably printed over the whole area—, the insulator layer—preferably likewise Printed over the whole area—and the gate electrode layer are preferably arranged is preferably formed from a flexible plastic film, in particular from Polyester, polyethylene, polyethylene terephthalate or polyimide. It is particularly preferred in this case if an elongated flexible substrate made of plastic film, which, if appropriate, is embodied in multilayered fashion, is used as the carrier substrate. It has furthermore proved to be worthwhile if a thickness of the carrier substrate within the range of 6 μm to 200 μm, preferably within the range of 12 μm to 50 μm, is chosen.
In the case of a flexible carrier substrate it is advantageous, in particular, that said substrate can be processed in a continuous process, in particular roll-to-roll transport can be performed. In this case, the uncoated flexible carrier substrate is wound up onto a roll, the carrier substrate is unwound from the roll and led through one or more process machines for forming electrical functional layers of a multiplicity of field effect transistors and, if appropriate, further electrical components or electric circuits equipped therewith, and is finally wound up as a coated carrier substrate onto a further roll. This enables long carrier substrate strips to be processed, wherein the positioning relative to the process machine/machines only has to be effected once at the beginning of a new carrier substrate roll.
It has proved to be particularly worthwhile if the field effect transistor comprises at least one organic functional layer. All layers required for the construction of the field effect transistor are referred to as functional layer.
All types of organic, organometallic and inorganic plastics are regarded as “organic” materials for forming an organic functional layer in this case. Accordingly, a restriction in the dogmatic sense to organic material as carbon-containing material is not intended, rather the use of silicones, for example, is also envisaged. Furthermore, the term is not intended to be subject to any restriction whatsoever with regard to the molecular size, in particular to polymeric and/or oligomeric materials, rather the use of “small molecules” is perfectly possible as well.
In this case, inorganic functional layers, in particular ones formed by sputtering or vapor deposition, can be combined with organic functional layers or the field effect transistor can be constructed entirely with organic functional layers. It has proved to be worthwhile if at least one organic functional layer, in particular the semiconductor layer and/or the insulator layer, is formed by printing.
In this case, it has proved to be worthwhile to form the source/drain electrode layers and the gate electrode layer in each case from at least one metallic layer, for example from at least one of the materials gold, silver, copper, aluminum, platinum, titanium or the like. These are then preferably patterned by means of a laser or etching. Polyaniline or polypyrrole, inter alia, have proved to be worthwhile as electrically conductive organic materials for forming electrode layers. A layer stack composed of at least two layers can also be used for forming an electrode layer.
An embodiment of the semiconductor layer and/or of the insulator layer as an organic functional layer has proved to be worthwhile. Polyvinyl phenol or polyhydroxystyrene (PHS/PVP), inter alia, has proved to be worthwhile as organic insulation material. Polythiophene, for example, is suitable as organic semiconductor material.
During the positioning of a laser with respect to a functional layer already formed on a carrier substrate, usually small deviations with respect to the ideal Position arise, thus resulting in a deviation of the patterned functional layer formed with respect to the layout. If a photoresist is applied to a functional layer over the whole area and exposed by means of a mask, and the non-cured regions of the resist are removed, an etching process is carried out and the photoresist is subsequently removed, then positional deviations arise here, too, for the functional layer formed relative to the layout as a result of small deviations during the positioning of the mask from its ideal position.
Furthermore, a functional layer can for example already be printed with an etching-resistant mask layer in the desired regions and the non-printed regions of the functional layer can be removed by etching. Afterward, the etching-resistant mask layer is stripped away and the regions of the functional layer that have remained underneath and are patterned in the desired form are uncovered. Deviations from the ideal position likewise arise during the printing of the mask layer in the same way as during the direct printing of a functional layer. Said deviations are transferred from the mask layer directly to the functional layer patterned thereby.
It has furthermore proved to be worthwhile if an inkjet patterning method is used, wherein high process speeds are possible. In this case, a functional layer can be formed by means of inkjet printing directly and already in the desired form on the carrier substrate. However, the inkjet method also makes it possible to apply a mask layer in order to pattern a previously formed functional layer using said mask layer.
Preferably, a relative speed of the carrier substrate with respect to a patterning unit in a continuous processing process is chosen within the range of 0.5 to 200 m/min, preferably within the range of 10 to 100 m/min. This enables mass production of electronic components and circuits with low manufacturing costs.
It has proved to be worthwhile if a functional layer of the field effect transistor is embodied with in each 35 case a layer thickness within the range of 1 nm to 100 μm, preferably within the range of 10 nm to 300 nm.
A logic component having at least one field effect transistor according to the invention has proved to be worthwhile. Such a logic component is, in particular, a structural element from the group comprising inverter components, NOR gates, NAND gates, AND gates and OR gates.
It is particularly preferred in this case if the logic component is an inverter component comprising a field effect transistor and at least one charging component having at least one first electrode and at least one second electrode, wherein the at least one second electrode is embodied for connection to a supply voltage, and wherein at least one of the first electrodes is electrically conductively connected to at least one drain electrode layer of the field effect transistor which, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, overlaps the gate electrode layer at least in regions. A drain electrode layer is thus connected which adjoins a channel region with gate electrode layer.
It has proved to be worthwhile if the electrically conductive connection between the at least one first electrode and the at least one drain electrode layer of the field effect transistor is formed by at least one interconnect and/or at least one via. In this case, an interconnect is understood to be an electrical connection in one plane, while a via is understood to be an electrically conductive connection across a plurality of planes.
Preferably, the inverter component comprises a field effect transistor having at least one source electrode layer and at least two drain electrode layers and also comprises the at least one charging component having at least two first electrodes, wherein a respective one of the drain electrode layers is electrically conductively connected to a respective one of the first electrodes. An electric circuit comprising at least one logic component according to the invention has been proved to be worthwhile. An electric circuit comprising at least two logic components, in particular at least two inverter components, is particularly preferred in this case.
In this case, it has proved to be advantageous if a first inverter component has a first gate electrode layer, and the first gate electrode layer is electrically conductively connected to the at least one interconnect and/or the at least one via of a second inverter component which is assigned to a second inverter component and electrically conductively connects the at least one drain electrode layer and the at least one first electrode of the charging component of the second inverter component to one another.
In this case, it has proved to be worthwhile if the at least one interconnect is arranged on the plane of the at least one source electrode layer and the at least one drain electrode layer, and the first gate electrode layer and the at least one interconnect are electrically conductively connected to one another by means of at least one via in the semiconductor layer and the insulator layer.
However, it has also proved to be worthwhile in this case if the first gate electrode layer is electrically conductively connected to the at least one drain electrode layer and the at least one first electrode of the second inverter component by means of at least one via in the semiconductor layer and the insulator layer. What is particularly preferred in this case is a method in which by means of at least one via in the semiconductor layer and the insulator layer, with the formation of the gate electrode layer, the electrically conductive connection to the at least one drain electrode layer and the at least one first electrode of the second inverter component is also formed simultaneously.
The object is achieved for the electric circuit on a carrier substrate, wherein at least one first component and at least one second component, which are electrically conductively connected to one another, are formed on the carrier substrate, by virtue of the fact that at least two second components are formed, wherein an electrically conductive functional layer of the first component is electrically conductively connected to an electrically conductive functional layer of one of the at least two second components by means of a printed interconnect, wherein the at least one first component is alternatively connected to one or the other of the at least two second components and at least one unused, surplus second component is thus present.
Even though space for surplus second components is provided in the case of the electric circuit according to the invention on the carrier substrate, up to 50% of the area can nevertheless be saved by comparison with conventional electric circuits, without impairment of the essential properties of the electric circuit occurring, since the individual structural elements of the electric circuit can be made significantly smaller. Depending on the register tolerance present during the printing of the interconnect, one of the at least two second components is electrically conductively connected to the at least one first component.
In this case, it is preferred if the at least two second components are arranged one after another and adjacent to one another in the printing direction of the interconnect. In this case, the distance between the second components should be coordinated with the register tolerances that actually occur during printing.
Furthermore, it has proved to be worthwhile if at least two first components are formed, and one of the first components is electrically conductively connected to one of the second components by means of the interconnect, such that at least one first component and at least one second component are present in unused and surplus fashion.
For the at least two first components too, it is advantageous if they are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.
In particular, it has proved to be worthwhile if a field effect transistor according to the invention is embodied as first component, said transistor having at least one drain electrode layer as electrically conductive functional layer.
In combination with the field effect transistor according to the invention, it has proved to be worthwhile if the second component is embodied as a charging component having at least one first electrode as electrically conductive functional layer and at least one second electrode, wherein the at least one second electrode is embodied for connection to a supply voltage.
The object is achieved for the method for producing an electric circuit on a carrier substrate, wherein at least one first component and at least one second component, which are electrically conductively connected to one another, are formed on the carrier substrate, by virtue of the fact that at least two second components are formed, that an electrically conductive functional layer of the first component is electrically conductively connected to an electrically conductive functional layer of one of the at least two second components by printing an interconnect, wherein the at least one first component, depending on the register tolerance during the printing of the interconnect, is alternatively connected to one or the other of the at least two second components and at least one second component thus remains unused.
In this case, it is preferred if the at least two second components are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.
Preferably, furthermore at least two first components are formed, and one of the first components is electrically conductively connected to one of the second components by means of the interconnect, such that at least one first component and at least one second component remain unused.
The at least two first components, too, are preferably arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.

FIGS. 1 a to 7 are intended to elucidate by way of example the field effect transistor according to the invention and its use in logic components and electric circuits. Thus:

FIG. 1 a is an elevation cross section view through the field 30 effect transistor of FIG. 1 b arranged on a carrier substrate taken at line A-A′ of FIG. 1 b;

FIG. 1 b is shows a simplified diagrammatic plan view of a field effect transistor and a carrier substrate according to an embodiment of the present invention;

FIG. 2 a is an elevation cross section view through a further field effect transistor arranged on a carrier substrate taken at line B-B′ of FIG. 1 b;

FIG. 2 b is a simplified diagrammatic plan view of the transistor of FIG. 1 b and a further field effect transistor and the carrier substrate according to a further embodiment of the present invention;

FIG. 3 is a simplified diagrammatic plan view of a logic component forming an inverter component;

FIG. 4 is a simplified diagrammatic plan view of an electric circuit having two logic components, wherein each logic component comprises a charging component;

FIG. 5 is a simplified diagrammatic plan view of an electric circuit having two logic components, wherein each logic component comprises two charging components;

FIG. 6 is a simplified diagrammatic plan view of a further electric circuit having two logic components, wherein each logic component comprises two charging components; and

FIG. 7 is a simplified diagrammatic plan view of an embodiment of a layout of an electric circuit having a multiplicity of logic components in accordance with FIG. 6.

FIG. 1 a shows a cross section A-A′ through a field effect transistor 1 arranged on a carrier substrate 10 made of PET. The field effect transistor 1 comprises as 30 functional layers a source electrode layer 2 patterned in comb-shaped fashion and made of gold, silver, PEDOT or PANI and, in the same plane, a drain electrode layer 3 patterned in comb-shaped fashion and made of the same material. A semiconductor layer 5 made of polythiophene and an insulator layer 6 made of polyhydroxystyrene (PHS/PVP) are printed thereon over the whole area. A gate electrode layer 4 is situated on the insulator layer 6, said gate electrode layer only partly covering the channel 7 (see FIG. 1 b) between the source electrode layer 2 and the drain electrode layer 3.
FIG. 1 b shows a simplified plan view of the field effect transistor 1 and the carrier substrate 10 from FIG. 1 a, wherein the illustration of the semiconductor layer 5 and of the insulator layer 6 has been disregarded. Consequently, FIG. 1 b reveals the position of the comb-shaped source electrode layer 2 having three comb teeth relative to the comb-shaped 10 drain electrode layer 3 having two comb teeth, which are arranged in a manner intermeshed with one another on the carrier substrate 10. Situated between the source electrode layer 2 and the drain electrode layer 3 is the channel 7, which exhibits a meandering course as seen perpendicular to the plane of the carrier substrate 10. The semiconductor layer 5 arranged on the source electrode layer 2 and the drain electrode layer 3 and the insulator layer 6 are not depicted here, in order to be able to demonstrate the position and area extent of the gate electrode layer 4 with respect to the channel 7. It is evident that the gate electrode layer 4 only partly covers the channel 7. A positional displacement of the gate electrode layer 4 with regard to its orientation toward the source electrode layer 2 25 and the drain electrode layer 3 in the identified x directions or y directions on account of register tolerances during the formation of the gate electrode layer 4 does not affect essential electrical properties of the field effect transistor 1 (ON current, capacitance), since the area extent of the gate electrode layer 4 is chosen such that even in the event of a production-dictated maximum possible displacement of the gate electrode layer 4 in the x and/or y direction, a position of parts of the gate electrode layer 4 outside the channel region delimited by the source and drain electrode layers 2, 3 is not possible.
The simplest embodiment of the field effect transistor according to the invention would be here one which exhibits a comb-shaped source electrode layer which is embodied at least with two comb tines connected to one another and has a merely strip-shaped drain electrode layer situated between the two comb tines of the source electrode layer.
FIG. 2 a shows a cross section B-By through a further field effect transistor 1′ arranged on a carrier substrate 10. The field effect transistor 1″ comprises as functional layers a source electrode layer 2 patterned in comb-shaped fashion and made of gold, silver, PEDOT or PANI and, in the same plane, two drain electrode layers 3 a, 3 b patterned in comb-shaped fashion and made of the same material, said drain electrode layers being electrically insulated from one another. A semiconductor layer 5 made of a printable polymeric material, such as polythiophene, and an insulator layer 6 made of polyhydroxystyrene (PSH/PVP) are printed thereon over the whole area. A gate electrode layer 4 is situated on the insulator layer 6, said gate electrode layer only partly covering the channel 7 (see FIG. 2 b) between the source electrode layer 2 and the drain electrode layers 3 a, 3 b. Alternatively, the drain electrode layers could also be embodied here in such a way that they are merely embodied in the form of four lines lying next to one another which in each case project into the comb-shaped source electrode layer 2 and are not electrically conductively connected to one another. The source electrode layer could also be embodied merely in the form of lines, such that a plurality of source electrode layers, here in particular five source electrode layers, could be present without electrical contact next to one another on the carrier substrate 10.
FIG. 2 b shows the simplified plan view of the field effect transistor 1′ and the carrier substrate 10 from FIG. 2 a, wherein the illustration of the semiconductor layer 5 and of the insulator layer 6 has been disregarded. Consequently, FIG. 2 b reveals the position of the comb-shaped source electrode layer 2 having five comb teeth relative to the two comb-shaped 5 drain electrode layers 3 a, 3 b each having two comb teeth, which are arranged in a manner intermeshed with one another on the carrier substrate 10. Situated between the source electrode layer 2 and the drain electrode layers 3 a, 3 b is the channel 7, which exhibits a meandering course as seen perpendicular to the plane of the carrier substrate 10. The semiconductor layer 5 arranged on the source electrode layer 2 and the drain electrode layers 3 a, 3 b and the insulator layer 6 are not depicted here, in order to be able to demonstrate the position and area extent of the gate electrode layer 4 with respect to the channel 7. It is evident that the gate electrode layer 4 only partly covers the channel 7. A positional displacement of the gate electrode layer 4 with regard to its orientation toward the source electrode layer 2 and the drain electrode layers 3 a, 3 b in the identified x direction on account of register tolerances during the formation of the gate electrode layer 4 does not affect the electrical properties of the field effect transistor 1′, since the area extent of the gate electrode layer 4 is chosen such that even in the event of a production-dictated maximum possible displacement of the gate electrode layer 4 in the identified x direction, a position of parts of the gate electrode layer 4 outside the channel region delimited by the source and drain electrode layers 2, 3 a, 3 b is not possible. Alternatively, the field effect transistor in accordance with FIGS. 2 a and 2 b can also be embodied with three or more drain electrode layers, wherein the gate electrode layer covers at least one drain electrode layer, or else a plurality of drain electrode layers simultaneously. However, at least one drain electrode layer and/or a channel region are/is present as a surplus or unused structure.
FIG. 3 shows in the simplified plan view a logic component in the form of an inverter component having a field effect transistor 1′″ and a charging component 9. The inverter input of the inverter component is identified by the reference symbol 8. In order to better visualize the position of the diverse electrode layers with respect to one another, the illustration of the semiconductor layers and of the insulator layers has been dispensed with in FIG. 3. The field effect transistor 1′″ has a source electrode layer 2 and four drain electrode layers 3 a, 3 b, 3 c, 3 d that are electrically insulated from one another. The source electrode layer 2 can be connected to a first supply voltage U1. The gate electrode layer 4 of the field effect transistor 1′″ only covers the two central drain electrode layers 3 a, 3 b, while the two outer drain electrode layers 3 a, 3 d are not covered and are thus unused. A positional inaccuracy of the gate electrode layer 4 on account of register tolerances can be compensated for in the y directions by the surplus drain electrode layers 3 a, 3 d. A positional inaccuracy of the gate electrode layer 4 on account of register tolerances in the x directions is compensated for by the increased width of the gate electrode layer 4 relative to the width of the source and drain electrode layers 2, 3 a, 3 b, 3 c, 3 d. The charging component 9 has a first electrode 12 and a second electrode 13, wherein the second electrode 13 can be connected to a supply voltage.
The drain electrode layers 3 b, 3 c are electrically conductively connected to the first electrode 12 of the charging component 9 by means of an interconnect 11. Openings, so-called vias 11 a, are provided in the semiconductor layer and insulator layer (not separately illustrated), in order to be able to produce an electrically conductive connection between the source/drain plane and the gate plane. The interconnect 11 that electrically conductively connects the drain electrode layers 3 b, 3 c to the second electrode 13 of the charging component 9 by means of at least one of the vias 11 a arranged thereabove or therebelow forms the gate electrode layer 4 of the field effect transistor 1″, or the inverter input 8 of the inverter component, or is electrically conductively connected thereto directly or indirectly by means of vias.
FIG. 4 shows in the simplified plan view an electric circuit having a first logic component in the form of a first inverter component 100, enclosed by a line in order to identify the associated structural elements, and a second logic component, which is embodied in the form of a second inverter component 100′ and is likewise enclosed by a line in order to identify the associated structural elements. In order to better visualize the position of the diverse electrode layers with respect to one another, the illustration of the semiconductor layers and of the insulator layers has been dispensed with in FIG. 4.
The first inverter component 100 has a field effect transistor 1′ in accordance with FIGS. 2 a, 2 b and a first charging component 9′. The source electrode layer 2 (see FIG. 2 b) of the first field effect transistor 1′ is connected to a first supply voltage U₁. The first charging component 9′ has a first electrode 12′ and a second electrode 13′, wherein the second electrode 13′ is connected to a second supply voltage U₂. The inverter input of the first inverter component 100 is identified by the reference symbol 8′. The first drain electrode layer 3 a (see FIG. 2 b) of the first field effect transistor 1′ is electrically conductively connected to the first electrode 12′ of the first charging component 9′ by means of an interconnect 11′.
The second inverter component 100′ has a field effect transistor 1″, which is embodied structurally identically to the first inverter component 1′, and a second charging component 9″, which is embodied structurally identically to the first charging component 9″, and has a first electrode 12″ and a second electrode 13″, which is connected to a second supply voltage U₂. The inverter input of the second inverter component 100′ is identified by the reference symbol 8″. The first drain electrode layer 3 a (see FIG. 2 b) of the second field effect transistor 1″ is electrically conductively connected to the first electrode 12″ of the second charging component 9″ by means of an interconnect 11″
Openings, so-called vias 11 a′, 11 a″, are provided in the semiconductor layer and insulator layer (not separately illustrated), in order to be able to produce an electrically conductive connection between the source/drain plane and the gate plane.
The interconnect 11″ of the second inverter component 100′ that electrically conductively connects the first drain electrode layer 3 a (see FIG. 2 b) of the second field effect transistor 1″ to the first electrode 12″ of the second charging component 9″ by means of at least one of the two vias 11 a″ arranged thereabove or therebelow forms the gate electrode layer 4 of the first field effect transistor 1′, or the inverter input 8′ of the first inverter component 100, or is electrically conductively connected thereto directly or indirectly by means of vias.
The interconnect 11′ of the first inverter component 100 that electrically conductively connects the first drain electrode layer 3 a (see FIG. 2 b) of the first field effect transistor 1′ to the first electrode 12′ of the first charging component 9′ is electrically conductively connected to a further electrical component by means of at least one of the two vias 11 a′ arranged thereabove or therebelow.
The interconnects 11′, 11″ of the first and second inverter components 100, 100′ are formed here simultaneously with the formation of the gate electrode layers 4.
FIG. 5 shows in the simplified plan view a similar electric circuit to FIG. 4. The electric circuit has a first logic component in the form of a first inverter component 101, enclosed by a line in order to identify the associated structural elements, and a second logic component in the form of a second inverter component 101′, which is likewise enclosed by a line in order to identify the associated structural elements. In order to better visualize the position of the diverse electrode layers with respect to one another, the illustration of the semiconductor layers and of the insulator layers has been dispensed with here, too, as already in FIG. 4.
The first inverter component 101 has a field effect transistor 1′ in accordance with FIGS. 2 a, 2 b and a first charging component 9 a and a second charging 25 component 9 b. The source electrode layer 2 (see FIG. 2 b) of the first field effect transistor 1′ is connected to a first supply voltage U. The first charging component 9 a has a first electrode 12 a and a second electrode 13 a, wherein the second electrode 13 a is connected to a second supply voltage U₂. The second charging component 9 b has a first electrode 12 b and a second electrode 13 b, wherein the second electrode 13 b is likewise connected to the second supply voltage U₂. The inverter input of the first inverter component 101 is identified by the reference symbol 8′. The first drain electrode layer 3 a (see FIG. 2B) of the first field effect transistor 1′ is electrically conductively connected to the first electrode 12 b of the second charging component 9 b by means of an interconnect 11′.
The second inverter component 101′ has a field effect transistor 1″, which is embodied structurally identically to the first inverter component 1′, and a third charging component 9 a′, which is embodied structurally identically to the first charging component 9 a, and a fourth charging component 9 b′, which is embodied structurally identically to the second charging component 9 b. The third charging component 9 a′ has a first electrode 12 a′ and a second electrode 13 a′, which is connected to a second supply voltage U₂. The fourth charging component 9 b′ has a first electrode 12 b′ and a second electrode 13 b′, which is connected to the second supply voltage U₂. The inverter input of the second inverter component 101′ is identified by the reference symbol 8″. The first drain electrode layer 3 a (see FIG. 2 b) of the second field effect transistor 1″ is electrically conductively connected to the first electrode 12 b′ of the fourth charging component 9 b′ by means of an interconnect 11″.
Openings, so-called vias 11 a′, 11 a″, are provided in the semiconductor layer and insulator layer (not separately illustrated), in order to be able to produce an electrically conductive connection between the source/drain plane and the gate plane.
The interconnect 11″ of the second inverter component 101′ that electrically conductively connects the first drain electrode layer 3 a (see FIG. 2 b) of the second field effect transistor I″ to the first electrode 12 b′ of the fourth charging component 9 b′ by means of at least one of the two vias 11 a″ arranged thereabove or therebelow forms the gate electrode layer 4 of the first field effect transistor 1′, or the inverter input 8′ of the first inverter component 101, or is electrically conductively connected thereto directly or indirectly by means of vias.
The interconnect 11′ of the first inverter component 101 that electrically conductively connects the first drain electrode layer 3 a (see FIG. 2 b) of the first field effect transistor 1′ to the first electrode 12 b of the second charging component 9 b is electrically conductively connected to a further electrical component by means of at least one of the two vias 11 a′ arranged thereabove or therebelow.
The interconnects 11′, 11″ of the first and second inverter components 101, 101′ are formed here simultaneously with the formation of the gate electrode layers 4. Since no electrically conductive connection is formed between the first charging component 9 a and the field effect transistor 1′, and between the charging component 9 a′ and the field effect transistor 1″, no leakage currents occur here either.
FIG. 6 shows in the simplified plan view a similar electric circuit to FIG. 5. The electric circuit has a first logic component in the form of a first inverter component 101, enclosed by a line in order to identify the associated structural elements, and a second logic component in the form of a second inverter component 101′, which is likewise enclosed by a line in order to identify the associated structural elements. In order to better visualize the position of the diverse electrode layers with respect to one another, the illustration of the semiconductor layers and of the insulator layers has been dispensed with here, too, as already in FIGS. 4 and 5.
The first inverter component 101 has a field effect transistor 1′ in accordance with FIGS. 2 a, 2 b and a first charging component 9 a and a second charging component 9 b. The source electrode layer 2 (see FIG. 2 b) of the first field effect transistor 1′ is connected to a first supply voltage U₁. The first charging component 9 a has a first electrode 12 a and a second electrode 13 a. The second charging component 9 b has a first electrode 12 b and a second electrode 13 b, wherein the second electrode 13 b is connected to a second supply voltage U₁. The inverter input of the first inverter component 101 is identified by the reference symbol 8′. The first drain electrode layer 3 a (see FIG. 2 b) of the first field effect transistor 1′ is electrically conductively connected to the first electrode 12 b of the second charging component 9 b by 10 means of a via 11 a′.
The second inverter component 101′ has a field effect transistor 1″, which is embodied structurally identically to the first inverter component 1′, and furthermore a third charging component 9 a′, which is embodied structurally identically to the first charging component 9 a, and a fourth charging component 9 b′, which is embodied structurally identically to the second charging component 9 b. The third charging component 9 a′ has a first electrode 12 a′ and a second electrode 13 a′. The fourth charging component 9 b′ has a first electrode 12 b′ and a second electrode 13 b′, which is connected to a second supply voltage U₂. The inverter input of the second inverter component 101′ is identified by the reference symbol 8″. The first drain electrode layer 3 a (see FIG. 2 b) of the second field effect transistor 1″ is electrically conductively connected to the first electrode 12 b′ of the fourth charging component 9 b′ by means of a via 11 a″.
The vias 11 a′, 11 a″ form openings in the semiconductor layer and insulator layer (not separately illustrated), in order to be able to Produce an electrically conductive connection between the source/drain plane and the gate plane.
The first drain electrode layer 3 a (see FIG. 2 b) of the second field effect transistor 1″, which layer is electrically conductively connected to the first electrode 12 b′ of the fourth charging component 9 b′, is furthermore electrically conductively connected, by means of a via 11 a″, to the gate electrode layer 4 of the first field effect transistor 1′ or the inverter 5 input 8′ of the first inverter component 101.
The first drain electrode layer 3 a (see FIG. 2 b) of the first field effect transistor 1′, which layer is electrically conductively connected to the first electrode 12 b of the second charging component 9 b, is furthermore electrically conductively connected to a further electrical component by means of a via 11 a′.
Since, unlike in FIG. 5, an electrically conductive connection is formed between the first charging component 9 a and the field effect transistor 1′, and between the charging component 9 a′ and the field effect transistor 1″, small leakage currents occur here.
FIG. 7 shows in plan view a preferred layout for a printed electric circuit in accordance with FIG. 6 on a carrier substrate 10, wherein a multiplicity of logic components comprising field effect transistors 1 and charging components 9 are provided one after another in series in the printing direction (see the arrow on the far right). On the left-hand side of the carrier substrate 10, the electric circuit has a multiplicity of field effect transistors 1 which are embodied similarly to FIG. 1 b on the carrier substrate 10 with in each case a source electrode layer 2, a drain electrode layer 3, thereon a semiconductor layer (not visible here) and thereon an insulator layer 6, and in each case a gate electrode layer 4 on the insulator layer 6. The source electrode layer 2 of the field effect transistors 1 is connected to a first supply voltage U₁. Non-connected source/drain regions, that is to say channel regions not covered by a gate electrode layer 4, between source and drain electrode layers 2, 3 are further discernible.
A multiplicity of charging components 9 each having a first electrode 12 and a second electrode 13 are situated on the right-hand side of the carrier substrate 10, wherein the second electrode 13 is connected to a second supply voltage U₂.
In order to better visualize the position of the diverse electrode layers 2, 3, 4, 12, 13 with respect to one another, here the electrode layers 2, 3, 12, 13 arranged below the insulator layer 6 or below the insulator layer 6 and if appropriate the semiconductor layer are visible through the insulator layer 6.
A respective drain electrode layer 3 is electrically conductively connected to a first electrode 12 of a charging component by means of an interconnect 14. Situated between the field effect transistors 1 on the left-hand side and the charging components 9 on the right-hand side of the carrier substrate 10 is a strip-shaped opening in the printing direction, in which opening no semiconductor layer and no insulator layer 6 are arranged, rather the carrier substrate 10 with interconnects 14 printed thereon can be directly discerned. Said strip-shaped opening forms a via 11 a, in which an electrically conductive connection between interconnects 14 and the gate electrode layer 4 printed onto the insulator layer 6 is formed by means of an interconnect 11. An electrically conductive connection of the respective gate electrode layer 4 to charging components 9 on the right-hand side and to drain electrode layers 3 of the adjacent field effect transistor 1 that are electrically conductively connected to precisely said charging components 9 is produced in this case.
Since a respective electrically conductive connection or interconnect 14 is formed between all of the first electrodes 12 of the charging components 9 and the drain electrode layers 3 of the field effect transistors 1, small leakage currents occur here in the region of non-connected source/ drain electrode layers 2, 3.
The field effect transistor according to the invention can thus be embodied in different forms and layouts and be used for forming a multiplicity of different logic components and electric circuits.

Claims

1. A field effect transistor (1, 1′, 1″, 1′″) comprising at least one source electrode layer (2) and at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d) arranged in the same plane, a semiconductor layer (5), an insulator layer (6) and a gate electrode layer (4),

characterized

in that the gate electrode layer (4), as seen perpendicular to the plane of the at least one source electrode layer (2) and the at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d), only partly covers a channel (7) arranged between the at least one source electrode layer (2) and the at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d).

2. The field effect transistor as claimed in claim 1,

characterized

in that the channel (7) extends between the at least one source electrode layer (2) and at least two drain electrode layers (3 a, 3 b, 3 c, 3 d), wherein the drain electrode layers (3 a, 3 b, 3 c, 3 d) are embodied in a manner electrically insulated from one another.

3. The field effect transistor as claimed in either of claims 1 and 2,

characterized

in that the gate electrode layer (4), as seen perpendicular to the plane of the at least one source electrode layer (2) and the at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d), covers an area of 10 to 90%, in particular of 25 to 50%, of the channel (7).

4. The field effect transistor as claimed in any of claims 1 to 3,

characterized

in that the gate electrode layer (4) is embodied as a bottom gate electrode or as a top gate electrode.

5. The field effect transistor as claimed in any of claims 1 to 4,

characterized

in that the field effect transistor (1, 1′, 1″, 1′″) comprises at least one organic functional layer.

6. The field effect transistor as claimed in claim 5,

characterized

in that at least one organic functional layer is formed by printing.

7. The field effect transistor as claimed in either of claims 5 and 6,

characterized

in that the semiconductor layer (5) and/or the insulator layer (6) are/is embodied as an organic functional layer.

8. The field effect transistor as claimed in any of claims 1 to 7,

characterized

in that the source electrode layer (2), the at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d), the semiconductor layer (5), the insulator layer (6) and the gate electrode layer (4) are arranged on a carrier substrate (10).

9. The field effect transistor as claimed in claim 8,

characterized

in that the carrier substrate (10) is formed from a flexible plastic film, in particular from polyester, polyethylene, polyethylene terephthalate or polyimide.

10. A logic component having at least one field effect transistor (1, 1′, 1″, 1′″) as claimed in any of claims 1 to 9.

11. The logic component as claimed in claim 10,

characterized

in that the logic component is a structural element from the group comprising inverter components (100, 100′, 101, 101′), NOR gates, NAND gates, AND gates and OR gates.

12. The logic component as claimed in claim 11,

characterized

in that the logic component is an inverter component (100, 100′, 101, 101′) comprising a field effect transistor (1, 1′, 1″, 1′″) and at least one charging component (9, 9′, 9″, 9 a, 9 b, 9 a′, 9 b′) having at least one first electrode (12, 12′, 12″, 12 a, 12 b, 12 a′, 12 b′) and at least one second electrode (13, 13′, 13″, 13 a, 13 b, 13 a′, 13 b′), wherein the at least one second electrode (13, 13′, 13″, 13 a, 13 b, 13 a′, 13 b′) is embodied for connection to a supply voltage, and wherein at least one of the first electrodes (12, 12′, 12″, 12 a, 12 b, 12 a′, 12 b′) is electrically conductively connected to at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d) of the field effect transistor (1, 1′, 1″, 1′″) which, as seen perpendicular to the plane of the at least one source electrode layer (2) and the at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d), overlaps the gate electrode layer (4) at least in regions.

13. The logic component as claimed in claim 12,

characterized

in that the electrically conductive connection between the at least one first electrode (12, 12′, 12″, 12 a, 12 b, 12 a′, 12 b′) and the at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d) of the field effect transistor (1, 1′, 1′″) is formed by at least one interconnect (11, 11′, 11″) and/or at least one via (11 a, 11 a′, 11 a″).

14. The logic component as claimed in either of claims 12 and 13,

characterized

in that the inverter component (100, 100′, 101, 101′) comprises a field effect transistor (1, 1′, 1″, 1′″) having at least one source electrode layer (2) and at least two drain electrode layers (3 a, 3 b, 3 c, 3 d) and also comprises at least two charging components (9′, 9″, 9 a, 9 b, 9 a′, 9 b′) having at least two first electrodes (12′, 12″, 12 a, 12 b, 12 a′, 12 b′), wherein a respective one of the drain electrode layers (3 a, 3 b, 3 c, 3 d) is electrically conductively connected to a respective one of the first electrodes (12′, 12″, 12 a, 12 b, 12 a′, 12 b′).

15. An electric circuit comprising at least one logic component as claimed in any of claims 10 to 14.

16. The electric circuit as claimed in claim 15,

characterized

in that the electric circuit comprises at least two inverter components (100, 100′, 101, 101′).

17. The electric circuit as claimed in claim 16,

characterized

in that a first inverter component (100, 101) has a first gate electrode layer, and in that the first gate electrode layer is electrically conductively connected to the at least one interconnect (11″) and/or the at least one via (11 a″) of a second inverter component (100′, 101′) which, as claimed in claim 13, electrically conductively connects the at least one drain electrode layer and the at least one first electrode (12″, 12 b′) of the charging component (9″, 9 b′) of the second inverter component (100′, 101′).

18. The electric circuit as claimed in claim 17,

characterized

in that the at least one interconnect (11″) is arranged on the plane of the at least one source electrode layer (2) and the at least one drain electrode layer (3, 3 a, 3 b, 3 c, 3 d), and in that the first gate electrode layer and the at least one interconnect (11″) are electrically conductively connected to one another by means of at least one via (11 a″) in the semiconductor layer (5) and the insulator layer (6).

19. The electric circuit as claimed in claim 17,

characterized

in that the first gate electrode layer, as claimed in claim 13, is electrically conductively connected to the at least one drain electrode layer and the at least one first electrode (12 b′) of the second inverter component (101′) by means of at least one via (11 a″) in the semiconductor layer (5) and the insulator layer (6).

20. An electric circuit, more particularly as claimed in any of claims 15 to 19, on a carrier substrate (10), wherein at least one first component and at least one second component, which are electrically conductively connected to one another, are formed on the carrier substrate (10),

characterized

in that at least two second components are formed, in that an electrically conductive functional layer of the first component is electrically conductively connected to an electrically conductive functional layer of one of the at least two second components by means of a printed interconnect, wherein the at least one first component is alternatively connected to one or the other of the at least two second components and at least one unused, surplus second component is thus present.

21. The electric circuit as claimed in claim 20,

characterized

in that the at least two second components are arranged one after another and adjacent to one another in the printing direction of the interconnect.

22. The electric circuit as claimed in either of claims 20 and 21,

characterized

in that at least two first components are formed, and in that one of the first components is electrically conductively connected to one of the second components by means of the interconnect, such that at least one first component and at least one second component are present in unused and surplus fashion.

23. The electric circuit as claimed in claim 22,

characterized

in that the at least two first components are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.

24. The electric circuit as claimed in any of claims 20 to 23,

characterized

in that a field effect transistor (1′, 1″, 1′″) as claimed in any of claims 1 to 9 is embodied as first component, said transistor having at least one drain electrode layer as electrically conductive functional layer.

25. The electric circuit as claimed in claim 24,

characterized

in that a charging component (9 a, 9 b; 9 a′, 9 b′) having at least one first electrode (12 a, 12 b, 12 a′, 12 b′) as electrically conductive functional layer and at least one second electrode (13 a, 13 b, 13 a′, 13 b′) is embodied as second component, wherein the at least one second electrode (13 a, 13 b, 13 a′, 13 b′) is embodied for connection to a supply voltage.

26. A method for producing an electric circuit, more particularly as claimed in any of claims 20 to 25, on a carrier substrate (10), wherein at least one first component and at least one second component, which are electrically conductively connected to one another, are formed on the carrier substrate (10),

characterized

in that at least two second components are formed, in that an electrically conductive functional layer of the first component is electrically conductively connected to an electrically conductive functional layer of one of the at least two second components by printing an interconnect, wherein the at least one first component, depending on the register tolerance during the printing of the interconnect, is alternatively connected to one or the other of the at least two second components and at least one second component thus remains unused.

27. The method as claimed in claim 26,

characterized

in that the at least two second components are arranged one after another and adjacent to one another as seen in the printing direction of the interconnect.

28. The method as claimed in either of claims 26 and 27,

characterized

in that at least two first components are formed, and in that one of the first components is electrically conductively connected to one of the second components by means of the interconnect, such that at least one first component and at least one second component remain unused.

29. The method as claimed in claim 28,

characterized