US20130025926A1 - Circuit substrate - Google Patents
Circuit substrate Download PDFInfo
- Publication number
- US20130025926A1 US20130025926A1 US13/644,667 US201213644667A US2013025926A1 US 20130025926 A1 US20130025926 A1 US 20130025926A1 US 201213644667 A US201213644667 A US 201213644667A US 2013025926 A1 US2013025926 A1 US 2013025926A1
- Authority
- US
- United States
- Prior art keywords
- layer
- conductive
- circuit substrate
- inner pad
- conductive block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09545—Plated through-holes or blind vias without lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
- H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- FIGS. 5A and 5B are cross-sectional views showing final two steps of a process of fabricating a circuit substrate according to another embodiment of the present invention.
- FIG. 8 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention.
- the covering layer 150 is removed.
- the covering layer 150 can be peeled from the dielectric layer 130 after weakening the bonding between the covering layer 150 and the dielectric layer 130 .
- the outer pad 144 is exposed after removing the covering layer 150 to be connected with a chip or a package.
- the thickness of the outer pad 144 is related to the covering layer 150 ; namely, the thickness of the outer pad 144 can be controlled by adjusting the thickness of the covering layer 150 .
Abstract
A circuit substrate having a base layer, a patterned conductive layer, a dielectric layer and a conductive block is provided. The patterned conductive layer is disposed on the base layer and having an inner pad. The dielectric layer is disposed on the base layer and covering the patterned conductive layer. The conductive block penetrates the dielectric layer, the conductive block being substantially coplanar with the dielectric layer and connecting the inner pad.
Description
- This application is a Divisional of and claims the priority benefit of U.S. patent application Ser. No. 12/835,085, filed on Jul. 13, 2010, now pending, which claims the priority benefit of U.S. provisional application Ser. No. 61/315,408, filed on Mar. 19, 2010, and also claims the priority benefits of Taiwan application serial no. 99116309, filed on May 21, 2010 and Taiwan application serial no. 98137833, filed on Nov. 6, 2009. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of the Invention
- The present invention relates to a circuit substrate and fabricating method thereof. More particularly, the present invention relates to a circuit substrate with a pad and a conductive block formed in one piece with each other and the fabricating method thereof.
- 2. Description of Related Art
- In current semiconductor package technology, a circuit substrate is one of the most frequently used components. A conventional circuit substrate is mainly composed of a plurality of patterned conductive layers and a plurality of dielectric layers alternately stacked to one another. In addition, the patterned conductive layers are electrically connected through a plurality of conductive vias. As the integration of traces in the circuit substrate increases, how to utilize the limited space of circuit substrate effectively in circuit layout has become an important subject.
- The present invention further provides a circuit substrate including a base layer, a patterned conductive layer, a dielectric layer and a conductive block. The patterned conductive layer having an inner pad is disposed on the base layer. The dielectric layer is disposed on the base layer and the dielectric layer covers the patterned conductive layer. The conductive block penetrates the dielectric layer, and the conductive block is substantially coplanar with the dielectric layer and connected the inner pad.
- The present invention provides a method comprising following steps for fabricating a circuit substrate. A base layer, a patterned conductive layer, a dielectric layer and a covering layer are provided, wherein the patterned conductive layer having an inner pad is disposed on the base layer, the dielectric layer is disposed on the base layer and covers the patterned conductive layer, and the covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second layer is provided, wherein the conductive block, the outer pad and the surplus layer are formed in one piece together. Then, the patterned mask, the surplus layer and the covering layer are removed.
- In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanying figures are described in detail below.
- The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIGS. 1A through 1I are cross-sectional views showing a process of fabricating a circuit substrate according to an embodiment of the present invention. -
FIG. 2 is a perspective view showing the inner pad and the conductive block ofFIG. 1 . -
FIG. 3 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. -
FIG. 4 is a perspective view showing the inner pad and the conductive block ofFIG. 3 . -
FIGS. 5A and 5B are cross-sectional views showing final two steps of a process of fabricating a circuit substrate according to another embodiment of the present invention. -
FIG. 6 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. -
FIG. 7 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. -
FIG. 8 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. -
FIGS. 1A through 1I are cross-sectional views showing a process of fabricating a circuit substrate according to an embodiment of the present invention. First, as shown inFIG. 1A , abase layer 110, a patternedconductive layer 120, adielectric layer 130 and a coveringlayer 150 are provided. Thebase layer 110 may be a circuit layer of a chip, a circuit layer of a chip carrier, or a circuit layer of a printed circuit board. The patternedconductive layer 120 is disposed in thebase layer 110 and the patternedconductive layer 120 has aninner pad 122. Thedielectric layer 130 is disposed on thebase layer 110 and thedielectric layer 130 covers the patternedconductive layer 120. The coveringlayer 150 is disposed on thedielectric layer 130. The material of the coveringlayer 150 may be nonmetal such as organic material or may be metal used as a barrier. Particularly, in an embodiment, the coveringlayer 150 is made of the material capable of being peeled from thedielectric layer 130. - In the present embodiment, the
dielectric layer 130 can be made of resin, and thedielectric layer 130 and thecovering layer 150 thereon are laminated with thebase layer 110 and the patternedconductive layer 120, such that thedielectric layer 130 is located between thebase layer 110 and the coveringlayer 150 and covers the patternedconductive layer 120. In other words, in the present embodiment, a double layered structure comprising thedielectric layer 130 and thecovering layer 150 is provided and laminated with thebase layer 110 and the patternedconductive layer 120 thereon. For the fabrication process of the present invention, the double layered structure including thedielectric layer 130 and the coveringlayer 150 facilitates simplifying the fabricating process. In another embodiment, thedielectric layer 130 and thecovering layer 150 can be formed on thebase layer 110 in sequence to cover the patternedconductive layer 120. - Referring to
FIG. 1B , a part of the coveringlayer 150 is removed by dry etching to form afirst opening 152. In the present embodiment, the material of the coveringlayer 150 is nonmetal, and the dry etching for removing the part of the coveringlayer 150 may be laser ablation or plasma etching. In another embodiment, if the material of the coveringlayer 150 is metal, patterning process including photolithography and etching is adopted to form thefirst opening 152 rather than laser ablation. Comparing with the patterning process, the dry etching (especially laser ablation) requires less processing time in forming thefirst opening 152. - Then, referring to
FIG. 1B again, a part of thedielectric layer 130 exposed by thefirst opening 152 is removed to form adielectric opening 132, wherein thedielectric opening 132 exposes a part of theinner pad 122. - In the present embodiment, if the material of the
covering layer 150 is nonmetal, the part of thedielectric layer 130 exposed by thefirst opening 152 can be removed by dry etching. The dry etching used for removing a portion of thedielectric layer 130 is, for example, laser ablation or plasma etching. - Referring to
FIG. 1C , aconductive seed layer 140 a is formed on the inner wall of thedielectric opening 132, the inner wall of thefirst opening 152, and thecovering layer 150. The material of theconductive seed layer 140 a is copper, for example. - Referring to FIG. ID, a
patterned mask 160 having asecond opening 162 to expose thefirst opening 152, thedielectric opening 132 and a part of theinner pad 122 is formed on a part of theconductive seed layer 140 a located on thecovering layer 150. - Next, referring to
FIG. 1E , aconductive structure 140 is formed by plating in using theconductive seed layer 140 a for transmitting current. The material of theconductive structure 140 is copper, for example. Theconductive structure 140 includes aconductive block 142 filling thedielectric opening 132 and covering a part of theinner pad 122, anouter pad 144 filling thefirst opening 152, and asurplus layer 146 filling thesecond opening 162. Theconductive block 142, theouter pad 144 and thesurplus layer 146 are formed by plating to provide an integrative structure. - Then, referring to
FIG. 1F , the patternedmask 160 is removed. - Referring to
FIG. 1G , thesurplus layer 146 and the part of theconductive seed layer 140 a located on thecovering layer 150 are removed. In the present embodiment, thesurplus layer 146 and the part of theconductive seed layer 140 a located on thecovering layer 150 can be removed by grinding, polishing or etching. - Referring to
FIG. 1H , thecovering layer 150 is removed. In the present embodiment, thecovering layer 150 can be peeled from thedielectric layer 130 after weakening the bonding between the coveringlayer 150 and thedielectric layer 130. It is noted that theouter pad 144 is exposed after removing thecovering layer 150 to be connected with a chip or a package. In addition, the thickness of theouter pad 144 is related to thecovering layer 150; namely, the thickness of theouter pad 144 can be controlled by adjusting the thickness of thecovering layer 150. - Referring to
FIG. 1I , asurface passivation layer 170 may further be formed on theouter pad 144 and a part of theconductive seed layer 140 a. The material of thesurface passivation layer 170 may comprises Ni/Au stacked layer, Ni/Pd/Au stacked layer, Ni/Sn stacked layer, Pd, Au or the alloy thereof, or thesurface passivation layer 170 may be an organic solderability preservation (OSP). -
FIG. 2 is a perspective view showing the inner pad and the conductive block ofFIG. 1 . Referring toFIGS. 1I and 2 , the outer diameter of theinner pad 122 is greater than that of theconductive block 142. In addition, the patternedconductive layer 120 further has aninner trace 124, wherein theinner pad 122 is formed of an end portion of theinner trace 124, and the outer diameter of theinner pad 122 is greater than a line width of theinner trace 124. In the present embodiment, theinner trace 124 may be served as a signal trace, a grounding trace or a power trace. -
FIG. 3 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention.FIG. 4 is a perspective view showing the inner pad and the conductive block ofFIG. 3 . Referring toFIGS. 3 and 4 , the present embodiment is similar to the above embodiment shown inFIGS. 1A through 1I except that an outer diameter of theinner pad 122 is smaller than an outer diameter of theconductive block 142 such that theconductive block 142 encompasses theinner pad 122. In addition, the patternedconductive layer 120 further has aninner trace 124, wherein theinner pad 122 is formed of an end portion of theinner trace 124, and the outer diameter of theinner pad 122 is substantially equal to a line width of theinner trace 124. -
FIGS. 5A and 5B are cross-sectional views showing final two steps of a process of fabricating a circuit substrate according to another embodiment of the present invention. Referring toFIG. 5A , following the steps as shown inFIGS. 1A through 1H , theouter pad 144 and a part of theconductive seed layer 140 a are removed such that theconductive block 142 is substantially coplanar with thedielectric layer 130 and connected with a part of theinner pad 122 via theconductive seed layer 140 a. Referring toFIG. 5B , finally, asurface passivation layer 170 may be formed on theouter pad 142 and a part of theconductive seed layer 140 a. -
FIG. 6 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. Referring toFIG. 6 , the present embodiment is similar to the above embodiment shown inFIG. 5B except that an outer diameter of theinner pad 122 is smaller than an outer diameter of theconductive block 142 such that theconductive block 142 encompasses theinner pad 122.FIG. 4 shows the same concept. -
FIG. 7 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. Being different from the aforementioned embodiment ofFIG. 1I , the present embodiment increases the inner diameter of thefirst opening 152 by performing another etching process to broaden thefirst opening 152 after forming thefirst opening 152 and thedielectric opening 132 inFIG. 1B , such that the outer diameter of theouter pad 144 later formed inFIGS. 1C through 1E is greater than that of theconductive block 142. -
FIG. 8 is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. Referring toFIG. 8 , the present embodiment is similar to the above embodiment shown inFIG. 7 except that an outer diameter of theinner pad 122 is smaller than an outer diameter of theconductive block 142 such that theconductive block 142 encompasses theinner pad 122.FIG. 4 shows the same concept. - In summary, the present invention forms an opening in the covering layer by dry etching so as to reduce the processing time and facilitate the formation of the outer pad. In addition, the thickness of the outer pad can be precisely controlled through the covering layer. The conductive block and the outer pad are formed in one piece, such that misalignment between the outer pad and the conductive block during plural patterning steps of the conventional process can be prevented. Furthermore, the conductive block embedded in the dielectric layer can replace the outer pad to serve as an electrode of the circuit substrate.
- Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.
Claims (5)
1. A circuit substrate, comprising:
a base layer;
a patterned conductive layer disposed on the base layer and having an inner pad;
a dielectric layer disposed on the base layer and covering the patterned conductive layer; and
a conductive block penetrating the dielectric layer, the conductive block being substantially coplanar with the dielectric layer and connecting the inner pad.
2. The circuit substrate as claimed in claim 1 , further comprising:
a surface passivation layer disposed on the conductive block.
3. The circuit substrate as claimed in claim 1 , wherein an outer diameter of the inner pad is greater than an outer diameter of the conductive block such that the inner pad and the conductive block together form a structure having a cross-section in an inverted-T-shape profile.
4. The circuit substrate as claimed in claim 1 , wherein an outer diameter of the inner pad is smaller than an outer diameter of the conductive block such that the conductive block encompasses the inner pad.
5. The circuit substrate as claimed in claim 1 , wherein the patterned conductive layer further has an inner trace, and an end portion of the inner trace forms the inner pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/644,667 US20130025926A1 (en) | 2009-11-06 | 2012-10-04 | Circuit substrate |
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
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TW098137833A TWI412308B (en) | 2009-11-06 | 2009-11-06 | Circuit substrate and fabricating process thereof |
TW98137833 | 2009-11-06 | ||
US31540810P | 2010-03-19 | 2010-03-19 | |
TW99116309A TWI403236B (en) | 2010-03-19 | 2010-05-21 | Process for fabricating circuit substrate, and circuit substrate |
TW99116309 | 2010-05-21 | ||
US12/835,085 US8302298B2 (en) | 2009-11-06 | 2010-07-13 | Process for fabricating circuit substrate |
US13/644,667 US20130025926A1 (en) | 2009-11-06 | 2012-10-04 | Circuit substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/835,085 Division US8302298B2 (en) | 2009-11-06 | 2010-07-13 | Process for fabricating circuit substrate |
Publications (1)
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US20130025926A1 true US20130025926A1 (en) | 2013-01-31 |
Family
ID=43973305
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US12/835,085 Active 2031-03-25 US8302298B2 (en) | 2009-11-06 | 2010-07-13 | Process for fabricating circuit substrate |
US13/644,667 Abandoned US20130025926A1 (en) | 2009-11-06 | 2012-10-04 | Circuit substrate |
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US12/835,085 Active 2031-03-25 US8302298B2 (en) | 2009-11-06 | 2010-07-13 | Process for fabricating circuit substrate |
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WO2017039866A1 (en) * | 2015-08-31 | 2017-03-09 | Intel Corporation | Electronic package and method forming an electrical package |
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TWI412308B (en) * | 2009-11-06 | 2013-10-11 | Via Tech Inc | Circuit substrate and fabricating process thereof |
TWI436713B (en) | 2010-07-26 | 2014-05-01 | Via Tech Inc | Circuit substrate, fabricating process of circuit substrate |
US9706652B2 (en) * | 2010-12-24 | 2017-07-11 | Lg Innotek Co., Ltd. | Printed circuit board and method for manufacturing same |
JP5913063B2 (en) * | 2012-11-27 | 2016-04-27 | 日本特殊陶業株式会社 | Wiring board |
WO2017199712A1 (en) * | 2016-05-16 | 2017-11-23 | 株式会社村田製作所 | Ceramic electronic component |
CN211858622U (en) * | 2017-06-16 | 2020-11-03 | 株式会社村田制作所 | Circuit board and circuit module |
US20220201852A1 (en) * | 2020-12-18 | 2022-06-23 | Rohm And Haas Electronic Materials Llc | Method for manufactunring a multilayer circuit structure having embedded trace layers |
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- 2010-07-13 US US12/835,085 patent/US8302298B2/en active Active
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US8302298B2 (en) | 2012-11-06 |
US20110108315A1 (en) | 2011-05-12 |
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