US20130057178A1 - Light emitting diode (led) system having application specific integrated circuit (asic) and wireless system - Google Patents

Light emitting diode (led) system having application specific integrated circuit (asic) and wireless system Download PDF

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US20130057178A1
US20130057178A1 US13/670,526 US201213670526A US2013057178A1 US 20130057178 A1 US20130057178 A1 US 20130057178A1 US 201213670526 A US201213670526 A US 201213670526A US 2013057178 A1 US2013057178 A1 US 2013057178A1
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Prior art keywords
led
application specific
specific integrated
asic
light emitting
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US13/670,526
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Trung Tri Doan
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SemiLEDs Optoelectronics Co Ltd
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SemiLEDs Optoelectronics Co Ltd
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Priority claimed from US12/540,523 external-priority patent/US8084780B2/en
Priority claimed from US13/309,718 external-priority patent/US8933467B2/en
Application filed by SemiLEDs Optoelectronics Co Ltd filed Critical SemiLEDs Optoelectronics Co Ltd
Priority to US13/670,526 priority Critical patent/US20130057178A1/en
Assigned to SEMILEDS OPTOELECTONICS CO., LTD. reassignment SEMILEDS OPTOELECTONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DOAN, TRUNG TRI
Publication of US20130057178A1 publication Critical patent/US20130057178A1/en
Priority to TW102140225A priority patent/TW201431433A/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • This disclosure relates generally to light emitting diodes (LED) and more particularly to systems incorporating light emitting diodes (LEDs).
  • LEDs Light emitting diodes
  • LEDs are used in a wide range of electronic devices such as displays, communication devices, and lamps. Advances in LED technology have improved the efficiency and service life of light emitting diodes (LEDs), and have made them smaller and lighter. However, most advances have been directed to the structure and function of the light emitting diodes (LEDs), rather than the associated LED systems. Light emitting diodes (LEDs) are typically part of a LED system that includes driver circuitry and associated electronic devices such as resistors, capacitors, diodes and circuit boards.
  • FIG. 1 illustrates a prior art LED circuit 10 .
  • the prior art LED system 10 includes a LED driver IC 12 , and two light emitting diode (LED) chips 14 in electrical communication with the LED driver IC chip 12 .
  • the LED driver IC 12 is configured to provide driver and functionality circuits for the light emitting diode (LED) chips 14 .
  • the LED driver IC 12 includes a VIN pin, a SEN pin, a DIM pin, a SW pin and a GND pin.
  • the LED system 10 also includes various electronic components including resistors, capacitors, a Schottky diode, and an inductor configured substantially as shown.
  • the LED system 10 requires a relatively complex manufacturing process to mount and interconnect all of the electronic elements. In addition, relatively large amounts of current and power are required to drive the electronic elements, which generates a large amount of heat.
  • FIG. 1 is an electrical schematic diagram of a prior art LED system
  • FIG. 2 is a schematic plan view of a LED system having integrated components and smart functionality
  • FIG. 3 is a schematic plan view of the LED system having additional functionality built into a semiconductor substrate
  • FIG. 4 is a schematic bottom view of the LED system showing circuitry on the substrate
  • FIG. 5 is a schematic plan view of the LED system equivalent to FIG. 2 ;
  • FIG. 5A is a schematic side elevation view of FIG. 5 illustrating a first mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • ASIC application specific integrated circuit
  • LED LED
  • FIG. 5B is a schematic side elevation view of FIG. 5 illustrating a second mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • ASIC application specific integrated circuit
  • LED LED
  • FIG. 6 is a schematic plan view of the LED system having additional functionality equivalent to FIG. 3 ;
  • FIG. 6A is a schematic side elevation view of FIG. 6 illustrating a first mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • ASIC application specific integrated circuit
  • LED LED
  • FIG. 6B is a schematic side elevation view of FIG. 6 illustrating a second mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • ASIC application specific integrated circuit
  • LED LED
  • FIG. 7 is a schematic plan view of the LED system equivalent to FIG. 2 or FIG. 3 ;
  • FIG. 7A is a schematic electrical diagram of the LED system of FIG. 7 ;
  • FIG. 8 is a schematic plan view of the LED system having multiple LED chips electrically connected in series;
  • FIG. 8A is a schematic electrical diagram of the LED system of FIG. 8 ;
  • FIG. 9 is a schematic plan view of the LED system having multiple LED chips electrically connected in parallel;
  • FIG. 9A is a schematic electrical diagram of the LED system of FIG. 9 ;
  • FIG. 10 is an electrical schematic diagram of the application specific integrated circuit (ASIC) of the LED system
  • FIG. 10A is an electrical schematic diagram of a first output configuration of the application specific integrated circuit (ASIC) of the LED system;
  • ASIC application specific integrated circuit
  • FIG. 10B is an electrical schematic diagram of a second output configuration of the application specific integrated circuit (ASIC) of the LED system;
  • ASIC application specific integrated circuit
  • FIG. 11A is a schematic cross sectional view a first encapsulated package for the LED system
  • FIG. 11B is a schematic cross sectional view a second encapsulated package for the LED system
  • FIG. 11C is a schematic cross sectional view a third encapsulated package for the LED system.
  • FIG. 12 is an electrical schematic diagram of a LED integrated circuit formed by the LED system
  • FIG. 13 is a schematic cross sectional view of a light emitting diode (LED) of the LED system.
  • FIG. 14 is a schematic cross sectional view of a light emitting diode (LED) system having an application specific integrated circuit (ASIC) and a wireless receiver.
  • LED light emitting diode
  • ASIC application specific integrated circuit
  • a LED system 30 includes a substrate 32 , a light emitting diode (LED) 34 mounted to the substrate 32 , and an application specific integrated circuit (ASIC) die 36 mounted to the substrate 32 in electrical communication with the light emitting diode (LED) 34 .
  • the LED system 30 includes only one application specific integrated circuit (ASIC) die 36 , it is to be understood that the LED system can include a plurality of application specific integrated circuit (ASIC) dice 36 .
  • the substrate 32 functions as a mounting substrate, and also provides functionality for operating the light emitting diode (LED) 34 and the application specific integrated circuit (ASIC) die 36 as an integrated assembly.
  • the light emitting diode (LED) 34 can comprise a conventional LED fabricated using known processes.
  • LEDs Suitable light emitting diodes
  • ASIC application specific integrated circuit
  • the light emitting diode (LED) 34 can comprise a Group-III nitride based material such as GaN, InGaN, AlGaN, AlInGaN or other (Ga, In or Al) N-based materials.
  • the doped and active layers of the light emitting diode (LED) 34 can be formed on a carrier substrate made of a suitable material such as silicon (Si), silicon carbide (SiC) or sapphire (Al 2 O 3 ).
  • Si silicon
  • SiC silicon carbide
  • Al 2 O 3 Al 2 O 3
  • SEMILEDS, INC. manufactures ultra thin vertical light emitting diodes (VLED) under the trademark MvpLEDTM.
  • the light emitting diode (LED) 34 is shown separately. However, it is to be understood that this configuration for the light emitting diode (LED) 34 is merely exemplary, and other configurations can be employed.
  • the light emitting diode (LED) 34 includes a device substrate 72 , a vertical light emitting diode (VLED) die 74 mounted to the device substrate 72 , and an electrically insulating, light transmissive passivation layer 76 which encapsulates the light emitting diode (VLED) die 74 .
  • VLED vertical light emitting diode
  • the light emitting diode (LED) 34 is shown with only one vertical light emitting diode (VLED) die 74 mounted to the device substrate 72 .
  • the light emitting diode (LED) 34 can include a plurality of vertical light emitting diode (VLED) dice 74 mounted to the device substrate 72 , and arranged in a desired array to form an optoelectronic device, such as an LED display.
  • the device substrate 72 can comprise a semiconductor material, such as silicon (Si), or another material, such GaAs, SiC, AlN, Al 2 O 3 , or sapphire.
  • the device substrate 72 can include a cavity 78 wherein the vertical light emitting diode (VLED) die 74 is mounted, and a back side 80 .
  • An electrically conductive die attach layer 82 can be used to attach the vertical light emitting diode (VLED) die 74 to the substrate 72 .
  • the vertical light emitting diode (VLED) die 74 can be fabricated as disclosed in U.S. application Ser. No. 12/983,436 entitled “Vertical Light Emitting Diode (VLED) Die And Method Of Fabrication”, which is incorporated herein by reference.
  • the vertical light emitting diode (VLED) die 74 includes a first metal 84 ; a second metal 86 ; a p-type semiconductor layer 88 on the first metal 84 ; a multiple quantum well (MQW) layer 90 on the p-type semiconductor layer 88 ; and an n-type semiconductor layer 92 on the multiple quantum well (MQW) layer 90 .
  • MQW multiple quantum well
  • a preferred material for the p-type semiconductor layer 88 comprises p-GaN.
  • Other suitable materials for the p-type semiconductor layer 88 include AlGaN, InGaN and AlInGaN.
  • a preferred material for the n-type semiconductor layer 92 comprises p-GaN.
  • Other suitable materials for the n-type semiconductor layer 92 include AlGaN, InGaN and AlInGaN.
  • the multiple quantum well (MQW) layer 90 can comprise a semiconductor material, such as GaAs, sandwiched between two layers of a semiconductor material, such as AlAs having a wider bandgap.
  • Wire bonded wires 94 electrically connect the n-type semiconductor layer 92 to electrodes on the substrate 72 and the vertical light emitting diode (VLED) die 74 .
  • VLED vertical light emitting diode
  • the substrate 32 includes a front side (circuit side) having conductors 40 formed thereon, which electrically connect the application specific integrated circuit (ASIC) die 36 to the light emitting diode (LED) 34 .
  • ASIC application specific integrated circuit
  • LED light emitting diode
  • the application specific integrated circuit (ASIC) die 36 and the light emitting diode (LED) 34 can be mounted to the substrate using a suitable technique such as flip chip or C4 bonding.
  • the substrate 32 can comprise silicon, or another semiconductor material such as gallium arsenide, and the conductors 40 can be fabricated using well known semiconductor fabrication processes.
  • the substrate 32 can comprise silicon carbide (SiC) or sapphire (Al 2 O 3 ).
  • the substrate 32 can comprise a ceramic material, a printed circuit board (PCB) material, a metal core printed circuit board (PCB), an FR-4 printed circuit board (PCB), a metal lead frame, an organic lead frame, a silicon submount substrate, or any packaging substrate used in the art.
  • PCB printed circuit board
  • PCB metal core printed circuit board
  • PCB FR-4 printed circuit board
  • metal lead frame an organic lead frame
  • silicon submount substrate or any packaging substrate used in the art.
  • the substrate 32 can have any polygonal shape (e.g., square, rectangular) and any suitable size.
  • the substrate 32 can be die-sized, such that the LED system 30 has a chip scale size similar to that of a chip scale package (CSP) or a system on a chip (COS).
  • the substrate 32 can be wafer sized such that a wafer scale system is provided.
  • an alternate embodiment LED system 30 A is substantially similar to the LED system 30 ( FIG. 2 ), but includes a substrate 32 A configured to provide additional electrical functionality.
  • the substrate 32 A comprises a semiconductor material having a segment 42 formed with application specific integrated circuits (ASICs) 44 configured to perform additional electrical functions.
  • the application specific integrated circuits (ASICs) 44 can include semiconductor components, circuits, and base materials integrated into the substrate 32 A.
  • the application specific integrated circuits (ASICs) 44 can include resistors, diodes (p-n), capacitors, gates, metal-oxide field effect transistors (MOSFET), and flip flops.
  • the application specific integrated circuits (ASICs) 44 can be combined with the integrated circuits in the application specific integrated circuit (ASIC) die 36 to provide smart on-board control of the light emitting diode (LED) 34 .
  • the semiconductor substrate 32 A can comprise a portion of a semiconductor wafer having the application specific integrated circuits (ASICs) 44 formed therein using conventional semiconductor fabrication techniques such as implanting, photopatterning.
  • the light emitting diode (LED) 34 can be mounted to a blank portion of the substrate 32 A spaced from the application specific integrated circuits (ASICs) 44 , and electrically connected to the application specific integrated circuits (ASICs) 44 using suitable connecting elements and interconnects.
  • the substrate 32 or 32 A includes a back side 48 having an array of contacts 46 in electrical communication with the application specific integrated circuit (ASIC) die 36 ( FIG. 2 ), and with the application specific integrated circuits (ASICs) 44 ( FIG. 3 ).
  • the contacts 46 function as the terminal contacts for connecting the LED system 30 ( FIG. 2 ) or 30 A ( FIG. 3 ) to the outside world including other electronic devices and circuitry.
  • the contacts 46 can comprise bumps or pads made of a bondable material such as solder, metal or a conductive polymer, configured for bonding to corresponding electrodes on a module substrate, circuit board or other support substrate.
  • the contacts 46 can be arranged in a suitable dense area array, such as a ball grid array (BGA) or fine ball grid array (FBGA). Further, the contacts 46 can be electrically connected to the application specific integrated circuit (ASIC) die 36 ( FIG. 2 ) and to the application specific integrated circuits (ASICs) 44 ( FIG. 3 ) using suitable elements, such as interconnects, conductive traces, redistribution conductors and conductive vias formed on the substrate 32 or 32 A.
  • BGA ball grid array
  • FBGA fine ball grid array
  • the contacts 46 can be configured to integrate and expand the electrical functions of the application specific integrated circuit (ASIC) die 36 ( FIG. 2 ), the application specific integrated circuits (ASICs) 44 ( FIG. 3 ), and the light emitting diode (LED) 34 ( FIG. 2 ), and to provide smart control for the LED system 30 ( FIG. 2 ) or 30 A ( FIG. 3 ).
  • the contacts 44 can be configured as: a.) multi purpose input-output ports; b.) power inputs (AC or DC) for driving the LED system 30 or 30 A; c.) dimming control ports; d.) current setting ports; e.) feedback sensor ports; f.) communication ports; and g.) common ground ports.
  • the application specific integrated circuits (ASICs) 44 ( FIG. 3 ), and the light emitting diode (LED) 34 ( FIG. 2 ) form an integrated LED circuit.
  • FIGS. 5 , 5 A and 5 B an exemplary mounting arrangement for mounting the light emitting diode (LED) 34 and the application specific integrated circuit (ASIC) die 36 to the substrate 32 in LED system 30 are illustrated.
  • the LED chip 34 has a p-, n-same side configuration and is mounted in a chip-on-board (COB) configuration using interconnects 50 , and a flip chip bonding method such as C4 (controlled collapse chip connection).
  • the application specific integrated circuit (ASIC) die 36 includes interconnects 52 and is flip chip mounted to the substrate 32 in a chip on board configuration.
  • COB chip-on-board
  • ASIC application specific integrated circuit
  • the LED chip 34 has a p-, n-different side configuration and is mounted to the substrate 32 using a die attach bonding layer 54 (e.g., solder, silver epoxy), and a wire bonded wire 56 bonded to contacts on the LED chip 34 and the substrate 32 .
  • a die attach bonding layer 54 e.g., solder, silver epoxy
  • FIGS. 6 , 6 A and 6 B an exemplary mounting arrangement for mounting the light emitting diode (LED) 34 and the application specific integrated circuit (ASIC) die 36 to the substrate 32 A in LED system 30 A are illustrated.
  • the LED chip 34 has a p-, n-same side configuration and is mounted in a chip-on-board (COB) configuration using interconnects 50 , and a flip chip bonding method such as C4 (controlled collapse chip connection).
  • the application specific integrated circuit (ASIC) die 36 can be flip chip mounted to the application specific integrated circuits 44 on the substrate 32 A in a chip on board configuration substantially as previously described.
  • COB chip-on-board
  • ASIC application specific integrated circuit
  • the LED chip 34 has a p-, n-different side configuration and is mounted to the substrate 32 A using a die attach bonding layer 54 (e.g., solder, silver epoxy), and a wire bonded wire 56 bonded to contacts on the LED chip 34 and the substrate 32 A.
  • a die attach bonding layer 54 e.g., solder, silver epoxy
  • FIGS. 7 and 7A an exemplary electrical configuration for the application specific integrated circuit (ASIC) die 36 and the light emitting diode (LED) 34 for the LED system 30 or 30 A are illustrated.
  • the light emitting diode (LED) 34 can be electrically connected via the conductors 40 to ground pins on the application specific integrated circuit (ASIC) die 36 .
  • the light emitting diode (LED) 34 can be connected to a dedicated ground pin on the substrate 32 or 32 A.
  • the LED system 30 or 30 A can also include multiple light emitting diodes (LEDs) 34 A- 34 D mounted directly to the substrate 32 or 32 A.
  • the light emitting diodes (LEDs) 34 A- 34 D can all be configured to produce the same wavelengths and colors of light (e.g., red, green, blue, white, UV, laser, IR), or can be configured to produce different combinations thereof.
  • a first light emitting diode (LED) 34 A can produce white light
  • a second light emitting diode (LED) 34 B can produce green light
  • a third light emitting diode (LED) 34 C can produce blue light
  • a fourth light emitting diode (LED) 34 D can produce red light.
  • the application specific integrated circuit (ASIC) die 36 and the application specific integrated circuits 44 ( FIG. 3 ) can be adapted to provide smart color control for the light emitting diodes (LEDs) 34 A- 34 D.
  • the light emitting diodes (LEDs) 34 A- 34 D can be electrically connected in series and grounded to ground pins on the application specific integrated circuit (ASIC) die 36 .
  • the light emitting diodes (LEDs) 34 A- 34 D can be connected to a dedicated ground pin on the substrate 32 or 32 A.
  • the LED system 30 or 30 A can also include multiple light emitting diodes (LEDs) 34 A- 34 D electrically connected in parallel.
  • the light emitting diodes (LEDs) 34 A- 34 D can be electrically connected in multiple parallel strings with each string containing a plurality of light emitting diodes (LEDs) 34 connected in series.
  • FIG. 10 illustrates an input/output configuration for the application specific integrated circuit (ASIC) die 36 .
  • the input/output configuration and the application specific integrated circuits of the application specific integrated circuit (ASIC) die 36 are configured to integrate the light emitting diode 34 and the application specific integrated circuit (ASIC) die 36 into an integrated assembly.
  • FIG. 10A illustrates an output configuration for the application specific integrated circuit (ASIC) die 36 with a string of light emitting diodes (LED) 34 electrically connected in series to ground.
  • FIG. 10B illustrates an output configuration for the application specific integrated circuit (ASIC) die 36 with a single light emitting diode (LED) 34 electrically connected to ground.
  • LED light emitting diode
  • Table 1 describes the input port configuration for the application specific integrated circuit (ASIC) die 36 .
  • LED Brightness Tuning/White Balance Parameter can be burn into Flash/ROM GDN Common
  • SPI 1 Multi-purpose A/D When SPI En is disable, A/D port function will be enable 2)
  • SPI EN Port When SPI EN Port is Enable, LED Brightness Tuning/White Balance Parameter can be burn into Flash/ROM GDN Common
  • Some features of LED system 30 or 30A include: Adjustable LED (load) current LED Output port current can be scaled to multiple ratio for the purpose of: White Balancing (for White or RGB applications) or White Color Coordinate Tuning Brightness Calibration Soft Turn On-Off Dimmable Dimming - PWM Dimming - 0-10 V Dimming - TRAC Failsafe System Build in Safety Protection Over Temperature when Tj > 150° C. Over Voltage/Overload Under voltage lockout Reverse polarity protection
  • an LED package 58 A includes the substrate 32 or 32 A, the application specific integrated circuit (ASIC) die 36 , and the light emitting diode (LED) 34 , substantially as previously described.
  • the light emitting diode (LED) 34 can include a phosphor layer 60 for producing white light.
  • the LED package 58 A also includes a polymer lens 66 on the substrate 32 or 32 A, which encapsulates the LED system 30 or 30 A.
  • the polymer lens 66 can comprise a suitable polymer such as epoxy formed by molding or other suitable process.
  • an LED package 58 B includes the substrate 32 or 32 A, the application specific integrated circuit (ASIC) die 36 , and the light emitting diode (LED) 34 , substantially as previously described.
  • the LED package 58 A also includes a polymer lens 66 on the substrate 32 or 32 A which encapsulates the LED system 30 or 30 A.
  • the polymer lens 66 also includes a phosphor layer 62 for producing white light.
  • an LED package 58 C includes the substrate 32 or 32 A, the application specific integrated circuit (ASIC) die 36 , and the light emitting diode (LED) 34 , substantially as previously described.
  • the substrate 32 or 32 A also includes a reflective recess 64 wherein the application specific integrated circuit (ASIC) die 36 , and the light emitting diode (LED) 34 are mounted.
  • the LED integrated circuit 68 includes the contacts 46 on the substrate 32 or 32 A.
  • the LED integrated circuit 68 can also include the application (ASIC)s 44 on the substrate 32 A.
  • the LED integrated circuit 68 also includes the application specific integrated circuits 38 in the application specific integrated circuit (ASIC) die 36 .
  • the LED integrated circuit 68 also includes the light emitting diode 34 . Because the LED integrated circuit 68 has integrated elements power consumption and heat generation are less than with the prior art LED circuit 10 ( FIG. 1 ).
  • the LED system 30 or 30 A can be made smaller such that a chip scale system can be provided.
  • a light emitting diode (LED) system 30 B includes a substrate 32 B, a light emitting diode (LED) 34 on the substrate 32 B, and an application specific integrated circuit (ASIC) die 36 B on the substrate 32 B having integrated circuits 38 B in electrical communication with conductors 40 B on the substrate 32 B and the light emitting diode (LED) 34 .
  • the light emitting diode (LED) system 30 B also includes a wireless receiver 96 on the substrate 32 B in electrical communication with the application specific integrated circuit (ASIC) die 36 B, and a wireless transmitter 98 configured to send signals 100 to the wireless receiver 96 for controlling the application specific integrated circuit (ASIC) die 36 B.
  • the wireless transmitter 98 can comprise a stand alone unit or can be contained on a mobile communications device, such as a mobile telephone, smart telephone, portable computer, “IPAD” or “IPHONE”.
  • the wireless transmitter 98 can also include an input device, such as a key pad, configured to receive user input for sending the signals 100 .
  • the wireless transmitter 98 can include automated input devices, such as motion detectors, for controlling the signals 100 .
  • the application specific integrated circuit (ASIC) die 36 B can include output ports in electrical communication with the light emitting diode (LED) 34 .
  • the application specific integrated circuit (ASIC) die 36 B also includes two power contacts 102 , 104 , which can be on the substrate 32 B or on the die 36 B.
  • the power contacts 102 , 104 can be placed in electrical communication with an AC or DC power source (not shown) for supplying power for the light emitting diode (LED) system 30 B.
  • the wireless transmitter 98 is configured to control the operation of the application specific integrated circuit (ASIC) die 36 B and thus the light emitting diode (LED) 34 .
  • the signals 100 can be used to turn the light emitting diode (LED) 34 on and off, and to control the brightness of the light emitting diode (LED) 34 .
  • LED light emitting diode
  • the signals 100 can be used to control the dice separately.
  • the integrated circuits 38 B can be formed in the substrate substantially as previously described for substrate 32 A ( FIG. 3 ).
  • a method for controlling the light emitting diode (LED) system 30 B can include the steps of providing the substrate 32 B; providing one or more application specific integrated circuits (ASIC) 38 B on the substrate 32 B; providing at least one light emitting diode (LED) 34 on the substrate 32 B in electrical communication with the application specific integrated circuits (ASIC) 38 B; providing a wireless receiver 96 on the substrate 32 B configured to receive signals 100 for controlling the application specific integrated circuits (ASIC) 38 B; providing a wireless transmitter 98 in signal communication with the wireless receiver 96 configured to send the signals 100 to the wireless receiver 96 ; and sending the signals 100 from the wireless transmitter 98 to the wireless receiver 96 for controlling the application specific integrated circuits (ASIC) 38 B and the light emitting diode (LED) 34 .
  • ASIC application specific integrated circuits
  • LED light emitting diode

Abstract

A light emitting diode (LED) system includes a substrate, an application specific integrated circuit (ASIC) die on the substrate having a pair of power contacts, at least one light emitting diode (LED) on the substrate controlled by the application specific integrated circuit (ASIC) die, a wireless receiver on the substrate configured to receive signals for controlling the application specific integrated circuit (ASIC) die, and a wireless transmitter in signal communication with the wireless receiver configured to send the signals.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation-in-part of Ser. No. 13/309,718, filed on Dec. 2, 2011, which is a continuation-in-part of Ser. No. 12/540,523, filed on Aug. 13, 2009, U.S. Pat. No. 8,084,780 B2.
    • BACKGROUND
  • This disclosure relates generally to light emitting diodes (LED) and more particularly to systems incorporating light emitting diodes (LEDs).
  • Light emitting diodes (LEDs) are used in a wide range of electronic devices such as displays, communication devices, and lamps. Advances in LED technology have improved the efficiency and service life of light emitting diodes (LEDs), and have made them smaller and lighter. However, most advances have been directed to the structure and function of the light emitting diodes (LEDs), rather than the associated LED systems. Light emitting diodes (LEDs) are typically part of a LED system that includes driver circuitry and associated electronic devices such as resistors, capacitors, diodes and circuit boards.
  • FIG. 1 illustrates a prior art LED circuit 10. The prior art LED system 10 includes a LED driver IC 12, and two light emitting diode (LED) chips 14 in electrical communication with the LED driver IC chip 12. The LED driver IC 12 is configured to provide driver and functionality circuits for the light emitting diode (LED) chips 14. The LED driver IC 12 includes a VIN pin, a SEN pin, a DIM pin, a SW pin and a GND pin. The LED system 10 also includes various electronic components including resistors, capacitors, a Schottky diode, and an inductor configured substantially as shown. The LED system 10 requires a relatively complex manufacturing process to mount and interconnect all of the electronic elements. In addition, relatively large amounts of current and power are required to drive the electronic elements, which generates a large amount of heat.
  • In view of the foregoing, improved LED systems are needed in the art, which are more efficient than prior art LED systems. However, the foregoing examples of the related art and limitations related therewith, are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Exemplary embodiments are illustrated in the referenced figures of the drawings. It is intended that the embodiments and the figures disclosed herein are to be considered illustrative rather than limiting.
  • FIG. 1 is an electrical schematic diagram of a prior art LED system;
  • FIG. 2 is a schematic plan view of a LED system having integrated components and smart functionality;
  • FIG. 3 is a schematic plan view of the LED system having additional functionality built into a semiconductor substrate;
  • FIG. 4 is a schematic bottom view of the LED system showing circuitry on the substrate;
  • FIG. 5 is a schematic plan view of the LED system equivalent to FIG. 2;
  • FIG. 5A is a schematic side elevation view of FIG. 5 illustrating a first mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • FIG. 5B is a schematic side elevation view of FIG. 5 illustrating a second mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • FIG. 6 is a schematic plan view of the LED system having additional functionality equivalent to FIG. 3;
  • FIG. 6A is a schematic side elevation view of FIG. 6 illustrating a first mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • FIG. 6B is a schematic side elevation view of FIG. 6 illustrating a second mounting arrangement for an application specific integrated circuit (ASIC) and (LED) chip on the substrate;
  • FIG. 7 is a schematic plan view of the LED system equivalent to FIG. 2 or FIG. 3;
  • FIG. 7A is a schematic electrical diagram of the LED system of FIG. 7;
  • FIG. 8 is a schematic plan view of the LED system having multiple LED chips electrically connected in series;
  • FIG. 8A is a schematic electrical diagram of the LED system of FIG. 8;
  • FIG. 9 is a schematic plan view of the LED system having multiple LED chips electrically connected in parallel;
  • FIG. 9A is a schematic electrical diagram of the LED system of FIG. 9;
  • FIG. 10 is an electrical schematic diagram of the application specific integrated circuit (ASIC) of the LED system;
  • FIG. 10A is an electrical schematic diagram of a first output configuration of the application specific integrated circuit (ASIC) of the LED system;
  • FIG. 10B is an electrical schematic diagram of a second output configuration of the application specific integrated circuit (ASIC) of the LED system;
  • FIG. 11A is a schematic cross sectional view a first encapsulated package for the LED system;
  • FIG. 11B is a schematic cross sectional view a second encapsulated package for the LED system;
  • FIG. 11C is a schematic cross sectional view a third encapsulated package for the LED system;
  • FIG. 12 is an electrical schematic diagram of a LED integrated circuit formed by the LED system;
  • FIG. 13 is a schematic cross sectional view of a light emitting diode (LED) of the LED system; and
  • FIG. 14 is a schematic cross sectional view of a light emitting diode (LED) system having an application specific integrated circuit (ASIC) and a wireless receiver.
    •  DETAILED DESCRIPTION
  • Referring to FIG. 2, a LED system 30 includes a substrate 32, a light emitting diode (LED) 34 mounted to the substrate 32, and an application specific integrated circuit (ASIC) die 36 mounted to the substrate 32 in electrical communication with the light emitting diode (LED) 34. Although the LED system 30 includes only one application specific integrated circuit (ASIC) die 36, it is to be understood that the LED system can include a plurality of application specific integrated circuit (ASIC) dice 36. The substrate 32 functions as a mounting substrate, and also provides functionality for operating the light emitting diode (LED) 34 and the application specific integrated circuit (ASIC) die 36 as an integrated assembly. The light emitting diode (LED) 34 can comprise a conventional LED fabricated using known processes. Suitable light emitting diodes (LEDs) are commercially available from SEMILEDS, INC. located in Boise, Id., and Miao-Li County, Taiwan, R.O.C. The application specific integrated circuit (ASIC) die 36 can comprise a semiconductor die having application specific integrated circuits 38 formed therein.
  • The light emitting diode (LED) 34 can comprise a Group-III nitride based material such as GaN, InGaN, AlGaN, AlInGaN or other (Ga, In or Al) N-based materials. In addition, the doped and active layers of the light emitting diode (LED) 34 can be formed on a carrier substrate made of a suitable material such as silicon (Si), silicon carbide (SiC) or sapphire (Al2O3). For example, SEMILEDS, INC. manufactures ultra thin vertical light emitting diodes (VLED) under the trademark MvpLED™. U.S. Pat. No. 7,723,718, entitled “Epitaxial Structure For Metal Devices”, which is incorporated herein be reference, discloses methods for fabricating vertical light emitting diodes (VLED).
  • Referring to FIG. 13, the light emitting diode (LED) 34 is shown separately. However, it is to be understood that this configuration for the light emitting diode (LED) 34 is merely exemplary, and other configurations can be employed. The light emitting diode (LED) 34 includes a device substrate 72, a vertical light emitting diode (VLED) die 74 mounted to the device substrate 72, and an electrically insulating, light transmissive passivation layer 76 which encapsulates the light emitting diode (VLED) die 74. For illustrative purposes in FIG. 13, the light emitting diode (LED) 34 is shown with only one vertical light emitting diode (VLED) die 74 mounted to the device substrate 72. However, in actual practice the light emitting diode (LED) 34 can include a plurality of vertical light emitting diode (VLED) dice 74 mounted to the device substrate 72, and arranged in a desired array to form an optoelectronic device, such as an LED display. The device substrate 72 can comprise a semiconductor material, such as silicon (Si), or another material, such GaAs, SiC, AlN, Al2O3, or sapphire. The device substrate 72 can include a cavity 78 wherein the vertical light emitting diode (VLED) die 74 is mounted, and a back side 80. An electrically conductive die attach layer 82 can be used to attach the vertical light emitting diode (VLED) die 74 to the substrate 72.
  • Still referring to FIG. 13, the vertical light emitting diode (VLED) die 74 can be fabricated as disclosed in U.S. application Ser. No. 12/983,436 entitled “Vertical Light Emitting Diode (VLED) Die And Method Of Fabrication”, which is incorporated herein by reference. The vertical light emitting diode (VLED) die 74 includes a first metal 84; a second metal 86; a p-type semiconductor layer 88 on the first metal 84; a multiple quantum well (MQW) layer 90 on the p-type semiconductor layer 88; and an n-type semiconductor layer 92 on the multiple quantum well (MQW) layer 90. A preferred material for the p-type semiconductor layer 88 comprises p-GaN. Other suitable materials for the p-type semiconductor layer 88 include AlGaN, InGaN and AlInGaN. A preferred material for the n-type semiconductor layer 92 comprises p-GaN. Other suitable materials for the n-type semiconductor layer 92 include AlGaN, InGaN and AlInGaN. The multiple quantum well (MQW) layer 90 can comprise a semiconductor material, such as GaAs, sandwiched between two layers of a semiconductor material, such as AlAs having a wider bandgap. Wire bonded wires 94 electrically connect the n-type semiconductor layer 92 to electrodes on the substrate 72 and the vertical light emitting diode (VLED) die 74.
  • Referring again to FIG. 2, the substrate 32 includes a front side (circuit side) having conductors 40 formed thereon, which electrically connect the application specific integrated circuit (ASIC) die 36 to the light emitting diode (LED) 34. As will be further explained, the application specific integrated circuit (ASIC) die 36 and the light emitting diode (LED) 34 can be mounted to the substrate using a suitable technique such as flip chip or C4 bonding. The substrate 32 can comprise silicon, or another semiconductor material such as gallium arsenide, and the conductors 40 can be fabricated using well known semiconductor fabrication processes. As another example, the substrate 32 can comprise silicon carbide (SiC) or sapphire (Al2O3). Alternately, the substrate 32 can comprise a ceramic material, a printed circuit board (PCB) material, a metal core printed circuit board (PCB), an FR-4 printed circuit board (PCB), a metal lead frame, an organic lead frame, a silicon submount substrate, or any packaging substrate used in the art.
  • The substrate 32 can have any polygonal shape (e.g., square, rectangular) and any suitable size. In addition, the substrate 32 can be die-sized, such that the LED system 30 has a chip scale size similar to that of a chip scale package (CSP) or a system on a chip (COS). Alternately, the substrate 32 can be wafer sized such that a wafer scale system is provided.
  • Referring to FIG. 3, an alternate embodiment LED system 30A is substantially similar to the LED system 30 (FIG. 2), but includes a substrate 32A configured to provide additional electrical functionality. In particular, the substrate 32A comprises a semiconductor material having a segment 42 formed with application specific integrated circuits (ASICs) 44 configured to perform additional electrical functions. The application specific integrated circuits (ASICs) 44 can include semiconductor components, circuits, and base materials integrated into the substrate 32A. For example, the application specific integrated circuits (ASICs) 44 can include resistors, diodes (p-n), capacitors, gates, metal-oxide field effect transistors (MOSFET), and flip flops. The application specific integrated circuits (ASICs) 44 can be combined with the integrated circuits in the application specific integrated circuit (ASIC) die 36 to provide smart on-board control of the light emitting diode (LED) 34.
  • The semiconductor substrate 32A can comprise a portion of a semiconductor wafer having the application specific integrated circuits (ASICs) 44 formed therein using conventional semiconductor fabrication techniques such as implanting, photopatterning. The light emitting diode (LED) 34 can be mounted to a blank portion of the substrate 32A spaced from the application specific integrated circuits (ASICs) 44, and electrically connected to the application specific integrated circuits (ASICs) 44 using suitable connecting elements and interconnects.
  • As shown in FIG. 4, the substrate 32 or 32A includes a back side 48 having an array of contacts 46 in electrical communication with the application specific integrated circuit (ASIC) die 36 (FIG. 2), and with the application specific integrated circuits (ASICs) 44 (FIG. 3). The contacts 46 function as the terminal contacts for connecting the LED system 30 (FIG. 2) or 30A (FIG. 3) to the outside world including other electronic devices and circuitry. The contacts 46 can comprise bumps or pads made of a bondable material such as solder, metal or a conductive polymer, configured for bonding to corresponding electrodes on a module substrate, circuit board or other support substrate. In addition, the contacts 46 can be arranged in a suitable dense area array, such as a ball grid array (BGA) or fine ball grid array (FBGA). Further, the contacts 46 can be electrically connected to the application specific integrated circuit (ASIC) die 36 (FIG. 2) and to the application specific integrated circuits (ASICs) 44 (FIG. 3) using suitable elements, such as interconnects, conductive traces, redistribution conductors and conductive vias formed on the substrate 32 or 32A.
  • The contacts 46 can be configured to integrate and expand the electrical functions of the application specific integrated circuit (ASIC) die 36 (FIG. 2), the application specific integrated circuits (ASICs) 44 (FIG. 3), and the light emitting diode (LED) 34 (FIG. 2), and to provide smart control for the LED system 30 (FIG. 2) or 30A (FIG. 3). For example, the contacts 44 can be configured as: a.) multi purpose input-output ports; b.) power inputs (AC or DC) for driving the LED system 30 or 30A; c.) dimming control ports; d.) current setting ports; e.) feedback sensor ports; f.) communication ports; and g.) common ground ports. In addition, the application specific integrated circuits (ASICs) 44 (FIG. 3), and the light emitting diode (LED) 34 (FIG. 2) form an integrated LED circuit.
  • Referring to FIGS. 5, 5A and 5B, an exemplary mounting arrangement for mounting the light emitting diode (LED) 34 and the application specific integrated circuit (ASIC) die 36 to the substrate 32 in LED system 30 are illustrated. In FIG. 5A, the LED chip 34 has a p-, n-same side configuration and is mounted in a chip-on-board (COB) configuration using interconnects 50, and a flip chip bonding method such as C4 (controlled collapse chip connection). Similarly, the application specific integrated circuit (ASIC) die 36 includes interconnects 52 and is flip chip mounted to the substrate 32 in a chip on board configuration. In FIG. 5B, the LED chip 34 has a p-, n-different side configuration and is mounted to the substrate 32 using a die attach bonding layer 54 (e.g., solder, silver epoxy), and a wire bonded wire 56 bonded to contacts on the LED chip 34 and the substrate 32.
  • Referring to FIGS. 6, 6A and 6B, an exemplary mounting arrangement for mounting the light emitting diode (LED) 34 and the application specific integrated circuit (ASIC) die 36 to the substrate 32A in LED system 30A are illustrated. In FIG. 6A, the LED chip 34 has a p-, n-same side configuration and is mounted in a chip-on-board (COB) configuration using interconnects 50, and a flip chip bonding method such as C4 (controlled collapse chip connection). The application specific integrated circuit (ASIC) die 36 can be flip chip mounted to the application specific integrated circuits 44 on the substrate 32A in a chip on board configuration substantially as previously described. In FIG. 6B, the LED chip 34 has a p-, n-different side configuration and is mounted to the substrate 32A using a die attach bonding layer 54 (e.g., solder, silver epoxy), and a wire bonded wire 56 bonded to contacts on the LED chip 34 and the substrate 32A.
  • Referring to FIGS. 7 and 7A, an exemplary electrical configuration for the application specific integrated circuit (ASIC) die 36 and the light emitting diode (LED) 34 for the LED system 30 or 30A are illustrated. As shown in FIG. 7A, the light emitting diode (LED) 34 can be electrically connected via the conductors 40 to ground pins on the application specific integrated circuit (ASIC) die 36. Alternately, the light emitting diode (LED) 34 can be connected to a dedicated ground pin on the substrate 32 or 32A.
  • Referring to FIGS. 8 and 8A, the LED system 30 or 30A can also include multiple light emitting diodes (LEDs) 34A-34D mounted directly to the substrate 32 or 32A. The light emitting diodes (LEDs) 34A-34D can all be configured to produce the same wavelengths and colors of light (e.g., red, green, blue, white, UV, laser, IR), or can be configured to produce different combinations thereof. For example, a first light emitting diode (LED) 34A can produce white light, a second light emitting diode (LED) 34B can produce green light, a third light emitting diode (LED) 34C can produce blue light, and a fourth light emitting diode (LED) 34D can produce red light. In addition, the application specific integrated circuit (ASIC) die 36, and the application specific integrated circuits 44 (FIG. 3) can be adapted to provide smart color control for the light emitting diodes (LEDs) 34A-34D. As shown in FIG. 8A, the light emitting diodes (LEDs) 34A-34D can be electrically connected in series and grounded to ground pins on the application specific integrated circuit (ASIC) die 36. Alternately, the light emitting diodes (LEDs) 34A-34D can be connected to a dedicated ground pin on the substrate 32 or 32A.
  • Referring to FIGS. 9 and 9A, the LED system 30 or 30A can also include multiple light emitting diodes (LEDs) 34A-34D electrically connected in parallel. As another alternative, the light emitting diodes (LEDs) 34A-34D can be electrically connected in multiple parallel strings with each string containing a plurality of light emitting diodes (LEDs) 34 connected in series.
  • Referring to FIGS. 10, 10A and 10B, electrical characteristics of the LED system 30 or 30A are illustrated. FIG. 10 illustrates an input/output configuration for the application specific integrated circuit (ASIC) die 36. In general, the input/output configuration and the application specific integrated circuits of the application specific integrated circuit (ASIC) die 36 are configured to integrate the light emitting diode 34 and the application specific integrated circuit (ASIC) die 36 into an integrated assembly. FIG. 10A illustrates an output configuration for the application specific integrated circuit (ASIC) die 36 with a string of light emitting diodes (LED) 34 electrically connected in series to ground. FIG. 10B illustrates an output configuration for the application specific integrated circuit (ASIC) die 36 with a single light emitting diode (LED) 34 electrically connected to ground.
  • Table 1 describes the input port configuration for the application specific integrated circuit (ASIC) die 36.
  • TABLE 1
    INPUT PORT CONFIGURATION
    PORT PORT DESCRIPTION
    Vin Power Source input for LED Systems. Power input is enable for:
    a) DC Voltage
    Range 1.5 VDC-60 VDAC
    a) AC Voltage
    Range
    90 VAC-264 VAC/50 Hz-60 Hz
    DIM This is dimming input control port. Dimming is allowed from
    0% to 100% brightness. Allow dimming type:
    a) OVDC to 10 VDC Type Method
    b) Pulse Width Modulation
    c) Convention Triac Dimmer
    SEN This port has 2 functions
    SPI EN 1) Constant Current Output to LED setting.
    2) Enable Serial Write to Flash/ROM for White Balance Setting
    SW This port is to use for Soft Turn ON/OFF purpose
    A/D This port has 2 functions:
    SPI 1) Multi-purpose A/D
    When SPI En is disable, A/D port function will be enable
    2) SPI
    When SPI EN Port is Enable, LED Brightness Tuning/White
    Balance Parameter can be burn into Flash/ROM
    GDN Common
    Some features of LED system 30 or 30A include:
    Adjustable LED (load) current
    LED Output port current can be scaled to multiple ratio for the purpose of:
     White Balancing (for White or RGB applications) or White Color
     Coordinate Tuning
     Brightness Calibration
    Soft Turn On-Off
    Dimmable
     Dimming - PWM
     Dimming - 0-10 V
     Dimming - TRAC
    Failsafe System
     Build in Safety Protection
     Over Temperature when Tj > 150° C.
     Over Voltage/Overload
     Under voltage lockout
     Reverse polarity protection
  • Referring to FIGS. 11A-11C, different packaging configurations for the LED system 30 or 30A are illustrated. In FIG. 11A, an LED package 58A includes the substrate 32 or 32A, the application specific integrated circuit (ASIC) die 36, and the light emitting diode (LED) 34, substantially as previously described. In addition, the light emitting diode (LED) 34 can include a phosphor layer 60 for producing white light. The LED package 58A also includes a polymer lens 66 on the substrate 32 or 32A, which encapsulates the LED system 30 or 30A. The polymer lens 66 can comprise a suitable polymer such as epoxy formed by molding or other suitable process.
  • In FIG. 11B, an LED package 58B includes the substrate 32 or 32A, the application specific integrated circuit (ASIC) die 36, and the light emitting diode (LED) 34, substantially as previously described. The LED package 58A also includes a polymer lens 66 on the substrate 32 or 32A which encapsulates the LED system 30 or 30A. In this embodiment, the polymer lens 66 also includes a phosphor layer 62 for producing white light.
  • In FIG. 11C, an LED package 58C includes the substrate 32 or 32A, the application specific integrated circuit (ASIC) die 36, and the light emitting diode (LED) 34, substantially as previously described. In this embodiment, the substrate 32 or 32A also includes a reflective recess 64 wherein the application specific integrated circuit (ASIC) die 36, and the light emitting diode (LED) 34 are mounted.
  • Referring to FIG. 12 an electrical schematic of an LED integrated circuit 68 formed by the LED system 30 or 30A is illustrated. The LED integrated circuit 68 includes the contacts 46 on the substrate 32 or 32A. The LED integrated circuit 68 can also include the application (ASIC)s 44 on the substrate 32A. The LED integrated circuit 68 also includes the application specific integrated circuits 38 in the application specific integrated circuit (ASIC) die 36. The LED integrated circuit 68 also includes the light emitting diode 34. Because the LED integrated circuit 68 has integrated elements power consumption and heat generation are less than with the prior art LED circuit 10 (FIG. 1). In addition, the LED system 30 or 30A can be made smaller such that a chip scale system can be provided.
  • Referring to FIG. 14, a light emitting diode (LED) system 30B includes a substrate 32B, a light emitting diode (LED) 34 on the substrate 32B, and an application specific integrated circuit (ASIC) die 36B on the substrate 32B having integrated circuits 38B in electrical communication with conductors 40B on the substrate 32B and the light emitting diode (LED) 34. The light emitting diode (LED) system 30B also includes a wireless receiver 96 on the substrate 32B in electrical communication with the application specific integrated circuit (ASIC) die 36B, and a wireless transmitter 98 configured to send signals 100 to the wireless receiver 96 for controlling the application specific integrated circuit (ASIC) die 36B. The wireless transmitter 98 can comprise a stand alone unit or can be contained on a mobile communications device, such as a mobile telephone, smart telephone, portable computer, “IPAD” or “IPHONE”. The wireless transmitter 98 can also include an input device, such as a key pad, configured to receive user input for sending the signals 100. Alternately, the wireless transmitter 98 can include automated input devices, such as motion detectors, for controlling the signals 100.
  • As previously described, the application specific integrated circuit (ASIC) die 36B can include output ports in electrical communication with the light emitting diode (LED) 34. The application specific integrated circuit (ASIC) die 36B also includes two power contacts 102, 104, which can be on the substrate 32B or on the die 36B. The power contacts 102, 104 can be placed in electrical communication with an AC or DC power source (not shown) for supplying power for the light emitting diode (LED) system 30B. Although power comes from the outside through the power contacts 102, 104 the wireless transmitter 98 is configured to control the operation of the application specific integrated circuit (ASIC) die 36B and thus the light emitting diode (LED) 34. For example, the signals 100 can be used to turn the light emitting diode (LED) 34 on and off, and to control the brightness of the light emitting diode (LED) 34. With multiple light emitting diode (LED) dice 34, the signals 100 can be used to control the dice separately. Also, rather than being contained on the application specific integrated circuit (ASIC) die 36B, the integrated circuits 38B can be formed in the substrate substantially as previously described for substrate 32A (FIG. 3).
  • A method for controlling the light emitting diode (LED) system 30B can include the steps of providing the substrate 32B; providing one or more application specific integrated circuits (ASIC) 38B on the substrate 32B; providing at least one light emitting diode (LED) 34 on the substrate 32B in electrical communication with the application specific integrated circuits (ASIC) 38B; providing a wireless receiver 96 on the substrate 32B configured to receive signals 100 for controlling the application specific integrated circuits (ASIC) 38B; providing a wireless transmitter 98 in signal communication with the wireless receiver 96 configured to send the signals 100 to the wireless receiver 96; and sending the signals 100 from the wireless transmitter 98 to the wireless receiver 96 for controlling the application specific integrated circuits (ASIC) 38B and the light emitting diode (LED) 34.
  • Thus the disclosure describes improved LED systems. While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and subcombinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions and sub-combinations as are within their true spirit and scope.

Claims (20)

1. A light emitting diode (LED) system comprising:
a substrate;
one or more application specific integrated circuits (ASIC) on the substrate;
at least one light emitting diode (LED) on the substrate in electrical communication with the application specific integrated circuits (ASIC);
a wireless receiver on the substrate configured to receive signals for controlling the application specific integrated circuits (ASIC), and
a wireless transmitter in signal communication with the wireless receiver configured to send the signals to the wireless receiver.
2. The system of claim 1 wherein the application specific integrated circuits (ASIC) are contained on a semiconductor die.
3. The system of claim 1 wherein the application specific integrated circuits (ASIC) are contained on the substrate.
4. The system of claim 1 wherein the application specific integrated circuits (ASIC) are contained on a semiconductor die having a pair of power contacts.
5. The system of claim 1 wherein the wireless transmitter is operable by a user to send the signals.
6. The system of claim 1 wherein the wireless transmitter comprises a mobile communications device.
7. The system of claim 1 wherein the wireless transmitter includes an automated input device.
8. The system of claim 1 wherein the light emitting diode (LED) comprises a vertical light emitting diode (VLED) die.
9. A light emitting diode (LED) system comprising:
a substrate;
at least one application specific integrated circuit (ASIC) die on the substrate having a plurality of integrated circuits and a pair of power contacts;
at least one light emitting diode (LED) on the substrate in electrical communication with the application specific integrated circuit (ASIC) die;
a wireless receiver on the substrate configured to receive signals and to control the application specific integrated circuit (ASIC) die and the light emitting diode (LED) responsive to the signals; and
a wireless transmitter in signal communication with the wireless receiver configured to send the signals for controlling the application specific integrated circuit (ASIC) die and the light emitting diode (LED).
10. The system of claim 9 wherein the wireless transmitter is operable by a user to send the signals.
11. The system of claim 9 wherein the wireless transmitter comprises a mobile communications device.
12. The system of claim 9 wherein the application specific integrated circuit (ASIC) die comprises a plurality of dice.
13. The system of claim 9 wherein the light emitting diode (LED) comprises a vertical light emitting diode (VLED) die.
14. A method for controlling a light emitting diode (LED) system comprising:
providing a substrate;
providing one or more application specific integrated circuits (ASIC) on the substrate;
providing at least one light emitting diode (LED) on the substrate in electrical communication with the application specific integrated circuits (ASIC);
providing a wireless receiver on the substrate configured to receive signals for controlling the application specific integrated circuits (ASIC);
providing a wireless transmitter in signal communication with the wireless receiver configured to send the signals to the wireless receiver; and
sending the signals from the wireless transmitter to the wireless receiver for controlling the application specific integrated circuits (ASIC) and the light emitting diode (LED).
15. The method of claim 14 wherein the application specific integrated circuits (ASIC) are contained on a semiconductor die.
16. The method of claim 14 wherein the application specific integrated circuits (ASIC) are contained on the substrate.
17. The method of claim 14 wherein the application specific integrated circuits (ASIC) are contained on a semiconductor die having a pair of power contacts.
18. The method of claim 14 wherein the wireless transmitter is operable by a user to send the signals.
19. The method of claim 14 wherein the wireless transmitter comprises a mobile communications device.
20. The method of claim 14 wherein the application specific integrated circuit (ASIC) die comprises a plurality of dice.
US13/670,526 2009-08-13 2012-11-07 Light emitting diode (led) system having application specific integrated circuit (asic) and wireless system Abandoned US20130057178A1 (en)

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TW102140225A TW201431433A (en) 2012-11-07 2013-11-06 A light emitting diode system and control method thereof

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US12/540,523 US8084780B2 (en) 2009-08-13 2009-08-13 Smart integrated semiconductor light emitting system including light emitting diodes and application specific integrated circuits (ASIC)
US13/309,718 US8933467B2 (en) 2009-08-13 2011-12-02 Smart integrated semiconductor light emitting system including nitride based light emitting diodes (LED) and application specific integrated circuits (ASIC)
US13/670,526 US20130057178A1 (en) 2009-08-13 2012-11-07 Light emitting diode (led) system having application specific integrated circuit (asic) and wireless system

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