US20130171810A1 - Methods of fabricating semiconductor device using high-k layer for spacer etch stop and related devices - Google Patents
Methods of fabricating semiconductor device using high-k layer for spacer etch stop and related devices Download PDFInfo
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- US20130171810A1 US20130171810A1 US13/542,717 US201213542717A US2013171810A1 US 20130171810 A1 US20130171810 A1 US 20130171810A1 US 201213542717 A US201213542717 A US 201213542717A US 2013171810 A1 US2013171810 A1 US 2013171810A1
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 210
- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 41
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- 229910021332 silicide Inorganic materials 0.000 claims description 25
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- 230000008569 process Effects 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 230000003139 buffering effect Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
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- 239000010410 layer Substances 0.000 description 431
- 230000006870 function Effects 0.000 description 30
- 239000012535 impurity Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- -1 (Ba Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
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- 238000010586 diagram Methods 0.000 description 3
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- 238000012986 modification Methods 0.000 description 3
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- 229910004129 HfSiO Inorganic materials 0.000 description 2
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- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
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- 229910017121 AlSiO Inorganic materials 0.000 description 1
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- 229910005883 NiSi Inorganic materials 0.000 description 1
- 241000627951 Osteobrama cotio Species 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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Abstract
Description
- This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0147035 filed on Dec. 30, 2011, the disclosure of which is hereby incorporated by reference in its entirety.
- 1. Field
- Example embodiments relate to methods of fabricating a semiconductor device and related devices using a high-K layer as a spacer etch stop.
- 2. Description of Related Art
- Various methods have been researched in which a spacer is formed on side surfaces of a gate electrode and a deep junction is formed.
- Example embodiments relate to methods of fabricating a semiconductor device and related devices using a high-K layer as a spacer etch stop.
- Example embodiments provide methods of fabricating a semiconductor device and related devices capable of protecting the surface of a substrate while a spacer is formed.
- The technical objectives are not limited to the above disclosure; other objectives may become apparent to those of ordinary skill in the art based on the following descriptions.
- In accordance with example embodiments, a method of fabricating a semiconductor device is provided. The method may include forming a gate electrode on a substrate. A first buffer layer, a second buffer layer and a third buffer layer may sequentially be formed on side surfaces of the gate electrode and on the substrate near the gate electrode. The third buffer layer may be a material layer having a higher dielectric constant than the second buffer layer. A first spacer may be formed covering the side surfaces of the gate electrode on the third buffer layer. The third buffer layer on the substrate near the gate electrode may be exposed. The second buffer layer may be exposed on the substrate by removing the exposed third buffer layer. The first buffer layer may be exposed on the substrate by removing the exposed second buffer layer. A deep junction may be formed in the substrate using the first spacer as an ion implantation mask. The first spacer may be removed. The first buffer layer may remain over the deep junction when the first spacer is removed. The first spacer may include a material layer different than the third buffer layer, the second buffer layer, and the first buffer layer. In some example embodiments, the third buffer layer may be an insulating layer including a metal.
- In example embodiments, the first buffer layer may include silicon oxide, the second buffer layer may include silicon nitride, and the first spacer may include one selected from poly-silicon, amorphous silicon and a combination thereof.
- In example embodiments, the second buffer layer may include a material layer different than the third buffer layer. The third buffer layer may be thinner than the second buffer layer.
- In example embodiments, the forming of the third buffer layer may include forming the second buffer layer over the first buffer layer, and doping metal elements in a surface of the second buffer layer.
- In example embodiments, the removing of the exposed third buffer layer may include performing an isotropic etch process. The second buffer layer may remain over the first buffer layer when removing the exposed third buffer layer. An under-cut region may be formed between the first spacer and the second buffer layer.
- In example embodiments, the removing of the exposed second buffer layer may include performing an isotropic etch process. The first buffer layer may remain over the substrate near the gate electrode when removing the exposed second buffer layer. The second buffer layer may be a material layer different from the first buffer layer. An under-cut region may be formed between the first spacer and the first buffer layer.
- In example embodiments, the forming of the first spacer may include forming a first spacer layer on the third buffer layer, and anisotropically etching the first spacer layer until the third buffer layer is exposed. The first spacer layer may be about 3 to 10 times thicker than the third buffer layer.
- In example embodiments, the substrate may be exposed by removing the exposed first buffer layer, after removing the first spacer. A metal silicide layer may be formed on the deep junction.
- In example embodiments, a second spacer may be formed on the side surfaces of the gate electrode, prior to the forming of the first buffer layer. A shallow junction may be formed in the substrate near the gate electrode. The second spacer may be expanded between the first buffer layer and the substrate. The second spacer may include a material layer that is the same as the first buffer layer.
- In accordance with example embodiments, a method of fabricating a semiconductor device is provided. The method may include forming a gate electrode on a substrate. An inner spacer may be formed covering side surfaces of the gate electrode and the substrate. A shallow junction may be formed in the substrate near the gate electrode. A buffer layer and an etch stop layer may sequentially be formed on the inner spacer. The etch stop layer may be an insulating layer having a plurality of metal elements. An outer spacer may be formed covering the side surfaces of the gate electrode on the etch stop layer. The etch stop layer may be exposed on the shallow junction. The buffer layer may be exposed on the shallow junction by removing the exposed etch stop layer. The inner spacer may be exposed on the shallow junction by removing the exposed buffer layer. A deep junction may be formed in the substrate using the outer spacer as an ion implantation mask. The outer spacer may be removed. The substrate may be exposed by removing the exposed inner spacer. A metal silicide layer may be formed on the deep junction. The outer spacer may include a material layer different than the etch stop layer, the buffer layer, and the inner spacer.
- In accordance with example embodiments, a method of fabricating a semiconductor device is provided. The method includes forming a gate electrode on a substrate, forming a buffering layer structure along exposed surfaces of the gate electrode, wherein the buffering layer structure includes at least two buffer layers of which an outermost buffer layer has a dielectric constant higher than at least one inner buffer layer, forming a first spacer along side surfaces of the gate electrode and partially exposing the outermost buffer layer, wherein the first spacer includes a material layer different than that of the at least two buffer layers, repeatedly exposing the buffering layer structure to sequentially pattern the at least two buffer layers, forming a deep junction in the substrate using the first spacer as an ion implantation mask, and removing the first spacer.
- Side surfaces of the deep junction may be spaced apart from the side surfaces of the gate electrode by a distance equal to a width of a patterned innermost buffer layer.
- The method may further include forming a second spacer covering side surfaces of the gate electrode and the substrate, wherein the second spacer includes a material layer different than the material layer of the first spacer, and forming a shallow junction in the substrate prior to the forming of the buffering layer structure, wherein the shallow junction corresponds to the gate electrode.
- The repeatedly exposing of the buffering layer structure may include exposing the at least one inner buffer layer over the shallow junction by removing the exposed outermost buffer layer, and exposing the second spacer over the shallow junction by removing the exposed at least one inner buffer layer.
- An innermost buffer layer of the at least two buffer layers may remain over the deep junction when removing the first spacer.
- Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
FIGS. 1-50 represent non-limiting, example embodiments as described herein. -
FIGS. 1 and 29 are flowcharts illustrating a method of fabricating a semiconductor device in accordance with example embodiments; -
FIGS. 2 to 28 and 30 to 48 are cross-sectional views illustrating processes explaining methods of fabricating of a semiconductor device in accordance with example embodiments; and -
FIGS. 49 and 50 are block diagrams illustrating a system for explaining electronic devices in accordance with application of example embodiments. - Various embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. These inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concept to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
- It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concept.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- Example embodiments relate to methods of fabricating a semiconductor device and related devices using a high-K layer as a spacer etch stop.
-
FIG. 1 is a flowchart illustrating a method of fabricating a semiconductor device in accordance with example embodiments.FIGS. 2 to 28 are cross-sectional views of processes explaining a method of fabricating of a semiconductor device in accordance with example embodiments. - Referring to
FIG. 1 , in accordance with example embodiments, a method of fabricating a semiconductor device may include forming a gate electrode (operation 110), forming an inner spacer (operation 120), forming a shallow junction (operation 130), forming a first buffer layer (operation 140), forming a second buffer layer (operation 150), forming an etch stop layer having a high-K material (operation 160), forming an outer spacer (operation 170), partially removing the etch stop layer (operation 180), partially removing the second buffer layer (operation 190), forming a deep junction (operation 200), removing the outer spacer (operation 210), forming a metal silicide layer (operation 220), and forming an interlayer insulating layer and a contact plug (operation 230). - In some example embodiments, the etch stop layer may be referred to as a third buffer layer. In other example embodiments, the inner spacer may be referred to as a first spacer, and the outer spacer may be referred to as a second spacer. In still other example embodiments, the inner spacer may be referred to as a second spacer, and the outer spacer may be referred to as a first spacer. Hereinafter, the example embodiments will be described in detail with reference to the drawings.
- Referring to
FIGS. 1 and 2 , anelement isolation layer 13 may be formed to define anactive region 12 on asubstrate 11. Agate dielectric layer 15 may be formed on theactive region 12. Agate electrode 17 may be formed on the gate dielectric layer 15 (operation 110). - The
substrate 11 may be a semiconductor substrate (e.g., a silicon wafer or a silicon on insulator (SOI)). Theactive region 12 may include P-type or N-type impurities. For example, theactive region 12 may be a single crystalline semiconductor having P-type impurities. Theelement isolation layer 13 may be formed using shallow trench isolation (STI) technology. Theelement isolation layer 13 may include an insulation layer (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof). - The
gate dielectric layer 15 may cover theactive region 12. Thegate dielectric layer 15 may include silicon oxide, silicon nitride, silicon oxynitride, a high-K material, or a combination of thereof. For example, thegate dielectric layer 15 may be silicon oxide. Thegate electrode 17 may cross over theactive region 12. Thegate electrode 17 may be formed using a thin forming process and a patterning process. Thegate electrode 17 may include a conductor (e.g., poly-silicon, a metal, metal silicide, metal nitride, or a combination thereof). For example, thegate electrode 17 may be a poly-silicon. - Referring to
FIGS. 1 and 3 , theinner spacer 19 may be formed to cover side surfaces of the gate electrode 17 (operation 120). An upper surface of thesubstrate 11 may be covered with theinner spacer 19 to a constant thickness. Theinner spacer 19 may cover the side surface and the upper surface of thegate electrode 17, and may cover thegate dielectric layer 15. Thegate dielectric layer 15 may be interposed between theinner spacer 19 and theactive region 12. Theinner spacer 19 may be L-shaped. Theinner spacer 19 may include a silicon oxide, a silicon nitride, a silicon oxynitride, or a combination thereof. For example, theinner spacer 19 may be a silicon oxide (e.g., a medium temperature oxide (MTO)). Theinner spacer 19 may be formed to have a thickness between about 5 nm and 15 nm. For example, theinner spacer 19 may be formed to have a thickness of approximately 10 nm. - Referring to
FIGS. 1 and 4 , ashallow junction 21 may be formed by ion implanting impurities into theactive region 12 near thegate electrode 17 using theinner spacer 19 as an ion implantation mask (operation 130). Theshallow junction 21 may include conductive type impurities different from theactive region 12. For example, theshallow junction 21 may include N-type impurities. Theshallow junction 21 may be arranged outside theinner spacer 19. - Referring to
FIGS. 1 and 5 , afirst buffer layer 31 may be formed on the inner spacer 19 (operation 140). Thefirst buffer layer 31 may include the same material as theinner spacer 19. For example, thefirst buffer layer 31 may be silicon oxide (e.g., medium temperature oxide (MTO)). Thefirst buffer layer 31 may be formed to have a thickness between 5 nm and 15 nm. For example, thefirst buffer layer 31 may be formed to have a thickness of approximately 10 nm. Thefirst buffer layer 31 may cover side surfaces of thegate electrode 17 and theshallow junction 21. Thefirst buffer layer 31 may be L-shaped. Theinner spacer 19 may be interposed between thefirst buffer layer 31 and thegate dielectric layer 15. - Referring to
FIGS. 1 and 6 , asecond buffer layer 33 may be formed on the first buffer layer 31 (operation 150). Thesecond buffer layer 33 may include a material layer having an etch selectivity with respect to thefirst buffer layer 31. Thesecond buffer layer 33 may include a material different from thefirst buffer layer 31. For example, thefirst buffer layer 31 may be silicon oxide, and thesecond buffer layer 33 may be silicon nitride. Thesecond buffer layer 33 may be formed to have a thickness between about 5 nm and 15 nm. Thesecond buffer layer 33 may be thinner than thefirst buffer layer 31. For example, thesecond buffer layer 33 may be formed to have a thickness of approximately 7 nm. Thesecond buffer layer 33 may cover side surfaces of thegate electrode 17 and theshallow junction 21. Thesecond buffer layer 33 may be L-shaped. Thefirst buffer layer 31 may be interposed between thesecond buffer layer 33 and theinner spacer 19. - Referring to
FIGS. 1 and 7 , anetch stop layer 35 may be formed on the second buffer layer 33 (operation 160). Theetch stop layer 35 may be referred to as a third buffer layer. Theetch stop layer 35 may include a material layer having an etch selectivity with respect to thesecond buffer layer 33. Theetch stop layer 35 may include a material different from thesecond buffer layer 33 and thefirst buffer layer 31. Theetch stop layer 35 may include a high-K material. Theetch stop layer 35 may be an insulating layer including metal elements. Theetch stop layer 35 may be an insulating layer having a higher dielectric constant than thesecond buffer layer 33. Theetch stop layer 35 may include AlO, AlSiO, (Ba,Sr) TiO, BaSrO, BeAlO, CeO, CeHfO, BiSiO, CoTiO/SiN, EuAlO, HfO, HfSiO, HfSiON, LaO, LaAlO, LaScO, LaSiO, MgAlO, NdAlO, PrAlO, SmAlO, SrTiO, PbTiO, BaTiO, TaO, TaO—TiO, TiO, TiO/SiN, WO, YO, YSiO, ZrO, PbZrO, PST (PbScTaO), PZN (PbZnNbO), PZT (PbZrTiO), PMN (PbMgNbO), Zr—Al—O, ZrSiO, (Zr,Sn) TiO, or a combination thereof. For example, theetch stop layer 35 may include HfO or HfSiO. - The
etch stop layer 35 may be formed to have a thickness between about 2 nm and 10 nm. Theetch stop layer 35 may be thinner than thesecond buffer layer 33. For example, theetch stop layer 35 may be formed to have a thickness of approximately 5 nm. Theetch stop layer 35 may cover side surfaces of thegate electrode 17 and theshallow junction 21. Theetch stop layer 35 may be L-shaped. Thesecond buffer layer 33 may be interposed between theetch stop layer 35 and thefirst buffer layer 31. - The
etch stop layer 35 may be formed on thesecond buffer layer 33 using thin-film deposition technology (e.g., an atomic layer deposition (ALD) method, a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, and a combination thereof). In example embodiments, theetch stop layer 35 may be formed by doping metal elements in the surface of thesecond buffer layer 33. For example, theetch stop layer 35 may be formed by doping Hf, Zr, Ta or a combination thereof in the surface of thesecond buffer layer 33. - Referring to
FIGS. 1 and 8 , anouter spacer layer 37L may be formed on theetch stop layer 35. Theouter spacer layer 37L may include a material layer having an etch selectivity with respect to theetch stop layer 35. Theouter spacer layer 37L may include a material different from theetch stop layer 35, thesecond buffer layer 33, and thefirst buffer layer 31. Theouter spacer layer 37L may include poly-silicon, amorphous silicon, or a combination thereof. Thefirst buffer layer 31, thesecond buffer layer 33, theetch stop layer 35 and theouter spacer layer 37L may be material layers different from one another. - The
outer spacer layer 37L may be formed to have a thickness between about 10 nm and 35 nm. Theouter spacer layer 37L may be thicker than theetch stop layer 35. Theouter spacer layer 37L may be 3 to 10 times thicker than theetch stop layer 35. For example, theouter spacer layer 37L may be formed to have a thickness of approximately 30 nm. Theouter spacer layer 37L may cover side surfaces of thegate electrode 17 and theshallow junction 21. Theouter spacer layer 37L may be L-shaped. Theetch stop layer 35 may be interposed between theouter spacer layer 37L and thesecond buffer layer 33. - Referring to
FIGS. 1 and 9 , anouter spacer 37 may be formed by anisotropically etching theouter spacer layer 37L until theetch stop layer 35 is exposed (operation 170). The anisotropic etch of theouter spacer layer 37L may be performed using a reactive ion etching (RIE) process. For example, the anisotropic etch of theouter spacer layer 37L may be applied with inductively coupled plasma-reactive ion etching (ICP-RIE), or capacitively coupled plasma-reactive ion etching (CCP-RIE), technologies. Theetch stop layer 35 may exhibit a high etch selectivity in the anisotropic etch process of theouter spacer layer 37L. Theetch stop layer 35 may be preserved (or remain) on thesecond buffer layer 33 while forming theouter spacer 37. Theetch stop layer 35 may be exposed on the upper portion of theshallow junction 21. Theetch stop layer 35 may function to prevent theshallow junction 21 from being damaged while theouter spacer 37 is formed. - In a case where the
outer spacer layer 37L is silicon nitride, and theetch stop layer 35 is silicon oxide, the ICP-RIE method exhibits an etch selectivity of approximately 6:1. - In a case where the
outer spacer layer 37L is silicon nitride, and theetch stop layer 35 is silicon oxide, the CCP-RIE method exhibits an etch selectivity of approximately 1.7:1. - As described in example embodiments, in a case where the
outer spacer layer 37L is poly-silicon or amorphous silicon and theetch stop layer 35 is an insulating layer including metal elements, the ICP-RIE method relatively exhibits a much higher etch selectivity than experimental Example 1. - In a case where the
outer spacer layer 37L is poly-silicon or amorphous silicon and theetch stop layer 35 is an insulating layer including metal elements, the CCP-RIE method relatively exhibits a much higher etch selectivity than experimental Example 2. For example, in a case where theouter spacer layer 37L is silicon nitride and theetch stop layer 35 is HfO, it was revealed that both the ICP-RIE method and the CCP-RIE method exhibit an etch selectivity of approximately 10:1 or more. - In Experimental Examples 1 and 2, it may be understood that in the spacer formation technology using a combination of silicon nitride and silicon oxide, it is difficult to protect the surface of the semiconductor substrate and there is a limitation on size reduction of the semiconductor substrate. However, in Experimental Examples 3 and 4, it may be understood that in a case where the
outer spacer layer 37L is poly-silicon or amorphous silicon and theetch stop layer 35 is an insulating layer including metal elements, theetch stop layer 35 is very favorable to prevent theshallow junction 21 from being damaged while theouter spacer 37 is formed, as described in example embodiments. In addition, even if theetch stop layer 35 has a very thin thickness, because theetch stop layer 35 can function to prevent theshallow junction 21 from being damaged, it may be understood that the configuration is favorable to reduce the size of the semiconductor device. - Referring to
FIGS. 1 and 10 , thesecond buffer layer 33 may be exposed by partially removing the etch stop layer 35 (operation 180). The removal of theetch stop layer 35 may be applied with an isotropic etching process. For example, the removal of theetch stop layer 35 may be applied with a cleaning process using a standard clean-1 (SC-1). In example embodiments, the removal of theetch stop layer 35 may be applied with a dry etching process using plasma. Thesecond buffer layer 33 may be exposed on an upper portion of thegate electrode 17. In addition, thesecond buffer layer 33 may be exposed on an upper portion of theshallow junction 21. Thesecond buffer layer 33 may exhibit a high etch selectivity with respect to theetch stop layer 35. Thesecond buffer layer 33 may function to prevent theshallow junction 21 from being damaged while theetch stop layer 35 is removed. - The
outer spacer 37 may exhibit a high etch selectivity with respect to theetch stop layer 35. Theouter spacer 37 may be preserved (or remain) on side surfaces of thegate electrode 17. Theetch stop layer 35 may be preserved (or remain) between theouter spacer 37 and thesecond buffer layer 33. A first undercut area 35UC may be formed between theouter spacer 37 and thesecond buffer layer 33. The first undercut area 35UC may be formed on a lower portion of theouter spacer 37. - Referring to
FIGS. 1 and 11 , thefirst buffer layer 31 may be exposed by partially removing the second buffer layer 33 (operation 190). The removal of thesecond buffer layer 33 may be applied with an isotropic etching process. Thefirst buffer layer 31 may be exposed on an upper portion of thegate electrode 17. In addition, thefirst buffer layer 31 may be exposed on an upper portion of theshallow junction 21. Thefirst buffer layer 31 may exhibit a high etch selectivity with respect to thesecond buffer layer 33. Thefirst buffer layer 31 may function to prevent theshallow junction 21 from being damaged while thesecond buffer layer 33 is removed. - The
etch stop layer 35 and theouter spacer 37 may exhibit a high etch selectivity with regard to thesecond buffer layer 33. Theetch stop layer 35 and theouter spacer 37 may be preserved (or remain) on side surfaces of thegate electrode 17. Thesecond buffer layer 33 may be preserved (or remain) between theetch stop layer 35 and thefirst buffer layer 31. A second undercut area 33UC may be formed between theetch stop layer 35 and thefirst buffer layer 31. The second undercut area 33UC may be formed on a lower portion of theouter spacer 37. - Referring to
FIGS. 1 and 12 , adeep junction 41 may be formed by ion-implanting impurities into theactive region 12 using theouter spacer 37 as an ion implantation mask (operation 200). Thedeep junction 41 may include conductive type impurities different from theactive region 12. Thedeep junction 41 may include the same conductive type impurities as theshallow junction 21. For example, thedeep junction 41 may include N-type impurities. Thedeep junction 41 may be aligned with an outer side of theouter spacer 37. Thegate dielectric layer 15, theinner spacer 19 and thefirst buffer layer 31 may be preserved (remain) on theshallow junction 21 while forming thedeep function 41. - Referring to
FIGS. 1 and 13 , theetch stop layer 35 may be exposed by removing the outer spacer 37 (operation 210). The removal of theouter spacer 37 may be applied with an isotropic etching process. Thefirst buffer layer 31 may exhibit a high etch selectivity with respect to theouter spacer 37. Thefirst buffer layer 31 may be preserved (or remain) on theshallow junction 21 and thedeep junction 41 while removing theouter spacer 37. Thefirst buffer layer 31 may function to prevent theshallow junction 21 and thedeep junction 41 from being damaged while theouter spacer 37 is removed. - Referring to
FIGS. 1 and 14 , upper surfaces of thegate electrode 17 and thedeep junction 41 may be exposed by partially removing thefirst buffer layer 31, theinner spacer 19 and thegate dielectric layer 15. The removal of thefirst buffer layer 31, theinner spacer 19 and thegate dielectric layer 15 may be applied with an isotropic etching process. Theetch stop layer 35 and thesecond buffer layer 33 may exhibit a high etch selectivity with regard to thefirst buffer layer 31, theinner spacer 19 and thegate dielectric layer 15. Thefirst buffer layer 31 and theinner spacer 19 may be preserved (or remain) between thesecond buffer layer 33 and thegate electrode 17. Thegate dielectric layer 15 may be preserved (or remain) between thegate electrode 17 and theactive region 12. Theetch stop layer 35 may function to prevent a side surface of thegate electrode 17 from being exposed or damaged while thefirst buffer layer 31, theinner spacer 19 and thegate dielectric layer 15 are removed. - Referring to
FIGS. 1 and 15 , metal silicide layers 43 and 45 may be formed on upper surfaces of thegate electrode 17 and the deep junction 41 (operation 220). The metal silicide layers 43 and 45 may include a firstmetal silicide layer 43 formed on thedeep junction 41, and a secondmetal silicide layer 45 formed on thegate electrode 17. The metal silicide layers 43 and 45 may include CoSi, NiSi, TiSi, TaSi, WSi, or a combination thereof. - Referring to
FIGS. 1 and 16 , an intermediateetch stop layer 55 and an interlayer insulatinglayer 57 may sequentially be formed on thesubstrate 11 having the metal silicide layers 43 and 45. Acontact plug 59 may be formed which passes through the interlayer insulatinglayer 57 and the intermediateetch stop layer 55. The intermediateetch stop layer 55 may include nitride (e.g., silicon nitride). The interlayer insulatinglayer 57 may include oxide (e.g., silicon oxide). Thecontact plug 59 may include poly-silicon, a metal, metal silicide, metal nitride, or a combination thereof. - As described above, in accordance with example embodiments, the
outer spacer 37, thefirst buffer layer 31, thesecond buffer layer 33 and theetch stop layer 35 may include material layers different from one another. Theetch stop layer 35 may exhibit a high etch selectivity in the process of forming theouter spacer 37. Thesecond buffer layer 33 may exhibit a very high etch selectivity in the process of partially removing theetch stop layer 35. Thefirst buffer layer 31 may exhibit a very high etch selectivity in the process of partially removing thesecond buffer layer 33. Thefirst buffer layer 31 may be preserved (or remain) on theshallow junction 21 and thedeep junction 41 while thedeep junction 41 is formed using theouter spacer 37. Thefirst buffer layer 31 may be preserved (or remain) on theshallow junction 21 and thedeep junction 41 while theouter spacer 37 is completely removed. Themetal silicide layer 43 may formed on thedeep junction 41 after thefirst buffer layer 31 is partially removed. Theactive region 12 may be prevented from being exposed while thedeep junction 41 is formed using theouter spacer 37. - Referring to
FIG. 17 , the etch stop layer (35 shown inFIG. 15 ) and the second buffer layer (33 shown inFIG. 15 ) may be completely removed in example embodiments. Thefirst buffer layer 31 and theinner spacer 19 may be preserved (or remain) on the side surfaces of thegate electrode 17. - Referring to
FIG. 18 , thefirst buffer layer 31 may be in contact with the intermediateetch stop layer 55. - Referring to
FIG. 19 , anelement isolation layer 13 may be formed to define (or, alternatively, delimit) anactive region 12 on asubstrate 11. Agate dielectric layer 15 may be formed on theactive region 12. Agate electrode 17 may be formed on thegate dielectric layer 15. Aninner spacer 19 may be formed to cover side surfaces of thegate electrode 17. Ashallow junction 21 may be formed on theactive region 12 near thegate electrode 17. The upper surfaces of theshallow junction 21 and thegate electrode 17 may be exposed. Thegate dielectric layer 15 may be preserved (or remain) between thegate electrode 17 and theactive region 12. Thegate dielectric layer 15 may be preserved (or remain) between theinner spacer 19 and theactive region 12. - Referring to
FIG. 20 , afirst buffer layer 31 may be formed on theinner spacer 19. Thefirst buffer layer 31 may be in contact with the upper surface of thegate electrode 17 and theshallow junction 21. Thesecond buffer layer 33, theetch stop layer 35 and theouter spacer layer 37L may sequentially be formed on thefirst buffer layer 31. - Referring to
FIG. 21 , anouter spacer 37 may be formed by anisotropically etching theouter spacer layer 37L until theetch stop layer 35 is exposed. - Referring to
FIG. 22 , thesecond buffer layer 33 may be exposed by partially removing theetch stop layer 35. - Referring to
FIG. 23 , thefirst buffer layer 31 may be exposed by partially removing thesecond buffer layer 33. Thefirst buffer layer 31 may be exposed on an upper portion of thegate electrode 17. In addition, thefirst buffer layer 31 may be exposed on theshallow junction 21. Thefirst buffer layer 31 may function to prevent theshallow junction 21 from being damaged while thesecond buffer layer 33 is removed. Adeep junction 41 may be formed by ion implanting impurities into theactive region 12 using theouter spacer 37 as an ion implantation mask. Thefirst buffer layer 31 may be preserved (or remain) on theshallow junction 21 and thedeep junction 41 while thedeep junction 41 is formed. - Referring to
FIG. 24 , theetch stop layer 35 may be exposed by removing theouter spacer 37. Thefirst buffer layer 31 may be preserved (or remain) on theshallow junction 21 and thedeep junction 41 while theouter spacer 37 is removed. Thefirst buffer layer 31 may function to prevent theshallow junction 21 and thedeep junction 41 from being damaged while theouter spacer 37 is removed. - Referring to
FIG. 25 , upper surfaces of thegate electrode 17 and thedeep junction 41 may be exposed by partially removing thefirst buffer layer 31. Metal silicide layers 43 and 45 may be formed on upper surfaces of thegate electrode 17 and thedeep junction 41 - Referring to
FIG. 26 , an intermediateetch stop layer 55 and an interlayer insulatinglayer 57 may in turn (or sequentially) be formed on thesubstrate 11 having the metal silicide layers 43 and 45. Acontact plug 59 may be formed which passes through the interlayer insulatinglayer 57 and the intermediateetch stop layer 55. - Referring to
FIG. 27 , the etch stop layer (35 shown inFIG. 25 ) and the second buffer layer (33 shown inFIG. 25 ) may be completely removed in example embodiments. Thefirst buffer layer 31 and theinner spacer 19 may be preserved (or remain) on the side surfaces of thegate electrode 17. - Referring to
FIG. 28 , thefirst buffer layer 31 may be in contact with the intermediateetch stop layer 55. - Referring to
FIG. 29 , a method of fabricating a semiconductor device in accordance with example embodiments may include forming a gate electrode (operation 110), forming an inner spacer (operation 120), forming a shallow junction (operation 130), forming a buffer layer (operation 150), forming an etch stop layer having a high-K material (operation 160), forming an outer spacer (operation 170), partially removing the etch stop layer (operation 180), partially removing the buffer layer (operation 190), forming a deep junction (operation 200), removing the outer spacer (operation 210), forming a metal silicide layer (operation 220), and forming an interlayer insulating layer and a contact plug (operation 230). Hereafter, example embodiments will be described in detail with reference to the drawings. - Referring to
FIGS. 29 and 30 , anelement isolation layer 13 may be formed to define (or delimit) anactive region 12 on asubstrate 11. Agate dielectric layer 15 may be formed on theactive region 12. Agate electrode 17 may be formed on the gate dielectric layer 15 (operation 110). Aninner spacer 19 may be formed to cover side surfaces of the gate electrode 17 (operation 120). Ashallow junction 21 may be formed by ion implanting impurities into theactive region 12 near thegate electrode 17 using theinner spacer 19 as an ion implantation mask (operation 130). Thebuffer layer 33 may be formed on the inner spacer 19 (operation 150). - The
buffer layer 33 may include a material layer having an etch selectivity with respect to theinner spacer 19. Thefirst buffer layer 33 may include a different material from theinner spacer 19. For example, theinner spacer 19 may be silicon oxide, and thebuffer layer 33 may be silicon nitride. Thebuffer layer 33 may be formed to have a thickness of about 5 nm to 15 nm. Thebuffer layer 33 may be formed to be thinner than theinner spacer 19. For example, thebuffer layer 33 may be formed to have a thickness of about 7 nm. Thebuffer layer 33 may cover a side surface of thegate electrode 17 and theshallow junction 21. Thebuffer layer 33 may be L-shaped. Theinner spacer 19 may be interposed between thebuffer layer 33 and thegate dielectric layer 15. - Referring to
FIGS. 29 and 31 , anetch stop layer 35 may be formed on the buffer layer 33 (operation 160). Anouter spacer layer 37L may be formed on theetch stop layer 35. - Referring to
FIGS. 29 and 32 , anouter spacer 37 may be formed by anisotropically etching theouter spacer layer 37L until theetch stop layer 35 is exposed (operation 170). - Referring to
FIGS. 29 and 33 , thebuffer layer 33 may be exposed by partially removing the etch stop layer 35 (operation 180). Theinner spacer 19 may be exposed by partially removing the buffer layer 33 (operation 190). Adeep junction 41 may be formed by ion implanting impurities into theactive region 12 using theouter spacer 37 as an ion implantation mask (operation 200). - Referring to
FIGS. 29 and 34 , theetch stop layer 35 may be exposed by removing the outer spacer 37 (operation 210). Theinner spacer 19 may be preserved (or remain) on theshallow junction 21 and thedeep junction 41 while theouter spacer 37 is removed. Theinner spacer 19 may function to prevent theshallow junction 21 and thedeep junction 41 from being damaged while theouter spacer 37 is removed. - Referring to
FIGS. 29 and 35 , upper surfaces of thegate electrode 17 and thedeep junction 41 may be exposed by partially removing theinner spacer 19 and thegate dielectric layer 15. Metal silicide layers 43 and 45 may be formed on upper surfaces of thegate electrode 17 and the deep junction 41 (operation 220). - Referring to
FIGS. 29 and 36 , an intermediateetch stop layer 55 and an interlayer insulatinglayer 57 may in turn (or sequentially) be formed on thesubstrate 11 having the metal silicide layers 43 and 45. Acontact plug 59 may be formed which passes through the interlayer insulatinglayer 57 and the intermediate etch stop layer 55 (operation 230). - Referring to
FIG. 37 , the etch stop layer (35 shown inFIG. 35 ) and the buffer layer (33 shown inFIG. 35 ) may be completely removed in example embodiments. Theinner spacer 19 may be preserved (or remain) on the side surfaces of thegate electrode 17. - Referring to
FIG. 38 , theinner spacer 19 may be in contact with the intermediateetch stop layer 55. - Referring to
FIG. 39 , anelement isolation layer 13 may be formed to define (or delimit) anactive region 12 on asubstrate 11. Agate dielectric layer 15 may be formed on theactive region 12. Agate electrode 17 may be formed on thegate dielectric layer 15. Thegate dielectric layer 15 may be interposed between thegate electrode 17 and theactive region 12. Aninner spacer 19 may be formed to cover side surfaces of thegate electrode 17. Theinner spacer 19 may cover theactive region 12 near both sides ofgate electrode 17. Ashallow junction 21 may be formed by ion implanting impurities into theactive region 12 near thegate electrode 17 using theinner spacer 19 as an ion implantation mask. Abuffer layer 33 may be formed on theinner spacer 19. - Referring to
FIG. 40 , anetch stop layer 35 may be formed on thebuffer layer 33. Anouter spacer layer 37L may be formed on theetch stop layer 35. - Referring to
FIG. 41 , anouter spacer 37 may be formed by anisotropically etching theouter spacer layer 37L until theetch stop layer 35 is exposed. - Referring to
FIG. 42 , thebuffer layer 33 may be exposed by partially removing theetch stop layer 35. - Referring to
FIG. 43 , theinner spacer 19 may be exposed by partially removing thebuffer layer 33. Adeep junction 41 may be formed by ion implanting impurities into theactive region 12 using theouter spacer 37 as an ion implantation mask. - Referring to
FIG. 44 , theetch stop layer 35 may be exposed by removing theouter spacer 37. - Referring to
FIG. 45 , upper surfaces of thegate electrode 17 and thedeep junction 41 may be exposed by partially removing theinner spacer 19. Metal silicide layers 43 and 45 may be formed on the upper surfaces of thegate electrode 17 and thedeep junction 41. - Referring to
FIG. 46 , an intermediateetch stop layer 55 and an interlayer insulatinglayer 57 may sequentially be formed on thesubstrate 11 having the metal silicide layers 43 and 45. Acontact plug 59 may be formed which passes through the interlayer insulatinglayer 57 and the intermediateetch stop layer 55. - Referring to
FIG. 47 , the etch stop layer (45 shown inFIG. 35 ) and the buffer layer (33 shown inFIG. 45 ) may be completely removed in example embodiments. Theinner spacer 19 may be preserved (or remain) on the side surfaces of thegate electrode 17. - Referring to
FIG. 48 , theinner spacer 19 may be in contact with the intermediateetch stop layer 55. -
FIG. 49 is a block diagram illustrating a system for explaining an electronic device in accordance with application of example embodiments. - Referring to
FIG. 49 , a semiconductor device similar to that described with reference toFIGS. 1 to 48 may be applied to anelectric system 2100. Theelectric system 2100 may include abody 2110, amicroprocessor unit 2120, apower unit 2130, a function unit 2140, and adisplay controller unit 2150. Thebody 2100 may be a mother board formed by a printed circuit board (PCB). Themicroprocessor unit 2120, thepower unit 2130, the function unit 2140, and thedisplay controller unit 2150 may be mounted on thebody 2110. Thedisplay unit 2160 may be disposed inside or outside thebody 2100. For example, thedisplay unit 2160 may be disposed on a surface of thebody 2110 to display images processed by thedisplay controller unit 2150 to a user. - The
power unit 2130 may function to receive a constant voltage from an external battery (not shown) and divide the received voltage into required voltages levels to supply the divided voltages to themicroprocessor unit 2120, the function unit 2140, thedisplay controller unit 2150, etc. Themicroprocessor unit 2120 may receive a voltage from thepower unit 2130 to then control the function unit 2140 and thedisplay controller unit 2160. The function unit 2140 may perform various functions of theelectronic system 2100. For example, in a case where theelectronic system 2100 is a portable phone, the function unit 2140 may include various components, which can perform portable functions such as dialing, outputting video to thedisplay unit 2160 and outputting audio to a speaker, in communication with anexternal apparatus 2170, and the like, and functions as a camera image processor when a camera is mounted together. - In an application of example embodiments, in a case where the
electronic system 2100 is connected with a memory card or the like in order to expand capacity, the function unit 2140 may be a memory card controller. The function unit 2140 may transmit/receive signals to/from theexternal apparatus 2170 through a wired orwireless communication unit 2180. Further, in a case where theelectronic system 2100 needs a universal serial bus (USB) in order to expand function, the function unit 2140 may function as an interface controller. Furthermore, the function unit 2140 may include a mass storage device. - The semiconductor device similar to that described with reference to
FIGS. 1 to 48 may be applied to the function unit 2140 or themicroprocessor unit 2120. For example, the function unit 2140 may include thedeep junction 41 and metal silicide layers 43 and 45. In this case, the function unit 2140 may exhibit superior electrical properties compared to the related art due to the configuration of thedeep junction 41 and metal silicide layers 43 and 45. Accordingly, the electrical properties of theelectronic system 2100 may be improved, compared to the related art. -
FIG. 50 is a block diagram schematically illustrating anotherelectronic system 2400 including at least one of semiconductor devices in accordance with application example embodiments. - Referring to
FIG. 50 , theelectronic system 2400 may include at least one of semiconductor devices in accordance with example embodiments. Theelectronic system 2400 may be used to manufacture a mobile device or computer. For example, theelectronic system 2400 may include amemory system 2412, amicroprocessor unit 2414, aRAM 2416 and apower supply device 2418. Themicroprocessor unit 2414 may program and control theelectronic system 2400. TheRAM 2416 may be used as an operation memory of themicroprocessor unit 2414. Themicroprocessor unit 2414, theRAM 2416 and/or other configuration elements may be assembled into a single package. Thememory system 2412 may store codes for operation of themicroprocessor unit 2414, data processed by themicroprocessor unit 2414, or external input data. Thememory system 2412 may include a controller and a memory. - The semiconductor device similar to that described with reference to
FIGS. 1 to 48 may be applied to themicroprocessor unit 2414, theRAM 2416, or thememory system 2412. For example, themicroprocessor unit 2414 may include thedeep junction 41 and metal silicide layers 43 and 45. In this case, themicroprocessor unit 2414 may exhibit superior electrical properties compared to the related art due to the configuration of thedeep junction 41 and metal silicide layers 43 and 45. Accordingly, the electrical properties of theelectronic system 2400 may be improved, compared to the related art. - In accordance with example embodiments, an outer spacer, a first buffer layer, the second buffer layer and the etch stop layer may be material layers different from one another. The etch stop layer may be an insulating layer including metal elements. The etch stop layer may exhibit a very high etch selectivity in a process of forming the outer spacer. The surface of the semiconductor substrate may be protected while the outer spacer is formed. Exposure of the semiconductor substrate may be prevented by using the outer spacer while a deep junction is formed. Therefore, in accordance with example embodiments, a semiconductor device can be implemented which is favorable to highly integrate and has excellent electrical properties.
- The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.
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KR101878311B1 (en) | 2018-07-17 |
US8481392B1 (en) | 2013-07-09 |
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