US20130318333A1

US20130318333A1 - Operating processors over a network

Info

Publication number: US20130318333A1
Application number: US13/679,783
Authority: US
Inventors: Tatsuya Iwamoto
Original assignee: Sony Computer Entertainment Inc
Current assignee: Sony Interactive Entertainment Inc
Priority date: 2005-09-27
Filing date: 2012-11-16
Publication date: 2013-11-28
Also published as: JP4719655B2; EP1770520A3; CN1972293A; US8316220B2; CN1941780A; US20070074206A1; JP2007095065A; EP2284702A1; EP1770520A2

Abstract

A client processor can save an execution state of a process that runs on two or more secondary processors in a single file. The single file can be transferred from the client processor over a network to a host processor. The single file is configured to permit the host processor to resume processing of the suspended process. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Description

CLAIM OF PRIORITY

This application is a continuation of U.S. patent application Ser. No. 11/238,086, filed Sep. 27, 2005 and entitled “OPERATING CELL PROCESSORS OVER A NETWORK”, the entire disclosures of which are incorporated herein by reference.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to commonly-assigned U.S. patent application Ser. No. 11/238,077, filed Sep. 27, 2005 and entitled “CELL PROCESSOR METHODS AND APPARATUS” to John P. Bates, Payton R. White and Attila Vass, now U.S. Pat. No. 8,141,076, the entire disclosures of which are incorporated herein by reference.
This application is also related to commonly-assigned U.S. patent application Ser. No. 11/238,095, filed Sep. 27, 2005, now U.S. Pat. No. 7,522,168, the entire disclosures of which are incorporated herein by reference.
This application is related to commonly-assigned co-pending U.S. patent application Ser. No. 11/238,087, filed Sep. 27, 2005, now U.S. Pat. No. 8,037,474, the entire disclosures of which are incorporated herein by reference.
This application is also related to commonly-assigned U.S. patent application Ser. No. 11/238,085, filed Sep. 27, 2005, now U.S. Pat. No. 7,506,123, the entire disclosures of which are incorporated herein by reference.

FIELD OF THE INVENTION

Embodiments of the present invention are directed cell processors and more particularly to operating multiple cell processors over a network.

BACKGROUND OF THE INVENTION

Cell processors are a type of microprocessor that utilizes parallel processing. The basic configuration of a cell processor includes a “Power Processor Element” (“PPE”) (sometimes called “Processing Element”, or “PE”), and multiple “Synergistic Processing Elements” (“SPE”). The PPEs and SPEs are linked together by an internal high speed bus dubbed “Element Interconnect Bus” (“EIB”). Cell processors are designed to be scalable for use in applications ranging from the hand held devices to main frame computers.
In certain cell processors, the SPEs provide a monolithic execution environment. Each SPE has a well isolated execution set or context that facilitates portability and network transparency of applications running on the cell processor. Such portable SPE applications have been called SPUlets or APUlets. However, there are disadvantages associated with the identical execution environment sizes for the SPUlets. Specifically, SPUlets only come in a single grain size. A normal prior art SPUlet can simply be a single executable file image that is to be loaded into a single SPE. As applications expect more resources for execution, splitting these resources into multiple SPUlets is not efficient, particularly when such SPUlets need to be transferred across a network.
Thus, there is a need in the art, for a data structure having a larger sized unit of migration so that cell processor applications can be packaged and migrated to operate and interoperate across and in a network.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a cell broadband engine architecture implementing an extended SPUlet according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a cell processor an embodiment of the present invention.

FIG. 3 is a block diagram illustrating an extended SPUlet according to an embodiment of the present invention.

FIG. 4 is a flow diagram illustrating execution of an extended SPUlet according to an embodiment of the present invention.

FIG. 5A is a block diagram illustrating memory allocation of an extended SPUlet during a stage of execution.

FIG. 5B is a block diagram illustrating memory allocation of an extended SPUlet during a different stage of execution.

FIG. 6 is a flow diagram illustrating network operation of cell processors using extended SPUlets according to an embodiment of the present invention.

FIG. 7 is a flow diagram illustrating an example of saving the state of an SPU.

FIG. 8 is a block diagram illustrating the memory structure of suspended state information to be saved for a SPUlet that has been suspended according to an embodiment of the present invention.

FIG. 9 is flow diagram illustrating an example of resuming operation of an extended SPUlet that has been suspended.

FIG. 10 is a flow diagram illustrating illustrates a process resumption of suspended execution of an SPE.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.
In embodiments of the present invention, a cell processor can load, store and save information relating to the operation of one or more SPE of the cell processor in units of migration referred to herein as extended SPUlets. Unlike prior art SPUlets, an extended SPUlet according to embodiments of the present invention may include either two or more SPU images or one or more SPU images and additional information related to operation of multiple SPU, e.g., shared initialized data. Generally, the shared data is shared by two or more SPE that execute the extended SPUlet. To isolate the execution context, it is desirable to avoid PPU access to the shared data. However, the PPU may do so for the purpose of management, such as suspend and resume. Communication between the extended SPUlet and managing PPU can be done through a message box area of memory specifically set up for that purpose. The extended SPUlet provides a larger grain size than prior art SPUlets. The extended SPUlet can address issues of setting up multiple SPEs, providing additional memory for shared initialized data, additional code, etc., and memory mapping between the SPEs and system main memory.
A cell processor may generally include four separate types of functional components: a PowerPC Processor Element (PPE), a Synergistic Processor Unit (SPU), a Memory Flow Controller (MFC) and an Internal Interrupt Controller (IIC). The computational units in the CBEA-compliant processor are the PPE and the SPU. Each SPU must have a dedicated local storage, a dedicated MFC with its associated Memory Management Unit MMU), and Replacement Management Table (RMT). The combination of these components is referred to as an SPU Element, (SPE). A cell processor may be a single chip, a multi-chip module (or modules), or multiple single-chip modules on a motherboard or other second-level package, depending on the technology used and the cost/performance characteristics of the intended design point.
By way of example, and without limitation, FIG. 1 illustrates a type of cell processor 100 characterized by an architecture known as Cell Broadband engine architecture (CBEA)—compliant processor. A cell processor can include multiple groups of PPEs (PPE groups) and multiple groups of SPEs (SPE groups) as shown in this example. Alternatively, the cell processor may have only a single SPE group and a single PPE group with a single SPE and a single PPE. Hardware resources can be shared between units within a group. However, the SPEs and PPEs must appear to software as independent elements.
In the example depicted in FIG. 1, the cell processor 100 includes a number of groups of SPEs SG-0 . . . SG_n and a number of groups of PPEs PG_0 . . . PG_p. Each SPE group includes a number of SPEs SPE0 . . . SPEg. The cell processor 100 also includes a main memory MEM and an input/output function I/O. One or more extended SPUlets 102 of the types described herein may be stored in the main memory MEM.
Each PPE group includes a number of PPEs PPE_0 . . . PPE_g SPE. In this example a group of SPEs shares a single cache SL1. The cache SL1 is a first-level cache for direct memory access (DMA) transfers between local storage and main storage. Each PPE in a group has its own first level (internal) cache L1. In addition the PPEs in a group share a single second-level (external) cache L2. While caches are shown for the SPE and PPE in FIG. 1, they are optional for cell processors in general and CBEA in particular.
An Element Interconnect Bus EIB connects the various components listed above. The SPEs of each SPE group and the PPEs of each PPE group can access the EIB through bus interface units BIU. The cell processor 100 also includes two controllers typically found in a processor: a Memory Interface Controller MIC that controls the flow of data between the EIB and the main memory MEM, and a Bus Interface Controller BIC, which controls the flow of data between the I/O and the EIB. Although the requirements for the MIC, BIC, BIUs and EIB may vary widely for different implementations, those of skill in the art will be familiar their functions and circuits for implementing them.
Each SPE is made includes an SPU (SPU0 . . . SPUg). Each SPU in an SPE group has its own local storage area LS and a dedicated memory flow controller MFC that includes an associated memory management unit MMU that can hold and process memory-protection and access-permission information.
The PPEs may be 64-bit PowerPC Processor Units (PPUs) with associated caches. A CBEA-compliant system includes a vector multimedia extension unit in the PPE. The PPEs are general-purpose processing units, which can access system management resources (such as the memory-protection tables, for example). Hardware resources defined in the CBEA are mapped explicitly to the real address space as seen by the PPEs. Therefore, any PPE can address any of these resources directly by using an appropriate effective address value. A primary function of the PPEs is the management and allocation of tasks for the SPEs in a system.
The SPUs are less complex computational units than PPEs, in that they do not perform any system management functions. They generally have a single instruction, multiple data (SIMD) capability and typically process data and initiate any required data transfers (subject to access properties set up by a PPE) in order to perform their allocated tasks. The purpose of the SPU is to enable applications that require a higher computational unit density and can effectively use the provided instruction set. A significant number of SPUs in a system, managed by the PPEs, allow for cost-effective processing over a wide range of applications. The SPUs implement a new instruction set architecture.
MFC components are essentially the data transfer engines. The MFC provides the primary method for data transfer, protection, and synchronization between main storage of the cell processor and the local storage of an SPE. An MFC command describes the transfer to be performed. A principal architectural objective of the MFC is to perform these data transfer operations in as fast and as fair a manner as possible, thereby maximizing the overall throughput of a cell processor. Commands for transferring data are referred to as MFC DMA commands. These commands are converted into DMA transfers between the local storage domain and main storage domain.
Each MFC can typically support multiple DMA transfers at the same time and can maintain and process multiple MFC commands. In order to accomplish this, the MFC maintains and processes queues of MFC commands The MFC can queue multiple transfer requests and issues them concurrently. Each MFC provides one queue for the associated SPU (MFC SPU command queue) and one queue for other processors and devices (MFC proxy command queue). Logically, a set of MFC queues is always associated with each SPU in a cell processor, but some implementations of the architecture can share a single physical MFC between multiple SPUs, such as an SPU group. In such cases, all the MFC facilities must appear to software as independent for each SPU. Each MFC DMA data transfer command request involves both a local storage address (LSA) and an effective address (EA). The local storage address can directly address only the local storage area of its associated SPU. The effective address has a more general application, in that it can reference main storage, including all the SPU local storage areas, if they are aliased into the real address space (that is, if MFC_SR1[D] is set to ‘1’).
An MFC presents two types of interfaces: one to the SPUs and another to all other processors and devices in a processing group. The SPUs use a channel interface to control the MFC. In this case, code running on an SPU can only access the MFC SPU command queue for that SPU. Other processors and devices control the MFC by using memory-mapped registers. It is possible for any processor and device in the system to control an MFC and to issue MFC proxy command requests on behalf of the SPU. The MFC also supports bandwidth reservation and data synchronization features. To facilitate communication between the SPUs and/or between the SPUs and the PPU, the SPEs and PPEs may include signal notification registers that are tied to signaling events. Typically, the PPEs and SPEs are coupled by a star topology in which the PPE acts as a router to transmit messages to the SPEs. Such a topology does not provide for direct communication between SPEs. Instead each SPE and each PPE has a one-way signal notification register referred to as a mailbox. The mailbox can be used for SPE to host OS synchronization.
The IIC component manages the priority of the interrupts presented to the PPEs. The main purpose of the IIC is to allow interrupts from the other components in the processor to be handled without using the main system interrupt controller. The IIC is really a second level controller. It is intended to handle all interrupts internal to a CBEA-compliant processor or within a multiprocessor system of CBEA-compliant processors. The system interrupt controller will typically handle all interrupts external to the cell processor.
In a cell processor system, software often must first check the IIC to determine if the interrupt was sourced from an external system interrupt controller. The IIC is not intended to replace the main system interrupt controller for handling interrupts from all I/O devices.
There are two types of storage domains within the cell processor: local storage domain and main storage domain. The local storage of the SPEs exists in the local storage domain. All other facilities and memory are in the main storage domain. Local storage consists of one or more separate areas of memory storage, each one associated with a specific SPU. Each SPU can only execute instructions (including data load and data store operations) from within its own associated local storage domain. Therefore, any required data transfers to, or from, storage elsewhere in a system must always be performed by issuing an MFC DMA command to transfer data between the local storage domain (of the individual SPU) and the main storage domain, unless local storage aliasing is enabled.
An SPU program references its local storage domain using a local address. However, privileged software can allow the local storage domain of the SPU to be aliased into main storage domain by setting the D bit of the MFC_SR1 to ‘1’. Each local storage area is assigned a real address within the main storage domain. (A real address is either the address of a byte in the system memory, or a byte on an I/O device.) This allows privileged software to map a local storage area into the effective address space of an application to allow DMA transfers between the local storage of one SPU and the local storage of another SPU.
Other processors or devices with access to the main storage domain can directly access the local storage area, which has been aliased into the main storage domain using the effective address or I/O bus address that has been mapped through a translation method to the real address space represented by the main storage domain.
Data transfers that use the local storage area aliased in the main storage domain should do so as caching inhibited, since these accesses are not coherent with the SPU local storage accesses (that is, SPU load, store, instruction fetch) in its local storage domain. Aliasing the local storage areas into the real address space of the main storage domain allows any other processors or devices, which have access to the main storage area, direct access to local storage. However, since aliased local storage must be treated as non-cacheable, transferring a large amount of data using the PPE load and store instructions can result in poor performance. Data transfers between the local storage domain and the main storage domain should use the MFC DMA commands to avoid stalls.
The addressing of main storage in the CBEA is compatible with the addressing defined in the PowerPC Architecture. The CBEA builds upon the concepts of the PowerPC Architecture and extends them to addressing of main storage by the MFCs.
An application program executing on an SPU or in any other processor or device uses an effective address to access the main memory. The effective address is computed when the PPE performs a load, store, branch, or cache instruction, and when it fetches the next sequential instruction. An SPU program must provide the effective address as a parameter in an MFC command The effective address is translated to a real address according to the procedures described in the overview of address translation in PowerPC Architecture, Book III. The real address is the location in main storage which is referenced by the translated effective address. Main storage is shared by all PPEs, MFCs, and I/O devices in a system. All information held in this level of storage is visible to all processors and to all devices in the system. This storage area can either be uniform in structure, or can be part of a hierarchical cache structure. Programs reference this level of storage using an effective address.
The main memory of a system typically includes both general-purpose and nonvolatile storage, as well as special-purpose hardware registers or arrays used for functions such as system configuration, data-transfer synchronization, memory-mapped I/O, and I/O subsystems. There are a number of different possible configurations for the main memory. By way of example and without limitation, Table I lists the sizes of address spaces in main memory for a particular cell processor implementation known as Cell Broadband Engine Architecture (CBEA)

TABLE I

Address Space	Size	Description

Real Address Space	2^m	bytes	where m ≦ 62
Effective Address Space	2⁶⁴	bytes	An effective address is translated to a virtual
			address using the segment lookaside buffer (SLB).
Virtual Address Space	2ⁿ	bytes	where 65 ≦ 80
			A virtual address is translated to a real address
			using the page table.
Real Page	2¹²	bytes
Virtual Page	2^p	bytes	where 12 ≦ p ≦ 28
			Up to eight page sizes can be supported
			simultaneously. A small 4-KB (p = 12) page is
			always supported. The number of large pages and
			their sizes are implementation-dependent.
Segment	2²⁸	bytes	The number of virtual segments is 2(n − 28) where
			65 ≦ n ≦ 80

Note:
The values of “m,” “n,” and “p” are implementation-dependent.

The cell processor 100 may include an optional facility for managing critical resources within the processor and system. The resources targeted for management under the cell processor are the translation lookaside buffers (TLBs) and data and instruction caches. Management of these resources is controlled by implementation-dependent tables.
Tables for managing TLBs and caches are referred to as replacement management tables RMT, which may be associated with each MMU. Although these tables are optional, it is often useful to provide a table for each critical resource, which can be a bottleneck in the system. An SPE group may also contain an optional cache hierarchy, the SL1 caches, which represent first level caches for DMA transfers. The SL1 caches may also contain an optional RMT.
The foregoing is intended to provide an introduction and description of the terminology used in cell processor implementations. The foregoing discussion is also intended to set forth a context for data structures and methods according to embodiments of the present invention. Such embodiments are not limited to implementation on or with cell processors having the architecture described above. However, any or all of the embodiments described below may be implemented using such cell architecture as an environment in which extended SPUlets may be encountered and utilized.
FIG. 2 depicts an example of a cell processor 200 operating with extended SPUlets. For the purposes of illustration, the cell processor includes a main memory 202, a single PPE 204 and eight SPEs 206. However, a cell processor may be configured with any number of SPE's. With respect to FIG. 2, the memory, PPE, and SPEs can communicate with each other and with an I/O device 208 over a ring-type element interconnect bus 210. Extended SPUlets 212 may be stored in main memory 202, transferred to other cell processors, e.g., via the I/O device 208 and a network 214, or loaded piecewise into the various SPEs 206 that make up the cell processor.
As set forth above, the extended SPUlets 102, 212 generally include one or more SPU images and additional data, such as uninitialized data or they may include two or more SPU images. FIG. 3 illustrates the arrangement of data that can make up an extended SPUlet 300. This data may include but is not limited to SPU images 302, share initialized data 304, information relating to uninitialized data 306 and a message box 308. The extended SPUlet 300 may optionally include a file header 310.
The SPU images 302 typically contain the contents of the local store of an SPE in a cell processor. SPU images may be gathered from the SPEs during processing with the cell processor. The SPU images may contain data that has been processed by the SPU, data to be processed by the SPU, and code for processing the data with the SPU. The SPU images 302 may also contain data regarding a DMA state of the MFC and a hardware state of the SPE when the extended SPUlet 300 was suspended. The initialized data 304 is data, having established values that can be stored in main memory and/or shared amongst several SPE that are executing a particular process, depending on the configuration. In contrast, uninitialized data has no pre-established value, but parameters regarding that data are known. For example, the information relating to uninitialized data 306 may refer to the type of data, size and location of memory space needed for that data. The message box 308 is a window of memory where incoming and outgoing streams of data can be accessed by the SPUs and PPU. The host operating system can provide system service (communication socket, etc.) through the message box 308. The extended SPUlet 300 may also return information to the client environment using the message box 308 as an interface.
The message box area 308 is used for communication between PPU and extended SPUlet 300. The message box area may be divided into multiple message boxes. Each box can be used for a single direction of communication, e.g., extended SPUlet to PPE or PPE to SPE. The message box 308 could be configured as a single buffer or a ring buffer with a management area that is updated by a reader and writer for hand shaking. The format of information within the message box area 308 is up to the application, but there could be certain preset protocols. Such preset protocols may be indicated in the file header 310.
By way of example and without limitation, the file header 310 could indicate that the message box 308 is used for the extended SPUlet to communicate back to a client using certain protocols handled by the host. Alternatively, the file header 310 may indicate that the message box 308 is used for an SPE to request system service to the PPU. Examples of such system service include requesting additional memory, opening a new network connection, and the like. Furthermore, the file header 310 may indicate that the message box 308 is used for the PPU to request suspension of the extended SPUlet 300.
It is important to note that the particular contents of an extended SPUlet depend on context. For example, when an extended SPUlet has been saved to main memory, the image of the extended SPUlet 300 in system memory includes the SPU images 302, shared initialized data 304, information regarding uninitialized data 306 and message box 308. This combination of data elements is referred to as the image of the extended SPUlet in system memory. However, when the extended SPUlet 300 is transferred from a client device across a network to another cell processor (referred to herein as a host processor) a file header 310 is combined with the SPU images 302 and initialized data 304. This combination of data elements (referred to herein as a file image) is what is transferred.
The file header 310 header may include information that tells the host cell processor about the extended SPUlet. The header information may be categorized as either Execution Information or Extended SPUlet Information. Execution Information may include Host resources, connection requirements, and other criteria describing the environment in which the SPUlet should run. Extended SPUlet information describes things like memory layout, mapping, start offsets and other initialization, message box configuration.
Such information may include, e.g., memory availability (i.e., how much memory is needed to run the extended SPUlet), SPU availability (i.e., how many SPU are needed to run the extended SPUlet), network latency and bandwidth and system frequency requirements for the extended SPUlet, control flow information (e.g., whether the host or client machine has the right to interrupt and suspend the extended SPUlet), memory offsets, breakpoints of one or more SPU images, size of one or more SPU images, memory mapping information, message box layout, message box capabilities and the like. It should be understood that the header may also define information in connection with a user, id, system, function, data type, channel, flag, key, password, protocol, target or profile or any metric in which system or operation may be established wherein such may relate to or be directed from the extended SPUlet and including but not limited to configuration, initialization, modification or synchronization of operations involving any program or system or module or object that satisfies an overall goal of the application in which the extended SPUlet operates to serve. Such applications may include security related applications and protocols, encoding, decoding and transcoding applications, transactions, etc. The file header 310 can be created by the PPE just prior to transmission and transmitted with the SPU images and initialized data. Alternatively, the file header 310 may be part of the file image and sent as part of a stack transmission.
In general, an SPU cannot access privileged SPU control. Consequently it is often necessary for the extended SPUlet 300 to load each SPE with suitable code, which can be started when loaded. Furthermore, in order to communicate, the extended SPUlet 300 desirably includes memory mapping information that maps the SPEs involved to each other and to any shared portion of main memory.
FIG. 4 illustrates a general method 400 for operating two or more cell processors over a network using extended SPUlets. The extended SPUlet is transferred as a file image from the client device to the host device at step 402. Transfer of the file image between the host and client cell processors may take place across any network or bus, including but not limited to secure and unsecure networks, local area networks (LAN), wide area networks (WAN), or a public network such as the Internet. In some embodiments, the client machine may send the file header 310 to the host machine before sending the rest of the extended SPUlet. The host machine can analyze the information in the file header for acceptance criteria, e.g., whether the host machine or another device in which the SPUlet is directed, is known or determined to have sufficient SPUs, security clearance, rights, configuration, memory, etc. available to run the extended SPUlet. The host machine can then decide whether or not to accept the extended SPUlet or pass the extended SPUlet to another device or the target machine in which the SPUlet is directed.
If the host machine accepts the extended SPUlet, it allocates system memory for the extended SPUlet at step 404. The host machine may use the information in the file header to allocate the size and data type for a block of memory for the SPU images 302 and shared initialized data 304. Once the memory space has been allocated, the host processor can load the SPU images 302 and initialized data 304 of the extended SPUlet 300 into the main memory of the host cell processor at step 406. The host cell processor can then allocate an area for uninitialized data (if any) and a message box. It is preferred that memory is allocated in main memory of the PPU. However, specialized SPUlet application may configure memory in the PPU and/or in one or more SPU local stores, depending on specialized SPUlet applications. Generally, memory is allocated in main memory to satisfy the extended reach memory requirements for complex processing, such as video transcoding. FIGS. 5A-5B illustrate the organization of data for the extended SPUlet on the cell processor of the host device (the host cell processor). As shown in 5A, the host processor received the file image containing the SPU images 302, initialized data 304 and file header 310. Typically, only the SPU images 302 and initialized data 304 are stored in the host cell processor's main memory. These form the main memory footprint of the extended SPUlet 300. The data in the header 310 may be discarded once the host processor is finished with it.
At step 408, the host cell processor allocates an area in its main memory for uninitialized data 506 and a message box 508. As shown in FIG. 5A the combination of SPU images 302, Initialized data 304 and the areas allocated for uninitialized data 506 and the message box 508 constitute the image in the host cell processors main memory for the extended SPUlet 300. At step 410, the host processor allocates SPEs 510 (as shown in FIG. 5B) for the extended SPUlet 300. Once the SPEs 510 are allocated, the SPU images 302 are loaded into the allocated SPEs 510 at step 412. The SPEs can then be run on the host cell processors at step 414.
FIG. 6 illustrates additional examples of how extended SPUlets can migrate among cell processors across a network. An extended SPUlet may be created by any client. FIG. 6 shows an example of an SPUlet created by a client cell processor 601. In this example, the client cell processor is running a process that uses two of its SPEs 602, 603. The instructions and data from are loaded from main memory 604 into SPU1 and SPU2 as indicated at 606, 608. SPU1 and SPU2 run at 610. The host cell processor's PPE 612 determines that it is necessary to interrupt at 614 and signals SPU1 and SPU2 to stop. Such an interrupt may occur for any number of reasons. For example, the PPE may determine that there is higher priority work that requires the SPEs 602, 603. Alternatively, the process may have proceeded to a point where it can be more efficiently completed elsewhere. In particular, the process may have proceeded to a point where it is about to generate a large amount of data that is to be transferred to a host device. It may be more efficient in terms of network bandwidth to transfer the partially completed process to the host device and let that device generate the data.
After the SPU1 and SPU2 are stopped local store contents of SPU1 and SPU2 are saved at 616, 618 to main memory 604 as SPU images 620, 622. At 624 the PPE 612 creates a file image an extended SPUlet containing the SPU images 620, 622 and initialized data 626. The initialized data may have been created in system memory by SPEs 602, 603 the PPE 612. The file image may be created by bundling the SPU images 620, 622 with the initialized data 626 and a file header as described above. At 628 the file image is sent over a network 630 to a host cell processor 631. Assuming acceptance criteria in the file header have been met, the SPU images 620, 622 and initialized data 626 are loaded into the host cell processor's main memory 634. From there, the SPU images 620, 622 can be loaded into the SPEs 632,633 of the host cell processor 631 as indicated at 636, 638 and run as indicated at 640, 642. The SPEs 632, 633 may continue to run until they are finished as in any normal cell processing application. Upon completion the extended SPUlet returns status to the client processor 601 and (optionally) notifies the host processor 631 of the completion. The operating system (OS) running on the host processor 631 can then destroy (i.e., overwrite) the extended SPUlet image and associated data in main memory 634.
Alternatively, at 644, the host cell processor's PPE 646 may interrupt the SPU operations on the SPEs 632, 633, e.g., to make them available for higher priority work. Once SPU operation has stopped, the SPU images can be saved to main memory as discussed above. The SPU images may be bundled with initialized data 648, code, etc. into a file image at 650. Alternatively, the PPE 646 can wait at 652 until SPEs become available. The SPUs can then resume SPU operation at 654, 656. Alternatively, the file image can be exported at 658 over the network 630 to another host 660 or back to the client processor 601.
In the preceding example SPU images 620, 622 were saved by the host cell processor 601 at 616, 618. Similarly, the process of creating the file image at 650 could involve saving SPU images on the host cell processor 631. To allow migration of the extended SPUlet a capability for suspending and resuming is desirable. Preferably, suspension involves a cooperative yield of execution. In particular, the host OS notifies the extended SPUlet to suspend. The SPUlet then stops all DMA and SPE execution, gracefully yields execution and notifies the host OS. The host OS can save the execution state of the extended SPUlet.
The flow diagram of FIG. 7 illustrates an example of a process 700 for a client or host cell processor to save an execution state for an extended SPUlet. For the purposes of illustration, this diagram shows the actions of a cell processor's PPE 701 and one of its SPE 702. Those of skill in the art will recognize that the same process can be expanded to save multiple SPU images.
The PPU 701 stop execution of whatever process is miming on the SPE 702. For example, the PPU can write to a stop register of the SPE's SPU at 703. The SPU core of the SPE 702 consequently stops at 704. In addition, it may be necessary to stop DMA activity on the MFC of the SPE 702. Specifically, the PPU 701 can write to a DMA STOP register of the MFC of the SPE 702 at 705 to stop the DMA at 706. Once DMA has stopped, at 707 the PPU 701 can harvest the DMA state of the SPE 702. This can be done by reading DMA registers containing information regarding the state of DMA operation at the time SPU execution stopped at 706. This information can be stored in main memory as part of an extended SPUlet for the SPE 702.
At 709 the PPU harvests the local state of the SPE 702, i.e., the contents of the local storage (LS) of the SPE 702. This operation may involve writing to an SPU register and DMA reading the LS contents via the MFC. The LS typically contains both code and data, which are saved to main memory as part of the extended SPUlet, e.g., the SPU image.
It is often desirable to save the hardware state of the SPU, i.e., the values of the registers and channels as part of the extended SPUlet. To save this information as part of the SPU image, the PPE may have to send an SPU SAVE code to the SPE 702 at 711. This operation may involve a register write and a DMA write to transfer the code. The PPU may then set the SPU's program counter at 713 and signal the SPU to run the SPU SAVE code at 715, e.g., by writing to the SPU's run register. The SPU starts the SPU SAVE code at 708 reads the registers and channels that make up the hardware state at 710 and sends the hardware state information to main memory at 712 as part of the extended SPUlet.
Saving the SPU image and other information is part of the process of suspending SPU operation. FIG. 8 illustrates an example of suspended information 800 that can be saved as an extended SPUlet. In this example, a task executing on a single Cell system has been suspended and made into an extended SPUlet that can migrate to another host. The information 800 includes SPU images 802, shared information 804 such as initialized data, additional code, information regarding uninitialized data 806 and a message box 808 as discussed above. The preceding information constitutes the system memory image 801. The SPU images 802 and shared information 804 may be combined with a file header 810 to form a file image 803. In addition the information 800 includes SPU images 812 corresponding to runtime LS states 805.
The SPU images 802 in the file image 803 are what gets loaded when the SPUlet starts executing. The SPU images 802 do not have to be full Local Storage size. They can load additional code from system memory on their own. The suspended SPU images 812 are snapshots of the Local Storage state, which has to be full Local Storage size and reflects the loading and unloading of code and data that had been done up to the point it was suspended.
The information 800 further includes SPE processor execution states 814 (e.g., the hardware states and DMA states discussed above). By way of example, and without limitation, the processor execution states 814 may include registers, channel state, MFC state, instruction pointer, decrementer, and floating point exception state. The execution states 814 are separated because an extended SPUlet initially does not require such information when it gets started. An extended SPUlet can assume a fresh start with no context information required. A suspended SPUlet, by contrast, needs to save all the hardware context information in order to resume execution.
In addition, the information 800 may include management information 816, such as connection information. At minimum, the host needs to store the information about the client such as IP addresses. The information necessary to resume execution and reestablish the connection with the client needs to be passed to the host where the extended SPUlet migrates to. What gets included here is dependent on the authentication model of the migration.
Although the idea does not exclude such a scenario, in order for the SPUlet to be capable of migration, it should likely need to be configured at compile time to be a migratable SPUlet.
Since migration is moving a program from one runtime environment to another, the program needs to be well isolated from anything else on the system. In embodiments of the invention a Cell-based distributed network may have all of its executable programs in the form of extended SPUlets to start with. In such a case if an extended SPUlet starts executing locally, migration to another host only requires saving the context. It is not necessary to dynamically create an extended SPUlet from arbitrary working sets of SPE programs.
The preceding discussion of FIG. 6 mentions resumption of suspended SPUlets at 654, 656. By way of example, and without loss of generality, the flow diagram of FIG. 9 illustrates a process 900 for resumption of suspended execution of an extended SPUlet. At 902 system resources, such as SPEs, and main memory, message box, etc. are reallocated to run the extended SPUlet. At 904 a main memory portion of the saved information, e.g., the SPU local store runtime images are loaded into SPEs. At 906 the SPE execution states are restored and execution of the SPEs resumes at 908.
By way of example, and without loss of generality, the flow diagram of FIG. 10 illustrates in further detail a process resumption of suspended execution of an SPE 1002 of a cell processor 1001. Those of skill in the art will recognize that the process depicted in FIG. 10 may be expanded to include resumption of suspended execution of multiple SPEs. In this example, a main memory 1004 of a cell processor 1001 is loaded with an extended SPUlet 1006, e.g., a file image, containing an SPU hardware state 1008, an SPU local store image 1010 and a DMA state 1012. The extended SPUlet 1006 may have been stored as a result of interruption and suspension of a process running on the cell processor 1001 or it may have been imported from another cell processor. In either case it is assumed for the purposes of this example that the SPE 1002 is stopped at 1014.
The PPU 1016 of the cell processor 1001 sends a hardware state loader program 1018 to the SPE 1002. This operation may involve a DMA write to the LS of the SPE 1002 and a register write to the SPU of the SPE 1002 to run the hardware state loader program at 1020. At 1022, under control of the hardware state loader program 1020, the SPE 1002 loads the SPU hardware state 1008 from the extended SPUlet 1006 stored in main memory 1004 and executes a STOP and SIGNAL instruction. Under this instruction, execution of the program in the SPU stops, and the external environment (e.g., the PPU 1016) is signaled. No further instructions are executed. At 1024 The PPU 1016 then loads the SPU image 1010 from main memory 1004 to the local store of the SPE 1002. At 1026, the PPU 1016 loads the DMA state 1012 from main memory 1004 to SPE local store, e.g., by writing to appropriate registers.
The PPU 1016 sends a DMA start command to the SPEs MFC at 1028 to start DMA operation. This may involve writing to an MFC start register. DMA runs commence at 1030. The program counter is set at 1032. The PPU 1016 sends an SPU run command at 1034, e.g., by writing to an SPU run register. The SPU then runs at 1036, e.g., starting from the point where operation had been suspended.
Note that the process for initially loading an extended SPUlet the hardware state filling and DMA state loading steps is essentially as described above with respect to FIG. 10 except that the hardware state and DMA state loading sequences may be eliminated. For an initial load, there is generally to DMA or hardware state to restore.
While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature described herein, whether preferred or not, may be combined with any other feature described herein, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.”

Claims

What is claimed is:

1. A method for operating a client processor and a host processor over a network, wherein the client processor has a client main memory, a client main processor and two or more client secondary processors and the host processor has a host main processor, a host main memory and two or more host secondary processors, wherein each client secondary processor and each host secondary processor has an exclusively associated memory, the method comprising:

running a process on a client processor wherein the process runs on two or more client secondary processors;

suspending the process that runs on the two or more client secondary processors;

saving an execution state of the process that runs on the two or more client secondary processors by either

a) saving an execution state of two or more client secondary processors running the process on the client processor into a single file in the main memory, wherein the execution state includes contents of the exclusively associated memories for the two or more client secondary processors, and a hardware state of the two or more client secondary processors that were miming the process, wherein the contents of the exclusively associated memories for the two or more client secondary processors includes executable code for miming the process, or

b) saving an execution state of one or more of the client secondary processors that were running the process that runs on the two or more client secondary processors and shared initialized data for the process that runs on the two or more client secondary processors into a single file in the main memory, wherein the execution state includes contents of the exclusively associated memory for at least one of the client secondary processors and shared initialized data of the suspended process and a hardware state of the at least one of the client secondary processors that were running the suspended process, wherein the contents of the exclusively associated memory of the at least one of the client secondary processors includes executable code for running the process; and

transferring the single file from the client processor over a network to the host processor;

wherein the single file containing the saved execution state of the process is configured to permit the host processor to resume processing of the suspended process.

2. The method of claim 1, further comprising allocating space in a main memory of a host processor (host main memory) for the contents of the exclusively associated memory of the one secondary processor and initialized data.

3. The method of claim 1 further comprising, allocating an area in a main memory of a host processor (host main memory) for uninitialized data and a message box.

4. The method of claim 1, further comprising loading the file onto the host processor.

5. The method of claim 1 wherein saving the state includes stopping a core of the secondary processor miming the process.

6. The method of claim 1 wherein saving the state further includes sending a save code to the secondary processor and running the code on the secondary processor.

7. The method of claim 1, further comprising resuming the process on a secondary processor of the host processor.

8. The method of claim 1, further comprising transferring a file header from the client processor to the host processor.

9. A non-transitory processor readable medium having embodied therein executable code and data representing a saved execution state of a processor system having a main processing unit, two or more secondary processors, and a main memory coupled to the main and secondary processors, wherein each secondary processor has an exclusively associated memory, the saved execution state comprising:

a single file containing either

a) contents of the exclusively associated memory for one of the two or more secondary processors and shared initialized data related to a suspended process execution state, wherein the contents of the exclusively associated memory and shared initialized data include executable code configured to run the suspended process on the processor system or

b) contents of exclusively associated memories of two or more secondary processors related to the execution state of a suspended process including executable code for processing data with the two or more secondary processors and data to be processed by executing the code with the two or more of the secondary processors, wherein the contents of the two or more of the exclusively associated memories include executable code configured to run the suspended process on the processor system;

wherein the single file containing the saved execution state of the process is configured to permit a different processor system to resume processing of the suspended process.

10. The processor readable medium of claim 9 wherein the file further comprises a file header.

11. The processor readable medium of claim 10 wherein the file header includes one or more of the following types of information: memory availability, secondary processor availability, network latency, network bandwidth, system frequency, control flow information, memory offsets, breakpoints of contents of one or more exclusively associated local memories for secondary processors, size of contents of one or more exclusively associated local memories for secondary processors, memory layout, memory mapping information, host resources, connection requirements, and other criteria describing the environment in which the file should run.

12. The processor readable medium of claim 10 wherein the file header defines information in connection with a user, id, system, function, data type, channel, flag, key, password, protocol, target or profile or any metric in which system or operation may be established wherein such may relate to or be directed from the file.

13. The processor readable medium of claim 10 wherein the file header defines information related to configuration, initialization, modification or synchronization of operations involving any program or system or module or object that satisfies an overall goal of the application in which the file operates.

14. The processor readable medium of claim 11 wherein the control flow information includes information regarding whether a host or client processor can interrupt the process.

15. A processor system having a main processing unit, two or more secondary processors and a main memory coupled to the main and secondary processors, wherein each secondary processor has an exclusively associated memory, the processor having embodied in the main memory or exclusively associated memory data representing a saved process execution state of a suspended process, the saved process execution state comprising:

a single file containing either

a) contents of an exclusively associated memory of a secondary processor and shared initialized data related to a suspended process execution state of a different processor system, wherein the contents of the exclusively associated memory includes executable code for running the suspended process on the processor system, or

b) contents of exclusively associated memories of two or more secondary processors related to the saved process execution state, wherein the contents of the two or more secondary processors includes executable code for running the suspended process on the processor system;

16. The processor system of claim 15 wherein the file further comprises a file header.

17. The processor system of claim 16 wherein the file header includes one or more of the following types of information: memory availability, secondary processor availability, network latency, network bandwidth, system frequency, control flow information, memory offsets, breakpoints of contents of one or more exclusively associated local memories for secondary processors, size of contents of one or more exclusively associated local memories for secondary processors, memory layout, memory mapping information, host resources, connection requirements, and other criteria describing the environment in which the file should run.

18. The processor system of claim 16 wherein the file header defines information in connection with a user, id, system, function, data type, channel, flag, key, password, protocol, target or profile or any metric in which system or operation may be established wherein such may relate to or be directed from the file.

19. The processor system of claim 16 wherein the file header defines information related to configuration, initialization, modification or synchronization of operations involving any program or system or module or object that satisfies an overall goal of the application in which the file operates.

20. The processor system of claim 17 wherein the control flow information includes information regarding whether a host or client processor system can interrupt the process.