US20130326161A1 - Method and Host Device for Assessing Execution of Trim Commands - Google Patents
Method and Host Device for Assessing Execution of Trim Commands Download PDFInfo
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- US20130326161A1 US20130326161A1 US13/524,924 US201213524924A US2013326161A1 US 20130326161 A1 US20130326161 A1 US 20130326161A1 US 201213524924 A US201213524924 A US 201213524924A US 2013326161 A1 US2013326161 A1 US 2013326161A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3485—Performance evaluation by tracing or monitoring for I/O devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0653—Monitoring storage devices or systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
Definitions
- Non-volatile memory storage devices based on NAND technology employ an erase/program cycle, which may impact performance if free blocks are not available at the time of write.
- Modern NAND-based storage devices erase blocks of storage proactively when they are not in use to improve performance.
- some host devices can send “trim” commands to NAND storage devices in order to indicate to the storage device that a certain logical block address (LBA) range is no longer in use by the host's file system.
- LBA logical block address
- trim commands effectively requires tuning and analysis to insure that enough free blocks are available and that the trim commands themselves do not reduce performance/endurance.
- Microsoft's Performance Toolkit includes the ability to log input/output commands at the driver level, but it lacks the analysis capability required to properly assess the effectiveness of trim commands in order to optimize performance.
- a trace of trim and write commands sent to a storage device are obtained.
- a subsequent write command to a same logical block address (LBA) as the trim command is identified, and an elapsed time between the trim and write commands is calculated.
- LBA logical block address
- This information can be used to display a histogram of the data and/or to optimize when the storage device executes trim commands and/or when the host device issues trim commands.
- Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.
- FIG. 1 is a block diagram of an exemplary host device and storage device of an embodiment.
- FIG. 2 is a flow chart of a trim command analysis process of an embodiment.
- FIG. 3 is a histogram resulting from a trim command analysis process of an embodiment.
- FIG. 4 is a flow chart of a trim command analysis process using free-space analysis of an embodiment.
- FIG. 5 is a flow chart of a trim command analysis process using physical free-block-count analysis of an embodiment.
- FIG. 1 is a block diagram of a host device 50 in communication with a storage device 100 of an embodiment.
- the phrase “in communication with” could mean directly in communication with or indirectly in communication with through one or more components, which may or may not be shown or described herein.
- the host device 50 and storage device 100 can each have mating physical connectors (interfaces) that allow the storage device 100 to be removably connected to the host device 50 .
- the host device 50 can take any suitable form, such as, but not limited to, a mobile phone, a digital media player, a game device, a personal digital assistant (PDA), a personal computer (PC), a kiosk, a set-top box, a TV system, a book reader, or any combination thereof.
- a mobile phone such as, but not limited to, a mobile phone, a digital media player, a game device, a personal digital assistant (PDA), a personal computer (PC), a kiosk, a set-top box, a TV system, a book reader, or any combination thereof.
- PDA personal digital assistant
- PC personal computer
- kiosk a set-top box
- TV system such as, but not limited to, a TV system, a book reader, or any combination thereof.
- the storage device 100 is a mass storage device and takes the form of a solid-state drive (SSD), as that type of storage device currently supports the trim command.
- SSD solid-state drive
- Other storage devices that can be used if they support the trim command include, but are not limited to, a handheld, removable memory card (such as a Secure Digital (SD) card or a MultiMedia Card (MMC)), a universal serial bus (USB) device, and embedded memory (e.g., a secure module embedded in the host device 50 ), such as an iNANDTM eSD/eMMC embedded flash drive by SanDisk Corporation.
- SD Secure Digital
- MMC MultiMedia Card
- USB universal serial bus
- embedded memory e.g., a secure module embedded in the host device 50
- iNANDTM eSD/eMMC embedded flash drive by SanDisk Corporation.
- the storage device 100 comprises a controller 110 and a memory 120 .
- the controller 110 comprises a memory interface 111 for interfacing with the memory 120 and a host interface 112 for interfacing with the host 50 .
- the controller 110 also comprises a central processing unit (CPU) 115 .
- the controller 110 can be implemented in any suitable manner.
- the controller 110 can take the form of a microprocessor or processor and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example.
- Suitable controllers can be obtained from Marvell or SandForce.
- the memory 120 can take any suitable form.
- the memory 120 takes the form of a solid-state (e.g., flash) memory.
- solid-state e.g., flash
- other forms of memory suitable for use with a trim command such as optical memory using packet-based writing can be used.
- the storage device 100 shown in FIG. 1 is but one of many possible implementations.
- the host device 50 comprises a controller 160 that has a storage device interface 161 for interfacing with the storage device 100
- the controller 160 also comprises a central processing unit (CPU) 163 , read access memory (RAM) 165 , and read only memory (ROM) 166 .
- the storage device 100 also contains a memory 172 for storing, for example, applications (apps) and programs (e.g., a browser, a media player, etc.) used in the operation of the host device 50 .
- the controller's RAM 165 and/or the memory 172 can be used as a buffer for storing commands to be sent to the storage device 100 .
- the host device 50 can contain other components (e.g., a display device, a speaker, a headphone jack, a video output connection, etc.), which are not shown in FIG. 1 to simplify the drawings. Also, other implementations of the host device 50 are possible.
- other components e.g., a display device, a speaker, a headphone jack, a video output connection, etc.
- the host device 50 is operable to render content stored in the storage device 100 .
- content can take any suitable form, including, but not limited to, a song, a movie, a game, an application (“app”), a game installer, etc.
- “render” can mean playing (e.g., when the content is a song or movie), deciphering (e.g., when the content is a game installer), or whatever action is needed to “enjoy” the content.
- the host device 50 contains the necessary software to render the content (e.g., a media player), whereas, in other embodiments, such software is provided to the host device 50 by the memory device 100 or another entity.
- the host device 50 can issue a “trim” command to inform the storage device 100 if a logical block address (LBA) is no longer in use (e.g., when a user deletes a file, when a file is moved or defragmented, etc.).
- LBA logical block address
- the storage device 100 may erase the page that contains the LBA, which provides additional free space to hold data for subsequent writes.
- the trim command from the host device 50 is often followed by a write command to write data to the erased LBA. If the storage device 100 executes the trim command when received from the host device 50 , the storage device 100 may incur an unnecessary performance penalty, as the erase process takes time and may not be immediately needed if there are free blocks available to execute the write command. Instead, the storage device 100 can execute the write command by storing data in the free blocks and, later during idle time, perform the erase operation. However, typical storage devices execute trim commands upon receipt.
- the following embodiments provide techniques that can be used to analyze the elapsed time between when a host device sends a trim command and when it sends a subsequent write command to the same LBA.
- This time delta can be used to assess trim command efficiency and determine whether the storage device 100 can delay or avoid execution of a trim command and still achieve the same or similar performance level as if the trim command were executed upon receipt.
- This information can also be used to delay when a trim command is sent by the host device 50 to the storage device 100 .
- the information can be visually displayed to a user (e.g., via a histogram) and/or can be used to manually, automatically, or semi-automatically tune the algorithm for executing or sending trim commands.
- the analysis can show whether the trim command, if executed immediately, would improve performance by freeing blocks that would otherwise have to be erased during the execution of a write command.
- FIG. 2 is a flow chart 200 of a trim command analysis process of an embodiment.
- the process starts by beginning a linear analysis of a capture trace of commands from the host device 50 to the storage device 100 that include trim and write commands (act 210 ).
- this process can be performed by the host device 50 , by the storage device 100 , or by a device (e.g., a bus analyzer) between the host device 50 and the storage device 100 .
- the trace can be a log of the commands sent to the storage device 100 .
- the trace can be a log of commands received from the host device 50 by the storage device 100 .
- the trace can be the commands captured in the transmission from the host device 50 to the storage device 100 . Also, this process can be done in real time as the commands are being sent to the storage device 100 or in an off-line manner.
- the storage device 100 does not need to execute trim commands immediately, as, on average, it takes at least 15 seconds before the host device 50 sends a write command to the same LBA. If it turns out that a write command is received in less than 15 second from the receipt of the trim command, the storage device 100 can still execute the write command without erasing if there are sufficient free blocks in the memory. Otherwise, the storage device 100 can perform the erase operation when it receives the write command sooner.
- a user or technician can tune the firmware of the storage device 100 , so the storage device 100 will delay at least 15 second before performing a trim command.
- the information from the histogram on the number of writes issued sooner than 15 seconds as a proportion of the total number of writes in the trace can be used to inform the storage device 100 of the average number of free blocks it should have available.
- the analysis can be performed by any suitable device, and the histogram can be displayed on the host device 50 or some other device. Also, instead of or in addition to displaying a histogram, the information gathered by this process can be used to tune the storage device 100 and/or the host device 50 to adjust the delay in executing or transmitting, respectively, a trim command.
- an operating system free disk space query may be used to further enhance the analysis by calculating theoretical free space available to the storage device 100 . That is, if the process knows how much free space there is, it can factor in how important it is to perform a trim command to obtain more free space (e.g., by adjusting the frequency of performing trim commands based on available free space).
- This is shown in the flow chart 400 of FIG. 4 . Acts 410 - 460 in this flow chart 400 are virtually identical to acts 210 - 260 in the flow chart 200 of FIG. 2 except for the added step of checking free space at the time of the trim command (act 422 ).
- the host device 50 will provide what its operating system believes to be the free space available on the storage device.
- Such commands can be issued periodically or once at the beginning of the analysis and thereafter adjusting the count based on the number of trims and writes.
- the free space information can be used along with the calculated elapsed time between trim and write commands to generate the histogram (act 435 ) or perform any other of the optimizations noted above.
- the process shown in FIG. 4 provides a more accurate analysis than the process shown in FIG. 2
- the free space used in that analysis may not be accurate, as the information is coming from the host device's operating system and not the storage device 100 and assumes that trim commands sent by the host device 50 are, in fact, executed by the storage device 100 . That is, anything marked as trimmed by the host's operating system, even thought not yet trimmed by the storage device 100 , will be marked as free space.
- the process takes into account the actual free space on the storage device 100 . This embodiment will be illustrated in conjunction with the flow chart 500 in FIG. 5 . Acts 510 - 560 in this flow chart 500 are virtually identical to acts 410 - 460 in the flow chart 400 of FIG.
Abstract
A method and host device for assessing execution of trim commands are provided. In one embodiment, a trace of trim and write commands sent to a storage device are obtained. For each trim command in the trace, a subsequent write command to a same logical block address (LBA) as the trim command is identified, and an elapsed time between the trim and write commands is calculated. This information can be used to display a histogram and/or to optimize when the storage device executes trim commands and/or when the host device issues trim commands.
Description
- This application claims the benefit of U.S. Provisional Patent Application No. 61/654,006, which was filed on May 31, 2012 and is hereby incorporated by reference herein.
- Non-volatile memory storage devices based on NAND technology employ an erase/program cycle, which may impact performance if free blocks are not available at the time of write. Modern NAND-based storage devices erase blocks of storage proactively when they are not in use to improve performance. At present, some host devices can send “trim” commands to NAND storage devices in order to indicate to the storage device that a certain logical block address (LBA) range is no longer in use by the host's file system. However, using trim commands effectively requires tuning and analysis to insure that enough free blocks are available and that the trim commands themselves do not reduce performance/endurance. Microsoft's Performance Toolkit includes the ability to log input/output commands at the driver level, but it lacks the analysis capability required to properly assess the effectiveness of trim commands in order to optimize performance.
- Embodiments of the present invention are defined by the claims, and nothing in this section should be taken as a limitation on those claims.
- By way of introduction, the below embodiments relate to a method and host device for assessing execution of trim commands. In one embodiment, a trace of trim and write commands sent to a storage device are obtained. For each trim command in the trace, a subsequent write command to a same logical block address (LBA) as the trim command is identified, and an elapsed time between the trim and write commands is calculated. This information can be used to display a histogram of the data and/or to optimize when the storage device executes trim commands and/or when the host device issues trim commands. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.
-
FIG. 1 is a block diagram of an exemplary host device and storage device of an embodiment. -
FIG. 2 is a flow chart of a trim command analysis process of an embodiment. -
FIG. 3 is a histogram resulting from a trim command analysis process of an embodiment. -
FIG. 4 is a flow chart of a trim command analysis process using free-space analysis of an embodiment. -
FIG. 5 is a flow chart of a trim command analysis process using physical free-block-count analysis of an embodiment. - Exemplary Host and Storage Devices
- Turning now to the drawings,
FIG. 1 is a block diagram of ahost device 50 in communication with astorage device 100 of an embodiment. As used herein, the phrase “in communication with” could mean directly in communication with or indirectly in communication with through one or more components, which may or may not be shown or described herein. For example, thehost device 50 andstorage device 100 can each have mating physical connectors (interfaces) that allow thestorage device 100 to be removably connected to thehost device 50. Thehost device 50 can take any suitable form, such as, but not limited to, a mobile phone, a digital media player, a game device, a personal digital assistant (PDA), a personal computer (PC), a kiosk, a set-top box, a TV system, a book reader, or any combination thereof. - In this embodiment, the
storage device 100 is a mass storage device and takes the form of a solid-state drive (SSD), as that type of storage device currently supports the trim command. Other storage devices that can be used if they support the trim command include, but are not limited to, a handheld, removable memory card (such as a Secure Digital (SD) card or a MultiMedia Card (MMC)), a universal serial bus (USB) device, and embedded memory (e.g., a secure module embedded in the host device 50), such as an iNAND™ eSD/eMMC embedded flash drive by SanDisk Corporation. - As shown in
FIG. 1 , thestorage device 100 comprises acontroller 110 and amemory 120. Thecontroller 110 comprises amemory interface 111 for interfacing with thememory 120 and ahost interface 112 for interfacing with thehost 50. Thecontroller 110 also comprises a central processing unit (CPU) 115. Thecontroller 110 can be implemented in any suitable manner. For example, thecontroller 110 can take the form of a microprocessor or processor and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. Suitable controllers can be obtained from Marvell or SandForce. Thememory 120 can take any suitable form. In one embodiment, thememory 120 takes the form of a solid-state (e.g., flash) memory. However, other forms of memory suitable for use with a trim command, such as optical memory using packet-based writing can be used. It should be noted that thestorage device 100 shown inFIG. 1 is but one of many possible implementations. - Turning now to the
host device 50, thehost device 50 comprises acontroller 160 that has astorage device interface 161 for interfacing with thestorage device 100 Thecontroller 160 also comprises a central processing unit (CPU) 163, read access memory (RAM) 165, and read only memory (ROM) 166. Thestorage device 100 also contains amemory 172 for storing, for example, applications (apps) and programs (e.g., a browser, a media player, etc.) used in the operation of thehost device 50. The controller'sRAM 165 and/or thememory 172 can be used as a buffer for storing commands to be sent to thestorage device 100. Thehost device 50 can contain other components (e.g., a display device, a speaker, a headphone jack, a video output connection, etc.), which are not shown inFIG. 1 to simplify the drawings. Also, other implementations of thehost device 50 are possible. - In some environments, the
host device 50 is operable to render content stored in thestorage device 100. As used herein, “content” can take any suitable form, including, but not limited to, a song, a movie, a game, an application (“app”), a game installer, etc. Depending on the type of content, “render” can mean playing (e.g., when the content is a song or movie), deciphering (e.g., when the content is a game installer), or whatever action is needed to “enjoy” the content. In some embodiments, thehost device 50 contains the necessary software to render the content (e.g., a media player), whereas, in other embodiments, such software is provided to thehost device 50 by thememory device 100 or another entity. - Embodiments Related to Assessing Execution of Trim Commands
- The
host device 50 can issue a “trim” command to inform thestorage device 100 if a logical block address (LBA) is no longer in use (e.g., when a user deletes a file, when a file is moved or defragmented, etc.). In response to the trim command, thestorage device 100 may erase the page that contains the LBA, which provides additional free space to hold data for subsequent writes. The trim command from thehost device 50 is often followed by a write command to write data to the erased LBA. If thestorage device 100 executes the trim command when received from thehost device 50, thestorage device 100 may incur an unnecessary performance penalty, as the erase process takes time and may not be immediately needed if there are free blocks available to execute the write command. Instead, thestorage device 100 can execute the write command by storing data in the free blocks and, later during idle time, perform the erase operation. However, typical storage devices execute trim commands upon receipt. - The following embodiments provide techniques that can be used to analyze the elapsed time between when a host device sends a trim command and when it sends a subsequent write command to the same LBA. This time delta can be used to assess trim command efficiency and determine whether the
storage device 100 can delay or avoid execution of a trim command and still achieve the same or similar performance level as if the trim command were executed upon receipt. This information can also be used to delay when a trim command is sent by thehost device 50 to thestorage device 100. The information can be visually displayed to a user (e.g., via a histogram) and/or can be used to manually, automatically, or semi-automatically tune the algorithm for executing or sending trim commands. In addition, the analysis can show whether the trim command, if executed immediately, would improve performance by freeing blocks that would otherwise have to be erased during the execution of a write command. - Returning to the drawings,
FIG. 2 is aflow chart 200 of a trim command analysis process of an embodiment. As shown inFIG. 2 , the process starts by beginning a linear analysis of a capture trace of commands from thehost device 50 to thestorage device 100 that include trim and write commands (act 210). It should be noted that this process can be performed by thehost device 50, by thestorage device 100, or by a device (e.g., a bus analyzer) between thehost device 50 and thestorage device 100. For example, if performed by thehost device 50, the trace can be a log of the commands sent to thestorage device 100. If performed by thestorage device 100, the trace can be a log of commands received from thehost device 50 by thestorage device 100. If performed by a bus analyzer or other intermediary device, the trace can be the commands captured in the transmission from thehost device 50 to thestorage device 100. Also, this process can be done in real time as the commands are being sent to thestorage device 100 or in an off-line manner. - Next, it is determined whether there is a trim command in the trace (act 215), and, if there is, an attempt is made to identify the first write command to the same LBA (acts 220 and 225). This may involve skipping read and other commands that may be present between the trim and write commands. If a write to the same LBA is found, the elapsed time between the trim and write commands is calculated (act 230), and the resulting calculation is saved (act 235) (here, for the generation of a histogram; however, as noted above, the calculation can be used to tune the trim execution or transmission algorithms).
- If a write to the same LBA is not found, it is determined whether another trim command was performed on the same LBA without an intervening write command (act 240). If another trim command was performed (either by error or due to the programming of the host device 50), the process logs this event as a “double trim” event (act 245). If, on the other hand, another trim command was not performed, the process logs this event as a “never rewritten” event (act 250). This can occur, for example, if the
host device 50 did not properly record the first trim command as having occurred. - The above process is repeated for the remaining trims in the trace. At the conclusion, a histogram from the calculations is displayed (act 255), and the process ends (act 260). An example of the resulting histogram is shown in
FIG. 3 . This histogram shows number of writes on the y-axis and the time between trim and write commands on the x-axis over a 30-day period. As shown inFIG. 3 , for the vast majority of writes, there were 15 or more seconds between trim and write commands to the same LBA. (There is also a significant number of “double trim” events and “never rewritten” events.) This means that thestorage device 100 does not need to execute trim commands immediately, as, on average, it takes at least 15 seconds before thehost device 50 sends a write command to the same LBA. If it turns out that a write command is received in less than 15 second from the receipt of the trim command, thestorage device 100 can still execute the write command without erasing if there are sufficient free blocks in the memory. Otherwise, thestorage device 100 can perform the erase operation when it receives the write command sooner. - With this histogram, a user or technician can tune the firmware of the
storage device 100, so thestorage device 100 will delay at least 15 second before performing a trim command. Also, the information from the histogram on the number of writes issued sooner than 15 seconds as a proportion of the total number of writes in the trace can be used to inform thestorage device 100 of the average number of free blocks it should have available. As noted above, the analysis can be performed by any suitable device, and the histogram can be displayed on thehost device 50 or some other device. Also, instead of or in addition to displaying a histogram, the information gathered by this process can be used to tune thestorage device 100 and/or thehost device 50 to adjust the delay in executing or transmitting, respectively, a trim command. - There are many alternatives that can be used with these embodiments. For example, an operating system free disk space query may be used to further enhance the analysis by calculating theoretical free space available to the
storage device 100. That is, if the process knows how much free space there is, it can factor in how important it is to perform a trim command to obtain more free space (e.g., by adjusting the frequency of performing trim commands based on available free space). This is shown in theflow chart 400 ofFIG. 4 . Acts 410-460 in thisflow chart 400 are virtually identical to acts 210-260 in theflow chart 200 ofFIG. 2 except for the added step of checking free space at the time of the trim command (act 422). This can be performed, for example, by sending a Get Disk Free Space command in a Windows-based host device or a STAT command in a Linux-based host device. In response to such a command, thehost device 50 will provide what its operating system believes to be the free space available on the storage device. Such commands can be issued periodically or once at the beginning of the analysis and thereafter adjusting the count based on the number of trims and writes. The free space information can be used along with the calculated elapsed time between trim and write commands to generate the histogram (act 435) or perform any other of the optimizations noted above. - While the process shown in
FIG. 4 provides a more accurate analysis than the process shown inFIG. 2 , the free space used in that analysis may not be accurate, as the information is coming from the host device's operating system and not thestorage device 100 and assumes that trim commands sent by thehost device 50 are, in fact, executed by thestorage device 100. That is, anything marked as trimmed by the host's operating system, even thought not yet trimmed by thestorage device 100, will be marked as free space. To address this, in another embodiment, the process takes into account the actual free space on thestorage device 100. This embodiment will be illustrated in conjunction with theflow chart 500 inFIG. 5 . Acts 510-560 in thisflow chart 500 are virtually identical to acts 410-460 in theflow chart 400 ofFIG. 4 except the physical blocks/pages from the storage device's flash translation layer (FTL) are checked instead of checking free space designated by the host device 50 (act 522). (The FTL maps the host LBAs to physical blocks in the memory.) This operation can be performed with a proprietary command to thestorage device 100. As with the above processes, the result of this process can be used for the generation of a histogram and/or for firmware, software, and infrastructure optimizations in order to improve performance of trim operations. - Conclusion
- It is intended that the foregoing detailed description be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any of the preferred embodiments described herein can be used alone or in combination with one another.
Claims (29)
1. A host device comprising:
a storage device interface through which the host device can communicate with a storage device; and
a controller in communication with storage device interface, wherein the controller is configured to:
obtain a trace of trim and write commands sent to the storage device; and
for each trim command in the trace:
identify a subsequent write command to a same logical block address (LBA) as the trim command; and
calculate an elapsed time between the trim and write commands.
2. The host device of claim 1 , wherein the controller is further configured to:
generate a histogram based on the calculated elapse time.
3. The host device of claim 1 , wherein the controller is further configured to:
adjust when the storage device executes trim commands based on the calculated elapse time.
4. The host device of claim 1 , wherein the controller is further configured to:
adjust when the host device issues trim commands based on the calculated elapse time.
5. The host device of claim 1 , wherein the controller is further configured to:
if a subsequent write command to the same LBA is not identified, determine whether another trim command was issued to the same LBA without an intervening write command.
6. The host device of claim 5 , wherein the controller is further configured to:
if another trim command was issued to the same LBA without an intervening write command, log a double trim occurrence.
7. The host device of claim 5 , wherein the controller is further configured to:
if another trim command was not issued to the same LBA without an intervening write command, log a never rewritten occurrence.
8. The host device of claim 1 , wherein the controller is further configured to:
determine available LBA space from host device data.
9. The host device of claim 8 , wherein the controller is further configured to:
adjust when the storage device executes trim commands based on the calculated elapse time and the available LBA space.
10. The host device of claim 8 , wherein the controller is further configured to:
adjust when the host device issues trim commands based on the calculated elapse time and the available LBA space.
11. The host device of claim 1 , wherein the controller is further configured to:
determine available physical blocks in the storage device.
12. The host device of claim 11 , wherein the controller is further configured to:
adjust when the storage device executes trim commands based on the calculated elapse time and the available LBA space.
13. The host device of claim 11 , wherein the controller is further configured to:
adjust when the host device issues trim commands based on the calculated elapse time and the available LBA space.
14. A method for assessing execution of trim commands, the method comprising:
performing the following in a device external to and in communication with a storage device:
obtaining a trace of trim and write commands sent to the storage device; and
for each trim command in the trace:
identifying if there is a subsequent write command to a same logical block address (LBA) as the trim command; and
if there is a subsequent write command to the same LBA, calculating an elapsed time between the trim and write commands.
15. The method of claim 14 further comprising:
generating a histogram based on the calculated elapse time.
16. The method of claim 14 further comprising:
adjusting when the storage device executes trim commands based on the calculated elapse time.
17. The method of claim 14 further comprising:
adjusting when the host device issues trim commands based on the calculated elapse time.
18. The method of claim 14 further comprising:
if there is not a subsequent write command to the same LBA, determining whether another trim command was issued to the same LBA without an intervening write command.
19. The method of claim 18 further comprising:
if another trim command was issued to the same LBA without an intervening write command, logging a double trim occurrence.
20. The method of claim 18 further comprising:
if another trim command was not issued to the same LBA without an intervening write command, logging a never rewritten occurrence.
21. The method of claim 14 further comprising:
determining available LBA space from host device data.
22. The method of claim 21 further comprising:
adjusting when the storage device executes trim commands based on the calculated elapse time and the available LBA space.
23. The method of claim 21 further comprising:
adjusting when the host device issues trim commands based on the calculated elapse time and the available LBA space.
24. The method of claim 14 further comprising:
determining available physical blocks in the storage device.
25. The method of claim 24 further comprising:
adjusting when the storage device executes trim commands based on the calculated elapse time and the available LBA space.
26. The method of claim 24 further comprising:
adjusting when the host device issues trim commands based on the calculated elapse time and the available LBA space.
27. The method of claim 26 , wherein the method is performed by the host device.
28. The method of claim 26 , wherein the method is performed by a device between the host and storage devices.
29. The method of claim 28 , wherein the device between the host and storage devices is a bus analyzer.
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KR1020147029465A KR101903834B1 (en) | 2012-05-31 | 2013-04-17 | Method and host device for assessing execution of trim commands |
CN201380023365.XA CN104272243B (en) | 2012-05-31 | 2013-04-17 | Method and host apparatus for the execution of assessing trimming instruction |
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Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140095775A1 (en) * | 2012-01-12 | 2014-04-03 | Fusion-io-Inc. | Systems and methods for cache endurance |
US20140359198A1 (en) * | 2013-05-28 | 2014-12-04 | Apple Inc. | Notification of storage device performance to host |
US20150012691A1 (en) * | 2013-07-05 | 2015-01-08 | Fujitsu Limited | Storage control apparatus, control program, and control method |
US20160155507A1 (en) * | 2012-12-21 | 2016-06-02 | Micron Technology, Inc. | Memory devices and their operation having trim registers associated with access operation commands |
US10089235B1 (en) * | 2017-07-28 | 2018-10-02 | Citrix Systems, Inc. | Dynamic trim processing with disk caching |
US10102117B2 (en) | 2012-01-12 | 2018-10-16 | Sandisk Technologies Llc | Systems and methods for cache and storage device coordination |
WO2019133300A1 (en) * | 2017-12-28 | 2019-07-04 | Micron Technology, Inc. | Techniques to update a trim parameter in non-volatile memory |
US10996986B2 (en) | 2018-12-13 | 2021-05-04 | Yandex Europe Ag | Method and system for scheduling i/o operations for execution |
US11003600B2 (en) | 2018-12-21 | 2021-05-11 | Yandex Europe Ag | Method and system for scheduling I/O operations for processing |
US11010090B2 (en) | 2018-12-29 | 2021-05-18 | Yandex Europe Ag | Method and distributed computer system for processing data |
US11048547B2 (en) | 2018-10-09 | 2021-06-29 | Yandex Europe Ag | Method and system for routing and executing transactions |
US11055160B2 (en) * | 2018-09-14 | 2021-07-06 | Yandex Europe Ag | Method of determining potential anomaly of memory device |
US11061720B2 (en) | 2018-09-14 | 2021-07-13 | Yandex Europe Ag | Processing system and method of detecting congestion in processing system |
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US11288254B2 (en) | 2018-10-15 | 2022-03-29 | Yandex Europe Ag | Method of and system for processing request in distributed database |
US11461363B2 (en) * | 2020-03-31 | 2022-10-04 | Sap Se | Memory allocation and deallocation mechanism to reduce fragmentation and enhance defragmentation performance |
US20220391129A1 (en) * | 2021-06-07 | 2022-12-08 | SK Hynix Inc. | Storage device, host device, and method of operating the same |
US11947799B1 (en) | 2019-10-11 | 2024-04-02 | Amzetta Technologies, Llc | Systems and methods for using the TRIM command with solid state devices |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104834484B (en) * | 2015-05-11 | 2018-10-23 | 上海新储集成电路有限公司 | Data processing system based on embedded programmable logic array and processing method |
KR102444694B1 (en) * | 2015-08-26 | 2022-09-20 | 에스케이하이닉스 주식회사 | Memory system and operation method for the same |
CN107797934B (en) * | 2016-09-05 | 2022-07-22 | 北京忆恒创源科技股份有限公司 | Method for processing de-allocation command and storage device |
US9927999B1 (en) | 2016-09-09 | 2018-03-27 | Western Digital Technologies, Inc. | Trim management in solid state drives |
KR102423278B1 (en) | 2017-11-28 | 2022-07-21 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
KR102493323B1 (en) | 2018-02-21 | 2023-01-31 | 에스케이하이닉스 주식회사 | Storage device and operating method thereof |
KR20230000690A (en) | 2021-06-25 | 2023-01-03 | 삼성전자주식회사 | Storage device performing adaptive write/read control and Operating method thereof |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100217927A1 (en) * | 2004-12-21 | 2010-08-26 | Samsung Electronics Co., Ltd. | Storage device and user device including the same |
US20100262795A1 (en) * | 2009-04-08 | 2010-10-14 | Steven Robert Hetzler | System, method, and computer program product for analyzing monitor data information from a plurality of memory devices having finite endurance and/or retention |
US20110145474A1 (en) * | 2009-12-14 | 2011-06-16 | Symwave, Inc. | Efficient Use Of Flash Memory In Flash Drives |
US20110208898A1 (en) * | 2010-02-23 | 2011-08-25 | Samsung Electronics Co., Ltd. | Storage device, computing system, and data management method |
US20120059978A1 (en) * | 2010-09-07 | 2012-03-08 | Daniel L Rosenband | Storage array controller for flash-based storage devices |
US20120110249A1 (en) * | 2010-10-29 | 2012-05-03 | Hyojin Jeong | Memory system, data storage device, user device and data management method thereof |
US20120110247A1 (en) * | 2010-10-27 | 2012-05-03 | International Business Machines Corporation | Management of cache memory in a flash cache architecture |
US20120117309A1 (en) * | 2010-05-07 | 2012-05-10 | Ocz Technology Group, Inc. | Nand flash-based solid state drive and method of operation |
US20120131263A1 (en) * | 2010-11-22 | 2012-05-24 | Phison Electronics Corp. | Memory storage device, memory controller thereof, and method for responding host command |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6813731B2 (en) | 2001-02-26 | 2004-11-02 | Emc Corporation | Methods and apparatus for accessing trace data |
US7644239B2 (en) * | 2004-05-03 | 2010-01-05 | Microsoft Corporation | Non-volatile memory cache performance improvement |
US7562202B2 (en) * | 2004-07-30 | 2009-07-14 | United Parcel Service Of America, Inc. | Systems, methods, computer readable medium and apparatus for memory management using NVRAM |
JP5364750B2 (en) * | 2011-03-25 | 2013-12-11 | 株式会社東芝 | Memory system and control method of nonvolatile memory device |
US8654472B2 (en) * | 2011-11-29 | 2014-02-18 | HGST Netherlands B.V. | Implementing enhanced fragmented stream handling in a shingled disk drive |
US8949512B2 (en) * | 2012-02-17 | 2015-02-03 | Apple Inc. | Trim token journaling |
-
2012
- 2012-06-15 US US13/524,913 patent/US8996768B2/en active Active
- 2012-06-15 US US13/524,924 patent/US20130326161A1/en not_active Abandoned
-
2013
- 2013-04-17 CN CN201380023365.XA patent/CN104272243B/en not_active Expired - Fee Related
- 2013-04-17 KR KR1020147029465A patent/KR101903834B1/en active IP Right Grant
- 2013-04-17 WO PCT/US2013/036903 patent/WO2013180842A1/en active Application Filing
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100217927A1 (en) * | 2004-12-21 | 2010-08-26 | Samsung Electronics Co., Ltd. | Storage device and user device including the same |
US20100262795A1 (en) * | 2009-04-08 | 2010-10-14 | Steven Robert Hetzler | System, method, and computer program product for analyzing monitor data information from a plurality of memory devices having finite endurance and/or retention |
US20110145474A1 (en) * | 2009-12-14 | 2011-06-16 | Symwave, Inc. | Efficient Use Of Flash Memory In Flash Drives |
US20110208898A1 (en) * | 2010-02-23 | 2011-08-25 | Samsung Electronics Co., Ltd. | Storage device, computing system, and data management method |
US20120117309A1 (en) * | 2010-05-07 | 2012-05-10 | Ocz Technology Group, Inc. | Nand flash-based solid state drive and method of operation |
US20120059978A1 (en) * | 2010-09-07 | 2012-03-08 | Daniel L Rosenband | Storage array controller for flash-based storage devices |
US20120110247A1 (en) * | 2010-10-27 | 2012-05-03 | International Business Machines Corporation | Management of cache memory in a flash cache architecture |
US20120110249A1 (en) * | 2010-10-29 | 2012-05-03 | Hyojin Jeong | Memory system, data storage device, user device and data management method thereof |
US20120131263A1 (en) * | 2010-11-22 | 2012-05-24 | Phison Electronics Corp. | Memory storage device, memory controller thereof, and method for responding host command |
Non-Patent Citations (2)
Title |
---|
Giryoung et al, "Performance analysis of SSD write using TRIM in NTFS and EXT4", Nov. 29 2011-Dec. 1 2011, Computer Sciences and Convergence Information Technology (ICCIT), 2011 6th International Conference, Pages 422-423 * |
Koltsidas et al, "Data Management Over Flash Memory", June 12-16, 2011,SIGMOD'11, Athens, Greece, Pages 1209-1212 * |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9767032B2 (en) * | 2012-01-12 | 2017-09-19 | Sandisk Technologies Llc | Systems and methods for cache endurance |
US20140095775A1 (en) * | 2012-01-12 | 2014-04-03 | Fusion-io-Inc. | Systems and methods for cache endurance |
US10102117B2 (en) | 2012-01-12 | 2018-10-16 | Sandisk Technologies Llc | Systems and methods for cache and storage device coordination |
US10468105B2 (en) | 2012-12-21 | 2019-11-05 | Micron Technology, Inc. | Apparatus having memory arrays and having trim registers associated with memory array access operation commands |
US20160155507A1 (en) * | 2012-12-21 | 2016-06-02 | Micron Technology, Inc. | Memory devices and their operation having trim registers associated with access operation commands |
US9997246B2 (en) * | 2012-12-21 | 2018-06-12 | Micron Technology, Inc. | Memory devices and their operation having trim registers associated with access operation commands |
US11031081B2 (en) | 2012-12-21 | 2021-06-08 | Micron Technology, Inc. | Apparatus having memory arrays and having trim registers associated with memory array access operation commands |
US20140359198A1 (en) * | 2013-05-28 | 2014-12-04 | Apple Inc. | Notification of storage device performance to host |
US20150012691A1 (en) * | 2013-07-05 | 2015-01-08 | Fujitsu Limited | Storage control apparatus, control program, and control method |
US10089235B1 (en) * | 2017-07-28 | 2018-10-02 | Citrix Systems, Inc. | Dynamic trim processing with disk caching |
US10635595B2 (en) | 2017-07-28 | 2020-04-28 | Citrix Systems, Inc. | Dynamic delete command partitioning with disk caching |
WO2019133300A1 (en) * | 2017-12-28 | 2019-07-04 | Micron Technology, Inc. | Techniques to update a trim parameter in non-volatile memory |
US10649656B2 (en) | 2017-12-28 | 2020-05-12 | Micron Technology, Inc. | Techniques to update a trim parameter in non-volatile memory |
US11928330B2 (en) | 2017-12-28 | 2024-03-12 | Micron Technology, Inc. | Techniques to update a trim parameter in non-volatile memory |
US11194472B2 (en) | 2017-12-28 | 2021-12-07 | Micron Technology, Inc. | Techniques to update a trim parameter in nonvolatile memory |
US11061720B2 (en) | 2018-09-14 | 2021-07-13 | Yandex Europe Ag | Processing system and method of detecting congestion in processing system |
US11055160B2 (en) * | 2018-09-14 | 2021-07-06 | Yandex Europe Ag | Method of determining potential anomaly of memory device |
US11449376B2 (en) | 2018-09-14 | 2022-09-20 | Yandex Europe Ag | Method of determining potential anomaly of memory device |
US11048547B2 (en) | 2018-10-09 | 2021-06-29 | Yandex Europe Ag | Method and system for routing and executing transactions |
US11288254B2 (en) | 2018-10-15 | 2022-03-29 | Yandex Europe Ag | Method of and system for processing request in distributed database |
US10996986B2 (en) | 2018-12-13 | 2021-05-04 | Yandex Europe Ag | Method and system for scheduling i/o operations for execution |
US11003600B2 (en) | 2018-12-21 | 2021-05-11 | Yandex Europe Ag | Method and system for scheduling I/O operations for processing |
US11010090B2 (en) | 2018-12-29 | 2021-05-18 | Yandex Europe Ag | Method and distributed computer system for processing data |
US11184745B2 (en) | 2019-02-06 | 2021-11-23 | Yandex Europe Ag | Actor system and method for transmitting a message from a first actor to a second actor |
US11947799B1 (en) | 2019-10-11 | 2024-04-02 | Amzetta Technologies, Llc | Systems and methods for using the TRIM command with solid state devices |
US11461363B2 (en) * | 2020-03-31 | 2022-10-04 | Sap Se | Memory allocation and deallocation mechanism to reduce fragmentation and enhance defragmentation performance |
US20220391129A1 (en) * | 2021-06-07 | 2022-12-08 | SK Hynix Inc. | Storage device, host device, and method of operating the same |
Also Published As
Publication number | Publication date |
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KR101903834B1 (en) | 2018-10-02 |
CN104272243A (en) | 2015-01-07 |
KR20150021495A (en) | 2015-03-02 |
US8996768B2 (en) | 2015-03-31 |
US20130326096A1 (en) | 2013-12-05 |
WO2013180842A1 (en) | 2013-12-05 |
CN104272243B (en) | 2017-08-08 |
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