US20140015031A1

US20140015031A1 - Apparatus and Method for Memory Device

Info

Publication number: US20140015031A1
Application number: US13/547,741
Authority: US
Inventors: Ping-Pang Hsieh; Chih-Ming Lee; Yu-Jen Chen; Shiu-Ko Jangjian
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2012-07-12
Filing date: 2012-07-12
Publication date: 2014-01-16
Also published as: US20150221752A1; US10164073B2

Abstract

An apparatus comprises a gate stack formed over a substrate, wherein the gate stack comprises a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate and a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure. The apparatus further comprises a first drain/source region and a first recess formed between a top surface of the first drain/source region and the second dielectric layer.

Description

BACKGROUND

Modern electronic devices such as a notebook computer comprise a variety of memories to store information. Memory circuits include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them. Non-volatile memories include a variety of sub-categories, such as read-only-memory (ROM), electrically erasable programmable read-only memory (EEPROM) and flash memory.
Flash memory is a non-volatile device that can be electrically erased and reprogrammed. A typical flash memory comprises a memory array having a large number of flash memory cells arranged in rows, columns, and blocks. One of the most commonly known flash memories is the one-transistor flash memory. The memory cell of the one-transistor flash memory is fabricated as a field-effect transistor having two gates, namely a control gate and a floating gate. The floating gate is capable of holding charges and is separated from source and drain regions.
Each of the memory cells can be electrically charged by injecting hot electrons across an oxide layer (tunneling layer) onto the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the substrate through the tunneling layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of charges in the floating gate.
As technologies evolve, semiconductor process nodes have been scaled down for high density flash memory integrated circuits. As a result, the form factor of flash memory devices has been improved from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As semiconductor devices are scaled down, new techniques are needed to maintain the electronic components' performance from one generation to the next. For example, poor or reduced cycling and data retention capabilities are two major concerns in the tunnel oxide when the tunnel oxide traps more electrons than desired during program erase operations. Such undesirable trapping of electrons makes the overall flash memory device less efficient.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a cross sectional view of a memory device in accordance with an embodiment;

FIG. 2 illustrates a cross sectional view of a memory device after a gate stack is formed over a substrate through a patterning process in accordance with an embodiment;

FIG. 3 illustrates a cross sectional view of a memory device after an oxygen flush process is applied to the surface of the memory device shown in FIG. 2 in accordance with an embodiment;

FIG. 4 illustrates a cross sectional view of a memory device after an ion implantation process is applied to the memory device shown in FIG. 3 in accordance with an embodiment;

FIG. 5 illustrates a cross sectional view of a memory device after a pre-clean process is applied to the memory device shown in FIG. 4 in accordance with an embodiment; and

FIG. 6 illustrates a cross sectional view of a memory device after a gate oxidation process is applied to the surface of the gate stack of the memory device shown in FIG. 5 in accordance with an embodiment.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.
The present disclosure will be described with respect to embodiments in a specific context, a flash memory device having two recesses between a gate stack and drain/source regions. The embodiments of the disclosure may also be applied, however, to a variety of memory semiconductor devices. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.
FIG. 1 illustrates a cross sectional view of a memory device in accordance with an embodiment. As shown in FIG. 1, a first active region 104 and a second active region 106 are formed in a substrate 102. In addition, the first active region 104 and the second active region 106 are formed on opposite sides of a gate structure including a tunneling layer 112, a floating gate 114, an inter-poly dielectric layer 116 and a control gate 118. In accordance with an embodiment, the first active region 104 and the second active region 106 may be a drain region and a source region respectively.
As shown in FIG. 1, the tunneling layer 112 is formed over the substrate 102. The floating gate 114 is formed over the tunneling layer 112. The inter-poly dielectric layer 116 is stacked on top of the floating gate 114 and the control gate 118 is stacked on top of the inter-poly dielectric layer 116. The portions protruding over the substrate 102 form a gate stack of the memory device 100. Moreover, there may be a gate oxide layer 122 formed on the surface of the gate stack. FIG. 1 shows there may be a recess between the top surface of the active regions (e.g., the first active region 104) and the bottom of the tunneling layer 112. The height of the recess is defined as d1. In accordance with an embodiment, d1 is in a range from about 5 Angstroms to about 200 Angstroms.
The substrate 102 may be formed of suitable semiconductor materials such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, with other crystal orientations, may also be used. Additionally, the substrate 102 may comprise a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate 102 may be doped with a p-type dopant, such as boron, aluminum, gallium, or the like, although the substrate may alternatively be doped with an n-type dopant, as is known in the art.
In accordance with an embodiment in which the substrate 102 is a p-type substrate, the drain/source region 104 and the drain/source 106 may be formed by implanting appropriate n-type dopants such as phosphorous, arsenic, antimony, or the like. The drain/ source regions 104 and 106 may be implanted using the tunneling layer 112, the floating gate 114, the blocking layer 116, the control gate 118 as masks to form the source/ drain regions 104 and 106. The detailed fabrication process of the drain and source regions will be described below with respect to FIG. 4.
In accordance with an embodiment, the tunneling layer 112 may comprise oxide materials such as silicon oxide. The silicon oxide layer may be implemented using a suitable process such as furnace, rapid thermal oxide (RTO), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), combinations of these or the like. However, any suitable deposition process may alternatively be utilized. In accordance with another embodiment, the tunneling layer 112 may comprise a high-k dielectric material such as AlLaO₃, HfAlO₃, HfO₂, Ta₂O₅, Al₂O₃, ZrO₂, TiO₂, SrTiO₃, and any combinations thereof.
The floating gate layer 114 is commonly known as a storage layer. According to the operation principles of flash memory device, the floating gate layer 114 is employed to store gate charge so that the logic statue of the memory device can be retained even if electrical power is terminated. In accordance with an embodiment, the floating gate layer 114 may be formed of heavily doped poly-silicon. In accordance with another embodiment, the floating layer 114 may be formed of silicon nitride. In accordance with yet another embodiment, floating gate layer 114 may comprises conductive materials such as metal silicides, metal nitrides and the like. In yet other embodiments, floating gate layer 114 includes nano crystal with nano crystal islands isolated by dielectric materials.
The inter-poly dielectric layer 116 is commonly known as a blocking layer. Throughout the description, the inter-poly dielectric layer 116 may be alternatively referred to as a blocking layer 116. In accordance with an embodiment, the inter-poly dielectric layer 116 may be formed of SiO₂—Si₃N₄—SiO₂(ONO). In accordance with another embodiment, the inter-poly dielectric layer 116 may be formed of high-k dielectric materials such as Al₂O₃. It should be noted while FIG. 1 illustrates the blocking layer 116 is a single layer, the blocking layer 116 may also be a composite layer including more than one layer, each layer comprising one or more of the above-listed materials.
The control gate 118 is formed over the blocking layer 116. The control gate 118 may be formed of conductive materials such as polysilicon doped with n-type impurities, polysilicon doped with p-type impurities, metals, metal silicides, metal nitrides, and combinations thereof.
One advantageous feature of having the blocking layer 116 and the tunneling layer 112 is that these two dielectric layers prevent the gate charge of the floating gate layer 114 from leaking out to the substrate or the control gate 118. As a result, the date retention of the flash memory may be improved.
FIGS. 2-6 illustrate intermediate steps of fabricating a flashing memory having two recesses in accordance with an embodiment. FIG. 2 illustrates a cross sectional view of a memory device after a gate stack is formed over a substrate through a patterning process in accordance with an embodiment. The tunneling layer 112, the floating gate 114, the blocking layer 116 and the control gate 118 may be patterned using a photolithographic masking and etching process. For example, a photosensitive material may be placed over the gate stack, exposed to an energy source such as light, and developed. Once the photoresist has been formed, one or more etching steps may be utilized to remove those regions of the tunneling layer 112, the floating gate layer 114, the blocking layer 116 and the control gate 118 that were exposed by the photoresist.
FIG. 3 illustrates a cross sectional view of a memory device after an oxygen flush process is applied to the surface of the memory device shown in FIG. 2 in accordance with an embodiment. In order to form a uniform oxide layer on top of the memory device, an oxygen flush process is applied to the top surface of the memory device. In accordance with an embodiment, the memory device may be placed in a dry etch chamber. The oxygen flush may be implemented by using suitable techniques such as oxygen plasma. An oxide layer 302 may grow on top of the surface of the gate stack the memory device. Likewise, oxide layers 304 and 306 may grow on top of the surface of the substrate 102. The growth rate of the oxide layer is proportional to time and the concentration of O₂plasma. However, the growth rate may saturate when the thickness of the oxide layer is in a range from about 20 Angstroms to about 300 Angstroms.
The saturation of the oxide layer helps to form a uniform surface layer on top of the memory device. One advantageous feature of having such a uniform oxide surface layer is the memory device may have a uniform implantation profile in the subsequent ion implantation process. The uniform implantation profiles helps to improve the threshold voltage of the memory device. The detailed process of the ion implantation process will be described below with respect to FIG. 4.
FIG. 4 illustrates a cross sectional view of a memory device after an ion implantation process is applied to the memory device shown in FIG. 3 in accordance with an embodiment. A first drain/source region 104 and a second drain/source region 106 may be formed in the substrate 102 on opposite sides of the gate stack. In according with an embodiment in which the substrate 102 is an n-type substrate, the drain/ source regions 104 and 106 may be formed by implanting appropriate p-type dopants such as boron, gallium, indium, or the like. Alternatively, in accordance with an embodiment in which the substrate 102 is a p-type substrate, the drain/ source regions 104 and 106 may be formed by implanting appropriate n-type dopants such as phosphorous, arsenic, or the like. These drain/ source regions 104 and 106 may be implanted using the gate stack shown in FIG. 4 as masks. A uniform implantation profile of the drain/ source regions 104 and 106 helps to improve the performance of the flash memory device.
FIG. 5 illustrates a cross sectional view of a memory device after a pre-clean process is applied to the memory device shown in FIG. 4 in accordance with an embodiment. During the formation of the gate stack through an etching process, many residues such as polymer may stay on the surface of the substrate. Such residues may have a negative impact on the performance characteristics of the flash memory. In order to improve the performance such as leakage current of the memory device, the surface of the gate stack must be cleaned before forming a gate oxide layer. A gate pre-clean process may be implemented using suitable cleaning processes such as dry cleaning or wet cleaning. In accordance with an embodiment, a wet cleaning process may comprise applying an HF solution first and performing SPM (SPM is a mixture of H₂SO₄and H₂O₂) and APM (APM is a mixture of NH₄OH, H₂O₂and H₂O) solutions subsequently.
In comparison with the cross sectional view of FIG. 4, the oxide layers on the top surface of the substrate and the gate stack have been removed after the pre-clean process is applied to the memory device. As shown in FIG. 5, there are no undercuts at the blocking layer 116 because the oxide layer (not shown but illustrated in FIG. 4) helps to prevent the ONO of the blocking layer 116 from being damaged during the pre-clean process. As a result, the blocking layer 116 is free of lateral undercuts. Such an undercut free blocking layer helps to improve the data retention of a flash memory device. In addition, by reducing the undercut at the ONO layer, a high coupling ratio flash memory device can be achieved.
FIG. 6 illustrates a cross sectional view of a memory device after a gate oxidation process is applied to the surface of the gate stack of the memory device shown in FIG. 5 in accordance with an embodiment. The gate oxidation process may be implemented by using suitable techniques such as a thermal process, a furnace process or the like. In accordance with an embodiment, the thickness of the gate oxide layer is a range from about 15 Angstroms to about 300 Angstroms. It should be noted that FIG. 6 is not drawn to scale. The gate oxide layer is very thin.
Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

What is claimed is:

1. An apparatus comprising:

a gate stack formed over a substrate, wherein the gate stack comprises:

a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate; and

a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure;

a first drain/source region; and

a first recess formed between a top surface of the first drain/source region and the second dielectric layer.

2. The apparatus of claim 1, further comprising:

a second drain/source region formed on an opposite side of the gate stack from the first drain/source region; and

a second recess formed between a top surface of the second drain/source region and the second dielectric layer.

3. The apparatus of claim 1, wherein:

the first dielectric layer is a tunneling layer of a flash memory device.

4. The apparatus of claim 1, wherein:

the second dielectric layer is a blocking layer of a flash memory device.

5. The apparatus of claim 1, wherein:

the first recess is of a height in a range from 5 Angstroms to 200 Angstroms.

6. The apparatus of claim 1, wherein:

the first gate structure comprises a floating gate of a flash memory device.

7. The apparatus of claim 1, wherein:

the second gate structure comprises a control gate of a flash memory device.

8. A device comprising:

a tunneling layer formed over a substrate;

a floating gate formed over the tunneling layer;

a blocking layer is formed over the floating gate, wherein the block layer is free of lateral undercuts;

a control gate formed over the blocking layer;

a first step between a top surface of a first drain/source region and the tunneling layer; and

a second step between a top surface of a second drain/source region and the tunneling layer, wherein the second drain/source region is on an opposite side of the tunneling layer from the first drain/source region.

9. The device of claim 8, wherein:

the blocking layer comprises SiO₂—Si₃N₄—SiO₂(ONO).

10. The device of claim 8, further comprising:

a gate stack formed by the tunneling layer, the floating gate, the blocking layer and the control gate, wherein the gate stack is covered by an oxide layer.

11. The device of claim 8, wherein:

the first step is of a height in a range from 5 Angstroms to 200 Angstroms.

12. The device of claim 8, wherein:

the second step is of a height in a range from 5 Angstroms to 200 Angstroms.

13. The device of claim 8, wherein:

the floating gate comprises doped polysilicon.

14. The device of claim 8, wherein:

the control gate comprises doped polysilicon.

15. A method comprising:

forming a gate stack on a substrate;

applying an oxygen flush process to the gate stack and the substrate to form a first oxide layer on the substrate;

applying an ion implantation process to the gate stack and the substrate, wherein through the ion implantation process, a first drain/source region and a second drain/source region are formed on opposite sides of the gate stack;

applying a pre-cleaning process to the gate stack and the substrate, wherein the first oxide layer is removed after the pre-cleaning process; and

growing an oxide layer on the gate stack.

16. The method of claim 15, further comprising:

implementing the oxygen flush process by using oxygen plasma in a dry etch chamber.

17. The method of claim 15, further comprising:

depositing a tunneling layer on the substrate;

depositing a floating gate on the tunneling layer;

depositing a blocking layer on the floating gate; and

depositing a control gate on the blocking layer.

18. The method of claim 17, further comprising:

forming a SiO₂—Si₃N₄—SiO₂layer between the floating gate and the control gate, wherein the SiO₂—Si₃N₄—SiO₂layer is free of lateral undercuts.

19. The method of claim 15, further comprising:

removing the first oxide layer; and

forming a first recess between a top surface of the first drain/source region and a bottom of the gate stack.

20. The method of claim 15, further comprising:

removing the first oxide layer; and

forming a second recess between a top surface of the second drain/source region and a bottom of the gate stack.