US20140021603A1 - Using an interconnect bump to traverse through a passivation layer of a semiconductor die - Google Patents
Using an interconnect bump to traverse through a passivation layer of a semiconductor die Download PDFInfo
- Publication number
- US20140021603A1 US20140021603A1 US13/948,516 US201313948516A US2014021603A1 US 20140021603 A1 US20140021603 A1 US 20140021603A1 US 201313948516 A US201313948516 A US 201313948516A US 2014021603 A1 US2014021603 A1 US 2014021603A1
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- Prior art keywords
- interconnect
- semiconductor die
- bump
- semiconductor
- layer
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- H01L2924/13051—Heterojunction bipolar transistor [HBT]
Definitions
- Embodiments of the present disclosure relate to semiconductor dies and methods for electrically and thermally connecting the semiconductor dies to external circuitry.
- a semiconductor die which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed.
- the first passivation layer is over the first semiconductor device, which includes a first group of device fingers.
- the first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.
- the first interconnect bump is configured to conduct heat away from the first semiconductor device. Further, in one embodiment of the semiconductor die, the first interconnect bump is further configured to provide an external electrical connection to the first semiconductor device.
- the first interconnect bump may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of the first group of device fingers through the first opening in the first passivation layer, the first interconnect bump may provide improved thermal and electrical connectivity over existing designs.
- FIG. 1 shows a semiconductor die according to one embodiment of the semiconductor die.
- FIG. 2 shows the semiconductor die according to an alternate embodiment of the semiconductor die.
- FIG. 3 shows the semiconductor die according to an additional embodiment of the semiconductor die.
- FIG. 4 shows the semiconductor die according to another embodiment of the semiconductor die.
- FIG. 5 shows the semiconductor die according to a further embodiment of the semiconductor die.
- FIG. 6 shows a cross-section of a portion of the semiconductor die illustrated in FIG. 3 according to one embodiment of the cross-section.
- FIG. 7 shows the cross-section of the portion of the semiconductor die illustrated in FIG. 3 according to an alternate embodiment of the cross-section.
- FIG. 8 shows the cross-section of the portion of the semiconductor die illustrated in FIG. 3 according to an additional embodiment of the cross-section.
- FIG. 9 shows the cross-section of the portion of the semiconductor die illustrated in FIG. 3 according to another embodiment of the cross-section.
- FIG. 10 shows the semiconductor die attached to an external device according to one embodiment of the semiconductor die.
- FIG. 11 illustrates a process for forming the semiconductor die illustrated in FIG. 6 according to one embodiment of the semiconductor die.
- FIG. 12 illustrates a process for forming the semiconductor die illustrated in FIG. 9 according to an alternate embodiment of the semiconductor die.
- thermal conductivity of the coupling is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot.
- electrically connected is defined herein and for any claims that follow to require a coupling wherein the electrical resistivity is less than or equal to about 25 ⁇ 10 ⁇ 8 ohm-meters. Any intervening conductive elements would have an electrical resistivity of less than or equal to about 25 ⁇ 10 ⁇ 8 ohm-meters. Any intervening conductive elements would have a thermal conductivity of greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot.
- FIG. 1 shows a 3D view of a semiconductor die 10 according to one embodiment of the semiconductor die 10 .
- the semiconductor die 10 includes a first passivation layer 12 , a first interconnect bump 14 , and a second interconnect bump 16 .
- the first passivation layer 12 is the uppermost layer of the semiconductor die 10 .
- the first interconnect bump 14 protrudes through the first passivation layer 12 and the second interconnect bump 16 protrudes through the first passivation layer 12 .
- Alternate embodiments of the semiconductor die 10 may include any number of interconnect bumps protruding through the first passivation layer 12 .
- the first interconnect bump 14 is a flip chip bump. In one embodiment of the second interconnect bump 16 , the second interconnect bump 16 is a flip chip bump. In one embodiment of the first interconnect bump 14 , the first interconnect bump 14 includes Copper. In an alternate embodiment of the first interconnect bump 14 , the first interconnect bump 14 consists of Copper. In another embodiment of the first interconnect bump 14 , the first interconnect bump 14 includes any metal. In one embodiment of the second interconnect bump 16 , the second interconnect bump 16 includes Copper. In an alternate embodiment of the second interconnect bump 16 , the second interconnect bump 16 consists of Copper. In another embodiment of the second interconnect bump 16 , the second interconnect bump 16 includes any metal.
- a thermal conductivity of the first interconnect bump 14 is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. In one embodiment of the first interconnect bump 14 , an electrical resistivity of the first interconnect bump 14 is less than or equal to about 25 ⁇ 10 ⁇ 8 ohm-meters. In one embodiment of the second interconnect bump 16 , a thermal conductivity of the second interconnect bump 16 is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. In one embodiment of the second interconnect bump 16 , an electrical resistivity of the second interconnect bump 16 is less than or equal to about 25 ⁇ 10 ⁇ 8 ohm-meters.
- a height of the first interconnect bump 14 is between about 40 micrometers and about 100 micrometers. In one embodiment of the second interconnect bump 16 , a height of the second interconnect bump 16 is between about 40 micrometers and about 100 micrometers. In one embodiment of the first interconnect bump 14 , a width of the first interconnect bump 14 is between about 70 micrometers and about 90 micrometers and a length of the first interconnect bump 14 is between about 80 micrometers and about 500 micrometers. In one embodiment of the second interconnect bump 16 , a width of the second interconnect bump 16 is between about 70 micrometers and about 90 micrometers and a length of the second interconnect bump 16 is between about 80 micrometers and about 500 micrometers.
- the vertical corners of the first interconnect bump 14 are rounded. In one embodiment of the first interconnect bump 14 , the horizontal corners of the first interconnect bump 14 are rounded. In one embodiment of the second interconnect bump 16 , the vertical corners of the second interconnect bump 16 are rounded. In one embodiment of the second interconnect bump 16 , the horizontal corners of the second interconnect bump 16 are rounded. In an alternate embodiment of the first interconnect bump 14 , the first interconnect bump 14 is of any shape. In an alternate embodiment of the second interconnect bump 16 , the second interconnect bump 16 is of any shape.
- FIG. 2 shows a top view of the semiconductor die 10 according to an alternate embodiment of the semiconductor die 10 .
- the semiconductor die 10 illustrated in FIG. 2 is similar to the semiconductor die 10 illustrated in FIG. 1 ,except in the semiconductor die 10 illustrated in FIG. 2 , the first interconnect bump 14 and the second interconnect bump 16 are not shown for clarity.
- the first passivation layer 12 has a first opening 18 and a second opening 20 .
- the first interconnect bump 14 ( FIG. 1 ) protrudes through the first opening 18 in the first passivation layer 12 and the second interconnect bump 16 ( FIG. 1 ) protrudes through the second opening 20 in the first passivation layer 12 .
- the semiconductor die 10 further includes a first semiconductor device 22 and a second semiconductor device 24 .
- the first semiconductor device 22 and the second semiconductor device 24 can be seen through the first opening 18 and the second opening 20 , respectively.
- the first passivation layer 12 is over the first semiconductor device 22 and the first passivation layer 12 is over the second semiconductor device 24 .
- the first opening 18 is directly over the first semiconductor device 22 and the second opening 20 is directly over the second semiconductor device 24 .
- the first semiconductor device 22 has a first group 26 of device fingers and the second semiconductor device 24 has a second group 28 of device fingers.
- the first interconnect bump 14 ( FIG. 1 ) is thermally and electrically connected to each of the first group 26 of device fingers.
- the second interconnect bump 16 ( FIG. 1 ) is thermally and electrically connected to each of the second group 28 of device fingers.
- the first interconnect bump 14 ( FIG. 1 ) is configured to conduct heat away from the first semiconductor device 22 . Further, in one embodiment of the semiconductor die 10 , the first interconnect bump 14 ( FIG. 1 ) is further configured to provide an external electrical connection to the first semiconductor device 22 . Due to its relative size and form factor, the first interconnect bump 14 ( FIG. 1 ) may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of the first group 26 of device fingers through the first opening 18 in the first passivation layer 12 , the first interconnect bump 14 ( FIG. 1 ) may provide improved thermal and electrical connectivity over existing designs.
- the second interconnect bump 16 ( FIG. 1 ) is configured to conduct heat away from the second semiconductor device 24 . Further, in one embodiment of the semiconductor die 10 , the second interconnect bump 16 ( FIG. 1 ) is further configured to provide an external electrical connection to the second semiconductor device 24 . Due to its relative size and form factor, the second interconnect bump 16 ( FIG. 1 ) may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of the second group 28 of device fingers through the second opening 20 in the first passivation layer 12 , the second interconnect bump 16 ( FIG. 1 ) may provide improved thermal and electrical connectivity over existing designs.
- the first passivation layer 12 includes BenzoCycloButene. In an alternate embodiment of the first passivation layer 12 , the first passivation layer 12 includes Polyimide. In another embodiment of the first passivation layer 12 , the first passivation layer 12 includes any passivation material.
- the first semiconductor device 22 has a first group 30 of sub-cells, such that each of the first group 30 of sub-cells has a corresponding portion of the first group 26 of device fingers.
- the first group 26 of device fingers has 12 device fingers and each of the first group 30 of sub-cells has 4 device fingers.
- the second semiconductor device 24 has a second group 32 of sub-cells, such that each of the second group 32 of sub-cells has a corresponding portion of the second group 28 of device fingers.
- the second group 28 of device fingers has 12 device fingers and each of the second group 32 of sub-cells has 4 device fingers.
- Alternate embodiments of the semiconductor die 10 may include any number of semiconductor devices. Each semiconductor device may include any number of device fingers. Further, each semiconductor device may include any number of sub-cells. Each sub-cell may include any number of device fingers. Further, the semiconductor die 10 may include any number of interconnect bumps and the first passivation layer 12 may include any number of openings as long as each interconnect bump protrudes through an opening in the first passivation layer 12 .
- FIG. 3 shows the semiconductor die 10 according to an additional embodiment of the semiconductor die 10 .
- the semiconductor die 10 illustrated in FIG. 3 is similar to the semiconductor die 10 illustrated in FIG. 2 , except in the semiconductor die 10 illustrated in FIG. 3 , the semiconductor die 10 further includes a second passivation layer 34 .
- the first passivation layer 12 is over the second passivation layer 34 .
- the second passivation layer 34 is visible through the first opening 18 and through the second opening 20 .
- the second passivation layer 34 is over the first semiconductor device 22 ( FIG. 2 ) and over the second semiconductor device 24 ( FIG. 2 ).
- the second passivation layer 34 has a first group 36 of openings and a second group 38 of openings.
- the second passivation layer 34 includes Silicon Dioxide. In one embodiment of the second passivation layer 34 , the second passivation layer 34 includes Silicon Nitride. In another embodiment of the second passivation layer 34 , the second passivation layer 34 includes any passivation material. In one embodiment of the second passivation layer 34 , a thickness of the second passivation layer 34 adjacent to each of the first group 36 of openings is between about 150 nanometers and about 5500 nanometers. In one embodiment of the second passivation layer 34 , a thickness of the second passivation layer 34 adjacent to each of the second group 38 of openings is between about 150 nanometers and about 5500 nanometers.
- each of the first group 36 of openings is directly over a corresponding one of the first group 30 ( FIG. 2 ) of sub-cells.
- the first interconnect bump 14 ( FIG. 1 ) further protrudes through each of the first group 36 of openings.
- each of the second group 38 of openings is directly over a corresponding one of the second group 32 ( FIG. 2 ) of sub-cells.
- the second interconnect bump 16 ( FIG. 1 ) further protrudes through each of the second group 38 of openings.
- a location of a cross-section 40 of a portion of the semiconductor die 10 is illustrated in FIG. 3 .
- FIG. 4 shows the semiconductor die 10 according to another embodiment of the semiconductor die 10 .
- the semiconductor die 10 illustrated in FIG. 4 is similar to the semiconductor die 10 illustrated in FIG. 1 , except in the semiconductor die 10 illustrated in FIG. 4 , the second interconnect bump 16 ( FIG. 1 ) is omitted.
- FIG. 5 shows the semiconductor die 10 according to a further embodiment of the semiconductor die 10 .
- the semiconductor die 10 illustrated in FIG. 5 is similar to the semiconductor die 10 illustrated in FIG. 2 , except in the semiconductor die 10 illustrated in FIG. 5 , the second opening 20 is omitted and the first opening 18 is elongated, such that the first opening 18 is over both the first semiconductor device 22 and the second semiconductor device 24 .
- the first interconnect bump 14 ( FIG. 4 ) is thermally and electrically connected to both the first group 26 of device fingers and the second group 28 of device fingers.
- FIG. 6 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to one embodiment of the cross-section 40 .
- the cross-section 40 includes one of the first group 30 of sub-cells ( FIG. 2 ) of the first semiconductor device 22 ( FIG. 2 ); therefore, the cross-section 40 includes a portion of the first group 26 of device fingers.
- the cross-section 40 further includes a portion of the first passivation layer 12 , a portion of the second passivation layer 34 , a first semiconductor material 42 , a base mesa 44 , first semiconductor material contacts 46 , base contacts 48 , a second semiconductor material 50 , a dielectric material 52 , and a first interconnect layer 54 . As such, four of the first group 26 of device fingers are illustrated.
- the first semiconductor material contacts 46 are on the first semiconductor material 42 .
- the base mesa 44 is on the first semiconductor material 42 .
- the base contacts 48 are on the base mesa 44 .
- Each of the portion of the first group 26 of device fingers is on the base mesa 44 .
- each of the first group 26 of device fingers includes a corresponding portion of the second semiconductor material 50 and a corresponding portion of the first interconnect layer 54 , such that each corresponding portion of the first interconnect layer 54 is on the corresponding portion of the second semiconductor material 50 .
- the dielectric material 52 insulates the base contacts 48 from the portion of the first group 26 of device fingers.
- the first interconnect layer 54 provides a connection between the portion of the first group 26 of device fingers of the one of the first group 30 of sub-cells ( FIG. 2 ). In an alternate embodiment of the cross-section 40 (not shown), the first interconnect layer 54 does not provide the connection between the portion of the first group 26 of device fingers of the one of the first group 30 of sub-cells ( FIG. 2 ).
- the second passivation layer 34 is on a portion of the first interconnect layer 54 and is on a portion of the dielectric material 52 .
- the first passivation layer 12 is on a portion of the second passivation layer 34 . Therefore, only a portion of the first interconnect layer 54 , a portion of the second passivation layer 34 , and the first passivation layer 12 are exposed. A portion of the first opening 18 and one of the first group 36 of openings are identified for clarity.
- the first interconnect layer 54 includes gold. In one embodiment of the first interconnect layer 54 , the first interconnect layer 54 includes any metal. In one embodiment of the first semiconductor material 42 , the first semiconductor material 42 includes Gallium Arsenide. In one embodiment of the first semiconductor material 42 , the first semiconductor material 42 includes Gallium Nitride. In one embodiment of the first semiconductor material 42 , the first semiconductor material 42 includes Silicon. In one embodiment of the first semiconductor material 42 , the first semiconductor material 42 includes N-type Gallium Arsenide. In one embodiment of the first semiconductor material 42 , the first semiconductor material 42 includes P-type Gallium Arsenide.
- the second semiconductor material 50 includes Gallium Arsenide. In one embodiment of the second semiconductor material 50 , the second semiconductor material 50 includes Gallium Nitride. In one embodiment of the second semiconductor material 50 , the second semiconductor material 50 includes Silicon. In one embodiment of the second semiconductor material 50 , the second semiconductor material 50 includes N-type Gallium Arsenide. In one embodiment of the second semiconductor material 50 , the second semiconductor material 50 includes P-type Gallium Arsenide. In one embodiment of the base mesa 44 , the base mesa 44 includes Gallium Arsenide. In one embodiment of the base mesa 44 , the base mesa 44 includes Gallium Nitride. In one embodiment of the base mesa 44 , the base mesa 44 includes Silicon. In one embodiment of the base mesa 44 , the base mesa 44 includes P-type Gallium Arsenide. In one embodiment of the base mesa 44 , the base mesa 44 includes N-type Gallium Arsenide.
- the first semiconductor device 22 is a transistor.
- an emitter of the transistor includes the first group 26 of device fingers.
- a collector of the transistor includes the first group 26 of device fingers.
- the first semiconductor device 22 ( FIG. 2 ) is a heterojunction bipolar transistor. In one embodiment of the first semiconductor device 22
- the first semiconductor device 22 ( FIG. 2 ) is a bipolar junction transistor.
- FIG. 7 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to an alternate embodiment of the cross-section 40 .
- the cross-section 40 illustrated in FIG. 7 is similar to the cross-section 40 illustrated in FIG. 6 , except in the cross-section 40 illustrated in FIG. 7 , the first interconnect bump 14 is on the first passivation layer 12 , the second passivation layer 34 , and the first interconnect layer 54 . Further, the first interconnect bump 14 protrudes through the first passivation layer 12 and through the second passivation layer 34 . Also, the first interconnect bump 14 is thermally and electrically connected to the first semiconductor device 22 ( FIG. 2 ) via the first interconnect layer 54 .
- FIG. 8 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to an additional embodiment of the cross-section 40 .
- the cross-section 40 illustrated in FIG. 8 is similar to the cross-section 40 illustrated in FIG. 7 , except in the cross-section 40 illustrated in FIG. 8 , the semiconductor die 10 ( FIG. 3 ) further includes a first under bump metallization layer 56 on the first interconnect layer 54 , such that the first interconnect bump 14 is on the first under bump metallization layer 56 .
- the first interconnect bump 14 is over the first interconnect layer 54 .
- the first under bump metallization layer 56 includes Titanium.
- the first under bump metallization layer 56 includes any metal. In one embodiment of the first under bump metallization layer 56 , a thickness of the first under bump metallization layer 56 is between about 500 Angstroms and about 1500 Angstroms. In one embodiment of the first under bump metallization layer 56 , the first under bump metallization layer 56 is a seed layer for the first interconnect bump 14 . In one embodiment of the first under bump metallization layer 56 , the first under bump metallization layer 56 promotes adhesion to the first interconnect layer 54 . In one embodiment of the first under bump metallization layer 56 , the first under bump metallization layer 56 substantially prevents electro-migration of the first interconnect layer 54 .
- FIG. 9 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to another embodiment of the cross-section 40 .
- the cross-section 40 illustrated in FIG. 9 is similar to the cross-section 40 illustrated in FIG. 8 , except in the cross-section 40 illustrated in FIG. 9 , the semiconductor die 10 ( FIG. 3 ) further includes a second under bump metallization layer 58 on the first under bump metallization layer 56 , such that the first interconnect bump 14 is on the second under bump metallization layer 58 .
- the semiconductor die 10 ( FIG. 3 ) includes at least one under bump metallization layer 56 , 58 on the first interconnect layer 54 , such that the first interconnect bump 14 is on the at least one under bump metallization layer 56 , 58 .
- the second under bump metallization layer 58 includes Copper. In one embodiment of the second under bump metallization layer 58 , the second under bump metallization layer 58 includes Tungsten. In one embodiment of the second under bump metallization layer 58 , the second under bump metallization layer 58 includes any metal. In one embodiment of the second under bump metallization layer 58 , a thickness of the second under bump metallization layer 58 is between about 3000 Angstroms and about 5000 Angstroms.
- the first under bump metallization layer 56 and the second under bump metallization layer 58 are seed layers for the first interconnect bump 14 .
- the first under bump metallization layer 56 promotes adhesion to the first interconnect layer 54 .
- the first under bump metallization layer 56 substantially prevents electro-migration of the first interconnect layer 54 .
- FIG. 10 shows the semiconductor die 10 attached to an external device according to one embodiment of the semiconductor die 10 .
- FIG. 10 illustrates a front-view of the semiconductor die 10 illustrated in FIG. 4 .
- Solder 60 is on the first interconnect bump 14 and a laminate 62 is on the solder 60 .
- the first interconnect bump 14 is soldered to the laminate 62 . Since the laminate 62 is an external device, the first interconnect bump 14 provides an electrical connection from the first semiconductor device 22 ( FIG. 5 ) to an external device. Further, the first interconnect bump 14 provides an electrical connection from the second semiconductor device 24 ( FIG. 5 ) to an external device.
- a thickness of the solder 60 is equal to about 25 micrometers.
- the solder 60 is a Tin/Silver alloy. Other embodiments of the solder 60 may include other metals or other metal alloys.
- the laminate 62 functions as a heatsink. In one embodiment of the laminate 62 , the laminate 62 is configured to conduct heat away from the first semiconductor device 22 ( FIG. 5 ) via the first interconnect bump 14 . In an alternate embodiment of the laminate 62 , the laminate 62 is configured to conduct heat away from both the first semiconductor device 22 ( FIG. 5 ) and the second semiconductor device 24 ( FIG. 5 ) via the first interconnect bump 14 . In one embodiment of the laminate 62 , the laminate 62 provides a ground connection to the semiconductor die 10 via the first interconnect bump 14 . In an alternate embodiment of the laminate 62 , the laminate 62 provides a power supply connection to the semiconductor die 10 via the first interconnect bump 14 .
- FIG. 11 illustrates a process for forming the semiconductor die 10 illustrated in FIG. 6 according to one embodiment of the semiconductor die 10 .
- a semiconductor die 10 FIG. 2
- FIG. 2 Provide a semiconductor die 10 ( FIG. 2 ), which includes a first semiconductor device 22 ( FIG. 2 ) having a first group 26 ( FIG. 2 ) of device fingers and a first passivation layer 12 ( FIG. 2 ) over the first semiconductor device 22 ( FIG. 2 ) (Step 100 ).
- Form a first interconnect bump 14 ( FIG. 1 ) which is thermally and electrically connected to each of the first group 26 ( FIG. 2 ) of device fingers, such that the first interconnect bump 14 ( FIG. 1 ) protrudes through a first opening 18 ( FIG. 2 ) in the first passivation layer 12 ( FIG. 2 ) (Step 102 ).
- FIG. 12 illustrates a process for forming the semiconductor die 10 illustrated in FIG. 9 according to an alternate embodiment of the semiconductor die 10 .
- a semiconductor die 10 FIG. 2
- FIG. 2 which includes a first semiconductor device 22 ( FIG. 2 ) having a first group 26 ( FIG. 2 ) of device fingers and a first passivation layer 12 ( FIG. 2 ) over the first semiconductor device 22 ( FIG. 2 ), wherein each of the first group 26 ( FIG. 2 ) of device fingers includes a corresponding portion of a semiconductor material 50 ( FIG. 9 ) and a corresponding portion of a first interconnect layer 54 ( FIG. 9 ), such that each corresponding portion of the first interconnect layer 54 ( FIG. 9 ) is on the corresponding portion of the semiconductor material 50 ( FIG.
- Step 200 Form at least one under bump metallization layer 56 , 58 ( FIG. 9 ) on the first interconnect layer 54 ( FIG. 9 ) (Step 202 ).
- at least one under bump metallization layer 56 , 58 ( FIG. 9 ) is formed by sputtering.
- the first interconnect bump 14 ( FIG. 1 ) is formed by electroplating.
Abstract
A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.
Description
- This application claims the benefit of U.S. provisional patent application No. 61/674,577, filed Jul. 23, 2012, the disclosure of which is incorporated herein by reference in its entirety.
- Embodiments of the present disclosure relate to semiconductor dies and methods for electrically and thermally connecting the semiconductor dies to external circuitry.
- As size, functionality, density, and power of semiconductor dies increase, the number of electrical connections to and from a semiconductor die tends to increase, and the amount of heat needed to be discarded from a semiconductor die also tends to increase. Further, cost and size of a semiconductor die need to be minimized in today's competitive environment. Thus, there is a need for a semiconductor die that provides high functionality, high density, low cost, small size, and discards heat effectively.
- A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.
- In one embodiment of the semiconductor die, the first interconnect bump is configured to conduct heat away from the first semiconductor device. Further, in one embodiment of the semiconductor die, the first interconnect bump is further configured to provide an external electrical connection to the first semiconductor device. The first interconnect bump may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of the first group of device fingers through the first opening in the first passivation layer, the first interconnect bump may provide improved thermal and electrical connectivity over existing designs.
- Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.
- The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
-
FIG. 1 shows a semiconductor die according to one embodiment of the semiconductor die. -
FIG. 2 shows the semiconductor die according to an alternate embodiment of the semiconductor die. -
FIG. 3 shows the semiconductor die according to an additional embodiment of the semiconductor die. -
FIG. 4 shows the semiconductor die according to another embodiment of the semiconductor die. -
FIG. 5 shows the semiconductor die according to a further embodiment of the semiconductor die. -
FIG. 6 shows a cross-section of a portion of the semiconductor die illustrated inFIG. 3 according to one embodiment of the cross-section. -
FIG. 7 shows the cross-section of the portion of the semiconductor die illustrated inFIG. 3 according to an alternate embodiment of the cross-section. -
FIG. 8 shows the cross-section of the portion of the semiconductor die illustrated inFIG. 3 according to an additional embodiment of the cross-section. -
FIG. 9 shows the cross-section of the portion of the semiconductor die illustrated inFIG. 3 according to another embodiment of the cross-section. -
FIG. 10 shows the semiconductor die attached to an external device according to one embodiment of the semiconductor die. -
FIG. 11 illustrates a process for forming the semiconductor die illustrated inFIG. 6 according to one embodiment of the semiconductor die. -
FIG. 12 illustrates a process for forming the semiconductor die illustrated inFIG. 9 according to an alternate embodiment of the semiconductor die. - The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
- It will be understood that when an element such as a layer, region, or substrate is referred to as being “over,” “on,” “in,” or extending “onto” another element, it can be directly over, directly on, directly in, or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over,” “directly on,” “directly in,” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “coupled” to another element, it can be directly coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly coupled” to another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” to another element, it can be directly connected to the other element or intervening conductive elements may be present. In contrast, when an element is referred to as being “directly connected” to another element, there are no intervening conductive elements present.
- The term “thermally connected” is defined herein and for any claims that follow to require a coupling wherein the thermal conductivity of the coupling is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. The term “electrically connected” is defined herein and for any claims that follow to require a coupling wherein the electrical resistivity is less than or equal to about 25×10−8 ohm-meters. Any intervening conductive elements would have an electrical resistivity of less than or equal to about 25×10−8 ohm-meters. Any intervening conductive elements would have a thermal conductivity of greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot.
- Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
-
FIG. 1 shows a 3D view of a semiconductor die 10 according to one embodiment of the semiconductor die 10. The semiconductor die 10 includes afirst passivation layer 12, afirst interconnect bump 14, and asecond interconnect bump 16. In one embodiment of thefirst passivation layer 12, thefirst passivation layer 12 is the uppermost layer of thesemiconductor die 10. - The
first interconnect bump 14 protrudes through thefirst passivation layer 12 and thesecond interconnect bump 16 protrudes through thefirst passivation layer 12. Alternate embodiments of the semiconductor die 10 may include any number of interconnect bumps protruding through thefirst passivation layer 12. - In one embodiment of the
first interconnect bump 14, thefirst interconnect bump 14 is a flip chip bump. In one embodiment of thesecond interconnect bump 16, thesecond interconnect bump 16 is a flip chip bump. In one embodiment of thefirst interconnect bump 14, thefirst interconnect bump 14 includes Copper. In an alternate embodiment of thefirst interconnect bump 14, thefirst interconnect bump 14 consists of Copper. In another embodiment of thefirst interconnect bump 14, thefirst interconnect bump 14 includes any metal. In one embodiment of thesecond interconnect bump 16, thesecond interconnect bump 16 includes Copper. In an alternate embodiment of thesecond interconnect bump 16, thesecond interconnect bump 16 consists of Copper. In another embodiment of thesecond interconnect bump 16, thesecond interconnect bump 16 includes any metal. - In one embodiment of the
first interconnect bump 14, a thermal conductivity of thefirst interconnect bump 14 is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. In one embodiment of thefirst interconnect bump 14, an electrical resistivity of thefirst interconnect bump 14 is less than or equal to about 25×10−8 ohm-meters. In one embodiment of thesecond interconnect bump 16, a thermal conductivity of thesecond interconnect bump 16 is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. In one embodiment of thesecond interconnect bump 16, an electrical resistivity of thesecond interconnect bump 16 is less than or equal to about 25×10−8 ohm-meters. - In one embodiment of the
first interconnect bump 14, a height of thefirst interconnect bump 14 is between about 40 micrometers and about 100 micrometers. In one embodiment of thesecond interconnect bump 16, a height of thesecond interconnect bump 16 is between about 40 micrometers and about 100 micrometers. In one embodiment of thefirst interconnect bump 14, a width of thefirst interconnect bump 14 is between about 70 micrometers and about 90 micrometers and a length of thefirst interconnect bump 14 is between about 80 micrometers and about 500 micrometers. In one embodiment of thesecond interconnect bump 16, a width of thesecond interconnect bump 16 is between about 70 micrometers and about 90 micrometers and a length of thesecond interconnect bump 16 is between about 80 micrometers and about 500 micrometers. - In one embodiment of the
first interconnect bump 14, the vertical corners of thefirst interconnect bump 14 are rounded. In one embodiment of thefirst interconnect bump 14, the horizontal corners of thefirst interconnect bump 14 are rounded. In one embodiment of thesecond interconnect bump 16, the vertical corners of thesecond interconnect bump 16 are rounded. In one embodiment of thesecond interconnect bump 16, the horizontal corners of thesecond interconnect bump 16 are rounded. In an alternate embodiment of thefirst interconnect bump 14, thefirst interconnect bump 14 is of any shape. In an alternate embodiment of thesecond interconnect bump 16, thesecond interconnect bump 16 is of any shape. -
FIG. 2 shows a top view of the semiconductor die 10 according to an alternate embodiment of the semiconductor die 10. The semiconductor die 10 illustrated inFIG. 2 is similar to the semiconductor die 10 illustrated inFIG. 1 ,except in the semiconductor die 10 illustrated inFIG. 2 , thefirst interconnect bump 14 and thesecond interconnect bump 16 are not shown for clarity. - The
first passivation layer 12 has afirst opening 18 and asecond opening 20. The first interconnect bump 14 (FIG. 1 ) protrudes through thefirst opening 18 in thefirst passivation layer 12 and the second interconnect bump 16 (FIG. 1 ) protrudes through thesecond opening 20 in thefirst passivation layer 12. The semiconductor die 10 further includes afirst semiconductor device 22 and asecond semiconductor device 24. Thefirst semiconductor device 22 and thesecond semiconductor device 24 can be seen through thefirst opening 18 and thesecond opening 20, respectively. As such, thefirst passivation layer 12 is over thefirst semiconductor device 22 and thefirst passivation layer 12 is over thesecond semiconductor device 24. In one embodiment of thefirst semiconductor device 22 and thesecond semiconductor device 24, thefirst opening 18 is directly over thefirst semiconductor device 22 and thesecond opening 20 is directly over thesecond semiconductor device 24. - The
first semiconductor device 22 has afirst group 26 of device fingers and thesecond semiconductor device 24 has asecond group 28 of device fingers. The first interconnect bump 14 (FIG. 1 ) is thermally and electrically connected to each of thefirst group 26 of device fingers. The second interconnect bump 16 (FIG. 1 ) is thermally and electrically connected to each of thesecond group 28 of device fingers. - In one embodiment of the semiconductor die 10, the first interconnect bump 14 (
FIG. 1 ) is configured to conduct heat away from thefirst semiconductor device 22. Further, in one embodiment of the semiconductor die 10, the first interconnect bump 14 (FIG. 1 ) is further configured to provide an external electrical connection to thefirst semiconductor device 22. Due to its relative size and form factor, the first interconnect bump 14 (FIG. 1 ) may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of thefirst group 26 of device fingers through thefirst opening 18 in thefirst passivation layer 12, the first interconnect bump 14 (FIG. 1 ) may provide improved thermal and electrical connectivity over existing designs. - In one embodiment of the semiconductor die 10, the second interconnect bump 16 (
FIG. 1 ) is configured to conduct heat away from thesecond semiconductor device 24. Further, in one embodiment of the semiconductor die 10, the second interconnect bump 16 (FIG. 1 ) is further configured to provide an external electrical connection to thesecond semiconductor device 24. Due to its relative size and form factor, the second interconnect bump 16 (FIG. 1 ) may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of thesecond group 28 of device fingers through thesecond opening 20 in thefirst passivation layer 12, the second interconnect bump 16 (FIG. 1 ) may provide improved thermal and electrical connectivity over existing designs. - In one embodiment of the
first passivation layer 12, thefirst passivation layer 12 includes BenzoCycloButene. In an alternate embodiment of thefirst passivation layer 12, thefirst passivation layer 12 includes Polyimide. In another embodiment of thefirst passivation layer 12, thefirst passivation layer 12 includes any passivation material. - The
first semiconductor device 22 has afirst group 30 of sub-cells, such that each of thefirst group 30 of sub-cells has a corresponding portion of thefirst group 26 of device fingers. For example, in thefirst semiconductor device 22 illustrated inFIG. 2 , thefirst group 26 of device fingers has 12 device fingers and each of thefirst group 30 of sub-cells has 4 device fingers. - Similarly, the
second semiconductor device 24 has asecond group 32 of sub-cells, such that each of thesecond group 32 of sub-cells has a corresponding portion of thesecond group 28 of device fingers. For example, in thesecond semiconductor device 24 illustrated inFIG. 2 , thesecond group 28 of device fingers has 12 device fingers and each of thesecond group 32 of sub-cells has 4 device fingers. - Alternate embodiments of the semiconductor die 10 may include any number of semiconductor devices. Each semiconductor device may include any number of device fingers. Further, each semiconductor device may include any number of sub-cells. Each sub-cell may include any number of device fingers. Further, the semiconductor die 10 may include any number of interconnect bumps and the
first passivation layer 12 may include any number of openings as long as each interconnect bump protrudes through an opening in thefirst passivation layer 12. -
FIG. 3 shows the semiconductor die 10 according to an additional embodiment of the semiconductor die 10. The semiconductor die 10 illustrated inFIG. 3 is similar to the semiconductor die 10 illustrated inFIG. 2 , except in the semiconductor die 10 illustrated inFIG. 3 , the semiconductor die 10 further includes asecond passivation layer 34. Thefirst passivation layer 12 is over thesecond passivation layer 34. As such, thesecond passivation layer 34 is visible through thefirst opening 18 and through thesecond opening 20. Thesecond passivation layer 34 is over the first semiconductor device 22 (FIG. 2 ) and over the second semiconductor device 24 (FIG. 2 ). Further, thesecond passivation layer 34 has afirst group 36 of openings and asecond group 38 of openings. - In one embodiment of the
second passivation layer 34, thesecond passivation layer 34 includes Silicon Dioxide. In one embodiment of thesecond passivation layer 34, thesecond passivation layer 34 includes Silicon Nitride. In another embodiment of thesecond passivation layer 34, thesecond passivation layer 34 includes any passivation material. In one embodiment of thesecond passivation layer 34, a thickness of thesecond passivation layer 34 adjacent to each of thefirst group 36 of openings is between about 150 nanometers and about 5500 nanometers. In one embodiment of thesecond passivation layer 34, a thickness of thesecond passivation layer 34 adjacent to each of thesecond group 38 of openings is between about 150 nanometers and about 5500 nanometers. - In one embodiment of the
second passivation layer 34, each of thefirst group 36 of openings is directly over a corresponding one of the first group 30 (FIG. 2 ) of sub-cells. As such, in one embodiment of the first interconnect bump 14 (FIG. 1 ), the first interconnect bump 14 (FIG. 1 ) further protrudes through each of thefirst group 36 of openings. In one embodiment of thesecond passivation layer 34, each of thesecond group 38 of openings is directly over a corresponding one of the second group 32 (FIG. 2 ) of sub-cells. As such, in one embodiment of the second interconnect bump 16 (FIG. 1 ), the second interconnect bump 16 (FIG. 1 ) further protrudes through each of thesecond group 38 of openings. A location of across-section 40 of a portion of the semiconductor die 10 is illustrated inFIG. 3 . -
FIG. 4 shows the semiconductor die 10 according to another embodiment of the semiconductor die 10. The semiconductor die 10 illustrated inFIG. 4 is similar to the semiconductor die 10 illustrated inFIG. 1 , except in the semiconductor die 10 illustrated inFIG. 4 , the second interconnect bump 16 (FIG. 1 ) is omitted. -
FIG. 5 shows the semiconductor die 10 according to a further embodiment of the semiconductor die 10. The semiconductor die 10 illustrated inFIG. 5 is similar to the semiconductor die 10 illustrated inFIG. 2 , except in the semiconductor die 10 illustrated inFIG. 5 , thesecond opening 20 is omitted and thefirst opening 18 is elongated, such that thefirst opening 18 is over both thefirst semiconductor device 22 and thesecond semiconductor device 24. In this regard, the first interconnect bump 14 (FIG. 4 ) is thermally and electrically connected to both thefirst group 26 of device fingers and thesecond group 28 of device fingers. -
FIG. 6 shows thecross-section 40 of the portion of the semiconductor die 10 illustrated inFIG. 3 according to one embodiment of thecross-section 40. Thecross-section 40 includes one of thefirst group 30 of sub-cells (FIG. 2 ) of the first semiconductor device 22 (FIG. 2 ); therefore, thecross-section 40 includes a portion of thefirst group 26 of device fingers. Thecross-section 40 further includes a portion of thefirst passivation layer 12, a portion of thesecond passivation layer 34, afirst semiconductor material 42, abase mesa 44, firstsemiconductor material contacts 46,base contacts 48, asecond semiconductor material 50, adielectric material 52, and afirst interconnect layer 54. As such, four of thefirst group 26 of device fingers are illustrated. - The first
semiconductor material contacts 46 are on thefirst semiconductor material 42. Thebase mesa 44 is on thefirst semiconductor material 42. Thebase contacts 48 are on thebase mesa 44. Each of the portion of thefirst group 26 of device fingers is on thebase mesa 44. Further, each of thefirst group 26 of device fingers includes a corresponding portion of thesecond semiconductor material 50 and a corresponding portion of thefirst interconnect layer 54, such that each corresponding portion of thefirst interconnect layer 54 is on the corresponding portion of thesecond semiconductor material 50. Thedielectric material 52 insulates thebase contacts 48 from the portion of thefirst group 26 of device fingers. - In the embodiment of the
cross-section 40 illustrated inFIG. 6 , thefirst interconnect layer 54 provides a connection between the portion of thefirst group 26 of device fingers of the one of thefirst group 30 of sub-cells (FIG. 2 ). In an alternate embodiment of the cross-section 40 (not shown), thefirst interconnect layer 54 does not provide the connection between the portion of thefirst group 26 of device fingers of the one of thefirst group 30 of sub-cells (FIG. 2 ). - The
second passivation layer 34 is on a portion of thefirst interconnect layer 54 and is on a portion of thedielectric material 52. Thefirst passivation layer 12 is on a portion of thesecond passivation layer 34. Therefore, only a portion of thefirst interconnect layer 54, a portion of thesecond passivation layer 34, and thefirst passivation layer 12 are exposed. A portion of thefirst opening 18 and one of thefirst group 36 of openings are identified for clarity. - In one embodiment of the
first interconnect layer 54, thefirst interconnect layer 54 includes gold. In one embodiment of thefirst interconnect layer 54, thefirst interconnect layer 54 includes any metal. In one embodiment of thefirst semiconductor material 42, thefirst semiconductor material 42 includes Gallium Arsenide. In one embodiment of thefirst semiconductor material 42, thefirst semiconductor material 42 includes Gallium Nitride. In one embodiment of thefirst semiconductor material 42, thefirst semiconductor material 42 includes Silicon. In one embodiment of thefirst semiconductor material 42, thefirst semiconductor material 42 includes N-type Gallium Arsenide. In one embodiment of thefirst semiconductor material 42, thefirst semiconductor material 42 includes P-type Gallium Arsenide. - In one embodiment of the
second semiconductor material 50, thesecond semiconductor material 50 includes Gallium Arsenide. In one embodiment of thesecond semiconductor material 50, thesecond semiconductor material 50 includes Gallium Nitride. In one embodiment of thesecond semiconductor material 50, thesecond semiconductor material 50 includes Silicon. In one embodiment of thesecond semiconductor material 50, thesecond semiconductor material 50 includes N-type Gallium Arsenide. In one embodiment of thesecond semiconductor material 50, thesecond semiconductor material 50 includes P-type Gallium Arsenide. In one embodiment of thebase mesa 44, thebase mesa 44 includes Gallium Arsenide. In one embodiment of thebase mesa 44, thebase mesa 44 includes Gallium Nitride. In one embodiment of thebase mesa 44, thebase mesa 44 includes Silicon. In one embodiment of thebase mesa 44, thebase mesa 44 includes P-type Gallium Arsenide. In one embodiment of thebase mesa 44, thebase mesa 44 includes N-type Gallium Arsenide. - In one embodiment of the first semiconductor device 22 (
FIG. 2 ), the first semiconductor device 22 (FIG. 2 ) is a transistor. In one embodiment of the transistor, an emitter of the transistor includes thefirst group 26 of device fingers. In one embodiment of the transistor, a collector of the transistor includes thefirst group 26 of device fingers. In one embodiment of the first semiconductor device 22 (FIG. 2 ), the first semiconductor device 22 (FIG. 2 ) is a heterojunction bipolar transistor. In one embodiment of thefirst semiconductor device 22 - (
FIG. 2 ), the first semiconductor device 22 (FIG. 2 ) is a bipolar junction transistor. -
FIG. 7 shows thecross-section 40 of the portion of the semiconductor die 10 illustrated inFIG. 3 according to an alternate embodiment of thecross-section 40. Thecross-section 40 illustrated inFIG. 7 is similar to thecross-section 40 illustrated inFIG. 6 , except in thecross-section 40 illustrated inFIG. 7 , thefirst interconnect bump 14 is on thefirst passivation layer 12, thesecond passivation layer 34, and thefirst interconnect layer 54. Further, thefirst interconnect bump 14 protrudes through thefirst passivation layer 12 and through thesecond passivation layer 34. Also, thefirst interconnect bump 14 is thermally and electrically connected to the first semiconductor device 22 (FIG. 2 ) via thefirst interconnect layer 54. -
FIG. 8 shows thecross-section 40 of the portion of the semiconductor die 10 illustrated inFIG. 3 according to an additional embodiment of thecross-section 40. Thecross-section 40 illustrated inFIG. 8 is similar to thecross-section 40 illustrated inFIG. 7 , except in thecross-section 40 illustrated inFIG. 8 , the semiconductor die 10 (FIG. 3 ) further includes a first underbump metallization layer 56 on thefirst interconnect layer 54, such that thefirst interconnect bump 14 is on the first underbump metallization layer 56. In general, thefirst interconnect bump 14 is over thefirst interconnect layer 54. In one embodiment of the first underbump metallization layer 56, the first underbump metallization layer 56 includes Titanium. In one embodiment of the first underbump metallization layer 56, the first underbump metallization layer 56 includes any metal. In one embodiment of the first underbump metallization layer 56, a thickness of the first underbump metallization layer 56 is between about 500 Angstroms and about 1500 Angstroms. In one embodiment of the first underbump metallization layer 56, the first underbump metallization layer 56 is a seed layer for thefirst interconnect bump 14. In one embodiment of the first underbump metallization layer 56, the first underbump metallization layer 56 promotes adhesion to thefirst interconnect layer 54. In one embodiment of the first underbump metallization layer 56, the first underbump metallization layer 56 substantially prevents electro-migration of thefirst interconnect layer 54. -
FIG. 9 shows thecross-section 40 of the portion of the semiconductor die 10 illustrated inFIG. 3 according to another embodiment of thecross-section 40. Thecross-section 40 illustrated inFIG. 9 is similar to thecross-section 40 illustrated inFIG. 8 , except in thecross-section 40 illustrated inFIG. 9 , the semiconductor die 10 (FIG. 3 ) further includes a second underbump metallization layer 58 on the first underbump metallization layer 56, such that thefirst interconnect bump 14 is on the second underbump metallization layer 58. In general, the semiconductor die 10 (FIG. 3 ) includes at least one underbump metallization layer first interconnect layer 54, such that thefirst interconnect bump 14 is on the at least one underbump metallization layer - In one embodiment of the second under
bump metallization layer 58, the second underbump metallization layer 58 includes Copper. In one embodiment of the second underbump metallization layer 58, the second underbump metallization layer 58 includes Tungsten. In one embodiment of the second underbump metallization layer 58, the second underbump metallization layer 58 includes any metal. In one embodiment of the second underbump metallization layer 58, a thickness of the second underbump metallization layer 58 is between about 3000 Angstroms and about 5000 Angstroms. In one embodiment of the first underbump metallization layer 56 and the second underbump metallization layer 58, the first underbump metallization layer 56 and the second underbump metallization layer 58 are seed layers for thefirst interconnect bump 14. In one embodiment of the first underbump metallization layer 56, the first underbump metallization layer 56 promotes adhesion to thefirst interconnect layer 54. In one embodiment of the first underbump metallization layer 56, the first underbump metallization layer 56 substantially prevents electro-migration of thefirst interconnect layer 54. -
FIG. 10 shows the semiconductor die 10 attached to an external device according to one embodiment of the semiconductor die 10.FIG. 10 illustrates a front-view of the semiconductor die 10 illustrated inFIG. 4 .Solder 60 is on thefirst interconnect bump 14 and a laminate 62 is on thesolder 60. As such, thefirst interconnect bump 14 is soldered to thelaminate 62. Since the laminate 62 is an external device, thefirst interconnect bump 14 provides an electrical connection from the first semiconductor device 22 (FIG. 5 ) to an external device. Further, thefirst interconnect bump 14 provides an electrical connection from the second semiconductor device 24 (FIG. 5 ) to an external device. In one embodiment of thesolder 60, a thickness of thesolder 60 is equal to about 25 micrometers. In one embodiment of thesolder 60, thesolder 60 is a Tin/Silver alloy. Other embodiments of thesolder 60 may include other metals or other metal alloys. - In one embodiment of the laminate 62, the laminate 62 functions as a heatsink. In one embodiment of the laminate 62, the laminate 62 is configured to conduct heat away from the first semiconductor device 22 (
FIG. 5 ) via thefirst interconnect bump 14. In an alternate embodiment of the laminate 62, the laminate 62 is configured to conduct heat away from both the first semiconductor device 22 (FIG. 5 ) and the second semiconductor device 24 (FIG. 5 ) via thefirst interconnect bump 14. In one embodiment of the laminate 62, the laminate 62 provides a ground connection to the semiconductor die 10 via thefirst interconnect bump 14. In an alternate embodiment of the laminate 62, the laminate 62 provides a power supply connection to the semiconductor die 10 via thefirst interconnect bump 14. -
FIG. 11 illustrates a process for forming the semiconductor die 10 illustrated inFIG. 6 according to one embodiment of the semiconductor die 10. Provide a semiconductor die 10 (FIG. 2 ), which includes a first semiconductor device 22 (FIG. 2 ) having a first group 26 (FIG. 2 ) of device fingers and a first passivation layer 12 (FIG. 2 ) over the first semiconductor device 22 (FIG. 2 ) (Step 100). Form a first interconnect bump 14 (FIG. 1 ), which is thermally and electrically connected to each of the first group 26 (FIG. 2 ) of device fingers, such that the first interconnect bump 14 (FIG. 1 ) protrudes through a first opening 18 (FIG. 2 ) in the first passivation layer 12 (FIG. 2 ) (Step 102). -
FIG. 12 illustrates a process for forming the semiconductor die 10 illustrated inFIG. 9 according to an alternate embodiment of the semiconductor die 10. Provide a semiconductor die 10 (FIG. 2 ), which includes a first semiconductor device 22 (FIG. 2 ) having a first group 26 (FIG. 2 ) of device fingers and a first passivation layer 12 (FIG. 2 ) over the first semiconductor device 22 (FIG. 2 ), wherein each of the first group 26 (FIG. 2 ) of device fingers includes a corresponding portion of a semiconductor material 50 (FIG. 9 ) and a corresponding portion of a first interconnect layer 54 (FIG. 9 ), such that each corresponding portion of the first interconnect layer 54 (FIG. 9 ) is on the corresponding portion of the semiconductor material 50 (FIG. 9 ) (Step 200). Form at least one underbump metallization layer 56, 58 (FIG. 9 ) on the first interconnect layer 54 (FIG. 9 ) (Step 202). In one embodiment of the at least one underbump metallization layer 56, 58 (FIG. 9 ), at least one underbump metallization layer 56, 58 (FIG. 9 ) is formed by sputtering. Form a first interconnect bump 14 (FIG. 1 ) on the at least one underbump metallization layer 56, 58 (FIG. 9 ), such that the first interconnect bump 14 (FIG. 1 ) protrudes through a first opening 18 (FIG. 2 ) in the first passivation layer 12 (FIG. 2 ) (Step 204). In one embodiment of the first interconnect bump 14 (FIG. 1 ), the first interconnect bump 14 (FIG. 1 ) is formed by electroplating. - Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
Claims (28)
1. A semiconductor die comprising:
a first semiconductor device having a first plurality of device fingers;
a first passivation layer over the first semiconductor device; and
a first interconnect bump thermally and electrically connected to each of the first plurality of device fingers, wherein the first interconnect bump protrudes through a first opening in the first passivation layer.
2. The semiconductor die of claim 1 further comprising a second semiconductor device having a second plurality of device fingers, wherein the first interconnect bump is thermally and electrically connected to each of the second plurality of device fingers.
3. The semiconductor die of claim 1 further comprising a second interconnect bump and a second semiconductor device having a second plurality of device fingers, wherein the second interconnect bump is thermally and electrically connected to each of the second plurality of device fingers, and the second interconnect bump protrudes through a second opening in the first passivation layer.
4. The semiconductor die of claim 1 further comprising a second passivation layer over the first semiconductor device, wherein:
the first passivation layer is over the second passivation layer;
the first semiconductor device has a plurality of sub-cells, wherein each of the plurality of sub-cells has a corresponding portion of the first plurality of device fingers; and
the second passivation layer has a plurality of openings, wherein the first interconnect bump protrudes through each of the plurality of openings.
5. The semiconductor die of claim 4 wherein the second passivation layer comprises Silicon Dioxide.
6. The semiconductor die of claim 4 wherein a thickness of the second passivation layer adjacent to each of the plurality of openings is between about 150 nanometers and about 5500 nanometers.
7. The semiconductor die of claim 1 wherein the first passivation layer comprises BenzoCycloButene.
8. The semiconductor die of claim 1 wherein the first interconnect bump is configured to conduct heat away from the first semiconductor device.
9. The semiconductor die of claim 1 wherein the first interconnect bump is configured to provide an electrical connection from the first semiconductor device to an external device.
10. The semiconductor die of claim 1 wherein the first interconnect bump is a flip chip bump.
11. The semiconductor die of claim 1 wherein each of the first plurality of device fingers comprises a corresponding portion of a semiconductor material and a corresponding portion of a first interconnect layer, wherein each corresponding portion of the first interconnect layer is on the corresponding portion of the semiconductor material.
12. The semiconductor die of claim 11 wherein the first interconnect layer comprises gold.
13. The semiconductor die of claim 11 wherein the semiconductor material comprises Gallium Arsenide.
14. The semiconductor die of claim 11 wherein the semiconductor material comprises N-type Gallium Arsenide.
15. The semiconductor die of claim 11 further comprising a first under bump metallization layer on the first interconnect layer, wherein the first interconnect bump is over the first under bump metallization layer.
16. The semiconductor die of claim 15 wherein the first under bump metallization layer comprises Titanium.
17. The semiconductor die of claim 15 wherein a thickness of the first under bump metallization layer is between about 500 Angstroms and about 1500 Angstroms.
18. The semiconductor die of claim 15 wherein the first interconnect bump is on the first under bump metallization layer.
19. The semiconductor die of claim 15 further comprising a second under bump metallization layer, wherein the first under bump metallization layer is on the first interconnect layer, the second under bump metallization layer is on the first under bump metallization layer, and the first interconnect bump is on the second under bump metallization layer.
20. The semiconductor die of claim 1 wherein the first semiconductor device is a transistor.
21. The semiconductor die of claim 20 wherein the transistor is a heterojunction bipolar transistor.
22. The semiconductor die of claim 20 wherein the transistor is a bipolar junction transistor.
23. The semiconductor die of claim 20 wherein an emitter of the transistor comprises the first plurality of device fingers.
24. The semiconductor die of claim 1 wherein the first interconnect bump comprises Copper.
25. The semiconductor die of claim 1 wherein a height of the first interconnect bump is between about 40 micrometers and about 100 micrometers.
26. The semiconductor die of claim 1 wherein a width of the first interconnect bump is between about 70 micrometers and about 90 micrometers, and a length of the first interconnect bump is between about 80 micrometers and about 500 micrometers.
27. A method comprising:
providing a semiconductor die, which comprises:
a first semiconductor device having a first plurality of device fingers, wherein each of the first plurality of device fingers comprises a corresponding portion of a semiconductor material and a corresponding portion of a first interconnect layer, such that each corresponding portion of the first interconnect layer is on the corresponding portion of the semiconductor material; and
a first passivation layer over the first semiconductor device; and
forming at least one under bump metallization layer on the first interconnect layer; and
forming a first interconnect bump on the at least one under bump metallization layer, wherein the first interconnect bump protrudes through a first opening in the first passivation layer.
28. A method comprising:
providing a semiconductor die, which comprises:
a first semiconductor device having a first plurality of device fingers; and
a first passivation layer over the first semiconductor device; and
forming a first interconnect bump, which is thermally and electrically connected to each of the first plurality of device fingers, wherein the first interconnect bump protrudes through a first opening in the first passivation layer.
Priority Applications (3)
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US13/948,516 US20140021603A1 (en) | 2012-07-23 | 2013-07-23 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
US15/278,960 US20170018520A1 (en) | 2012-07-23 | 2016-09-28 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
US16/113,243 US10777524B2 (en) | 2012-07-23 | 2018-08-27 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
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US201261674577P | 2012-07-23 | 2012-07-23 | |
US13/948,516 US20140021603A1 (en) | 2012-07-23 | 2013-07-23 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
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US13/948,516 Abandoned US20140021603A1 (en) | 2012-07-23 | 2013-07-23 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
US15/278,960 Abandoned US20170018520A1 (en) | 2012-07-23 | 2016-09-28 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
US16/113,243 Active US10777524B2 (en) | 2012-07-23 | 2018-08-27 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
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US16/113,243 Active US10777524B2 (en) | 2012-07-23 | 2018-08-27 | Using an interconnect bump to traverse through a passivation layer of a semiconductor die |
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Also Published As
Publication number | Publication date |
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US20180366431A1 (en) | 2018-12-20 |
US20170018520A1 (en) | 2017-01-19 |
US10777524B2 (en) | 2020-09-15 |
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