US20140103426A1 - Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge - Google Patents
Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge Download PDFInfo
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- US20140103426A1 US20140103426A1 US13/650,330 US201213650330A US2014103426A1 US 20140103426 A1 US20140103426 A1 US 20140103426A1 US 201213650330 A US201213650330 A US 201213650330A US 2014103426 A1 US2014103426 A1 US 2014103426A1
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- 239000004065 semiconductor Substances 0.000 title description 4
- 230000005669 field effect Effects 0.000 title description 2
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 210000000746 body region Anatomy 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 35
- 230000000149 penetrating effect Effects 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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Definitions
- This invention relates generally to the cell structure and device configuration of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and device configuration of a trench metal oxide semiconductor field effect transistor (MOSFET, the same hereinafter) with multiple trenched source-body contacts.
- MOSFET trench metal oxide semiconductor field effect transistor
- FIG. 1A shows a conventional trench MOSFET 100 of prior art, wherein a single trenched source-body contact 101 is penetrating through an n+ source region 102 and extending into a P body region 103 between two adjacent trenched gates 104 in an active area, wherein the n+ source region 102 is formed in an upper portion of the P body region 103 .
- the smaller pitch of the device the lower R ds .
- the minimum 10 um pitch is achieved by using 0.18 um and tungsten plug technologies for a cell density around 500 M/in 2 .
- the R ch is less than 10% of R ds .
- trench MOSFETs having device structure as shown in FIG. 1A no much improvement in R ds but significant increase in gate charge with higher cell density.
- U.S. Pat. No. 8,049,273 discloses a device structure 110 having multiple trenched source-body contacts 111 in unit cells for improving the peak induced voltage in switching converter, as shown in FIG. 1B .
- n+ source regions 112 are disposed not only along channel regions but also among the multiple trenched source-body contacts 111 , causing poor avalanche capability issue because two additional parasitic n+/P/N+ bipolar transistors exist in the device structure 110 .
- the present invention provides a trench MOSFET with multiple trenched source-body contacts for reducing gate charge.
- the multiple trenched source-body contacts are formed in unit cell and filled with tungsten plugs for a wide mesa between two adjacent gate trenches in an active area, furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement.
- UIS Unclamped Inductance Switching
- the present invention features a trench MOSFET comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type onto the substrate, wherein the epitaxial layer has a lower doping concentration than the substrate; a plurality of gate trenches starting from a top surface of the epitaxial layer and extending downward into the epitaxial layer; a plurality of body regions of a second conductivity type between two adjacent gate trenches; a plurality of source regions of the first conductivity type in an upper portion of the body regions in an active area; and multiple trenched source-body contacts each filled with a contact metal plug, penetrating through the source regions and extending into the body regions, wherein the source regions are only formed along channel regions near the gate trenches in the active area, not between two adjacent trenched source-body contacts.
- the present invention features a trench MOSFET further comprising a plurality of body contact doped regions of the second conductivity type within the body regions and surrounding at least bottoms of the multiple trenched source-body contacts, wherein the body contact doped regions have a higher doping concentration than the body regions.
- the present invention features a trench MOSFET wherein the gate trenches can be implemented to have single gate structure comprising a single electrode padded by a gate oxide layer, wherein the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.
- the present invention features a trench MOSFET wherein the gate trenches can be implemented to have single gate structure comprising a single electrode padded by a gate oxide layer, wherein the gate insulation layer has a greater thickness along bottom than along sidewalls of the single electrode.
- the present invention features a trench MOSFET wherein the gate trenches can be implemented to have terrace gate structure comprising a single electrode padded by a gate oxide layer, wherein the single electrode further extends beyond the top surface of the epitaxial layer, and the gate oxide layer has a greater thickness along bottom than along sidewalls of the single electrode.
- the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.
- the present invention features a trench MOSFET wherein the gate trenches can be implemented to have dual electrodes structure comprising a shielded electrode in a lower portion connected to a source metal, and a gate electrode in an upper portion of the gate trench, wherein the shielded electrode and the gate electrode are insulated from the epitaxial layer and insulated from each other.
- the contact metal plug is a tungsten metal layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TiN;
- the trench MOSFET further comprises multiple trenched body contacts filled with the contact metal plugs and extending into the body regions.
- FIG. 1A is a cross-sectional view of a trench MOSFET of a prior art.
- FIG. 1B is a 3D structural diagram showing a trench MOSFET of another prior art.
- FIG. 2 is a cross-sectional view of a preferred embodiment according to the present invention.
- FIG. 3 is a cross-sectional view of another preferred embodiment according to the present invention.
- FIG. 4 is a cross-sectional view of another preferred embodiment according to the present invention.
- FIG. 5 is a cross-sectional view of another preferred embodiment according to the present invention.
- FIG. 6 is a cross-sectional view of another preferred embodiment according to the present invention.
- FIG. 2 Please refer to FIG. 2 for a preferred embodiment of this invention wherein an N-channel trench MOSFET 200 is formed in an N ⁇ epitaxial layer 201 onto an N+ substrate 202 coated with a back metal of Ti/Ni/Ag on a rear side as a drain metal 203 .
- a plurality of gate trenches 204 are formed starting from a top surface of the N ⁇ epitaxial layer 201 and extending downward into the N ⁇ epitaxial layer 201 , each of the gate trenches 204 is formed having single gate structure comprising a single electrode 205 padded by a gate oxide layer 206 , wherein the gate oxide layer 206 has a thickness along sidewalls equal to along bottom of the single electrode 205 .
- the gate oxide layer 206 has a thickness along sidewalls greater than the bottom of the single electrode 205 .
- the single electrode 205 can be implemented by using doped poly-silicon layer.
- a plurality of P body regions 207 are formed in an upper portion of the N ⁇ epitaxial layer 201 between two adjacent gate trenches 204 .
- Two trenched source-body contacts 208 - 1 and 208 - 2 filled with contact metal plugs 209 - 1 and 209 - 2 are penetrating through a contact interlayer 210 and extending into the P body region 207 in an active area, wherein the contact metal plugs 209 - 1 and 209 - 2 are tungsten metal layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TiN.
- n+ source regions 211 are only formed along channel regions near a top surface of the N ⁇ epitaxial layer 201 in the active area, not between two adjacent trenched source-body contacts 208 - 1 and 208 - 2 for UIS current enhancement.
- a trenched body contact 214 is filled with the contact metal plug 215 which is as same as the contact metal plugs 209 - 1 and 209 - 2 and extending into the P body region 207 adjacent edge of the active area.
- a plurality of p+ body contact doped regions 212 are formed within the P body regions 207 surrounding at least bottoms of the trenched source-body contacts 208 - 1 and 208 - 2 and the trenched body contact 214 to reduce the contact resistance between the P body region 207 and the contact metal plugs 209 - 1 , 209 - 2 and 215 .
- a trenched gate contact 216 filled with the contact metal plug 218 which is as same as the contact metal plugs 209 - 1 and 209 - 2 connects a single electrode 205 ′ in a gate trench 204 ′ in a trenched gate contact area to a gate metal 217 for gate connection, wherein the single electrode 205 ′ has a greater width than the single electrode 205 in the active area.
- FIG. 3 shows a cross-sectional view of another trench MOSFET 300 according to the present invention.
- the trench MOSFET 300 has a similar structure to the trench MOSFET 200 in FIG. 2 except that, in FIG. 3 , the trench MOSFET 300 further comprises an additional trenched body contact 301 between the trenched source-body contacts 308 - 1 and 308 - 2 , similarly, n+ source regions 311 only formed along channel regions near the gate trenches 304 , not among the trenched source-body contacts 308 - 1 , 308 - 2 and 301 for UIS current enhancement. Accordingly, the P+ body contact doped regions 312 are formed within the P body regions 307 surrounding at least bottoms of all the trenched contacts to reduce the contact resistance between the P body regions 307 and the contact metal plugs.
- FIG. 4 shows a cross-sectional view of another trench MOSFET 400 according to the present invention.
- the trench MOSFET 400 has a similar structure to the trench MOSFET 200 in FIG. 2 except that, in FIG. 4 , all the gate trenches 404 are formed having single gate structure comprising a single electrode 405 padded by a gate oxide layer 406 , wherein the gate oxide layer 406 has a greater thickness along bottom than along sidewalls of the single electrode 405 .
- FIG. 5 shows a cross-sectional view of another trench MOSFET 500 according to the present invention.
- the trench MOSFET 500 has a similar structure to the trench MOSFET 200 in FIG. 2 except that, in FIG. 5 , all the gate trenches 504 are formed having terrace gate structure comprising a single electrode 505 padded by a gate oxide layer 506 , wherein the single electrode 505 further extends beyond the top surface of the epitaxial layer 501 , and the gate oxide layer 506 has a greater thickness along bottom than along sidewalls of the single electrode 505 .
- the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.
- FIG. 6 shows a cross-sectional view of another trench MOSFET 600 according to the present invention.
- the trench MOSFET 600 has a similar structure to the trench MOSFET 200 in FIG. 2 except that, in FIG. 6 , the gate trenches 604 are formed having dual electrodes structure comprising a shielded electrode (S, as illustrated in FIG. 6 ) 605 in a lower portion and a gate electrode (G, as illustrated in FIG.
- S shielded electrode
- G gate electrode
- the trench MOSFET 600 further comprises a shielded gate trench 610 only filled with the shielded electrode 605 which is connected to a source metal 611 of the trench MOSFET 600 via a trenched shielded electrode contact 612 filled with a contact metal plug.
Abstract
Description
- This invention relates generally to the cell structure and device configuration of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and device configuration of a trench metal oxide semiconductor field effect transistor (MOSFET, the same hereinafter) with multiple trenched source-body contacts.
-
FIG. 1A shows aconventional trench MOSFET 100 of prior art, wherein a single trenched source-body contact 101 is penetrating through ann+ source region 102 and extending into aP body region 103 between two adjacent trenchedgates 104 in an active area, wherein then+ source region 102 is formed in an upper portion of theP body region 103. For trench MOSFET like thetrench MOSFET 100 with voltage rating below 100V (Low Voltage), channel resistance Rch accounts for about 10% and 30% of total Rds at Vgs=10V and at Vgs=4.5V respectively for a 30V N-channel device. It can be seen that the channel resistance Rch plays an important role in on-resistance, especially at Vgs=4.5V. Therefore, the smaller pitch of the device, the lower Rds. So far, the minimum 10 um pitch is achieved by using 0.18 um and tungsten plug technologies for a cell density around 500 M/in2. However, for voltage rating beyond 100V (Middle and High Voltages), applications of the middle and high voltage devices are more at Vgs=10V. The Rch is less than 10% of Rds. For trench MOSFETs having device structure as shown inFIG. 1A , no much improvement in Rds but significant increase in gate charge with higher cell density. - Another prior art U.S. Pat. No. 8,049,273 discloses a
device structure 110 having multiple trenched source-body contacts 111 in unit cells for improving the peak induced voltage in switching converter, as shown inFIG. 1B . However,n+ source regions 112 are disposed not only along channel regions but also among the multiple trenched source-body contacts 111, causing poor avalanche capability issue because two additional parasitic n+/P/N+ bipolar transistors exist in thedevice structure 110. - Therefore, there is still a need in the art of the semiconductor power device, particularly for trench MOSFET design and fabrication, to provide a novel cell structure, device configuration that would resolve these difficulties and design limitations.
- The present invention provides a trench MOSFET with multiple trenched source-body contacts for reducing gate charge. According to the present invention, the multiple trenched source-body contacts are formed in unit cell and filled with tungsten plugs for a wide mesa between two adjacent gate trenches in an active area, furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement.
- In one aspect, the present invention features a trench MOSFET comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type onto the substrate, wherein the epitaxial layer has a lower doping concentration than the substrate; a plurality of gate trenches starting from a top surface of the epitaxial layer and extending downward into the epitaxial layer; a plurality of body regions of a second conductivity type between two adjacent gate trenches; a plurality of source regions of the first conductivity type in an upper portion of the body regions in an active area; and multiple trenched source-body contacts each filled with a contact metal plug, penetrating through the source regions and extending into the body regions, wherein the source regions are only formed along channel regions near the gate trenches in the active area, not between two adjacent trenched source-body contacts.
- In another aspect, the present invention features a trench MOSFET further comprising a plurality of body contact doped regions of the second conductivity type within the body regions and surrounding at least bottoms of the multiple trenched source-body contacts, wherein the body contact doped regions have a higher doping concentration than the body regions.
- In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have single gate structure comprising a single electrode padded by a gate oxide layer, wherein the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.
- In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have single gate structure comprising a single electrode padded by a gate oxide layer, wherein the gate insulation layer has a greater thickness along bottom than along sidewalls of the single electrode.
- In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have terrace gate structure comprising a single electrode padded by a gate oxide layer, wherein the single electrode further extends beyond the top surface of the epitaxial layer, and the gate oxide layer has a greater thickness along bottom than along sidewalls of the single electrode. Alternatively, the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode.
- In another aspect, the present invention features a trench MOSFET wherein the gate trenches can be implemented to have dual electrodes structure comprising a shielded electrode in a lower portion connected to a source metal, and a gate electrode in an upper portion of the gate trench, wherein the shielded electrode and the gate electrode are insulated from the epitaxial layer and insulated from each other.
- Preferred embodiments include one or more of the following features: the contact metal plug is a tungsten metal layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TiN; the trench MOSFET further comprises multiple trenched body contacts filled with the contact metal plugs and extending into the body regions.
- These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.
- The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
-
FIG. 1A is a cross-sectional view of a trench MOSFET of a prior art. -
FIG. 1B is a 3D structural diagram showing a trench MOSFET of another prior art. -
FIG. 2 is a cross-sectional view of a preferred embodiment according to the present invention. -
FIG. 3 is a cross-sectional view of another preferred embodiment according to the present invention. -
FIG. 4 is a cross-sectional view of another preferred embodiment according to the present invention. -
FIG. 5 is a cross-sectional view of another preferred embodiment according to the present invention. -
FIG. 6 is a cross-sectional view of another preferred embodiment according to the present invention. - In the following Detailed Description, reference is made to the accompanying drawings, which forms a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purpose of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be make without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
- Please refer to
FIG. 2 for a preferred embodiment of this invention wherein an N-channel trench MOSFET 200 is formed in an N−epitaxial layer 201 onto anN+ substrate 202 coated with a back metal of Ti/Ni/Ag on a rear side as adrain metal 203. A plurality ofgate trenches 204 are formed starting from a top surface of the N−epitaxial layer 201 and extending downward into the N−epitaxial layer 201, each of thegate trenches 204 is formed having single gate structure comprising asingle electrode 205 padded by agate oxide layer 206, wherein thegate oxide layer 206 has a thickness along sidewalls equal to along bottom of thesingle electrode 205. Alternative, thegate oxide layer 206 has a thickness along sidewalls greater than the bottom of thesingle electrode 205. Thesingle electrode 205 can be implemented by using doped poly-silicon layer. A plurality ofP body regions 207 are formed in an upper portion of the N−epitaxial layer 201 between twoadjacent gate trenches 204. Two trenched source-body contacts 208-1 and 208-2 filled with contact metal plugs 209-1 and 209-2 are penetrating through acontact interlayer 210 and extending into theP body region 207 in an active area, wherein the contact metal plugs 209-1 and 209-2 are tungsten metal layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TiN. Specially,n+ source regions 211 are only formed along channel regions near a top surface of the N−epitaxial layer 201 in the active area, not between two adjacent trenched source-body contacts 208-1 and 208-2 for UIS current enhancement. A trenchedbody contact 214 is filled with thecontact metal plug 215 which is as same as the contact metal plugs 209-1 and 209-2 and extending into theP body region 207 adjacent edge of the active area. A plurality of p+ body contact dopedregions 212 are formed within theP body regions 207 surrounding at least bottoms of the trenched source-body contacts 208-1 and 208-2 and the trenchedbody contact 214 to reduce the contact resistance between theP body region 207 and the contact metal plugs 209-1, 209-2 and 215. A trenchedgate contact 216 filled with thecontact metal plug 218 which is as same as the contact metal plugs 209-1 and 209-2 connects asingle electrode 205′ in agate trench 204′ in a trenched gate contact area to agate metal 217 for gate connection, wherein thesingle electrode 205′ has a greater width than thesingle electrode 205 in the active area. -
FIG. 3 shows a cross-sectional view of anothertrench MOSFET 300 according to the present invention. Thetrench MOSFET 300 has a similar structure to thetrench MOSFET 200 inFIG. 2 except that, inFIG. 3 , thetrench MOSFET 300 further comprises an additional trenchedbody contact 301 between the trenched source-body contacts 308-1 and 308-2, similarly,n+ source regions 311 only formed along channel regions near thegate trenches 304, not among the trenched source-body contacts 308-1, 308-2 and 301 for UIS current enhancement. Accordingly, the P+ body contact dopedregions 312 are formed within theP body regions 307 surrounding at least bottoms of all the trenched contacts to reduce the contact resistance between theP body regions 307 and the contact metal plugs. -
FIG. 4 shows a cross-sectional view of another trench MOSFET 400 according to the present invention. The trench MOSFET 400 has a similar structure to thetrench MOSFET 200 inFIG. 2 except that, inFIG. 4 , all thegate trenches 404 are formed having single gate structure comprising asingle electrode 405 padded by agate oxide layer 406, wherein thegate oxide layer 406 has a greater thickness along bottom than along sidewalls of thesingle electrode 405. -
FIG. 5 shows a cross-sectional view of anothertrench MOSFET 500 according to the present invention. Thetrench MOSFET 500 has a similar structure to thetrench MOSFET 200 inFIG. 2 except that, inFIG. 5 , all thegate trenches 504 are formed having terrace gate structure comprising asingle electrode 505 padded by agate oxide layer 506, wherein thesingle electrode 505 further extends beyond the top surface of theepitaxial layer 501, and thegate oxide layer 506 has a greater thickness along bottom than along sidewalls of thesingle electrode 505. Alternatively, the gate oxide layer has a thickness along sidewalls equal to or greater than bottom of the single electrode. -
FIG. 6 shows a cross-sectional view of anothertrench MOSFET 600 according to the present invention. Thetrench MOSFET 600 has a similar structure to thetrench MOSFET 200 inFIG. 2 except that, inFIG. 6 , thegate trenches 604 are formed having dual electrodes structure comprising a shielded electrode (S, as illustrated inFIG. 6 ) 605 in a lower portion and a gate electrode (G, as illustrated inFIG. 6 ) 606 in an upper portion of thegate trench 604, wherein sidewalls and bottom of the shieldedelectrode 605 are surrounded by agate insulation layer 607, sidewalls of thegate electrode 606 are surrounded by agate oxide layer 608, wherein the shieldedelectrode 605 and thegate electrode 606 are insulated from each other by aninter-insulation layer 609. Thetrench MOSFET 600 further comprises a shieldedgate trench 610 only filled with the shieldedelectrode 605 which is connected to asource metal 611 of thetrench MOSFET 600 via a trenched shieldedelectrode contact 612 filled with a contact metal plug. - Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
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US13/650,330 US8704297B1 (en) | 2012-10-12 | 2012-10-12 | Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge |
CN201310333026.3A CN103730500B (en) | 2012-10-12 | 2013-07-31 | Groove type metal oxide semiconductor FET |
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US13/650,330 US8704297B1 (en) | 2012-10-12 | 2012-10-12 | Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge |
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