US20140156915A1 - Partitioning a flash memory data storage device - Google Patents
Partitioning a flash memory data storage device Download PDFInfo
- Publication number
- US20140156915A1 US20140156915A1 US14/089,397 US201314089397A US2014156915A1 US 20140156915 A1 US20140156915 A1 US 20140156915A1 US 201314089397 A US201314089397 A US 201314089397A US 2014156915 A1 US2014156915 A1 US 2014156915A1
- Authority
- US
- United States
- Prior art keywords
- memory chips
- subset
- storage device
- data storage
- partition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
Definitions
- This description relates to a data storage device.
- Data storage devices may be used to store data.
- a data storage device may be used with a computing device to provide for the data storage needs of the computing device. In certain instances, it may be desirable to store large amounts of data on a data storage device. Also, it may be desirable to execute commands quickly to read data from and to write data to the data storage device.
- a method of partitioning a data storage device that includes a plurality of memory chips. The method includes determining a number memory chips in the data storage device.
- a host coupled to the data storage device defines a first partition and a second of the data storage device, where the first partition includes a first subset of the plurality of memory chips and where the second partition includes a second subset of the plurality of memory chips.
- the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.
- a method of partitioning a data storage device that includes a plurality of memory chips is disclosed, in which a physical configuration of the data storage device, including the number memory chips in the data storage device, and a partitioning scheme for the data storage device are read.
- a host coupled to the data storage device defines a first partition and a second partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and the second partition includes a second subset of the plurality of memory chips, and where the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.
- a logical to physical memory map is allocated for the first partition, and a logical to physical memory map is allocated for the first partition.
- Implementations can include one or more of the following features.
- Data can be written to the first partition while reading data from the second partition.
- Determining a number memory chips in the data storage device can include transmitting information from the data storage device to the host indicating the number of memory chips in the data storage device.
- the host can define an address location in the data storage device to which to write data from the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips.
- the data storage device can include a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, and then the number of physical channels can be determined.
- a first subset and a second subset of the channels can be defined, where channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips and where channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips.
- the host can define an address location in the data storage device to which to write data from the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.
- the first partition can include memory chips that are operably connected to a single channel.
- the host can re-define the first partition of the data storage device to include a third subset of the plurality of memory chips, where the third subset is different from the first subset, and where the third subset does not include any memory chips of the second subset and where the second subset does not include any memory chips of the third subset.
- An indication that one of the memory chips in the first subset has failed or is approaching failure can be received, and then re-defining the first partition can include defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.
- an apparatus in another general aspect, includes a data storage device that includes a plurality of memory chips, and a host operably coupled to the data storage device via an interface.
- the host includes a configuration detection engine configured to detect the number of memory chips in the data storage device, and a partition engine.
- the partition engine is configured to define a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and to define a second partition of the data storage device, where the second partition includes a second subset of the plurality of memory chips, and where the first subset does not include any memory chips of the second subset and where the second subset does not include any memory chips of the first subset.
- an apparatus in another general aspect, includes a data storage device that includes a plurality of memory chips, and a host operably coupled to the data storage device via an interface.
- the host includes a configuration detection engine configured to read a physical configuration of the data storage device, including the number memory chips in the data storage device and configured to read a partitioning scheme for the data storage device.
- the host also includes a partition engine configured to define a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and to define a second partition of the data storage device, where the second partition includes a second subset of the plurality of memory chips, and configured to allocate a logical to physical memory map for the first partition and to allocate a logical to physical memory map for the second partition.
- the first subset does not include any memory chips of the second subset, and the second subset does not include any memory chips of the first subset.
- Implementations can include one or more of the following features.
- the data storage device can be configured to transmit, upon receiving a command from the host, information from the data storage device to the host indicating the number of memory chips in the data storage device.
- the host can also include an address assignment engine configured to assign a memory address to data to be written to the data storage device, where the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips.
- the data storage device can include a plurality of physical channels for communication of data between the host and the plurality of memory chips, with each channel being operably connected to a different plurality of the memory chips.
- the configuration detection engine can be further configured to detect the number of channels in the data storage device, and the partition engine can be further configured to define a first subset of the channels, where channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips, and where the partition engine can be further configured to define a second subset of the channels, where channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips.
- the host can further include an address assignment engine configured to assign a memory address to data to be written to the data storage device, where the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.
- the first partition can include memory chips that are operably connected to a single channel.
- the partition engine can be further configured to re-define the first partition of the data storage device to include a third subset of the plurality of memory chips, where the third subset is different from the first subset, and where the third subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the third subset.
- the partition engine can be further configured to receive an indication that one of the memory chips in the first subset has failed or is approaching failure; and re-defining the first partition to include the third subset of the plurality of memory chips can include defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.
- FIG. 1 is an exemplary block diagram of a data storage device.
- FIG. 2 is an exemplary block diagram of a FPGA controller that can be used in the data storage device of FIG. 1 .
- FIG. 3A is an exemplary block diagram of exemplary computing devices for use with the data storage device of FIG. 1 .
- FIG. 3B is an exemplary block diagram of exemplary computing devices for use with the data storage device of FIG. 1 .
- FIG. 4 is an exemplary flowchart illustrating an example process of partitioning the data storage device of FIG. 1 .
- FIG. 5 is another exemplary flowchart illustrating an example process of partitioning the data storage device of FIG. 1 .
- Such a data storage apparatus may include a controller board having a controller that may be used with one or more different memory boards, with each of the memory boards having multiple flash memory chips.
- the data storage apparatus may communicate with a host using an interface on the controller board.
- the controller on the controller board may be configured to receive commands from the host using the interface and to execute those commands using the flash memory chips on the memory boards.
- FIG. 1 is a block diagram of a data storage device 100 .
- the data storage device 100 may include a controller board 102 and one or more memory boards 104 a and 104 b .
- the data storage device 100 may communicate with a host 106 over an interface 108 .
- the interface 108 may be between the host 106 and the controller board 102 .
- the controller board 102 may include a controller 110 , a DRAM 111 , multiple channels 112 , a power module 114 , and a memory module 116 .
- the memory boards 104 a and 104 b may include multiple flash memory chips 118 a and 118 b on each of the memory boards.
- the memory boards 104 a and 104 b also may include a memory device 120 a and 120 b.
- the data storage device 100 may be configured to store data on the flash memory chips 118 a and 118 b .
- the host 106 may write data to and read data from the flash memory chips 118 a and 118 b , as well as cause other operations to be performed with respect to the flash memory chips 118 a and 118 b .
- the reading and writing of data between the host 106 and the flash memory chips 118 a and 118 b , as well as the other operations, may be processed through and controlled by the controller 110 on the controller board 102 .
- the controller 110 may receive commands from the host 106 and cause those commands to be executed using the flash memory chips 118 a and 118 b on the memory boards 104 a and 104 b .
- the communication between the host 106 and the controller 110 may be through the interface 108 .
- the controller 110 may communicate with the flash memory chips 118 a and 118 b using the channels 112 .
- the controller board 102 may include DRAM 111 .
- the DRAM 111 may be operably coupled to the controller 110 and may be used to store information.
- the DRAM 111 may be used to store logical address to physical address maps and bad block information.
- the DRAM 111 also may be configured to function as a buffer between the host 106 and the flash memory chips 118 a and 118 b.
- the controller board 102 and each of the memory boards 104 a and 104 b are physically separate printed circuit boards (PCBs).
- the memory board 104 a may be on one PCB that is operably connected to the controller board 102 PCB.
- the memory board 104 a may be physically and/or electrically connected to the controller board 102 .
- the memory board 104 b may be a separate PCB from the memory board 104 a and may be operably connected to the controller board 102 PCB.
- the memory board 104 b may be physically and/or electrically connected to the controller board 102 .
- the memory boards 104 a and 104 b each may be separately disconnected and removable from the controller board 102 .
- the memory board 104 a may be disconnected from the controller board 102 and replaced with another memory board (not shown), where the other memory board is operably connected to controller board 102 .
- either or both of the memory boards 104 a and 104 b may be swapped out with other memory boards such that the other memory boards may operate with the same controller board 102 and controller 110 .
- the controller board 102 and each of the memory boards 104 a and 104 b may be physically connected in a disk drive form factor.
- the disk drive form factor may include different sizes such as, for example, a 3.5′′ disk drive form factor and a 2.5′′ disk drive form factor.
- the controller board 102 and each of the memory boards 104 a and 104 b may be electrically connected using a high density ball grid array (BGA) connector.
- BGA high density ball grid array
- Other variants of BGA connectors may be used including, for example, a fine ball grid array (FBGA) connector, an ultra fine ball grid array (UBGA) connector and a micro ball grid array (MBGA) connector.
- FBGA fine ball grid array
- UGA ultra fine ball grid array
- MBGA micro ball grid array
- Other types of electrical connection means also may be used.
- the interface 108 may include a high speed interface between the controller 110 and the host 106 .
- the high speed interface may enable fast transfers of data between the host 106 and the flash memory chips 118 a and 118 b .
- the high speed interface may include a Peripheral Component Interconnect Express (“PCIe”) interface.
- PCIe interface may be a PCIe x4 interface or a PCIe x8 interface.
- the PCIe interface 108 may include a PCIe connector cable assembly to the host 106 .
- the 110 may include an interface controller configured to interface between the host 106 and the interface 108 .
- the interface controller may include a PCIe endpoint controller.
- Other high speed interfaces, connectors, and connector assemblies also may be used.
- the communication between the controller board 102 and the flash memory chips 118 a and 118 b on the memory boards 104 a and 104 b may be arranged and configured into multiple channels 112 .
- Each of the channels 112 may communicate with one or more flash memory chips 118 a and 118 b .
- the controller 110 may be configured such that commands received from the host 106 may be executed by the controller 110 using each of the channels 112 simultaneously or at least substantially simultaneously. In this manner, multiple commands may be executed simultaneously on different channels 112 , which may improve throughput of the data storage device 100 .
- each of the channels 112 may support multiple flash memory chips.
- each of the channels 112 may support up to 32 flash memory chips.
- each of the 20 channels may be configured to support and communicate with 6 flash memory chips.
- each of the memory boards 104 a and 104 b would include 60 flash memory chips each.
- the data storage 100 device may be configured to store up to and including multiple terabytes of data.
- the controller 110 may include a microcontroller, a FPGA controller, other types of controllers, or combinations of these controllers.
- the controller 110 is a microcontroller.
- the microcontroller may be implemented in hardware, software, or a combination of hardware and software.
- the microcontroller may be loaded with a computer program product from memory (e.g., memory module 116 ) including instructions that, when executed, may cause the microcontroller to perform in a certain manner.
- the microcontroller may be configured to receive commands from the host 106 using the interface 108 and to execute the commands.
- the commands may include commands to read, write, copy and erase blocks of data using the flash memory chips 118 a and 118 b , as well as other commands.
- the controller 110 is a FPGA controller.
- the FPGA controller may be implemented in hardware, software, or a combination of hardware and software.
- the FPGA controller may be loaded with firmware from memory (e.g., memory module 116 ) including instructions that, when executed, may cause the FPGA controller to perform in a certain manner.
- the FPGA controller may be configured to receive commands from the host 106 using the interface 108 and to execute the commands.
- the commands may include commands to read, write, copy and erase blocks of data using the flash memory chips 118 a and 118 b , as well as other commands.
- the memory module 116 may be configured to store data, which may be loaded to the controller 110 .
- the memory module 116 may be configured to store one or more images for the FPGA controller, where the images include firmware for use by the FPGA controller.
- the memory module 116 may interface with the host 106 to communicate with the host 106 .
- the memory module 116 may interface directly with the host 106 and/or may interface indirectly with the host 106 through the controller 110 .
- the host 106 may communicate one or more images of firmware to the memory module 116 for storage.
- the memory module 116 includes an electrically erasable programmable read-only memory (EEPROM).
- EEPROM electrically erasable programmable read-only memory
- the memory module 116 also may include other types of memory modules.
- the memory boards 104 a and 104 b may be configured to operate with different types of flash memory chips 118 a and 118 b .
- the flash memory chips 118 a and the flash memory chips 118 b may be the same type of flash memory chips including requiring the same voltage from the power module 114 and being from the same flash memory chip vendor.
- vendor and manufacturer are used interchangeably throughout this document.
- the flash memory chips 118 a on the memory board 104 a may be a different type of flash memory chip from the flash memory chips 118 b on the memory board 104 b .
- the memory board 104 a may include SLC NAND flash memory chips and the memory board 104 b may include MLC NAND flash memory chips.
- the memory board 104 a may include flash memory chips from one flash memory chip manufacturer and the memory board 104 b may include flash memory chips from a different flash memory chip manufacturer. The flexibility to have all the same type of flash memory chips or to have different types of flash memory chips enables the data storage device 100 to be tailored to different applications being used by the host 106 .
- the memory boards 104 a and 104 b may include different types of flash memory chips on the same memory board.
- the memory board 104 a may include both SLC NAND chips and MLC NAND chips on the same PCB.
- the memory board 104 b may include both SLC NAND chips and MLC NAND chips. In this manner, the data storage device 100 may be advantageously tailored to meet the specifications of the host 106 .
- the memory board 104 a and 104 b may include other types of memory devices, including non-flash memory chips.
- the memory boards 104 a and 104 b may include random access memory (RAM) such as, for instance, dynamic RAM (DRAM) and static RAM (SRAM) as well as other types of RAM and other types of memory devices.
- RAM random access memory
- DRAM dynamic RAM
- SRAM static RAM
- the both of the memory boards 104 a and 104 may include RAM.
- one of the memory boards may include RAM and the other memory board may include flash memory chips.
- one of the memory boards may include both RAM and flash memory chips.
- the memory modules 120 a and 120 b on the memory boards 104 a and 104 b may be used to store information related to the flash memory chips 118 a and 118 b , respectively.
- the memory modules 120 a and 120 b may store device characteristics of the flash memory chips. The device characteristics may include whether the chips are SLC chips or MLC chips, whether the chips are NAND or NOR chips, a number of chip selects, a number of blocks, a number of pages per block, a number of bytes per page and a speed of the chips.
- the memory modules 120 a and 120 b may include serial EEPROMs.
- the EEPROMs may store the device characteristics.
- the device characteristics may be compiled once for any given type of flash memory chip and the appropriate EEPROM image may be generated with the device characteristics.
- the controller board 102 When the memory boards 104 a and 104 b are operably connected to the controller board 102 , then the device characteristics may be read from the EEPROMs such that the controller 110 may automatically recognize the types of flash memory chips 118 a and 118 b that the controller 110 is controlling. Additionally, the device characteristics may be used to configure the controller 110 to the appropriate parameters for the specific type or types of flash memory chips 118 a and 118 b.
- the controller 110 may include a FPGA controller.
- FIG. 2 an exemplary block diagram of a FPGA controller 210 is illustrated.
- the FPGA controller may be configured to operate in the manner described above with respect to controller 110 of FIG. 1 .
- the FPGA controller 210 may include multiple channel controllers 250 to connect the multiple channels 112 to the flash memory chips 218 .
- the flash memory chips 218 are illustrated as multiple flash memory chips that connect to each of the channel controllers 250 .
- the flash memory chips 218 are representative of the flash memory chips 118 a and 118 b of FIG. 1 , which are on the separate memory boards 104 a and 104 b of FIG. 1 .
- the separate memory boards are not shown in the example of FIG. 2 .
- the FPGA controller 210 may include a PCIe interface module 208 , a bi-directional direct memory access (DMA) controller 252 , a dynamic random access memory (DRAM) controller 254 , a command processor/queue 256 and an information and configuration interface module 258 .
- DMA direct memory access
- DRAM dynamic random access memory
- the FPGA controller 210 includes a PCIe interface to communicate with the host and a PCIe interface module 208 .
- the PCIe interface module 208 may be arranged and configured to receive commands from the host and to send commands to the host.
- the PCIe interface module 208 may provide data flow control between the host and the data storage device.
- the PCIe interface module 208 may enable high speed transfers of data between the host and the controller 210 and ultimately the flash memory chips 218 .
- the PCIe interface and the PCIe interface module 208 may include a 64-bit bus.
- the bi-directional direct memory access (DMA) controller 252 may be arranged and configured to control the operation of the bus between the PCIe interface module 208 and the command processor/queue 256 .
- DMA direct memory access
- the bi-directional DMA controller 252 may be configured to interface with the PCIe interface 208 , and each of the channel controllers 250 .
- the bi-directional DMA controller 252 enables bi-directional direct memory access between the host 106 and the flash memory chips 218 .
- the DRAM controller 254 may be arranged and configured to control the translation of logical to physical addresses. For example, in an implementation in which the host addresses the memory space using logical addresses, the DRAM controller 254 may assist the command processor/queue 256 with the translation of the logical addresses used by the host to the actual physical addresses in the flash memory chips 218 related to data being written to or read from the flash memory chips 218 . A logical address received from the host may be translated to a physical address for a location in one of the flash memory chips 218 . Similarly, a physical address for a location in one of the flash memory chips 218 may be translated to a logical address and communicated to the host.
- the command processor/queue 256 may be arranged and configured to receive the commands from the host through the PCIe interface module 208 and to control the execution of the commands through the channel controllers 250 .
- the command processor/queue 256 may maintain a queue for a number of commands to be executed and order the commands using an ordered list to ensure that the oldest commands may be processed first.
- the command processor 100 may maintain the order of the commands designated for the same flash memory chip and may reorder the commands designated for different flash memory chips. In this manner, multiple commands may be executed simultaneously and each of the channels 112 may be used simultaneously or at least substantially simultaneously.
- the command processor/queue 256 may be configured to process commands for different channels 112 out of order and preserve per-channel command ordering. For instance, commands that are received from the host and that are designated for different channels may be processed out of order by the command processor/queue 256 . In this manner, the channels may be kept busy. Commands that are received from the host for processing on the same channel may be processed in the order that the commands were received from the host by the command processor/queue 256 . In one exemplary implementation, the command processor/queue 256 may be configured to maintain a list of commands received from the host in an oldest-first sorted list to ensure timely execution of the commands.
- the channel controllers 250 may be arranged and configured to process commands from the command processor/queue 256 . Each of the channel controllers 250 may be configured to process commands for multiple flash memory chips 218 . In one exemplary implementation, each of the channel controllers 250 may be configured to process commands for up to and including 32 flash memory chips 218 .
- the channel controllers 250 may be configured to process the commands from the command processor/queue 256 in order as designated by the command processor/queue 256 .
- Examples of the commands that may be processed include, but are not limited to, reading a flash page, programming a flash page, copying a flash page, erasing a flash block, reading a flash block's metadata, mapping a flash memory chip's bad blocks, and resetting a flash memory chip.
- the information and configuration interface module 258 may be arranged and configured to interface with a memory module (e.g., memory module 116 of FIG. 1 ) to receive configuration information for the FPGA controller 210 .
- a memory module e.g., memory module 116 of FIG. 1
- the information and configuration interface module 258 may receive one or more images from the memory module to provide firmware to the FPGA controller 210 . Modifications to the images and to the firmware may be provided by the host to the controller 210 through the information and configuration interface module 258 .
- Modifications received through the information and configuration interface module 258 may be applied to any of the components of the controller 210 including, for example, the PCIe interface module 208 , the bi-directional direct memory access (DMA) controller 252 , the DRAM controller 254 , the command processor/queue 256 and the channel controllers 250 .
- the information and configuration interface module 258 may include one or more registers, which may be modified as necessary by instructions from the host.
- the FPGA controller 210 may be arranged and configured to cooperate and process commands in conjunction with the host.
- the FPGA controller 210 may perform or at least assist in performing error correction, bad block management, logical to physical mapping, garbage collection, wear levelling, partitioning and low level formatting related to the flash memory chips 218 .
- FIG. 3A is a schematic block diagram of an apparatus 300 including a data storage device 302 having a plurality of flash memory chips 318 a , 318 b , 318 c , 318 d , 318 e , 318 f , 318 g , 318 h , 318 i , 318 j , 318 k , 318 l that are organized into a first partition 321 and a second partition 322 .
- the first and second partition 321 and 322 define different physical areas of storage space in the data storage device 302 , such that directories and files of different categories can be stored in the different partitions, or so that one partition can be used for different purposes than the other partition.
- the first partition can include a first subset of the flash memory chips 318 a - f
- the second partition can include a second subset of the flash memory chips 318 g - 1 , where there are not any flash memory chips that are part of both partitions. That is, the boundary between the partitions 321 and 322 is drawn between individual flash memory chips to ensure that an individual flash memory chip does not belong to more than one partition.
- Organizing the data storage device into two or more partitions can serve a number of purposes. For example, operating system file stored on one partition can be kept separate from user files stored on another partition. Cache and log files that can change size dynamically and rapidly, potentially making a file system full, can be stored on one partition and kept separate from other files stored on a different partition. Partitions can be used for multi-booting setups, which allow users to have more than one operating system on a single computer. For example, a user could install Linux, Mac OS X, and Microsoft Windows or operating systems on different partitions of the same data storage device and have a choice of booting into any operating system (supported by the hardware) at power-up.
- Partitions can be used to protect or isolate files to make it easier to recover a corrupted file system or operating system installation. For example if one partition is corrupted but none of the other file systems are affected, the data on the storage device may still be salvageable. Using a separate partition for read-only data also reduces the chances of the file system on that partition becoming corrupted. Partitions also can raise overall computer performance on systems where smaller file systems are more efficient. For example, large hard drives with only one NTFS file system typically have a very large sequentially-accessed Master File Table (MFT), and it generally takes more time to read this MFT than the smaller MFTs of smaller partitions.
- MFT Master File Table
- the data storage device 302 may be used to store large amounts of data (e.g., many Gigabytes or Terabytes of data) that must be read quickly from the data storage device and supplied to the host.
- the data storage device can be used to cache large volumes of publicly accessible information (e.g., a large corpus of web pages from the World Wide Web, a large library of electronic versions of books, or digital information representing a large volume of telecommunications, etc.) that can be fetched by the host in response to a query.
- publicly accessible information e.g., a large corpus of web pages from the World Wide Web, a large library of electronic versions of books, or digital information representing a large volume of telecommunications, etc.
- the information stored in the data storage device also may need to be constantly updated to keep the information up to date as the relevant information changes. For example, if the information on the storage device relates to a corpus of web pages, the information stored on the storage device may need to be updated as the web pages change and as new web pages are created.
- a partitioned flash memory data storage device 302 can offer exceptional performance.
- write operations to a flash memory chip take much longer (e.g., 10-100 times longer) than read operations from a flash memory chip. Therefore, organizing the chips 318 a - 1 of the data storage device into two or more partitions, where the partitions are defined at boundaries between different chips, offers a way to ensure fast read operations while also allowing the information stored on the data storage device to be updated in real time.
- both partitions 321 and 322 can be used to store a corpus of data (e.g., a corpus of web pages) to be served in response to queries and the individual partitions can alternate between serving the requests and being updated with new information.
- the first partition 321 can be used to provide the information to the host (e.g., information that may be requested in response to a user query), while the data on the second partition 322 is updated (e.g., in response to changes or additions to the web pages of the corpus).
- the recently updated second partition 322 can be used to provide the information to the host, while the data on the first partition 321 is updated.
- This process can be repeated so that data is always served from a partition that acts as a read-only device, and therefore provides very fast responses to read commands from the host without being slowed down by write commands, while the other partition is being updated with new information. Defining the partitions such that an individual flash memory chip is included in only one partition ensures that no flash chip will have data written to it and read from it at substantially the same time, which would cause a delay is responding to a read request from the host 350 .
- the memory chips 318 a - 1 can be connected to a controller that may include a FPGA controller 310 .
- the FPGA controller may be configured to operate in the manner described above with respect to controller 110 of FIG. 1 or of FPGA 210 of FIG. 2 .
- the FPGA controller 310 may include multiple channel controllers 312 a , 312 b , 312 c , 312 d , 312 e , 312 f to connect the multiple channels 112 to the flash memory chips 318 a - 1 .
- the storage device can include more than 12 flash memory chips, more than six channel controllers, and many more than two flash memory chips may be operably connected to a channel controller across a physical channel.
- FIGS. 3A and 3B is merely schematic for clarity of illustration.
- channel controllers 312 a , 312 b , 312 c , 312 d , 312 e , 312 f can control channels that are operably connected to flash memory chips that are part of each partition 321 and 322 .
- channel controller 312 a can be operably connected to memory chip 318 a , which is part of the first partition 321 , and also to memory chip 318 g , which is part of the second partition 322 .
- at least one memory chip in the first partition 321 is connected to each communication channel between the data storage device 302 and the host
- at least one memory chip in the second partition 322 is connected to each communication channel between the data storage device 302 and the host 350 .
- Such a configuration results in maximum parallelism of communication between a partition 321 or 322 and the host, which can result in fast read access and fast write times from and to the data storage device 302 .
- approximately half the channel controllers can be operably connected to flash memory chips in a first partition and approximately half the channel controllers can be operably connected to flash memory chips in the second partition.
- flash memory chips 318 a , 318 b , 318 c , 318 d , 318 e , 318 f , 318 g , 318 h , 318 i , 318 j , 318 k , 318 l can be organized into a first partition 331 , a second partition 322 , a third partition 333 , and a fourth partition 334 , where the different partitions define different physical areas of storage space in the data storage device 302 , such that directories and files of different categories can be stored in the different partitions, or so that one partition can be used for different purposes than the other partition.
- the first partition 331 can include a first subset of the flash memory chips 318 a - c .
- the second partition 332 can include a second subset of the flash memory chips 318 d - f .
- the third partition 333 can include a third subset of the flash memory chips 318 g - i .
- the fourth partition 334 can include a fourth subset of the flash memory chips 318 j - l .
- a partitioned flash memory data storage device 302 can offer exceptional performance, e.g., when used to store a corpus of data (e.g., a corpus of web pages) to be served in response to queries, and the individual partitions can alternate between serving the requests and being updated with new information. For instance, in a first time period the first, second, and third partitions 331 , 332 , and 333 can be used to provide the information to the host (e.g., information that may be requested in response to a user query), while the data on the fourth partition 334 is updated (e.g., in response to changes or additions to the web pages of the corpus).
- the host e.g., information that may be requested in response to a user query
- the data on the fourth partition 334 is updated (e.g., in response to changes or additions to the web pages of the corpus).
- the recently updated fourth partition 334 along with the second and third partitions 332 and 332 can be used to provide the information to the host, while the data on the first partition 331 is updated.
- data on each partition can be updated in round robin fashion, while query requests are served by the other partitions. This process can be repeated so that data is always served from partitions that act as read-only devices, and therefore provides very fast responses to read commands from the host without being slowed down by write commands, while the other partition is being updated with new information.
- Defining four partitions results in redundancy of information stored on the data storage device, so that if a partition, channel, or individual memory chip fails, such that one partition is no longer usable, the remaining three partitions can continue to be used to provide a data storage device in which each of the remaining partitions takes turns being updated while the other remaining partitions serve data requests.
- the data storage device 302 can be connected to a host 350 though an interface 308 , which can be a high speed interface, such as, for example a PCIe interface.
- the host can include, for example, a processor 352 , a first memory 354 , a second memory 356 , and a partition engine 360 .
- the first memory 354 can include, for example, a non-volatile memory device (e.g., a hard disk) adapted for storing machine-readable, executable code instructions that can be executed by the processor 352 .
- the code instructions stored on the first memory 354 can be loaded into the second memory (e.g., a volatile memory, such as, a random access memory) 356 where they can be executed by the processor 352 to create the memory device detection engine 358 and the partition engine 360 .
- the second memory can include logical blocks of “user space” devoted to user mode applications and logical blocks of “kernel space” 364 devoted to running the lower-level resources that user-level applications must control to perform their functions.
- the memory device detection engine 358 and the partition engine 360 can reside in the kernel space 364 of the second memory 356 .
- the configuration detection engine 358 can be configured to detect the number of flash memory chips 318 on the data storage device 302
- the partition engine 360 can be configured to define the first partition 321 and the second partition 322 of the data storage device.
- the configuration detection engine 358 and the partition engine 360 which run on the host 350 , can be used by the host to discover hardware device properties of the data storage device 302 and then to define, via the host, the partitions 321 and 322 .
- the configuration detection engine 358 can issue a query command to the data storage device, and in response to the query command the data storage device can return information to the host about, for example, the number of flash memory chips 318 , the size (e.g., as measured in bytes) of each chip, the number of channels in the data storage device, the flash memory chips to which each the channel controller 312 a - e is operably connected.
- information can be stored on the EEPROM 116 on the FPGA 310 and/or on the EEPROM 120 a of the flash board of the data storage device 302 .
- the configuration detection engine can poll the EEPROM 116 or the EEPROM 120 a (e.g., during a boot-up operation of the host 350 ) to cause the data storage device to return such information to the host 350 .
- the host may poll the flash memory chips 318 to provide the information about, for example, the number of flash memory chips 318 , the size (e.g., as measured in bytes) of each chip, the number of channels in the data storage device, the flash memory chips to which each the channel controller 312 a - e is operably connected.
- the partition engine 360 can receive the information from the memory device detection engine 358 about the number of flash chips 318 , the size of each flash chip, the number of channels and the memory chips to which each channels is operably connected, and, based on this information, the partition engine can define a first partition 321 and second partition 322 in the data storage device 302
- the partition engine running on the host 350 can define the first partition to include memory blocks drawn from a first subset of the memory chips 318 and the second partition memory blocks drawn from a second subset of the memory chips 318 , where the first subset does not include any individual flash chips of the second subset and the second subset does not include any individual flash chips of the first subset.
- the partition engine 360 then can map the physical memory block addresses (which may include, for example, a unique channel number, a unique flash memory chip number, and a block address within the flash memory chip) to logical addresses that can be used by application programs running the in the user space, such that the user space applications running on the host 350 can read data from the data storage device 302 and write data to the data storage device 302 with reference to the logical space addresses.
- physical memory block addresses which may include, for example, a unique channel number, a unique flash memory chip number, and a block address within the flash memory chip
- the device can store information about the partitioning scheme, e.g., on the memory 116 , so that the when the device is booted at a later time, it can communicate the partitioning scheme to the host 106 for the host to use. For example, the device may maintain information about the physical configuration of the data storage device, including a number of flash memory chips in the device and about the partitioning scheme, including which flash memory storage chips and channels are associated with which partitions on the memory 116 .
- the storage device 100 can communicate this information to the host 106 , e.g., in response to a read operation performed by the configuration detection engine 358 of the host 106 .
- the partitioning engine 360 of the host 106 then can define the partitions for the operating system and applications running on the host. For example, the partitioning engine 360 can define a first and second partition based on the information read from the storage device 100 , where the first and second partitions do not include any of the same memory chips.
- the partitioning engine 360 also can allocate a logical to physical memory map for the first and second partitions, so that they user-level application programs can use logical addresses that then are mapped to physical memory addresses of the flash memory chips of the storage device 100 .
- the partition engine 360 also can be used to re-define the first partition of the data storage device to include a third subset of the plurality of flash memory chips, where the third subset is different from the first subset, and where the third subset does not include any flash memory chips of the second subset and wherein the second subset does not include any flash memory chips of the third subset.
- a user may decide that the original partition scheme shown in FIG. 3A does not suit his or her needs, and therefore may use the host to redefine the partitions 321 and 322 (e.g., to include more or fewer flash memory chips in the particular partitions) or to add additional partitions to the scheme.
- the first partition 321 can be redefined as partitions 331 and 333 . Allowing the user to define the partitions through the host rather that forcing the user to accept a partition scheme that is pre-defined by, or pre-loaded in, the controller 310 gives the user flexibility to define partitions as he or she desires and to change the partition scheme when the need arises.
- the imminent failure of one of the flash memory chips, e.g., 318 a may be detected by the host, and in response to this information, the partition engine may re-define the first partition 321 to exclude the flash memory chip 318 a from the partition, i.e., as the originally defined first partition but for the memory chip 318 a .
- any number of partitions can be defined (up to the number of flash memory chips 118 a and 118 b in the storage device 100 ), and different partitions within a partition scheme can include different numbers of flash memory chips and can include different amounts of memory space.
- the host also may include an address assignment engine 366 that can exist in the kernel 364 and that can assign physical memory addresses to data to be written to the data storage device 302 .
- an application running in user space 362 may call for data to be written from the host 350 to the data storage device 302 , and the user space application may specify that the data be written to a particular logical memory address.
- the address assignment engine 366 may translate logical addresses into physical addresses that can include, for example, a particular channel that the data should be written to, a particular flash memory chip operably connected to the specified channel to which the data should be written, and a particular physical block address of the specified memory chip to which the data should be written.
- the translation of logical addresses to physical memory space addresses can be performed by the address assignment engine 366 , such that the role of the DRAM controller 254 of the FPGA 210 is reduced or irrelevant.
- FIG. 4 is an exemplary flowchart illustrating an example process 400 of partitioning the data storage device of FIG. 1 , where the device includes a plurality of flash memory chips.
- the process 400 can include determining a number of flash memory chips in the data storage device ( 402 ).
- the configuration detection engine can query the data storage device to gather information about the number of flash memory chips in the data storage device.
- a first partition of the data storage device can be defined, via a host coupled to the data storage device, where the first partition includes a first subset of the plurality of flash memory chips ( 404 ).
- a second partition of the data storage device can be defined, via the host, where the second partition includes a second subset of the plurality of flash memory chips ( 406 ).
- the first subset does not include any flash memory chips of the second subset and that the second subset does not include any flash memory chips of the first subset.
- the process 400 can include writing data to the first partition while reading data from the second partition ( 408 ).
- Determining the number flash memory chips in the data storage device can include transmitting information from the data storage device to the host indicating the number of flash memory chips in the data storage device ( 410 ).
- An address location in the data storage device to which to write data from the host can be defined in the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips ( 412 ).
- the process 400 can further include determining the number of physical channels ( 414 ), determining a first subset of the channels, where channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips ( 416 ), determining a second subset of the channels, where channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips ( 418 ), and defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel ( 420 ).
- the process 400 can include re-defining, via the host coupled to the data storage device, the first partition of the data storage device to include a third subset of the plurality of flash memory chips (
- FIG. 5 is another exemplary flowchart illustrating an example process 500 of partitioning a data storage device that includes a plurality of flash memory chips
- the process 500 can include reading a physical configuration and of the data storage device, including the number flash memory chips in the data storage device ( 502 ).
- the process can also include reading a partitioning scheme for the data storage device ( 504 ).
- the configuration detection engine can read the physical configuration and the partitioning scheme from the memory 116 of the data storage device.
- a host coupled to the data storage device can define a first partition of the data storage device, where the first partition includes a first subset of the plurality of flash memory chips ( 506 ), and a logical to physical memory map for the first partition can be allocated ( 508 ).
- the host can define a second partition of the data storage device, where the second partition includes a second subset of the plurality of flash memory chips ( 510 ) and where the first subset does not include any flash memory chips of the second subset and wherein the second subset does not include any flash memory chips of the first subset, and a logical to physical memory map for the second partition can be allocated ( 512 ).
- Implementations of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Implementations may be implemented as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers.
- a computer program such as the computer program(s) described above, can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.
- a computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.
- Method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. Method steps also may be performed by, and an apparatus may be implemented as, special purpose logic circuitry, e.g., a FPGA or an ASIC (application-specific integrated circuit).
- special purpose logic circuitry e.g., a FPGA or an ASIC (application-specific integrated circuit).
- processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.
- a processor will receive instructions and data from a read-only memory or a random access memory or both.
- Elements of a computer may include at least one processor for executing instructions and one or more memory devices for storing instructions and data.
- a computer also may include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks.
- Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.
- semiconductor memory devices e.g., EPROM, EEPROM, and flash memory devices
- magnetic disks e.g., internal hard disks or removable disks
- magneto-optical disks e.g., CD-ROM and DVD-ROM disks.
- the processor and the memory may be supplemented by, or incorporated in special purpose logic circuitry.
- implementations may be implemented on a computer having a display device, e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer.
- a display device e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor
- keyboard and a pointing device e.g., a mouse or a trackball
- Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input.
- Implementations may be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation, or any combination of such back-end, middleware, or front-end components.
- Components may be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet.
- LAN local area network
- WAN wide area network
Abstract
A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.
Description
- This application is a Continuation of, and claims priority to, U.S. patent application Ser. No. 12/537,741, filed Aug. 7, 2009, entitled “Partitioning a Flash Memory Data Storage Device”, which, in turn, claims the benefit of U.S. Provisional Application No. 61/167,709, filed Apr. 8, 2009, and titled “Data Storage Device” and U.S. Provisional Application No. 61/187,835, filed Jun. 17, 2009, and titled “Partitioning and Striping in a Flash Memory Data Storage Device,” the disclosures of which are incorporated by reference herein in their entirety.
- This description relates to a data storage device.
- Data storage devices may be used to store data. A data storage device may be used with a computing device to provide for the data storage needs of the computing device. In certain instances, it may be desirable to store large amounts of data on a data storage device. Also, it may be desirable to execute commands quickly to read data from and to write data to the data storage device.
- According to one general aspect, a method of partitioning a data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number memory chips in the data storage device. A host coupled to the data storage device defines a first partition and a second of the data storage device, where the first partition includes a first subset of the plurality of memory chips and where the second partition includes a second subset of the plurality of memory chips. The first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.
- In another general aspect, a method of partitioning a data storage device that includes a plurality of memory chips is disclosed, in which a physical configuration of the data storage device, including the number memory chips in the data storage device, and a partitioning scheme for the data storage device are read. A host coupled to the data storage device defines a first partition and a second partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and the second partition includes a second subset of the plurality of memory chips, and where the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset. A logical to physical memory map is allocated for the first partition, and a logical to physical memory map is allocated for the first partition.
- Implementations can include one or more of the following features. Data can be written to the first partition while reading data from the second partition. Determining a number memory chips in the data storage device can include transmitting information from the data storage device to the host indicating the number of memory chips in the data storage device. The host can define an address location in the data storage device to which to write data from the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips.
- The data storage device can include a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, and then the number of physical channels can be determined. A first subset and a second subset of the channels can be defined, where channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips and where channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips. And the host can define an address location in the data storage device to which to write data from the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel. The first partition can include memory chips that are operably connected to a single channel.
- The host can re-define the first partition of the data storage device to include a third subset of the plurality of memory chips, where the third subset is different from the first subset, and where the third subset does not include any memory chips of the second subset and where the second subset does not include any memory chips of the third subset. An indication that one of the memory chips in the first subset has failed or is approaching failure can be received, and then re-defining the first partition can include defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.
- In another general aspect, an apparatus includes a data storage device that includes a plurality of memory chips, and a host operably coupled to the data storage device via an interface. The host includes a configuration detection engine configured to detect the number of memory chips in the data storage device, and a partition engine. The partition engine is configured to define a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and to define a second partition of the data storage device, where the second partition includes a second subset of the plurality of memory chips, and where the first subset does not include any memory chips of the second subset and where the second subset does not include any memory chips of the first subset.
- In another general aspect, an apparatus includes a data storage device that includes a plurality of memory chips, and a host operably coupled to the data storage device via an interface. The host includes a configuration detection engine configured to read a physical configuration of the data storage device, including the number memory chips in the data storage device and configured to read a partitioning scheme for the data storage device. The host also includes a partition engine configured to define a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and to define a second partition of the data storage device, where the second partition includes a second subset of the plurality of memory chips, and configured to allocate a logical to physical memory map for the first partition and to allocate a logical to physical memory map for the second partition. The first subset does not include any memory chips of the second subset, and the second subset does not include any memory chips of the first subset.
- Implementations can include one or more of the following features. For example, the data storage device can be configured to transmit, upon receiving a command from the host, information from the data storage device to the host indicating the number of memory chips in the data storage device. The host can also include an address assignment engine configured to assign a memory address to data to be written to the data storage device, where the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips.
- The data storage device can include a plurality of physical channels for communication of data between the host and the plurality of memory chips, with each channel being operably connected to a different plurality of the memory chips. Then, the configuration detection engine can be further configured to detect the number of channels in the data storage device, and the partition engine can be further configured to define a first subset of the channels, where channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips, and where the partition engine can be further configured to define a second subset of the channels, where channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips.
- The host can further include an address assignment engine configured to assign a memory address to data to be written to the data storage device, where the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips through a specific channel. The first partition can include memory chips that are operably connected to a single channel. The partition engine can be further configured to re-define the first partition of the data storage device to include a third subset of the plurality of memory chips, where the third subset is different from the first subset, and where the third subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the third subset. The partition engine can be further configured to receive an indication that one of the memory chips in the first subset has failed or is approaching failure; and re-defining the first partition to include the third subset of the plurality of memory chips can include defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.
-
FIG. 1 is an exemplary block diagram of a data storage device. -
FIG. 2 is an exemplary block diagram of a FPGA controller that can be used in the data storage device ofFIG. 1 . -
FIG. 3A is an exemplary block diagram of exemplary computing devices for use with the data storage device ofFIG. 1 . -
FIG. 3B is an exemplary block diagram of exemplary computing devices for use with the data storage device ofFIG. 1 . -
FIG. 4 is an exemplary flowchart illustrating an example process of partitioning the data storage device ofFIG. 1 . -
FIG. 5 is another exemplary flowchart illustrating an example process of partitioning the data storage device ofFIG. 1 . - This document describes an apparatus, system(s) and techniques for data storage. Such a data storage apparatus may include a controller board having a controller that may be used with one or more different memory boards, with each of the memory boards having multiple flash memory chips. The data storage apparatus may communicate with a host using an interface on the controller board. In this manner, the controller on the controller board may be configured to receive commands from the host using the interface and to execute those commands using the flash memory chips on the memory boards.
-
FIG. 1 is a block diagram of adata storage device 100. Thedata storage device 100 may include acontroller board 102 and one ormore memory boards data storage device 100 may communicate with ahost 106 over aninterface 108. Theinterface 108 may be between thehost 106 and thecontroller board 102. Thecontroller board 102 may include acontroller 110, aDRAM 111,multiple channels 112, apower module 114, and amemory module 116. Thememory boards flash memory chips memory boards memory device - In general, the
data storage device 100 may be configured to store data on theflash memory chips host 106 may write data to and read data from theflash memory chips flash memory chips host 106 and theflash memory chips controller 110 on thecontroller board 102. Thecontroller 110 may receive commands from thehost 106 and cause those commands to be executed using theflash memory chips memory boards host 106 and thecontroller 110 may be through theinterface 108. Thecontroller 110 may communicate with theflash memory chips channels 112. - The
controller board 102 may includeDRAM 111. TheDRAM 111 may be operably coupled to thecontroller 110 and may be used to store information. For example, theDRAM 111 may be used to store logical address to physical address maps and bad block information. TheDRAM 111 also may be configured to function as a buffer between thehost 106 and theflash memory chips - In one exemplary implementation, the
controller board 102 and each of thememory boards memory board 104 a may be on one PCB that is operably connected to thecontroller board 102 PCB. For example, thememory board 104 a may be physically and/or electrically connected to thecontroller board 102. Similarly, thememory board 104 b may be a separate PCB from thememory board 104 a and may be operably connected to thecontroller board 102 PCB. For example, thememory board 104 b may be physically and/or electrically connected to thecontroller board 102. - The
memory boards controller board 102. For example, thememory board 104 a may be disconnected from thecontroller board 102 and replaced with another memory board (not shown), where the other memory board is operably connected tocontroller board 102. In this example, either or both of thememory boards same controller board 102 andcontroller 110. - In one exemplary implementation, the
controller board 102 and each of thememory boards - In one exemplary implementation, the
controller board 102 and each of thememory boards - The
interface 108 may include a high speed interface between thecontroller 110 and thehost 106. The high speed interface may enable fast transfers of data between thehost 106 and theflash memory chips PCIe interface 108 may include a PCIe connector cable assembly to thehost 106. In this example, the 110 may include an interface controller configured to interface between thehost 106 and theinterface 108. The interface controller may include a PCIe endpoint controller. Other high speed interfaces, connectors, and connector assemblies also may be used. - In one exemplary implementation, the communication between the
controller board 102 and theflash memory chips memory boards multiple channels 112. Each of thechannels 112 may communicate with one or moreflash memory chips controller 110 may be configured such that commands received from thehost 106 may be executed by thecontroller 110 using each of thechannels 112 simultaneously or at least substantially simultaneously. In this manner, multiple commands may be executed simultaneously ondifferent channels 112, which may improve throughput of thedata storage device 100. - In the example of
FIG. 1 , twenty (20)channels 112 are illustrated. The completely solid lines illustrate the ten (10) channels between thecontroller 110 and theflash memory chips 118 a on thememory board 104 a. The mixed solid and dashed lines illustrate the ten (10) channels between thecontroller 110 and theflash memory chips 118 b on thememory board 104 b. As illustrated inFIG. 1 , each of thechannels 112 may support multiple flash memory chips. For instance, each of thechannels 112 may support up to 32 flash memory chips. In one exemplary implementation, each of the 20 channels may be configured to support and communicate with 6 flash memory chips. In this example, each of thememory boards flash memory chips data storage 100 device may be configured to store up to and including multiple terabytes of data. - The
controller 110 may include a microcontroller, a FPGA controller, other types of controllers, or combinations of these controllers. In one exemplary implementation, thecontroller 110 is a microcontroller. The microcontroller may be implemented in hardware, software, or a combination of hardware and software. For example, the microcontroller may be loaded with a computer program product from memory (e.g., memory module 116) including instructions that, when executed, may cause the microcontroller to perform in a certain manner. The microcontroller may be configured to receive commands from thehost 106 using theinterface 108 and to execute the commands. For instance, the commands may include commands to read, write, copy and erase blocks of data using theflash memory chips - In another exemplary implementation, the
controller 110 is a FPGA controller. The FPGA controller may be implemented in hardware, software, or a combination of hardware and software. For example, the FPGA controller may be loaded with firmware from memory (e.g., memory module 116) including instructions that, when executed, may cause the FPGA controller to perform in a certain manner. The FPGA controller may be configured to receive commands from thehost 106 using theinterface 108 and to execute the commands. For instance, the commands may include commands to read, write, copy and erase blocks of data using theflash memory chips - The
memory module 116 may be configured to store data, which may be loaded to thecontroller 110. For instance, thememory module 116 may be configured to store one or more images for the FPGA controller, where the images include firmware for use by the FPGA controller. Thememory module 116 may interface with thehost 106 to communicate with thehost 106. Thememory module 116 may interface directly with thehost 106 and/or may interface indirectly with thehost 106 through thecontroller 110. For example, thehost 106 may communicate one or more images of firmware to thememory module 116 for storage. In one exemplary implementation, thememory module 116 includes an electrically erasable programmable read-only memory (EEPROM). Thememory module 116 also may include other types of memory modules. - The
memory boards flash memory chips flash memory chips 118 a and theflash memory chips 118 b may be the same type of flash memory chips including requiring the same voltage from thepower module 114 and being from the same flash memory chip vendor. The terms vendor and manufacturer are used interchangeably throughout this document. - In another exemplary implementation, the
flash memory chips 118 a on thememory board 104 a may be a different type of flash memory chip from theflash memory chips 118 b on thememory board 104 b. For example, thememory board 104 a may include SLC NAND flash memory chips and thememory board 104 b may include MLC NAND flash memory chips. In another example, thememory board 104 a may include flash memory chips from one flash memory chip manufacturer and thememory board 104 b may include flash memory chips from a different flash memory chip manufacturer. The flexibility to have all the same type of flash memory chips or to have different types of flash memory chips enables thedata storage device 100 to be tailored to different applications being used by thehost 106. - In another exemplary implementation, the
memory boards memory board 104 a may include both SLC NAND chips and MLC NAND chips on the same PCB. Similarly, thememory board 104 b may include both SLC NAND chips and MLC NAND chips. In this manner, thedata storage device 100 may be advantageously tailored to meet the specifications of thehost 106. - In another exemplary implementation, the
memory board memory boards memory boards 104 a and 104 may include RAM. In another exemplary implementation, one of the memory boards may include RAM and the other memory board may include flash memory chips. Also, one of the memory boards may include both RAM and flash memory chips. - The
memory modules memory boards flash memory chips memory modules - In one exemplary implementation, the
memory modules memory boards controller board 102, then the device characteristics may be read from the EEPROMs such that thecontroller 110 may automatically recognize the types offlash memory chips controller 110 is controlling. Additionally, the device characteristics may be used to configure thecontroller 110 to the appropriate parameters for the specific type or types offlash memory chips - As discussed above, the
controller 110 may include a FPGA controller. Referring toFIG. 2 , an exemplary block diagram of aFPGA controller 210 is illustrated. The FPGA controller may be configured to operate in the manner described above with respect tocontroller 110 ofFIG. 1 . TheFPGA controller 210 may includemultiple channel controllers 250 to connect themultiple channels 112 to theflash memory chips 218. Theflash memory chips 218 are illustrated as multiple flash memory chips that connect to each of thechannel controllers 250. Theflash memory chips 218 are representative of theflash memory chips FIG. 1 , which are on theseparate memory boards FIG. 1 . The separate memory boards are not shown in the example ofFIG. 2 . TheFPGA controller 210 may include aPCIe interface module 208, a bi-directional direct memory access (DMA)controller 252, a dynamic random access memory (DRAM)controller 254, a command processor/queue 256 and an information andconfiguration interface module 258. - Information may be communicated with a host (e.g., host 106 of
FIG. 1 ) using an interface. In this example,FIG. 2 , theFPGA controller 210 includes a PCIe interface to communicate with the host and aPCIe interface module 208. ThePCIe interface module 208 may be arranged and configured to receive commands from the host and to send commands to the host. ThePCIe interface module 208 may provide data flow control between the host and the data storage device. ThePCIe interface module 208 may enable high speed transfers of data between the host and thecontroller 210 and ultimately theflash memory chips 218. In one exemplary implementation, the PCIe interface and thePCIe interface module 208 may include a 64-bit bus. The bi-directional direct memory access (DMA)controller 252 may be arranged and configured to control the operation of the bus between thePCIe interface module 208 and the command processor/queue 256. - The
bi-directional DMA controller 252 may be configured to interface with thePCIe interface 208, and each of thechannel controllers 250. Thebi-directional DMA controller 252 enables bi-directional direct memory access between thehost 106 and theflash memory chips 218. - The
DRAM controller 254 may be arranged and configured to control the translation of logical to physical addresses. For example, in an implementation in which the host addresses the memory space using logical addresses, theDRAM controller 254 may assist the command processor/queue 256 with the translation of the logical addresses used by the host to the actual physical addresses in theflash memory chips 218 related to data being written to or read from theflash memory chips 218. A logical address received from the host may be translated to a physical address for a location in one of theflash memory chips 218. Similarly, a physical address for a location in one of theflash memory chips 218 may be translated to a logical address and communicated to the host. - The command processor/
queue 256 may be arranged and configured to receive the commands from the host through thePCIe interface module 208 and to control the execution of the commands through thechannel controllers 250. The command processor/queue 256 may maintain a queue for a number of commands to be executed and order the commands using an ordered list to ensure that the oldest commands may be processed first. Thecommand processor 100 may maintain the order of the commands designated for the same flash memory chip and may reorder the commands designated for different flash memory chips. In this manner, multiple commands may be executed simultaneously and each of thechannels 112 may be used simultaneously or at least substantially simultaneously. - The command processor/
queue 256 may be configured to process commands fordifferent channels 112 out of order and preserve per-channel command ordering. For instance, commands that are received from the host and that are designated for different channels may be processed out of order by the command processor/queue 256. In this manner, the channels may be kept busy. Commands that are received from the host for processing on the same channel may be processed in the order that the commands were received from the host by the command processor/queue 256. In one exemplary implementation, the command processor/queue 256 may be configured to maintain a list of commands received from the host in an oldest-first sorted list to ensure timely execution of the commands. - The
channel controllers 250 may be arranged and configured to process commands from the command processor/queue 256. Each of thechannel controllers 250 may be configured to process commands for multipleflash memory chips 218. In one exemplary implementation, each of thechannel controllers 250 may be configured to process commands for up to and including 32flash memory chips 218. - The
channel controllers 250 may be configured to process the commands from the command processor/queue 256 in order as designated by the command processor/queue 256. Examples of the commands that may be processed include, but are not limited to, reading a flash page, programming a flash page, copying a flash page, erasing a flash block, reading a flash block's metadata, mapping a flash memory chip's bad blocks, and resetting a flash memory chip. - The information and
configuration interface module 258 may be arranged and configured to interface with a memory module (e.g.,memory module 116 ofFIG. 1 ) to receive configuration information for theFPGA controller 210. For example, the information andconfiguration interface module 258 may receive one or more images from the memory module to provide firmware to theFPGA controller 210. Modifications to the images and to the firmware may be provided by the host to thecontroller 210 through the information andconfiguration interface module 258. Modifications received through the information andconfiguration interface module 258 may be applied to any of the components of thecontroller 210 including, for example, thePCIe interface module 208, the bi-directional direct memory access (DMA)controller 252, theDRAM controller 254, the command processor/queue 256 and thechannel controllers 250. The information andconfiguration interface module 258 may include one or more registers, which may be modified as necessary by instructions from the host. - The
FPGA controller 210 may be arranged and configured to cooperate and process commands in conjunction with the host. TheFPGA controller 210 may perform or at least assist in performing error correction, bad block management, logical to physical mapping, garbage collection, wear levelling, partitioning and low level formatting related to theflash memory chips 218. -
FIG. 3A is a schematic block diagram of an apparatus 300 including adata storage device 302 having a plurality offlash memory chips first partition 321 and asecond partition 322. The first andsecond partition data storage device 302, such that directories and files of different categories can be stored in the different partitions, or so that one partition can be used for different purposes than the other partition. The first partition can include a first subset of the flash memory chips 318 a-f, while the second partition can include a second subset of theflash memory chips 318 g-1, where there are not any flash memory chips that are part of both partitions. That is, the boundary between thepartitions - Organizing the data storage device into two or more partitions can serve a number of purposes. For example, operating system file stored on one partition can be kept separate from user files stored on another partition. Cache and log files that can change size dynamically and rapidly, potentially making a file system full, can be stored on one partition and kept separate from other files stored on a different partition. Partitions can be used for multi-booting setups, which allow users to have more than one operating system on a single computer. For example, a user could install Linux, Mac OS X, and Microsoft Windows or operating systems on different partitions of the same data storage device and have a choice of booting into any operating system (supported by the hardware) at power-up. Partitions can be used to protect or isolate files to make it easier to recover a corrupted file system or operating system installation. For example if one partition is corrupted but none of the other file systems are affected, the data on the storage device may still be salvageable. Using a separate partition for read-only data also reduces the chances of the file system on that partition becoming corrupted. Partitions also can raise overall computer performance on systems where smaller file systems are more efficient. For example, large hard drives with only one NTFS file system typically have a very large sequentially-accessed Master File Table (MFT), and it generally takes more time to read this MFT than the smaller MFTs of smaller partitions.
- In another example embodiment, the
data storage device 302 may be used to store large amounts of data (e.g., many Gigabytes or Terabytes of data) that must be read quickly from the data storage device and supplied to the host. For example, the data storage device can be used to cache large volumes of publicly accessible information (e.g., a large corpus of web pages from the World Wide Web, a large library of electronic versions of books, or digital information representing a large volume of telecommunications, etc.) that can be fetched by the host in response to a query. Thus, it can be important that the relevant data be accessed and returned very quickly in response to a read command issued by the host. However, the information stored in the data storage device also may need to be constantly updated to keep the information up to date as the relevant information changes. For example, if the information on the storage device relates to a corpus of web pages, the information stored on the storage device may need to be updated as the web pages change and as new web pages are created. - In such a system, a partitioned flash memory
data storage device 302 can offer exceptional performance. In a flash memory storage device, write operations to a flash memory chip take much longer (e.g., 10-100 times longer) than read operations from a flash memory chip. Therefore, organizing the chips 318 a-1 of the data storage device into two or more partitions, where the partitions are defined at boundaries between different chips, offers a way to ensure fast read operations while also allowing the information stored on the data storage device to be updated in real time. For example, bothpartitions first partition 321 can be used to provide the information to the host (e.g., information that may be requested in response to a user query), while the data on thesecond partition 322 is updated (e.g., in response to changes or additions to the web pages of the corpus). Then, in a second time period, the recently updatedsecond partition 322 can be used to provide the information to the host, while the data on thefirst partition 321 is updated. This process can be repeated so that data is always served from a partition that acts as a read-only device, and therefore provides very fast responses to read commands from the host without being slowed down by write commands, while the other partition is being updated with new information. Defining the partitions such that an individual flash memory chip is included in only one partition ensures that no flash chip will have data written to it and read from it at substantially the same time, which would cause a delay is responding to a read request from thehost 350. - As discussed above, the memory chips 318 a-1 can be connected to a controller that may include a
FPGA controller 310. The FPGA controller may be configured to operate in the manner described above with respect tocontroller 110 ofFIG. 1 or ofFPGA 210 ofFIG. 2 . TheFPGA controller 310 may includemultiple channel controllers multiple channels 112 to the flash memory chips 318 a-1. Of course, as described above, the storage device can include more than 12 flash memory chips, more than six channel controllers, and many more than two flash memory chips may be operably connected to a channel controller across a physical channel. Thus, the implementation shown inFIGS. 3A and 3B is merely schematic for clarity of illustration. - In one implementation,
channel controllers partition channel controller 312 a can be operably connected tomemory chip 318 a, which is part of thefirst partition 321, and also tomemory chip 318 g, which is part of thesecond partition 322. In such a configuration, at least one memory chip in thefirst partition 321 is connected to each communication channel between thedata storage device 302 and the host, and at least one memory chip in thesecond partition 322 is connected to each communication channel between thedata storage device 302 and thehost 350. Such a configuration results in maximum parallelism of communication between apartition data storage device 302. - In another implementation, approximately half the channel controllers can be operably connected to flash memory chips in a first partition and approximately half the channel controllers can be operably connected to flash memory chips in the second partition.
- In another implementation, shown in
FIG. 3B ,flash memory chips first partition 331, asecond partition 322, athird partition 333, and afourth partition 334, where the different partitions define different physical areas of storage space in thedata storage device 302, such that directories and files of different categories can be stored in the different partitions, or so that one partition can be used for different purposes than the other partition. Thefirst partition 331 can include a first subset of the flash memory chips 318 a-c. Thesecond partition 332 can include a second subset of theflash memory chips 318 d-f. Thethird partition 333 can include a third subset of theflash memory chips 318 g-i. Thefourth partition 334 can include a fourth subset of the flash memory chips 318 j-l. Among thedifferent partitions partitions - In the system of
FIG. 3B , a partitioned flash memorydata storage device 302 can offer exceptional performance, e.g., when used to store a corpus of data (e.g., a corpus of web pages) to be served in response to queries, and the individual partitions can alternate between serving the requests and being updated with new information. For instance, in a first time period the first, second, andthird partitions fourth partition 334 is updated (e.g., in response to changes or additions to the web pages of the corpus). Then, in a second time period, the recently updatedfourth partition 334, along with the second andthird partitions first partition 331 is updated. Thus, data on each partition can be updated in round robin fashion, while query requests are served by the other partitions. This process can be repeated so that data is always served from partitions that act as read-only devices, and therefore provides very fast responses to read commands from the host without being slowed down by write commands, while the other partition is being updated with new information. Defining four partitions results in redundancy of information stored on the data storage device, so that if a partition, channel, or individual memory chip fails, such that one partition is no longer usable, the remaining three partitions can continue to be used to provide a data storage device in which each of the remaining partitions takes turns being updated while the other remaining partitions serve data requests. - As described above, the
data storage device 302 can be connected to ahost 350 though an interface 308, which can be a high speed interface, such as, for example a PCIe interface. The host can include, for example, aprocessor 352, afirst memory 354, asecond memory 356, and apartition engine 360. Thefirst memory 354 can include, for example, a non-volatile memory device (e.g., a hard disk) adapted for storing machine-readable, executable code instructions that can be executed by theprocessor 352. The code instructions stored on thefirst memory 354 can be loaded into the second memory (e.g., a volatile memory, such as, a random access memory) 356 where they can be executed by theprocessor 352 to create the memorydevice detection engine 358 and thepartition engine 360. The second memory can include logical blocks of “user space” devoted to user mode applications and logical blocks of “kernel space” 364 devoted to running the lower-level resources that user-level applications must control to perform their functions. The memorydevice detection engine 358 and thepartition engine 360 can reside in thekernel space 364 of thesecond memory 356. - The
configuration detection engine 358 can be configured to detect the number of flash memory chips 318 on thedata storage device 302, and thepartition engine 360 can be configured to define thefirst partition 321 and thesecond partition 322 of the data storage device. Thus, theconfiguration detection engine 358 and thepartition engine 360, which run on thehost 350, can be used by the host to discover hardware device properties of thedata storage device 302 and then to define, via the host, thepartitions configuration detection engine 358 can issue a query command to the data storage device, and in response to the query command the data storage device can return information to the host about, for example, the number of flash memory chips 318, the size (e.g., as measured in bytes) of each chip, the number of channels in the data storage device, the flash memory chips to which each the channel controller 312 a-e is operably connected. Such information can be stored on theEEPROM 116 on theFPGA 310 and/or on theEEPROM 120 a of the flash board of thedata storage device 302. The configuration detection engine can poll theEEPROM 116 or theEEPROM 120 a (e.g., during a boot-up operation of the host 350) to cause the data storage device to return such information to thehost 350. In another implementation, the host may poll the flash memory chips 318 to provide the information about, for example, the number of flash memory chips 318, the size (e.g., as measured in bytes) of each chip, the number of channels in the data storage device, the flash memory chips to which each the channel controller 312 a-e is operably connected. - The
partition engine 360 can receive the information from the memorydevice detection engine 358 about the number of flash chips 318, the size of each flash chip, the number of channels and the memory chips to which each channels is operably connected, and, based on this information, the partition engine can define afirst partition 321 andsecond partition 322 in thedata storage device 302 The partition engine running on thehost 350 can define the first partition to include memory blocks drawn from a first subset of the memory chips 318 and the second partition memory blocks drawn from a second subset of the memory chips 318, where the first subset does not include any individual flash chips of the second subset and the second subset does not include any individual flash chips of the first subset. Thepartition engine 360 then can map the physical memory block addresses (which may include, for example, a unique channel number, a unique flash memory chip number, and a block address within the flash memory chip) to logical addresses that can be used by application programs running the in the user space, such that the user space applications running on thehost 350 can read data from thedata storage device 302 and write data to thedata storage device 302 with reference to the logical space addresses. - After a partition scheme of multiple partitions has been defined and data has been stored on the flash memory chips of the
data storage device 100, the device can store information about the partitioning scheme, e.g., on thememory 116, so that the when the device is booted at a later time, it can communicate the partitioning scheme to thehost 106 for the host to use. For example, the device may maintain information about the physical configuration of the data storage device, including a number of flash memory chips in the device and about the partitioning scheme, including which flash memory storage chips and channels are associated with which partitions on thememory 116. Then, when the system including thehost 106 and thedata storage device 100 is booted, thestorage device 100 can communicate this information to thehost 106, e.g., in response to a read operation performed by theconfiguration detection engine 358 of thehost 106. Thepartitioning engine 360 of thehost 106 then can define the partitions for the operating system and applications running on the host. For example, thepartitioning engine 360 can define a first and second partition based on the information read from thestorage device 100, where the first and second partitions do not include any of the same memory chips. Thepartitioning engine 360 also can allocate a logical to physical memory map for the first and second partitions, so that they user-level application programs can use logical addresses that then are mapped to physical memory addresses of the flash memory chips of thestorage device 100. - The
partition engine 360 also can be used to re-define the first partition of the data storage device to include a third subset of the plurality of flash memory chips, where the third subset is different from the first subset, and where the third subset does not include any flash memory chips of the second subset and wherein the second subset does not include any flash memory chips of the third subset. For example, with reference toFIG. 3A andFIG. 3B , a user may decide that the original partition scheme shown inFIG. 3A does not suit his or her needs, and therefore may use the host to redefine thepartitions 321 and 322 (e.g., to include more or fewer flash memory chips in the particular partitions) or to add additional partitions to the scheme. In one implementation, thefirst partition 321 can be redefined aspartitions controller 310 gives the user flexibility to define partitions as he or she desires and to change the partition scheme when the need arises. In another implementation, the imminent failure of one of the flash memory chips, e.g., 318 a, may be detected by the host, and in response to this information, the partition engine may re-define thefirst partition 321 to exclude theflash memory chip 318 a from the partition, i.e., as the originally defined first partition but for thememory chip 318 a. Thus, any number of partitions can be defined (up to the number offlash memory chips - The host also may include an
address assignment engine 366 that can exist in thekernel 364 and that can assign physical memory addresses to data to be written to thedata storage device 302. For example, an application running inuser space 362 may call for data to be written from thehost 350 to thedata storage device 302, and the user space application may specify that the data be written to a particular logical memory address. Theaddress assignment engine 366 may translate logical addresses into physical addresses that can include, for example, a particular channel that the data should be written to, a particular flash memory chip operably connected to the specified channel to which the data should be written, and a particular physical block address of the specified memory chip to which the data should be written. In such an implementation, the translation of logical addresses to physical memory space addresses can be performed by theaddress assignment engine 366, such that the role of theDRAM controller 254 of theFPGA 210 is reduced or irrelevant. -
FIG. 4 is an exemplary flowchart illustrating anexample process 400 of partitioning the data storage device ofFIG. 1 , where the device includes a plurality of flash memory chips. Theprocess 400 can include determining a number of flash memory chips in the data storage device (402). For example, the configuration detection engine can query the data storage device to gather information about the number of flash memory chips in the data storage device. A first partition of the data storage device can be defined, via a host coupled to the data storage device, where the first partition includes a first subset of the plurality of flash memory chips (404). A second partition of the data storage device can be defined, via the host, where the second partition includes a second subset of the plurality of flash memory chips (406). As a result of this process it is ensured that the first subset does not include any flash memory chips of the second subset and that the second subset does not include any flash memory chips of the first subset. - Optionally, the
process 400 can include writing data to the first partition while reading data from the second partition (408). Determining the number flash memory chips in the data storage device can include transmitting information from the data storage device to the host indicating the number of flash memory chips in the data storage device (410). An address location in the data storage device to which to write data from the host can be defined in the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips (412). - When the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of flash memory chips, with each channel being operably connected to a different plurality of the memory chips, the
process 400 can further include determining the number of physical channels (414), determining a first subset of the channels, where channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips (416), determining a second subset of the channels, where channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips (418), and defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel (420). In addition, theprocess 400 can include re-defining, via the host coupled to the data storage device, the first partition of the data storage device to include a third subset of the plurality of flash memory chips (422). -
FIG. 5 is another exemplary flowchart illustrating anexample process 500 of partitioning a data storage device that includes a plurality of flash memory chips, Theprocess 500 can include reading a physical configuration and of the data storage device, including the number flash memory chips in the data storage device (502). The process can also include reading a partitioning scheme for the data storage device (504). For example, the configuration detection engine can read the physical configuration and the partitioning scheme from thememory 116 of the data storage device. A host coupled to the data storage device can define a first partition of the data storage device, where the first partition includes a first subset of the plurality of flash memory chips (506), and a logical to physical memory map for the first partition can be allocated (508). The host can define a second partition of the data storage device, where the second partition includes a second subset of the plurality of flash memory chips (510) and where the first subset does not include any flash memory chips of the second subset and wherein the second subset does not include any flash memory chips of the first subset, and a logical to physical memory map for the second partition can be allocated (512). - Implementations of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Implementations may be implemented as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program, such as the computer program(s) described above, can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.
- Method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. Method steps also may be performed by, and an apparatus may be implemented as, special purpose logic circuitry, e.g., a FPGA or an ASIC (application-specific integrated circuit).
- Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer may include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also may include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in special purpose logic circuitry.
- To provide for interaction with a user, implementations may be implemented on a computer having a display device, e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input.
- Implementations may be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation, or any combination of such back-end, middleware, or front-end components. Components may be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet.
- While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments.
Claims (21)
1. (canceled)
2. A method of partitioning a data storage device, the method comprising:
receiving, via an interface operably coupling a host with the data storage device, information indicating a number of a plurality of flash memory chips in the data storage device, a first portion of the plurality of flash memory chips being implemented in a first memory channel and a second portion of the plurality of flash memory chips being implemented in a second memory channel;
defining, by the host, a first partition of the data storage device, the first partition including a first subset of the plurality of flash memory chips that includes one or more memory chips of the first memory channel and one or more memory chips of the second memory channel; and
defining, by the host, a second partition of the data storage device, the second partition including a second subset of the plurality of flash memory chips that does not include any flash memory chips of the first subset, a boundary between the first partition and the second partition being defined by the first subset of memory chips and the second subset of memory chip.
3. The method of claim 2 , wherein the interface is a PCIe interface.
4. The method of claim 2 , further comprising:
transmitting first data, via the interface, from the host to the data storage device; and
writing the first data to the first partition while reading second data from the second partition.
5. The method of claim 2 , further comprising defining, by the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips.
6. The method of claim 2 , wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, the method further comprising:
determining a number of the plurality of physical channels;
determining a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips;
determining a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips; and
defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.
7. The method of claim 6 , wherein the second partition includes memory chips that are operably connected to a single channel.
8. The method of claim 2 , further comprising:
re-defining, via the host coupled to the data storage device, the first partition of the data storage device to include a third subset of the plurality of memory chips,
wherein the third subset is different from the first subset, and
wherein the third subset does not include any memory chips of the second subset.
9. The method of claim 8 , further comprising:
receiving an indication that one of the memory chips in the first subset has failed or is approaching failure,
wherein re-defining the first partition includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.
10. An apparatus comprising:
a data storage device including a plurality of memory chips, a first portion of the plurality of memory chips being implemented in a first memory channel and a second portion of the plurality of memory chips being implemented in a second memory channel;
an interface operably coupled with the data storage device; and
a host operably coupled with the data storage device via the interface, the host including:
a configuration detection engine configured to communicate with the data storage device, via the interface, to detect a number of the plurality of memory chips in the data storage device; and
a partition engine configured to define a first partition of the data storage device, the first partition including a first subset of the plurality of memory chips and to define a second partition of the data storage device, the second partition including a second subset of the plurality of memory chips,
the first subset including one or more memory chips of the first memory channel and one or more memory chips of the second memory channel;
the first subset not including any memory chips of the second subset; and
a boundary between the first partition and second partition being defined by the first subset of memory chips and the second subset of memory chips.
11. The apparatus of claim 10 , wherein:
the host is configured to transmit, via the interface, an information request command to the data storage device; and
the data storage device is configured to transmit, via the interface upon receiving the information request command, information indicating the number of the plurality of memory chips in the data storage device.
12. The apparatus of claim 10 , wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips.
13. The apparatus of claim 10 , wherein:
the data storage device includes a plurality of channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips,
the configuration detection engine is further configured to detect a number of the plurality of channels in the data storage device,
the partition engine is further configured to define a first subset of the channels, channels of the first subset of the channels being operably connected only to memory chips of the first subset of memory chips, and
the partition engine is further configured to define a second subset of the channels, channels of the second subset of the channels being operably connected only to memory chips of the second subset of memory chips.
14. The apparatus of claim 13 , wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, the assigned memory address specifying that the data be written to a specific one of the plurality of memory chips through a specific channel.
15. The apparatus of claim 13 , wherein the second partition includes memory chips that are operably connected to a single channel.
16. The apparatus of claim 10 , wherein:
the partition engine is further configured to re-define the first partition of the data storage device to include a third subset of the plurality of memory chips,
the third subset is different from the first subset, and
the third subset does not include any memory chips of the second subset.
17. The apparatus of claim 16 , wherein:
the partition engine is further configured to receive an indication, via the interface, that one of the memory chips in the first subset has failed or is approaching failure, and
re-defining the first partition to include the third subset of the plurality of memory chips includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.
18. The apparatus of claim 10 , wherein the interface is a PCIe interface.
19. A method of partitioning a data storage device, wherein the device includes a plurality of memory chips, the method comprising:
reading, by a host via a PCIe interface operably coupling the host with the data storage device, a physical configuration of the data storage device, the physical configuration including a number of the plurality of memory chips in the data storage device, a first portion of the plurality of memory chips being implemented in a first memory channel and a second portion of the plurality of memory chips being implemented in a second memory channel;
reading, but the host via the PCIe interface, a partitioning scheme for the data storage device;
defining, via by the host, a first partition of the data storage device, the first partition including a first subset of the plurality of memory chips;
allocating, by the host, a logical to physical memory map for the first partition;
defining, by the host, a second partition of the data storage device, the second partition including a second subset of the plurality of memory chips; and
allocating, by the host, a logical to physical memory map for the second partition,
the first subset including one or more memory chips of the first memory channel and one or more memory chips of the second memory channel;
the first subset not including any memory chips of the second subset; and
a boundary between the first partition and second partition is defined by the first subset of memory chips and the second subset of memory chips.
20. The method of claim 19 , further comprising:
transmitting, via the PCIe interface, first data from the host to the data storage device; and
by the data storage device, writing the first data to the first partition while reading second data from the second partition.
21. The method of claim 19 , wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, wherein the physical configuration of the data storage device further includes the number of the plurality of memory chips in the data storage device, the method further comprising:
determining a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips;
determining a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips; and
defining, by the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/089,397 US20140156915A1 (en) | 2009-04-08 | 2013-11-25 | Partitioning a flash memory data storage device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16770909P | 2009-04-08 | 2009-04-08 | |
US18783509P | 2009-06-17 | 2009-06-17 | |
US12/537,741 US8639871B2 (en) | 2009-04-08 | 2009-08-07 | Partitioning a flash memory data storage device |
US14/089,397 US20140156915A1 (en) | 2009-04-08 | 2013-11-25 | Partitioning a flash memory data storage device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/537,741 Continuation US8639871B2 (en) | 2009-04-08 | 2009-08-07 | Partitioning a flash memory data storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20140156915A1 true US20140156915A1 (en) | 2014-06-05 |
Family
ID=42935237
Family Applications (13)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/537,719 Active 2031-04-08 US8578084B2 (en) | 2009-04-08 | 2009-08-07 | Data storage device having multiple removable memory boards |
US12/537,727 Active 2029-08-28 US8250271B2 (en) | 2009-04-08 | 2009-08-07 | Command and interrupt grouping for a data storage device |
US12/537,733 Active 2031-03-15 US8380909B2 (en) | 2009-04-08 | 2009-08-07 | Multiple command queues having separate interrupts |
US12/537,725 Active 2030-10-05 US8239724B2 (en) | 2009-04-08 | 2009-08-07 | Error correction for a data storage device |
US12/537,741 Active 2031-03-02 US8639871B2 (en) | 2009-04-08 | 2009-08-07 | Partitioning a flash memory data storage device |
US12/537,709 Active 2030-10-19 US8205037B2 (en) | 2009-04-08 | 2009-08-07 | Data storage device capable of recognizing and controlling multiple types of memory chips operating at different voltages |
US12/537,704 Active 2031-03-25 US8566507B2 (en) | 2009-04-08 | 2009-08-07 | Data storage device capable of recognizing and controlling multiple types of memory chips |
US12/537,748 Active 2030-12-26 US8566508B2 (en) | 2009-04-08 | 2009-08-07 | RAID configuration in a flash memory data storage device |
US12/537,738 Abandoned US20100262773A1 (en) | 2009-04-08 | 2009-08-07 | Data striping in a flash memory data storage device |
US12/537,722 Active 2030-08-27 US8244962B2 (en) | 2009-04-08 | 2009-08-07 | Command processor for a data storage device |
US14/057,703 Abandoned US20140108708A1 (en) | 2009-04-08 | 2013-10-18 | Raid configuration in a flash memory data storage device |
US14/059,061 Abandoned US20140047172A1 (en) | 2009-04-08 | 2013-10-21 | Data storage device |
US14/089,397 Abandoned US20140156915A1 (en) | 2009-04-08 | 2013-11-25 | Partitioning a flash memory data storage device |
Family Applications Before (12)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/537,719 Active 2031-04-08 US8578084B2 (en) | 2009-04-08 | 2009-08-07 | Data storage device having multiple removable memory boards |
US12/537,727 Active 2029-08-28 US8250271B2 (en) | 2009-04-08 | 2009-08-07 | Command and interrupt grouping for a data storage device |
US12/537,733 Active 2031-03-15 US8380909B2 (en) | 2009-04-08 | 2009-08-07 | Multiple command queues having separate interrupts |
US12/537,725 Active 2030-10-05 US8239724B2 (en) | 2009-04-08 | 2009-08-07 | Error correction for a data storage device |
US12/537,741 Active 2031-03-02 US8639871B2 (en) | 2009-04-08 | 2009-08-07 | Partitioning a flash memory data storage device |
US12/537,709 Active 2030-10-19 US8205037B2 (en) | 2009-04-08 | 2009-08-07 | Data storage device capable of recognizing and controlling multiple types of memory chips operating at different voltages |
US12/537,704 Active 2031-03-25 US8566507B2 (en) | 2009-04-08 | 2009-08-07 | Data storage device capable of recognizing and controlling multiple types of memory chips |
US12/537,748 Active 2030-12-26 US8566508B2 (en) | 2009-04-08 | 2009-08-07 | RAID configuration in a flash memory data storage device |
US12/537,738 Abandoned US20100262773A1 (en) | 2009-04-08 | 2009-08-07 | Data striping in a flash memory data storage device |
US12/537,722 Active 2030-08-27 US8244962B2 (en) | 2009-04-08 | 2009-08-07 | Command processor for a data storage device |
US14/057,703 Abandoned US20140108708A1 (en) | 2009-04-08 | 2013-10-18 | Raid configuration in a flash memory data storage device |
US14/059,061 Abandoned US20140047172A1 (en) | 2009-04-08 | 2013-10-21 | Data storage device |
Country Status (7)
Country | Link |
---|---|
US (13) | US8578084B2 (en) |
EP (6) | EP2417531B1 (en) |
JP (6) | JP5657641B2 (en) |
CN (6) | CN102428454A (en) |
AU (5) | AU2010234773B2 (en) |
DE (6) | DE202010017661U1 (en) |
WO (5) | WO2010117877A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9244842B2 (en) | 2009-04-08 | 2016-01-26 | Google Inc. | Data storage device with copy command |
US10210298B2 (en) | 2015-11-24 | 2019-02-19 | Altera Corporation | Embedded memory blocks with adjustable memory boundaries |
CN109933291A (en) * | 2019-03-20 | 2019-06-25 | 浪潮商用机器有限公司 | A kind of processing method of SRAM data, device, equipment and storage medium |
US20230266897A1 (en) * | 2022-02-24 | 2023-08-24 | Micron Technology, Inc. | Dynamic zone group configuration at a memory sub-system |
Families Citing this family (321)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8296337B2 (en) | 2006-12-06 | 2012-10-23 | Fusion-Io, Inc. | Apparatus, system, and method for managing data from a requesting device with an empty data token directive |
US8935302B2 (en) | 2006-12-06 | 2015-01-13 | Intelligent Intellectual Property Holdings 2 Llc | Apparatus, system, and method for data block usage information synchronization for a non-volatile storage volume |
US8719501B2 (en) | 2009-09-08 | 2014-05-06 | Fusion-Io | Apparatus, system, and method for caching data on a solid-state storage device |
US8489817B2 (en) | 2007-12-06 | 2013-07-16 | Fusion-Io, Inc. | Apparatus, system, and method for caching data |
US7975109B2 (en) | 2007-05-30 | 2011-07-05 | Schooner Information Technology, Inc. | System including a fine-grained memory and a less-fine-grained memory |
US9519540B2 (en) | 2007-12-06 | 2016-12-13 | Sandisk Technologies Llc | Apparatus, system, and method for destaging cached data |
US7836226B2 (en) | 2007-12-06 | 2010-11-16 | Fusion-Io, Inc. | Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment |
US8732386B2 (en) * | 2008-03-20 | 2014-05-20 | Sandisk Enterprise IP LLC. | Sharing data fabric for coherent-distributed caching of multi-node shared-distributed flash memory |
US8229945B2 (en) | 2008-03-20 | 2012-07-24 | Schooner Information Technology, Inc. | Scalable database management software on a cluster of nodes using a shared-distributed flash memory |
JP2010015195A (en) * | 2008-06-30 | 2010-01-21 | Toshiba Corp | Storage controller and storage control method |
WO2010005430A1 (en) * | 2008-07-08 | 2010-01-14 | Hewlett-Packard Development Company, L.P. | Adaptable external drive |
TWI385672B (en) * | 2008-11-05 | 2013-02-11 | Lite On It Corp | Adaptive multi-channel controller and method for storage device |
TWI385517B (en) * | 2008-12-05 | 2013-02-11 | Apacer Technology Inc | Storage device and data management method |
US20100287217A1 (en) * | 2009-04-08 | 2010-11-11 | Google Inc. | Host control of background garbage collection in a data storage device |
US8578084B2 (en) | 2009-04-08 | 2013-11-05 | Google Inc. | Data storage device having multiple removable memory boards |
KR101516580B1 (en) | 2009-04-22 | 2015-05-11 | 삼성전자주식회사 | Controller, data storage device and data storage system having the same, and method thereof |
EP2254280A1 (en) | 2009-05-19 | 2010-11-24 | Electrolux Home Products Corporation N.V. | Bus control for a domestic appliance |
US8972627B2 (en) | 2009-09-09 | 2015-03-03 | Fusion-Io, Inc. | Apparatus, system, and method for managing operations for data storage media |
US9223514B2 (en) | 2009-09-09 | 2015-12-29 | SanDisk Technologies, Inc. | Erase suspend/resume for memory |
US9021158B2 (en) | 2009-09-09 | 2015-04-28 | SanDisk Technologies, Inc. | Program suspend/resume for memory |
JP5518197B2 (en) | 2009-09-09 | 2014-06-11 | フュージョン−アイオー・インコーポレーテッド | Apparatus, system, and method for allocating storage |
EP2476039B1 (en) | 2009-09-09 | 2016-10-26 | SanDisk Technologies LLC | Apparatus, system, and method for power reduction management in a storage device |
US9122579B2 (en) | 2010-01-06 | 2015-09-01 | Intelligent Intellectual Property Holdings 2 Llc | Apparatus, system, and method for a storage layer |
TWI454906B (en) * | 2009-09-24 | 2014-10-01 | Phison Electronics Corp | Data read method, and flash memory controller and storage system using the same |
US8244946B2 (en) * | 2009-10-16 | 2012-08-14 | Brocade Communications Systems, Inc. | Interrupt moderation |
US8307151B1 (en) * | 2009-11-30 | 2012-11-06 | Micron Technology, Inc. | Multi-partitioning feature on e-MMC |
US8285946B2 (en) * | 2009-12-15 | 2012-10-09 | International Business Machines Corporation | Reducing access contention in flash-based memory systems |
KR101008923B1 (en) * | 2010-01-15 | 2011-01-17 | 주식회사 노바칩스 | Semiconductor memory system including memory devices of various types and controlling method thereof |
US8671265B2 (en) | 2010-03-05 | 2014-03-11 | Solidfire, Inc. | Distributed data storage system providing de-duplication of data using block identifiers |
US8725931B1 (en) | 2010-03-26 | 2014-05-13 | Western Digital Technologies, Inc. | System and method for managing the execution of memory commands in a solid-state memory |
US10210162B1 (en) * | 2010-03-29 | 2019-02-19 | Carbonite, Inc. | Log file management |
US8856593B2 (en) | 2010-04-12 | 2014-10-07 | Sandisk Enterprise Ip Llc | Failure recovery using consensus replication in a distributed flash memory system |
US9164554B2 (en) * | 2010-04-12 | 2015-10-20 | Sandisk Enterprise Ip Llc | Non-volatile solid-state storage system supporting high bandwidth and random access |
US8677055B2 (en) | 2010-04-12 | 2014-03-18 | Sandisk Enterprises IP LLC | Flexible way of specifying storage attributes in a flash memory-based object store |
US9047351B2 (en) | 2010-04-12 | 2015-06-02 | Sandisk Enterprise Ip Llc | Cluster of processing nodes with distributed global flash memory using commodity server technology |
US8868487B2 (en) | 2010-04-12 | 2014-10-21 | Sandisk Enterprise Ip Llc | Event processing in a flash memory-based object store |
US20110252263A1 (en) * | 2010-04-13 | 2011-10-13 | Byungcheol Cho | Semiconductor storage device |
US8782327B1 (en) | 2010-05-11 | 2014-07-15 | Western Digital Technologies, Inc. | System and method for managing execution of internal commands and host commands in a solid-state memory |
US9026716B2 (en) | 2010-05-12 | 2015-05-05 | Western Digital Technologies, Inc. | System and method for managing garbage collection in solid-state memory |
WO2011143628A2 (en) | 2010-05-13 | 2011-11-17 | Fusion-Io, Inc. | Apparatus, system, and method for conditional and atomic storage operations |
US8954385B2 (en) | 2010-06-28 | 2015-02-10 | Sandisk Enterprise Ip Llc | Efficient recovery of transactional data stores |
WO2012016089A2 (en) | 2010-07-28 | 2012-02-02 | Fusion-Io, Inc. | Apparatus, system, and method for conditional and atomic storage operations |
US8725934B2 (en) | 2011-12-22 | 2014-05-13 | Fusion-Io, Inc. | Methods and appratuses for atomic storage operations |
US8677028B2 (en) * | 2010-08-23 | 2014-03-18 | Qualcomm Incorporated | Interrupt-based command processing |
US8417877B2 (en) * | 2010-08-31 | 2013-04-09 | Micron Technology, Inc | Stripe-based non-volatile multilevel memory operation |
US8984216B2 (en) | 2010-09-09 | 2015-03-17 | Fusion-Io, Llc | Apparatus, system, and method for managing lifetime of a storage device |
US9021192B1 (en) | 2010-09-21 | 2015-04-28 | Western Digital Technologies, Inc. | System and method for enhancing processing of memory access requests |
US9164886B1 (en) | 2010-09-21 | 2015-10-20 | Western Digital Technologies, Inc. | System and method for multistage processing in a memory storage subsystem |
US20120117305A1 (en) * | 2010-11-08 | 2012-05-10 | Greenliant Llc | Method Of Storing Blocks Of Data In A Plurality Of Memory Devices For High Speed Sequential Read, A Memory Controller And A Memory System |
US9003153B2 (en) | 2010-11-08 | 2015-04-07 | Greenliant Llc | Method of storing blocks of data in a plurality of memory devices in a redundant manner, a memory controller and a memory system |
JP5720204B2 (en) * | 2010-11-26 | 2015-05-20 | 富士通株式会社 | Access control program, access control method, and information processing apparatus |
US9246512B2 (en) * | 2010-12-02 | 2016-01-26 | Freescale Semiconductor, Inc. | Error correcting device, method for monitoring an error correcting device and data processing system |
US10817421B2 (en) | 2010-12-13 | 2020-10-27 | Sandisk Technologies Llc | Persistent data structures |
US9047178B2 (en) | 2010-12-13 | 2015-06-02 | SanDisk Technologies, Inc. | Auto-commit memory synchronization |
US9208071B2 (en) | 2010-12-13 | 2015-12-08 | SanDisk Technologies, Inc. | Apparatus, system, and method for accessing memory |
US10817502B2 (en) | 2010-12-13 | 2020-10-27 | Sandisk Technologies Llc | Persistent memory management |
US9218278B2 (en) | 2010-12-13 | 2015-12-22 | SanDisk Technologies, Inc. | Auto-commit memory |
WO2012082792A2 (en) | 2010-12-13 | 2012-06-21 | Fusion-Io, Inc. | Apparatus, system, and method for auto-commit memory |
US8601313B1 (en) | 2010-12-13 | 2013-12-03 | Western Digital Technologies, Inc. | System and method for a data reliability scheme in a solid state memory |
US8615681B2 (en) | 2010-12-14 | 2013-12-24 | Western Digital Technologies, Inc. | System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss |
US8601311B2 (en) | 2010-12-14 | 2013-12-03 | Western Digital Technologies, Inc. | System and method for using over-provisioned data capacity to maintain a data redundancy scheme in a solid state memory |
US20120239860A1 (en) | 2010-12-17 | 2012-09-20 | Fusion-Io, Inc. | Apparatus, system, and method for persistent data management on a non-volatile storage media |
US8473708B1 (en) * | 2010-12-23 | 2013-06-25 | Netapp, Inc. | Method and system for managing storage units |
US8694733B2 (en) | 2011-01-03 | 2014-04-08 | Sandisk Enterprise Ip Llc | Slave consistency in a synchronous replication environment |
US8700950B1 (en) | 2011-02-11 | 2014-04-15 | Western Digital Technologies, Inc. | System and method for data error recovery in a solid state subsystem |
US8874823B2 (en) | 2011-02-15 | 2014-10-28 | Intellectual Property Holdings 2 Llc | Systems and methods for managing data input/output operations |
US9201677B2 (en) | 2011-05-23 | 2015-12-01 | Intelligent Intellectual Property Holdings 2 Llc | Managing data input/output operations |
US9003104B2 (en) | 2011-02-15 | 2015-04-07 | Intelligent Intellectual Property Holdings 2 Llc | Systems and methods for a file-level cache |
US9141527B2 (en) | 2011-02-25 | 2015-09-22 | Intelligent Intellectual Property Holdings 2 Llc | Managing cache pools |
US8700951B1 (en) * | 2011-03-09 | 2014-04-15 | Western Digital Technologies, Inc. | System and method for improving a data redundancy scheme in a solid state subsystem with additional metadata |
WO2012129191A2 (en) | 2011-03-18 | 2012-09-27 | Fusion-Io, Inc. | Logical interfaces for contextual storage |
US9563555B2 (en) | 2011-03-18 | 2017-02-07 | Sandisk Technologies Llc | Systems and methods for storage allocation |
US8601085B1 (en) * | 2011-03-28 | 2013-12-03 | Emc Corporation | Techniques for preferred path determination |
US8924627B2 (en) * | 2011-03-28 | 2014-12-30 | Western Digital Technologies, Inc. | Flash memory device comprising host interface for processing a multi-command descriptor block in order to exploit concurrency |
US8874515B2 (en) | 2011-04-11 | 2014-10-28 | Sandisk Enterprise Ip Llc | Low level object version tracking using non-volatile memory write generations |
US8694857B2 (en) * | 2011-04-13 | 2014-04-08 | Inphi Corporation | Systems and methods for error detection and correction in a memory module which includes a memory buffer |
US8954670B1 (en) * | 2011-04-18 | 2015-02-10 | American Megatrends, Inc. | Systems and methods for improved fault tolerance in RAID configurations |
US9817700B2 (en) * | 2011-04-26 | 2017-11-14 | International Business Machines Corporation | Dynamic data partitioning for optimal resource utilization in a parallel data processing system |
US9396106B2 (en) * | 2011-05-12 | 2016-07-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Advanced management of a non-volatile memory |
US20120324143A1 (en) | 2011-06-15 | 2012-12-20 | Data Design Corporation | Methods and apparatus for data access by a reprogrammable circuit module |
US9417894B1 (en) | 2011-06-15 | 2016-08-16 | Ryft Systems, Inc. | Methods and apparatus for a tablet computer system incorporating a reprogrammable circuit module |
US10966339B1 (en) | 2011-06-28 | 2021-03-30 | Amazon Technologies, Inc. | Storage system with removable solid state storage devices mounted on carrier circuit boards |
US8806112B2 (en) | 2011-07-14 | 2014-08-12 | Lsi Corporation | Meta data handling within a flash media controller |
US20130019052A1 (en) * | 2011-07-14 | 2013-01-17 | Vinay Ashok Somanache | Effective utilization of flash interface |
US8868867B2 (en) * | 2011-09-15 | 2014-10-21 | The Regents Of The University Of California | Method for reducing latency of accessing data stored in a file system on a computer storage device by caching file system permission information in the computer storage device |
US8966172B2 (en) | 2011-11-15 | 2015-02-24 | Pavilion Data Systems, Inc. | Processor agnostic data storage in a PCIE based shared storage enviroment |
US8719647B2 (en) * | 2011-12-15 | 2014-05-06 | Micron Technology, Inc. | Read bias management to reduce read errors for phase change memory |
US8842122B2 (en) * | 2011-12-15 | 2014-09-23 | Qualcomm Incorporated | Graphics processing unit with command processor |
US9274937B2 (en) | 2011-12-22 | 2016-03-01 | Longitude Enterprise Flash S.A.R.L. | Systems, methods, and interfaces for vector input/output operations |
US8904091B1 (en) * | 2011-12-22 | 2014-12-02 | Western Digital Technologies, Inc. | High performance media transport manager architecture for data storage systems |
CN102521160B (en) * | 2011-12-22 | 2015-04-01 | 上海交通大学 | Write buffer detector and parallel channel write method |
CN102567257B (en) * | 2011-12-26 | 2014-08-27 | 华中科技大学 | Method for controlling data reading and writing of multi-channel solid-state disc |
US9838269B2 (en) | 2011-12-27 | 2017-12-05 | Netapp, Inc. | Proportional quality of service based on client usage and system metrics |
US9054992B2 (en) | 2011-12-27 | 2015-06-09 | Solidfire, Inc. | Quality of service policy sets |
US9251086B2 (en) | 2012-01-24 | 2016-02-02 | SanDisk Technologies, Inc. | Apparatus, system, and method for managing a cache |
US9116812B2 (en) | 2012-01-27 | 2015-08-25 | Intelligent Intellectual Property Holdings 2 Llc | Systems and methods for a de-duplication cache |
US10359972B2 (en) | 2012-08-31 | 2019-07-23 | Sandisk Technologies Llc | Systems, methods, and interfaces for adaptive persistence |
US9652182B2 (en) | 2012-01-31 | 2017-05-16 | Pavilion Data Systems, Inc. | Shareable virtual non-volatile storage device for a server |
US9378150B2 (en) * | 2012-02-28 | 2016-06-28 | Apple Inc. | Memory management unit with prefetch ability |
US9135064B2 (en) | 2012-03-07 | 2015-09-15 | Sandisk Enterprise Ip Llc | Fine grained adaptive throttling of background processes |
US9135192B2 (en) | 2012-03-30 | 2015-09-15 | Sandisk Technologies Inc. | Memory system with command queue reordering |
KR20130114354A (en) | 2012-04-09 | 2013-10-18 | 삼성전자주식회사 | Memory system and operating method of controller |
US20130339583A1 (en) * | 2012-06-19 | 2013-12-19 | Marvell World Trade Ltd. | Systems and methods for transferring data out of order in next generation solid state drive controllers |
US10339056B2 (en) | 2012-07-03 | 2019-07-02 | Sandisk Technologies Llc | Systems, methods and apparatus for cache transfers |
US9612966B2 (en) | 2012-07-03 | 2017-04-04 | Sandisk Technologies Llc | Systems, methods and apparatus for a virtual machine cache |
US9389999B2 (en) * | 2012-08-17 | 2016-07-12 | Infineon Technologies Ag | System and method for emulating an EEPROM in a non-volatile memory device |
US9122401B2 (en) * | 2012-08-23 | 2015-09-01 | Apple Inc. | Efficient enforcement of command execution order in solid state drives |
KR20140027859A (en) | 2012-08-27 | 2014-03-07 | 삼성전자주식회사 | Host device and system including the same |
US9009566B2 (en) * | 2012-09-12 | 2015-04-14 | Macronix International Co., Ltd. | Outputting information of ECC corrected bits |
US9471484B2 (en) | 2012-09-19 | 2016-10-18 | Novachips Canada Inc. | Flash memory controller having dual mode pin-out |
US10318495B2 (en) | 2012-09-24 | 2019-06-11 | Sandisk Technologies Llc | Snapshots for a non-volatile device |
US10509776B2 (en) | 2012-09-24 | 2019-12-17 | Sandisk Technologies Llc | Time sequence data management |
US9582465B2 (en) * | 2012-11-15 | 2017-02-28 | Elwha Llc | Flexible processors and flexible memory |
US9442854B2 (en) | 2012-11-15 | 2016-09-13 | Elwha Llc | Memory circuitry including computational circuitry for performing supplemental functions |
US8925098B2 (en) | 2012-11-15 | 2014-12-30 | Elwha Llc | Data security and access tracking in memory |
US8966310B2 (en) | 2012-11-15 | 2015-02-24 | Elwha Llc | Redundancy for loss-tolerant data in non-volatile memory |
US9026719B2 (en) | 2012-11-15 | 2015-05-05 | Elwha, Llc | Intelligent monitoring for computation in memory |
US8996951B2 (en) | 2012-11-15 | 2015-03-31 | Elwha, Llc | Error correction with non-volatile memory on an integrated circuit |
US9323499B2 (en) | 2012-11-15 | 2016-04-26 | Elwha Llc | Random number generator functions in memory |
CN103853629A (en) * | 2012-11-29 | 2014-06-11 | 艺伦半导体技术股份有限公司 | Data stream memorizing method and field programmable gate array |
US9448883B1 (en) * | 2012-12-04 | 2016-09-20 | Cadence Design Systems, Inc. | System and method for allocating data in memory array having regions of varying storage reliability |
US9069658B2 (en) | 2012-12-10 | 2015-06-30 | Google Inc. | Using a virtual to physical map for direct user space communication with a data storage device |
US9164888B2 (en) * | 2012-12-10 | 2015-10-20 | Google Inc. | Using a logical to physical map for direct user space communication with a data storage device |
US9236136B2 (en) | 2012-12-14 | 2016-01-12 | Intel Corporation | Lower page read for multi-level cell memory |
US9286002B1 (en) * | 2012-12-28 | 2016-03-15 | Virident Systems Inc. | Dynamic restriping in nonvolatile memory systems |
US9842660B1 (en) | 2012-12-28 | 2017-12-12 | Virident Systems, Llc | System and method to improve enterprise reliability through tracking I/O performance metrics in non-volatile random access memory |
US9980114B2 (en) | 2013-03-15 | 2018-05-22 | Elwha Llc | Systems and methods for communication management |
US9635605B2 (en) | 2013-03-15 | 2017-04-25 | Elwha Llc | Protocols for facilitating broader access in wireless communications |
US9451394B2 (en) | 2012-12-31 | 2016-09-20 | Elwha Llc | Cost-effective mobile connectivity protocols |
US9781664B2 (en) | 2012-12-31 | 2017-10-03 | Elwha Llc | Cost-effective mobile connectivity protocols |
US9876762B2 (en) | 2012-12-31 | 2018-01-23 | Elwha Llc | Cost-effective mobile connectivity protocols |
US9832628B2 (en) | 2012-12-31 | 2017-11-28 | Elwha, Llc | Cost-effective mobile connectivity protocols |
US9713013B2 (en) | 2013-03-15 | 2017-07-18 | Elwha Llc | Protocols for providing wireless communications connectivity maps |
US8965288B2 (en) | 2012-12-31 | 2015-02-24 | Elwha Llc | Cost-effective mobile connectivity protocols |
CN103942219A (en) * | 2013-01-22 | 2014-07-23 | 鸿富锦精密工业(深圳)有限公司 | Storage card partitioning system and method |
US10445229B1 (en) | 2013-01-28 | 2019-10-15 | Radian Memory Systems, Inc. | Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies |
US9652376B2 (en) | 2013-01-28 | 2017-05-16 | Radian Memory Systems, Inc. | Cooperative flash memory control |
US10642505B1 (en) | 2013-01-28 | 2020-05-05 | Radian Memory Systems, Inc. | Techniques for data migration based on per-data metrics and memory degradation |
US11249652B1 (en) | 2013-01-28 | 2022-02-15 | Radian Memory Systems, Inc. | Maintenance of nonvolatile memory on host selected namespaces by a common memory controller |
US9110592B2 (en) * | 2013-02-04 | 2015-08-18 | Microsoft Technology Licensing, Llc | Dynamic allocation of heterogenous memory in a computing system |
WO2014128967A1 (en) * | 2013-02-25 | 2014-08-28 | 株式会社日立製作所 | Storage control device and data write completion sensing method |
US9842053B2 (en) | 2013-03-15 | 2017-12-12 | Sandisk Technologies Llc | Systems and methods for persistent cache logging |
US9807582B2 (en) | 2013-03-15 | 2017-10-31 | Elwha Llc | Protocols for facilitating broader access in wireless communications |
US9781554B2 (en) | 2013-03-15 | 2017-10-03 | Elwha Llc | Protocols for facilitating third party authorization for a rooted communication device in wireless communications |
US9596584B2 (en) | 2013-03-15 | 2017-03-14 | Elwha Llc | Protocols for facilitating broader access in wireless communications by conditionally authorizing a charge to an account of a third party |
US10073626B2 (en) | 2013-03-15 | 2018-09-11 | Virident Systems, Llc | Managing the write performance of an asymmetric memory system |
US9866706B2 (en) | 2013-03-15 | 2018-01-09 | Elwha Llc | Protocols for facilitating broader access in wireless communications |
US9706060B2 (en) | 2013-03-15 | 2017-07-11 | Elwha Llc | Protocols for facilitating broader access in wireless communications |
US9706382B2 (en) | 2013-03-15 | 2017-07-11 | Elwha Llc | Protocols for allocating communication services cost in wireless communications |
US9813887B2 (en) | 2013-03-15 | 2017-11-07 | Elwha Llc | Protocols for facilitating broader access in wireless communications responsive to charge authorization statuses |
US9843917B2 (en) | 2013-03-15 | 2017-12-12 | Elwha, Llc | Protocols for facilitating charge-authorized connectivity in wireless communications |
US9135164B2 (en) | 2013-03-15 | 2015-09-15 | Virident Systems Inc. | Synchronous mirroring in non-volatile memory systems |
US9693214B2 (en) | 2013-03-15 | 2017-06-27 | Elwha Llc | Protocols for facilitating broader access in wireless communications |
US8996796B1 (en) | 2013-03-15 | 2015-03-31 | Virident Systems Inc. | Small block write operations in non-volatile memory systems |
CN103226976A (en) * | 2013-03-19 | 2013-07-31 | 中国科学院声学研究所 | Apparatus for realizing multi-chip Nandflash storage and read based on FPGA |
CN104102599A (en) * | 2013-04-11 | 2014-10-15 | 华邦电子股份有限公司 | Flash memory device and data transmission method |
US10558561B2 (en) | 2013-04-16 | 2020-02-11 | Sandisk Technologies Llc | Systems and methods for storage metadata management |
US10102144B2 (en) | 2013-04-16 | 2018-10-16 | Sandisk Technologies Llc | Systems, methods and interfaces for data virtualization |
US9842128B2 (en) | 2013-08-01 | 2017-12-12 | Sandisk Technologies Llc | Systems and methods for atomic storage operations |
US20150058529A1 (en) * | 2013-08-21 | 2015-02-26 | Sandisk Technologies Inc. | Systems and methods of processing access requests at a data storage device |
TWI486775B (en) * | 2013-09-18 | 2015-06-01 | Dexin Corp | Input device and data transmission method thereof |
US9513869B2 (en) | 2013-09-18 | 2016-12-06 | HGST Netherlands B.V. | Doorbell-less endpoint-initiated protocol for storage devices |
US9535870B2 (en) | 2013-09-18 | 2017-01-03 | HGST Netherlands B.V. | Acknowledgement-less protocol for solid state drive interface |
US9778859B2 (en) | 2013-09-18 | 2017-10-03 | Western Digital Technologies, Inc. | Doorless protocol having multiple queue read requests in flight |
WO2015047266A1 (en) * | 2013-09-26 | 2015-04-02 | Intel Corporation | Block storage apertures to persistent memory |
US10019320B2 (en) | 2013-10-18 | 2018-07-10 | Sandisk Technologies Llc | Systems and methods for distributed atomic storage operations |
US10073630B2 (en) | 2013-11-08 | 2018-09-11 | Sandisk Technologies Llc | Systems and methods for log coordination |
CN103559156B (en) * | 2013-11-11 | 2016-04-06 | 北京大学 | Communication system between a kind of FPGA and computing machine |
US9529710B1 (en) * | 2013-12-06 | 2016-12-27 | Western Digital Technologies, Inc. | Interleaved channels in a solid-state drive |
CN103744744B (en) * | 2014-02-08 | 2017-08-25 | 威盛电子股份有限公司 | The data verification method of data memory device and volatile memory |
US20150244795A1 (en) | 2014-02-21 | 2015-08-27 | Solidfire, Inc. | Data syncing in a distributed system |
US9666244B2 (en) | 2014-03-01 | 2017-05-30 | Fusion-Io, Inc. | Dividing a storage procedure |
US9423979B2 (en) | 2014-03-10 | 2016-08-23 | Kabushiki Kaisha Toshiba | Memory system and memory controller for determining whether one or plurality of pointers can be stored in a second buffer and for executing data transfer between data buffer and host using the pointers |
US9337869B2 (en) * | 2014-04-30 | 2016-05-10 | Storart Technology Co. Ltd. | Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same |
JP6227767B2 (en) * | 2014-05-12 | 2017-11-08 | 株式会社日立製作所 | Information processing apparatus, processing method thereof, and input / output apparatus |
KR102211709B1 (en) | 2014-05-19 | 2021-02-02 | 삼성전자주식회사 | Non-volatile Memory System and Host Device improving a signal characteristic and Operating Method of thereof |
US9460019B2 (en) | 2014-06-26 | 2016-10-04 | Intel Corporation | Sending packets using optimized PIO write sequences without SFENCEs |
US9477631B2 (en) | 2014-06-26 | 2016-10-25 | Intel Corporation | Optimized credit return mechanism for packet sends |
JP2016014972A (en) * | 2014-07-01 | 2016-01-28 | 富士通株式会社 | Communication control device, storage device, and communication control program |
US10146482B2 (en) | 2014-08-01 | 2018-12-04 | Toshiba Memory Corporation | Global error recovery system |
US9542118B1 (en) | 2014-09-09 | 2017-01-10 | Radian Memory Systems, Inc. | Expositive flash memory control |
US10552085B1 (en) | 2014-09-09 | 2020-02-04 | Radian Memory Systems, Inc. | Techniques for directed data migration |
JP2016057876A (en) * | 2014-09-10 | 2016-04-21 | 富士通株式会社 | Information processing apparatus, input/output control program, and input/output control method |
US9582201B2 (en) | 2014-09-26 | 2017-02-28 | Western Digital Technologies, Inc. | Multi-tier scheme for logical storage management |
TWI556254B (en) * | 2014-10-14 | 2016-11-01 | 慧榮科技股份有限公司 | Data storage device and data accessing method thereof |
US9632702B2 (en) | 2014-10-15 | 2017-04-25 | International Business Machines Corporation | Efficient initialization of a thinly provisioned storage array |
KR20160051367A (en) * | 2014-11-03 | 2016-05-11 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
US9565269B2 (en) | 2014-11-04 | 2017-02-07 | Pavilion Data Systems, Inc. | Non-volatile memory express over ethernet |
US9712619B2 (en) | 2014-11-04 | 2017-07-18 | Pavilion Data Systems, Inc. | Virtual non-volatile memory express drive |
KR101620260B1 (en) * | 2015-01-12 | 2016-05-12 | 엘지전자 주식회사 | Network system and a method controlling the same |
US9933950B2 (en) | 2015-01-16 | 2018-04-03 | Sandisk Technologies Llc | Storage operation interrupt |
US10175885B2 (en) | 2015-01-19 | 2019-01-08 | Toshiba Memory Corporation | Memory device managing data in accordance with command and non-transitory computer readable recording medium |
CN105808444B (en) * | 2015-01-19 | 2019-01-01 | 东芝存储器株式会社 | The control method of storage device and nonvolatile memory |
WO2016122602A1 (en) * | 2015-01-30 | 2016-08-04 | Hewlett Packard Enterprise Development Lp | Systems and methods for sharing non-volatile memory between multiple access models |
US9946607B2 (en) | 2015-03-04 | 2018-04-17 | Sandisk Technologies Llc | Systems and methods for storage error management |
KR102364381B1 (en) * | 2015-03-06 | 2022-02-18 | 에스케이하이닉스 주식회사 | Memory system and operation method for the same |
KR102309798B1 (en) * | 2015-04-16 | 2021-10-06 | 삼성전자주식회사 | SR-IOV based non volatile memory controller and method for dynamically allocating resources to queues by the non volatile memory controller |
CN104811235B (en) * | 2015-05-13 | 2018-07-06 | 朱洋 | The helicopter telecommunication domain interactive device of double frameworks |
JP6205386B2 (en) * | 2015-05-18 | 2017-09-27 | 長瀬産業株式会社 | Semiconductor device and information writing / reading method |
US10169258B2 (en) | 2015-06-09 | 2019-01-01 | Rambus Inc. | Memory system design using buffer(s) on a mother board |
US9547441B1 (en) * | 2015-06-23 | 2017-01-17 | Pure Storage, Inc. | Exposing a geometry of a storage device |
US10552058B1 (en) | 2015-07-17 | 2020-02-04 | Radian Memory Systems, Inc. | Techniques for delegating data processing to a cooperative memory controller |
CN108292279A (en) * | 2015-08-24 | 2018-07-17 | Src实验室有限责任公司 | When with reprograming reconfigurable device comprising the DRAM storage controls with memory module or the juxtaposed data dimension protecting block of subsystem, retain the system and method for DRAM data |
US9578054B1 (en) | 2015-08-31 | 2017-02-21 | Newman H-R Computer Design, LLC | Hacking-resistant computer design |
US10073652B2 (en) * | 2015-09-24 | 2018-09-11 | International Business Machines Corporation | Performance optimized storage vaults in a dispersed storage network |
US9697320B2 (en) * | 2015-09-24 | 2017-07-04 | Qualcomm Incorporated | Rectilinear macros having non-uniform channel spacing |
US9977623B2 (en) | 2015-10-15 | 2018-05-22 | Sandisk Technologies Llc | Detection of a sequential command stream |
US10467155B2 (en) * | 2015-10-26 | 2019-11-05 | Micron Technology, Inc. | Command packets for the direct control of non-volatile memory channels within a solid state drive |
JP2017084063A (en) * | 2015-10-27 | 2017-05-18 | Tdk株式会社 | Memory controller, flash memory system, and power supply voltage supply control method |
US10282103B1 (en) * | 2015-11-09 | 2019-05-07 | Seagate Technology Llc | Method and apparatus to delete a command queue |
US9996262B1 (en) | 2015-11-09 | 2018-06-12 | Seagate Technology Llc | Method and apparatus to abort a command |
US10572180B1 (en) * | 2015-11-09 | 2020-02-25 | Seagate Technology Llc | Method and apparatus to perform a function level reset in a memory controller |
US9779043B2 (en) | 2015-11-16 | 2017-10-03 | International Business Machines Corporation | Techniques for handling queued interrupts in a data processing system |
KR102446677B1 (en) | 2015-11-26 | 2022-09-23 | 삼성전자주식회사 | Method of operating storage controller and method of operating data storage device having the storage controller |
US10817528B2 (en) * | 2015-12-15 | 2020-10-27 | Futurewei Technologies, Inc. | System and method for data warehouse engine |
CN108475240A (en) * | 2016-01-13 | 2018-08-31 | 慧与发展有限责任合伙企业 | The input/output request of reconstruct |
JP6544246B2 (en) * | 2016-01-15 | 2019-07-17 | 富士通株式会社 | Nonvolatile storage and method of processing nonvolatile storage |
US9946596B2 (en) | 2016-01-29 | 2018-04-17 | Toshiba Memory Corporation | Global error recovery system |
US9817586B2 (en) * | 2016-02-23 | 2017-11-14 | Samsung Electronics Co., Ltd. | Method of application aware IO completion mode changer for key value device |
US10198315B2 (en) | 2016-02-29 | 2019-02-05 | Sandisk Technologies Llc | Non-volatile memory with corruption recovery |
US10192633B2 (en) * | 2016-03-01 | 2019-01-29 | Intel Corporation | Low cost inbuilt deterministic tester for SOC testing |
TWI610171B (en) * | 2016-03-22 | 2018-01-01 | 群聯電子股份有限公司 | Memory management method, memory storage device and memory control circuit unit |
US10191358B2 (en) * | 2016-04-13 | 2019-01-29 | Angela Jorgensen | Moving head projector system |
US10929022B2 (en) | 2016-04-25 | 2021-02-23 | Netapp. Inc. | Space savings reporting for storage system supporting snapshot and clones |
TWI592864B (en) * | 2016-06-21 | 2017-07-21 | 慧榮科技股份有限公司 | Data storage device and data maintenance method thereof |
US20180046409A1 (en) * | 2016-08-10 | 2018-02-15 | International Business Machines Corporation | Mass storage devices packages and software-defined arrays of such packages |
US10445018B2 (en) | 2016-09-09 | 2019-10-15 | Toshiba Memory Corporation | Switch and memory device |
US10642763B2 (en) | 2016-09-20 | 2020-05-05 | Netapp, Inc. | Quality of service policy sets |
US11314753B2 (en) | 2016-09-26 | 2022-04-26 | Splunk Inc. | Execution of a query received from a data intake and query system |
US11243963B2 (en) | 2016-09-26 | 2022-02-08 | Splunk Inc. | Distributing partial results to worker nodes from an external data system |
US10956415B2 (en) | 2016-09-26 | 2021-03-23 | Splunk Inc. | Generating a subquery for an external data system using a configuration file |
US11604795B2 (en) | 2016-09-26 | 2023-03-14 | Splunk Inc. | Distributing partial results from an external data system between worker nodes |
US11106734B1 (en) | 2016-09-26 | 2021-08-31 | Splunk Inc. | Query execution using containerized state-free search nodes in a containerized scalable environment |
US11321321B2 (en) | 2016-09-26 | 2022-05-03 | Splunk Inc. | Record expansion and reduction based on a processing task in a data intake and query system |
US11580107B2 (en) | 2016-09-26 | 2023-02-14 | Splunk Inc. | Bucket data distribution for exporting data to worker nodes |
US11550847B1 (en) | 2016-09-26 | 2023-01-10 | Splunk Inc. | Hashing bucket identifiers to identify search nodes for efficient query execution |
US11860940B1 (en) | 2016-09-26 | 2024-01-02 | Splunk Inc. | Identifying buckets for query execution using a catalog of buckets |
US11663227B2 (en) | 2016-09-26 | 2023-05-30 | Splunk Inc. | Generating a subquery for a distinct data intake and query system |
US11615104B2 (en) | 2016-09-26 | 2023-03-28 | Splunk Inc. | Subquery generation based on a data ingest estimate of an external data system |
US11126632B2 (en) | 2016-09-26 | 2021-09-21 | Splunk Inc. | Subquery generation based on search configuration data from an external data system |
US11461334B2 (en) | 2016-09-26 | 2022-10-04 | Splunk Inc. | Data conditioning for dataset destination |
US11269939B1 (en) | 2016-09-26 | 2022-03-08 | Splunk Inc. | Iterative message-based data processing including streaming analytics |
US11442935B2 (en) | 2016-09-26 | 2022-09-13 | Splunk Inc. | Determining a record generation estimate of a processing task |
US11222066B1 (en) | 2016-09-26 | 2022-01-11 | Splunk Inc. | Processing data using containerized state-free indexing nodes in a containerized scalable environment |
US11232100B2 (en) | 2016-09-26 | 2022-01-25 | Splunk Inc. | Resource allocation for multiple datasets |
US20180089324A1 (en) | 2016-09-26 | 2018-03-29 | Splunk Inc. | Dynamic resource allocation for real-time search |
US11281706B2 (en) | 2016-09-26 | 2022-03-22 | Splunk Inc. | Multi-layer partition allocation for query execution |
US11562023B1 (en) | 2016-09-26 | 2023-01-24 | Splunk Inc. | Merging buckets in a data intake and query system |
US11593377B2 (en) | 2016-09-26 | 2023-02-28 | Splunk Inc. | Assigning processing tasks in a data intake and query system |
US11586627B2 (en) | 2016-09-26 | 2023-02-21 | Splunk Inc. | Partitioning and reducing records at ingest of a worker node |
US11294941B1 (en) | 2016-09-26 | 2022-04-05 | Splunk Inc. | Message-based data ingestion to a data intake and query system |
US11163758B2 (en) | 2016-09-26 | 2021-11-02 | Splunk Inc. | External dataset capability compensation |
US11023463B2 (en) | 2016-09-26 | 2021-06-01 | Splunk Inc. | Converting and modifying a subquery for an external data system |
US11567993B1 (en) | 2016-09-26 | 2023-01-31 | Splunk Inc. | Copying buckets from a remote shared storage system to memory associated with a search node for query execution |
US11874691B1 (en) | 2016-09-26 | 2024-01-16 | Splunk Inc. | Managing efficient query execution including mapping of buckets to search nodes |
US10353965B2 (en) | 2016-09-26 | 2019-07-16 | Splunk Inc. | Data fabric service system architecture |
US11620336B1 (en) | 2016-09-26 | 2023-04-04 | Splunk Inc. | Managing and storing buckets to a remote shared storage system based on a collective bucket size |
US11599541B2 (en) | 2016-09-26 | 2023-03-07 | Splunk Inc. | Determining records generated by a processing task of a query |
US11250056B1 (en) * | 2016-09-26 | 2022-02-15 | Splunk Inc. | Updating a location marker of an ingestion buffer based on storing buckets in a shared storage system |
KR20180064588A (en) * | 2016-12-05 | 2018-06-15 | 에스케이하이닉스 주식회사 | Apparatus and method for controling a memory device |
EP3367251B1 (en) | 2016-12-29 | 2023-06-21 | Huawei Technologies Co., Ltd. | Storage system and solid state hard disk |
CN107102818A (en) * | 2017-03-16 | 2017-08-29 | 山东大学 | A kind of high-speed data processing method based on SD card |
US20180321855A1 (en) * | 2017-05-03 | 2018-11-08 | Samsung Electronics Co., Ltd. | Multistreaming in heterogeneous environments |
US9905294B1 (en) | 2017-05-03 | 2018-02-27 | Seagate Technology Llc | Writing logically offset pages of data to N-level memory cells coupled to a common word line |
CN107256363B (en) * | 2017-06-13 | 2020-03-06 | 杭州华澜微电子股份有限公司 | High-speed encryption and decryption device composed of encryption and decryption module array |
US10606484B2 (en) * | 2017-06-23 | 2020-03-31 | Google Llc | NAND flash storage device with NAND buffer |
US11921672B2 (en) | 2017-07-31 | 2024-03-05 | Splunk Inc. | Query execution at a remote heterogeneous data store of a data fabric service |
EP3657315A4 (en) * | 2017-08-10 | 2020-07-22 | Huawei Technologies Co., Ltd. | Data access method, device and system |
US11609623B2 (en) * | 2017-09-01 | 2023-03-21 | Qualcomm Incorporated | Ultra-low power neuromorphic artificial intelligence computing accelerator |
US10896182B2 (en) | 2017-09-25 | 2021-01-19 | Splunk Inc. | Multi-partitioning determination for combination operations |
TWI685847B (en) * | 2017-10-12 | 2020-02-21 | 慧榮科技股份有限公司 | Namespace planning of non-volatile memory of data storage device |
CN109656833B (en) | 2017-10-12 | 2022-11-11 | 慧荣科技股份有限公司 | Data storage device |
US10908832B2 (en) * | 2017-10-31 | 2021-02-02 | Micron Technology, Inc. | Common pool management |
CN107728953B (en) * | 2017-11-03 | 2021-03-02 | 记忆科技(深圳)有限公司 | Method for improving mixed read-write performance of solid state disk |
CN107943726A (en) * | 2017-11-16 | 2018-04-20 | 郑州云海信息技术有限公司 | A kind of data transmission system and method based on PCIe interface |
DE102018123494A1 (en) | 2017-11-17 | 2019-05-23 | Samsung Electronics Co., Ltd. | MEMORY DEVICE DESIGNED TO UPGRADE A FIELD-PROGRAMMABLE GATE ARRAY, AND OPERATING METHOD THEREFOR |
CN108092730B (en) * | 2017-12-27 | 2019-04-26 | 中国电子科技集团公司第五十四研究所 | A kind of sequential control method suitable for more equipment |
US10628359B2 (en) * | 2018-03-01 | 2020-04-21 | EMC IP Holding Company LLC | Storage management system and method |
KR101936951B1 (en) | 2018-04-11 | 2019-01-11 | 주식회사 맴레이 | Memory controlling device and memory system including the same |
US11334543B1 (en) | 2018-04-30 | 2022-05-17 | Splunk Inc. | Scalable bucket merging for a data intake and query system |
EP3573030B1 (en) * | 2018-05-23 | 2023-10-11 | Diebold Nixdorf Systems GmbH | System and method to control the access on information of a peripheral storage device |
KR102560251B1 (en) | 2018-06-20 | 2023-07-26 | 삼성전자주식회사 | Semiconductor device and semiconductor system |
US10884662B2 (en) | 2018-08-06 | 2021-01-05 | Silicon Motion, Inc. | Method for performing storage control in a storage server, associated memory device and memory controller thereof, and associated storage server |
US11574659B2 (en) * | 2018-09-11 | 2023-02-07 | Micron Technology, Inc. | Parallel access to volatile memory by a processing device for machine learning |
CN112771493B (en) * | 2018-09-28 | 2022-06-24 | 波利伍德股份有限公司 | Splitting write streams into multiple partitions |
CN110968449A (en) * | 2018-09-28 | 2020-04-07 | 方一信息科技(上海)有限公司 | BCH ECC error correction resource sharing system and method for multichannel flash memory controller |
KR102576373B1 (en) | 2018-09-28 | 2023-09-07 | 에스케이하이닉스 주식회사 | Control device for dynamically allocating storage space and data storage device including the control device |
US10817430B2 (en) * | 2018-10-02 | 2020-10-27 | Micron Technology, Inc. | Access unit and management segment memory operations |
KR20200053204A (en) | 2018-11-08 | 2020-05-18 | 삼성전자주식회사 | Storage device, operating method of storage device and operating method of host controlling storage device |
US10871907B2 (en) | 2018-12-31 | 2020-12-22 | Micron Technology, Inc. | Sequential data optimized sub-regions in storage devices |
CN109979498A (en) * | 2019-01-24 | 2019-07-05 | 深圳市景阳信息技术有限公司 | The method and device of the write-in of disk video data, reading |
CN110046114B (en) * | 2019-03-06 | 2020-08-14 | 上海熠知电子科技有限公司 | DMA controller based on PCIE protocol and DMA data transmission method |
JP7074705B2 (en) * | 2019-03-20 | 2022-05-24 | キオクシア株式会社 | Memory device and control method of memory device |
WO2020220216A1 (en) | 2019-04-29 | 2020-11-05 | Splunk Inc. | Search time estimate in data intake and query system |
US11715051B1 (en) | 2019-04-30 | 2023-08-01 | Splunk Inc. | Service provider instance recommendations using machine-learned classifications and reconciliation |
US20220043915A1 (en) * | 2019-04-30 | 2022-02-10 | Hewlett-Packard Development Company, L.P. | Storage of network credentials |
KR20210118453A (en) * | 2019-04-30 | 2021-09-30 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Electronic device and method for managing read levels of flash memory |
CN110209606B (en) * | 2019-04-30 | 2021-01-22 | 杭州电子科技大学 | Control method of PCIe-based multi-interface storage device |
KR20200134784A (en) * | 2019-05-23 | 2020-12-02 | 에스케이하이닉스 주식회사 | Storage device and operating method thereof |
CN110175056B (en) * | 2019-05-30 | 2022-02-11 | 西安微电子技术研究所 | Control device and control method for remotely and dynamically loading multi-target FPGA (field programmable Gate array) on heterogeneous platform |
KR20200142219A (en) | 2019-06-12 | 2020-12-22 | 삼성전자주식회사 | Electronic device and method of utilizing storage space thereof |
KR20210012305A (en) * | 2019-07-24 | 2021-02-03 | 삼성전자주식회사 | Integrated circuit device, system-on-chip including the same, and packet processing method |
CN112394887A (en) * | 2019-08-17 | 2021-02-23 | 森大(深圳)技术有限公司 | Oneepass printing data high-efficiency processing method, device, equipment and storage medium |
CN110673989B (en) * | 2019-08-27 | 2023-05-16 | 国网浙江省电力有限公司电力科学研究院 | Device and method for identifying daughter board card of backboard system |
US11494380B2 (en) | 2019-10-18 | 2022-11-08 | Splunk Inc. | Management of distributed computing framework components in a data fabric service system |
KR20210054187A (en) * | 2019-11-05 | 2021-05-13 | 에스케이하이닉스 주식회사 | Memory system, memory device, and operating method of memory system |
US11175984B1 (en) | 2019-12-09 | 2021-11-16 | Radian Memory Systems, Inc. | Erasure coding techniques for flash memory |
US11892956B2 (en) * | 2019-12-31 | 2024-02-06 | Micron Technology, Inc. | Performance of memory system background operations |
US11922222B1 (en) | 2020-01-30 | 2024-03-05 | Splunk Inc. | Generating a modified component for a data intake and query system using an isolated execution environment image |
KR20210156985A (en) | 2020-06-19 | 2021-12-28 | 삼성전자주식회사 | Semiconductor devices including work function layers |
KR20210158607A (en) | 2020-06-24 | 2021-12-31 | 삼성전자주식회사 | Semiconductor device including capping layer |
KR20210158615A (en) | 2020-06-24 | 2021-12-31 | 삼성전자주식회사 | Integrate circuit device including gate line |
US11704313B1 (en) | 2020-10-19 | 2023-07-18 | Splunk Inc. | Parallel branch operation using intermediary nodes |
KR20220067872A (en) * | 2020-11-18 | 2022-05-25 | 에스케이하이닉스 주식회사 | Controller and operation method thereof |
US11513980B2 (en) * | 2021-01-21 | 2022-11-29 | Silicon Motion, Inc. | Method and apparatus for performing access management of memory device with aid of universal asynchronous receiver-transmitter connection |
US20220350933A1 (en) * | 2021-04-29 | 2022-11-03 | EMC IP Holding Company LLC | Methods and systems for securing data in a distributed storage system |
US20230008974A1 (en) * | 2021-07-08 | 2023-01-12 | Toshiba Global Commerce Solutions Holdings Corporation | Methods, systems, and computer program products configured to provide consistent look and feel for user input |
CN115843379A (en) * | 2021-07-21 | 2023-03-24 | 美光科技公司 | Memory command aggregation to improve sequential memory command performance |
US20230120600A1 (en) * | 2021-10-20 | 2023-04-20 | Western Digital Technologies, Inc. | Data Storage Devices, Systems, and Related Methods for Grouping Commands of Doorbell Transactions from Host Devices |
KR102385572B1 (en) | 2021-11-02 | 2022-04-13 | 삼성전자주식회사 | Controller, storage device and operation method of the storage device |
CN116501670A (en) * | 2022-01-18 | 2023-07-28 | 联发科技(新加坡)私人有限公司 | Interrupt processing method of sensing device and integrated circuit thereof |
Family Cites Families (169)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4449182A (en) | 1981-10-05 | 1984-05-15 | Digital Equipment Corporation | Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems |
US4777595A (en) * | 1982-05-07 | 1988-10-11 | Digital Equipment Corporation | Apparatus for transferring blocks of information from one node to a second node in a computer network |
DE69033262T2 (en) * | 1989-04-13 | 2000-02-24 | Sandisk Corp | EEPROM card with replacement of faulty memory cells and buffer |
JPH0398972A (en) | 1989-09-08 | 1991-04-24 | Mitsubishi Electric Corp | Control device for elevator |
US5663901A (en) * | 1991-04-11 | 1997-09-02 | Sandisk Corporation | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
EP0610677A3 (en) | 1993-02-12 | 1995-08-02 | Ibm | Bimodal communications device driver. |
JPH07234764A (en) * | 1994-02-22 | 1995-09-05 | Toshiba Corp | Scheduler |
US5619687A (en) * | 1994-02-22 | 1997-04-08 | Motorola Inc. | Queue system having a time-out feature and method therefor |
JP3209634B2 (en) * | 1994-03-28 | 2001-09-17 | 株式会社日立製作所 | Computer system |
JP3561002B2 (en) * | 1994-05-18 | 2004-09-02 | 富士通株式会社 | Disk unit |
JPH0997124A (en) | 1995-09-29 | 1997-04-08 | Fujitsu Ltd | Electronic device, memory board and memory loading mechanism |
US5708814A (en) | 1995-11-21 | 1998-01-13 | Microsoft Corporation | Method and apparatus for reducing the rate of interrupts by generating a single interrupt for a group of events |
JPH09305330A (en) * | 1996-05-15 | 1997-11-28 | Oki Electric Ind Co Ltd | Disk array system |
JPH10214221A (en) * | 1997-01-31 | 1998-08-11 | Hitachi Ltd | Controller and memory system |
US6003112A (en) * | 1997-06-30 | 1999-12-14 | Intel Corporation | Memory controller and method for clearing or copying memory utilizing register files to store address information |
US5941998A (en) | 1997-07-25 | 1999-08-24 | Samsung Electronics Co., Ltd. | Disk drive incorporating read-verify after write method |
US7088387B1 (en) | 1997-08-05 | 2006-08-08 | Mitsubishi Electric Research Laboratories, Inc. | Video recording device responsive to triggering event |
US7158167B1 (en) * | 1997-08-05 | 2007-01-02 | Mitsubishi Electric Research Laboratories, Inc. | Video recording device for a targetable weapon |
DE19740525C1 (en) | 1997-09-15 | 1999-02-04 | Siemens Ag | Method of data storage and recovery in control system, esp. in motor vehicle, such as taxi |
JP3534585B2 (en) | 1997-10-21 | 2004-06-07 | 株式会社日立製作所 | Data storage control method and apparatus for external storage device using a plurality of flash memories |
US6009478A (en) | 1997-11-04 | 1999-12-28 | Adaptec, Inc. | File array communications interface for communicating between a host computer and an adapter |
US6175900B1 (en) | 1998-02-09 | 2001-01-16 | Microsoft Corporation | Hierarchical bitmap-based memory manager |
NL1011442C2 (en) | 1998-03-26 | 1999-09-28 | Franciscus Hubertus Johannes M | Front implement steering. |
US6172676B1 (en) | 1998-07-17 | 2001-01-09 | International Business Machines Corporation | Method and computer program product for implementing multiple drag and drop operations for large objects without blocking an operating system interface |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
JP2000357125A (en) * | 1999-06-16 | 2000-12-26 | Matsushita Electric Ind Co Ltd | Method and device for buffer memory control |
US6866581B2 (en) * | 1999-09-24 | 2005-03-15 | Igt | Video gaming apparatus for wagering with universal computerized controller and I/O interface for unique architecture |
US6757797B1 (en) | 1999-09-30 | 2004-06-29 | Fujitsu Limited | Copying method between logical disks, disk-storage system and its storage medium |
CA2388789A1 (en) | 1999-10-29 | 2001-05-10 | Opentv, Corp. | System and method for recording pushed data |
US7000245B1 (en) | 1999-10-29 | 2006-02-14 | Opentv, Inc. | System and method for recording pushed data |
US8250617B2 (en) | 1999-10-29 | 2012-08-21 | Opentv, Inc. | System and method for providing multi-perspective instant replay |
US6678463B1 (en) | 2000-08-02 | 2004-01-13 | Opentv | System and method for incorporating previously broadcast content into program recording |
US20020053004A1 (en) | 1999-11-19 | 2002-05-02 | Fong Pong | Asynchronous cache coherence architecture in a shared memory multiprocessor with point-to-point links |
US7024695B1 (en) | 1999-12-30 | 2006-04-04 | Intel Corporation | Method and apparatus for secure remote system management |
US20050160218A1 (en) | 2004-01-20 | 2005-07-21 | Sun-Teck See | Highly integrated mass storage device with an intelligent flash controller |
US8341332B2 (en) * | 2003-12-02 | 2012-12-25 | Super Talent Electronics, Inc. | Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices |
US8037234B2 (en) * | 2003-12-02 | 2011-10-11 | Super Talent Electronics, Inc. | Command queuing smart storage transfer manager for striping data to raw-NAND flash modules |
US8266367B2 (en) | 2003-12-02 | 2012-09-11 | Super Talent Electronics, Inc. | Multi-level striping and truncation channel-equalization for flash-memory system |
US6317330B1 (en) * | 2000-02-15 | 2001-11-13 | Bitmicro Networks, Inc. | Printed circuit board assembly |
US6434660B1 (en) | 2000-05-23 | 2002-08-13 | Centennial Technologies, Inc. | Emulating one tape protocol of flash memory to a different type protocol of flash memory |
US6772273B1 (en) * | 2000-06-29 | 2004-08-03 | Intel Corporation | Block-level read while write method and apparatus |
IL137085A (en) * | 2000-06-29 | 2004-08-31 | Eci Telecom Ltd | Method for effective utilizing of shared resources in computerized systems |
US7104804B2 (en) | 2000-07-03 | 2006-09-12 | Advanced Interconnect Solutions | Method and apparatus for memory module circuit interconnection |
JP2002023962A (en) * | 2000-07-07 | 2002-01-25 | Fujitsu Ltd | Disk device and its controlling method |
ATE371336T1 (en) | 2000-08-02 | 2007-09-15 | Opentv Inc | SYSTEM AND METHOD FOR IMMEDIATE REPEAT WITH MULTIPLE PERSPECTIVES |
JP4609680B2 (en) * | 2000-08-09 | 2011-01-12 | ソニー株式会社 | Data storage device |
US6820148B1 (en) * | 2000-08-17 | 2004-11-16 | Sandisk Corporation | Multiple removable non-volatile memory cards serially communicating with a host |
US6640274B1 (en) | 2000-08-21 | 2003-10-28 | Intel Corporation | Method and apparatus for reducing the disk drive data transfer interrupt service latency penalty |
US6865631B2 (en) | 2000-12-14 | 2005-03-08 | International Business Machines Corporation | Reduction of interrupts in remote procedure calls |
JP4818812B2 (en) * | 2006-05-31 | 2011-11-16 | 株式会社日立製作所 | Flash memory storage system |
US6931498B2 (en) | 2001-04-03 | 2005-08-16 | Intel Corporation | Status register architecture for flexible read-while-write device |
US20020178307A1 (en) * | 2001-05-25 | 2002-11-28 | Pua Khein Seng | Multiple memory card adapter |
US6781914B2 (en) | 2001-08-23 | 2004-08-24 | Winbond Electronics Corp. | Flash memory having a flexible bank partition |
ITRM20010524A1 (en) | 2001-08-30 | 2003-02-28 | Micron Technology Inc | FLASH MEMORY TABLE STRUCTURE. |
US7631084B2 (en) | 2001-11-02 | 2009-12-08 | Juniper Networks, Inc. | Method and system for providing secure access to private networks with client redirection |
KR100449708B1 (en) | 2001-11-16 | 2004-09-22 | 삼성전자주식회사 | Flash memory management method |
JP3802411B2 (en) | 2001-12-20 | 2006-07-26 | 株式会社東芝 | Data copy method for nonvolatile semiconductor memory device |
US6938188B1 (en) | 2002-01-29 | 2005-08-30 | Advanced Digital Information Corporation | Method for verifying functional integrity of computer hardware, particularly data storage devices |
US6854022B1 (en) | 2002-02-22 | 2005-02-08 | Western Digital Technologies, Inc. | Disk drive using rotational position optimization algorithm to facilitate write verify operations |
US7080245B2 (en) | 2002-05-23 | 2006-07-18 | Hewlett-Packard Development Company, L.P. | Method and system of switching between two or more images of firmware on a host device |
US7114051B2 (en) | 2002-06-01 | 2006-09-26 | Solid State System Co., Ltd. | Method for partitioning memory mass storage device |
US20040078729A1 (en) * | 2002-06-26 | 2004-04-22 | Siemens Aktiengesellschaft | Method, computer, and computer program for detecting a bad block on a hard disk |
JP2004071033A (en) | 2002-08-05 | 2004-03-04 | Mitsubishi Electric Corp | Data writing method for flash memory |
EP1396792B1 (en) | 2002-09-06 | 2005-06-15 | Sun Microsystems, Inc. | Memory copy command specifying source and destination of data executed in the memory controller |
US7137118B2 (en) | 2002-09-27 | 2006-11-14 | Texas Instruments Incorporated | Data synchronization hardware primitive in an embedded symmetrical multiprocessor computer |
US7296213B2 (en) * | 2002-12-11 | 2007-11-13 | Nvidia Corporation | Error correction cache for flash memory |
US6901461B2 (en) | 2002-12-31 | 2005-05-31 | Intel Corporation | Hardware assisted ATA command queuing |
CN1432929A (en) * | 2003-02-14 | 2003-07-30 | 威盛电子股份有限公司 | Arbitration structure and method for responding interruption service request in multiple microprocessor system |
JP4165747B2 (en) * | 2003-03-20 | 2008-10-15 | 株式会社日立製作所 | Storage system, control device, and control device program |
US7136938B2 (en) | 2003-03-27 | 2006-11-14 | International Business Machines Corporation | Command ordering based on dependencies |
KR100543447B1 (en) | 2003-04-03 | 2006-01-23 | 삼성전자주식회사 | Flash memory with error correction for page copy |
US7320100B2 (en) | 2003-05-20 | 2008-01-15 | Cray Inc. | Apparatus and method for memory with bit swapping on the fly and testing |
US7159104B2 (en) | 2003-05-20 | 2007-01-02 | Nvidia Corporation | Simplified memory detection |
US7200688B2 (en) | 2003-05-29 | 2007-04-03 | International Business Machines Corporation | System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command |
JP4653960B2 (en) | 2003-08-07 | 2011-03-16 | ルネサスエレクトロニクス株式会社 | Memory card and nonvolatile memory embedded microcomputer |
CN2662316Y (en) * | 2003-11-28 | 2004-12-08 | 中国科学院空间科学与应用研究中心 | System mainboard for embedded computer system |
US8176238B2 (en) | 2003-12-02 | 2012-05-08 | Super Talent Electronics, Inc. | Command queuing smart storage transfer manager for striping data to raw-NAND flash modules |
US7865809B1 (en) | 2004-03-11 | 2011-01-04 | Super Talent Electronics, Inc. | Data error detection and correction in non-volatile memory devices |
JP2005190106A (en) | 2003-12-25 | 2005-07-14 | Hitachi Ltd | Storage control subsystem for managing logical volume |
US7370230B1 (en) | 2004-01-08 | 2008-05-06 | Maxtor Corporation | Methods and structure for error correction in a processor pipeline |
US8108870B2 (en) * | 2004-01-29 | 2012-01-31 | Klingman Edwin E | Intelligent memory device having ASCII-named task registers mapped to addresses of a task |
US7127549B2 (en) | 2004-02-04 | 2006-10-24 | Sandisk Corporation | Disk acceleration using first and second storage devices |
WO2005082037A2 (en) | 2004-02-24 | 2005-09-09 | Paul Kaler | Intelligent solid state disk with hot-swappable components |
CA2557641A1 (en) | 2004-02-27 | 2005-09-15 | Tigi Corporation | System and method for data manipulation |
US7328304B2 (en) * | 2004-02-27 | 2008-02-05 | Intel Corporation | Interface for a block addressable mass storage system |
US7406572B1 (en) | 2004-03-26 | 2008-07-29 | Cypress Semiconductor Corp. | Universal memory circuit architecture supporting multiple memory interface options |
US20080147931A1 (en) | 2006-10-17 | 2008-06-19 | Smart Modular Technologies, Inc. | Data striping to flash memory |
US7490283B2 (en) | 2004-05-13 | 2009-02-10 | Sandisk Corporation | Pipelined data relocation and improved chip architectures |
US7205532B2 (en) | 2004-08-24 | 2007-04-17 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | Integrated ball grid array optical mouse sensor packaging |
US20060053308A1 (en) * | 2004-09-08 | 2006-03-09 | Raidy 2 Go Ltd. | Secured redundant memory subsystem |
US7283074B2 (en) | 2004-09-21 | 2007-10-16 | Telegent Systems, Inc. | Pilot-tone calibration for time-interleaved analog-to-digital converters |
KR100667780B1 (en) | 2004-11-22 | 2007-01-11 | 삼성전자주식회사 | Certification method, recording/reproducing apparatus and information recording medium |
US7730257B2 (en) | 2004-12-16 | 2010-06-01 | Broadcom Corporation | Method and computer program product to increase I/O write performance in a redundant array |
KR100621631B1 (en) * | 2005-01-11 | 2006-09-13 | 삼성전자주식회사 | Solid state disk controller apparatus |
JP2006195569A (en) | 2005-01-11 | 2006-07-27 | Sony Corp | Memory unit |
US7562366B2 (en) | 2005-02-03 | 2009-07-14 | Solarflare Communications, Inc. | Transmit completion event batching |
WO2006085323A2 (en) * | 2005-02-11 | 2006-08-17 | Sandisk Il Ltd. | Appliance with communication protocol emulation |
TWI266988B (en) | 2005-03-01 | 2006-11-21 | Sunplus Technology Co Ltd | Method and system for accessing A/V data in computer apparatus |
US20060211388A1 (en) * | 2005-03-07 | 2006-09-21 | Lambert Grady D | Stackable printed circuit boards |
US20080126658A1 (en) | 2006-05-28 | 2008-05-29 | Phison Electronics Corp. | Inlayed flash memory module |
US7822912B2 (en) | 2005-03-14 | 2010-10-26 | Phision Electronics Corp. | Flash storage chip and flash array storage system |
US7225289B2 (en) | 2005-03-14 | 2007-05-29 | Phison Electronics Corporation | Virtual IDE storage with PCI express interface |
JP2007004775A (en) * | 2005-05-23 | 2007-01-11 | Toshiba Corp | Semiconductor memory card |
KR100690804B1 (en) | 2005-06-13 | 2007-03-09 | 엘지전자 주식회사 | Method for executing garbage collection of mobile terminal |
TWI319160B (en) | 2005-07-11 | 2010-01-01 | Via Tech Inc | Memory card capable of supporting various voltage supply and control chip and method of supporting voltage thereof |
US7660306B1 (en) | 2006-01-12 | 2010-02-09 | Chelsio Communications, Inc. | Virtualizing the operation of intelligent network interface circuitry |
US20070079098A1 (en) * | 2005-10-03 | 2007-04-05 | Hitachi, Ltd. | Automatic allocation of volumes in storage area networks |
KR100993664B1 (en) * | 2005-10-17 | 2010-11-10 | 르네사스 일렉트로닉스 가부시키가이샤 | Semiconductor device and its fabrication method |
CN101346703B (en) | 2005-12-21 | 2012-11-21 | Nxp股份有限公司 | Non-volatile memory with block erasable locations |
CN101346704B (en) | 2005-12-22 | 2011-10-05 | Nxp股份有限公司 | Memory with block-erasable locations and a linked chain of pointers to locate blocks with pointer information |
WO2007079534A1 (en) * | 2006-01-12 | 2007-07-19 | Para Kanagasabai Segaram | A subsystem for computing devices |
US7549021B2 (en) | 2006-02-22 | 2009-06-16 | Seagate Technology Llc | Enhanced data integrity using parallel volatile and non-volatile transfer buffers |
WO2007096844A2 (en) | 2006-02-27 | 2007-08-30 | Nxp B.V. | Memory with block-erasable locations |
JP2007257791A (en) | 2006-03-24 | 2007-10-04 | Fujitsu Ltd | Semiconductor storage device |
JP4135747B2 (en) * | 2006-04-06 | 2008-08-20 | ソニー株式会社 | Data processing apparatus and flash memory access method |
US20070271495A1 (en) | 2006-05-18 | 2007-11-22 | Ian Shaeffer | System to detect and identify errors in control information, read data and/or write data |
CN100433697C (en) * | 2006-06-01 | 2008-11-12 | 东南大学 | Multi-channel high-speed data processor and processing method |
US7613876B2 (en) * | 2006-06-08 | 2009-11-03 | Bitmicro Networks, Inc. | Hybrid multi-tiered caching storage system |
US7506098B2 (en) | 2006-06-08 | 2009-03-17 | Bitmicro Networks, Inc. | Optimized placement policy for solid state storage devices |
WO2007146845A2 (en) | 2006-06-08 | 2007-12-21 | Bitmicro Networks, Inc. | Configurable and scalable hybrid multi-tiered caching storage system |
TW200805394A (en) | 2006-07-07 | 2008-01-16 | Alcor Micro Corp | Memory storage device and the read/write method thereof |
US8140738B2 (en) | 2006-07-20 | 2012-03-20 | Stmicroelectronics Pvt. Ltd. | Flash memory interface device |
US7487428B2 (en) * | 2006-07-24 | 2009-02-03 | Kingston Technology Corp. | Fully-buffered memory-module with error-correction code (ECC) controller in serializing advanced-memory buffer (AMB) that is transparent to motherboard memory controller |
US7827346B2 (en) | 2006-08-14 | 2010-11-02 | Plankton Technologies, Llc | Data storage device |
US7539842B2 (en) | 2006-08-15 | 2009-05-26 | International Business Machines Corporation | Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables |
CN100573435C (en) | 2006-08-18 | 2009-12-23 | 福昭科技(深圳)有限公司 | A kind of mass storage device based on flash memory |
US7904639B2 (en) | 2006-08-22 | 2011-03-08 | Mosaid Technologies Incorporated | Modular command structure for memory and memory system |
KR20080017982A (en) * | 2006-08-23 | 2008-02-27 | 삼성전자주식회사 | Flash memory system and program method thereof |
US7730269B2 (en) * | 2006-08-29 | 2010-06-01 | International Business Machines Corporation | Load management to reduce communication signaling latency in a virtual machine environment |
CN101118783A (en) * | 2006-09-07 | 2008-02-06 | 晶天电子(深圳)有限公司 | Electronic data flash memory fasten with flash memory bad blocks control system |
JP2008065575A (en) * | 2006-09-07 | 2008-03-21 | Fuji Xerox Co Ltd | Expanded memory device and memory expansion system |
JP4452261B2 (en) * | 2006-09-12 | 2010-04-21 | 株式会社日立製作所 | Storage system logical volume management method, logical volume management program, and storage system |
US20080077727A1 (en) | 2006-09-25 | 2008-03-27 | Baca Jim S | Multithreaded state machine in non-volatile memory devices |
WO2008040028A2 (en) | 2006-09-28 | 2008-04-03 | Virident Systems, Inc. | Systems, methods, and apparatus with programmable memory control for heterogeneous main memory |
US7587575B2 (en) | 2006-10-17 | 2009-09-08 | International Business Machines Corporation | Communicating with a memory registration enabled adapter using cached address translations |
JP4932427B2 (en) | 2006-10-20 | 2012-05-16 | 株式会社日立製作所 | Storage device and storage method |
US8935302B2 (en) | 2006-12-06 | 2015-01-13 | Intelligent Intellectual Property Holdings 2 Llc | Apparatus, system, and method for data block usage information synchronization for a non-volatile storage volume |
US8296337B2 (en) | 2006-12-06 | 2012-10-23 | Fusion-Io, Inc. | Apparatus, system, and method for managing data from a requesting device with an empty data token directive |
US7660911B2 (en) * | 2006-12-20 | 2010-02-09 | Smart Modular Technologies, Inc. | Block-based data striping to flash memory |
US7668177B1 (en) | 2006-12-28 | 2010-02-23 | Qlogic, Corporation | Method and system for quality of service in host bus adapters |
KR100813630B1 (en) | 2007-02-07 | 2008-03-14 | 삼성전자주식회사 | Flash memory system for improving read performance and read method thereof |
US20080209157A1 (en) | 2007-02-27 | 2008-08-28 | Inventec Corporation | Memory partitioning method |
JP5224706B2 (en) | 2007-03-23 | 2013-07-03 | キヤノン株式会社 | Storage device and storage device control method |
JP4781373B2 (en) * | 2007-05-14 | 2011-09-28 | 株式会社バッファロー | Storage device |
JP2008287404A (en) | 2007-05-16 | 2008-11-27 | Hitachi Ltd | Apparatus for detecting and recovering data corruption in reading in non-access memory cell, and method thereof |
JP2008293096A (en) | 2007-05-22 | 2008-12-04 | Shinko Electric Ind Co Ltd | Memory interface and system |
US20080294814A1 (en) | 2007-05-24 | 2008-11-27 | Sergey Anatolievich Gorobets | Flash Memory System with Management of Housekeeping Operations |
WO2008147752A1 (en) | 2007-05-24 | 2008-12-04 | Sandisk Corporation | Managing housekeeping operations in flash memory |
KR20080105390A (en) | 2007-05-30 | 2008-12-04 | 삼성전자주식회사 | Apparatus and method for controlling commands used in flash memory |
US8040710B2 (en) | 2007-05-31 | 2011-10-18 | Qimonda Ag | Semiconductor memory arrangement |
US7898813B2 (en) * | 2007-06-25 | 2011-03-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device and semiconductor memory card using the same |
US20090006720A1 (en) | 2007-06-27 | 2009-01-01 | Shai Traister | Scheduling phased garbage collection and house keeping operations in a flash memory system |
US8001444B2 (en) | 2007-08-08 | 2011-08-16 | Intel Corporation | ECC functional block placement in a multi-channel mass storage device |
US7639165B2 (en) | 2007-08-10 | 2009-12-29 | Marvell World Trade Ltd. | Calibrating replica digital-to-analog converters |
JP4977554B2 (en) | 2007-08-22 | 2012-07-18 | 株式会社日立製作所 | Storage system with a function to back up data in cache memory |
KR101466694B1 (en) | 2007-08-28 | 2014-11-28 | 삼성전자주식회사 | ECC circuit, and storage device having the same, and method there-of |
US8082482B2 (en) | 2007-08-31 | 2011-12-20 | International Business Machines Corporation | System for performing error correction operations in a memory hub device of a memory module |
US8086936B2 (en) | 2007-08-31 | 2011-12-27 | International Business Machines Corporation | Performing error correction at a memory device level that is transparent to a memory channel |
US20090063895A1 (en) | 2007-09-04 | 2009-03-05 | Kurt Smith | Scaleable and maintainable solid state drive |
US20090125790A1 (en) | 2007-11-13 | 2009-05-14 | Mcm Portfolio Llc | Method and Apparatus of Automatically Selecting Error Correction Algorithms by a NAND Flash Controller |
TWI384488B (en) | 2007-12-24 | 2013-02-01 | Skymedi Corp | Nonvolatile storage device and its data writing method |
US20100049914A1 (en) * | 2008-08-20 | 2010-02-25 | Goodwin Paul M | RAID Enhanced solid state drive |
US8266365B2 (en) | 2008-12-17 | 2012-09-11 | Sandisk Il Ltd. | Ruggedized memory device |
US8578084B2 (en) | 2009-04-08 | 2013-11-05 | Google Inc. | Data storage device having multiple removable memory boards |
US20100287217A1 (en) | 2009-04-08 | 2010-11-11 | Google Inc. | Host control of background garbage collection in a data storage device |
US20100262979A1 (en) | 2009-04-08 | 2010-10-14 | Google Inc. | Circular command queues for communication between a host and a data storage device |
US8595572B2 (en) | 2009-04-08 | 2013-11-26 | Google Inc. | Data storage device with metadata command |
JP5404804B2 (en) | 2009-05-25 | 2014-02-05 | 株式会社日立製作所 | Storage subsystem |
WO2011007459A1 (en) | 2009-07-17 | 2011-01-20 | 株式会社日立製作所 | Storage device and method of controlling same |
-
2009
- 2009-08-07 US US12/537,719 patent/US8578084B2/en active Active
- 2009-08-07 US US12/537,727 patent/US8250271B2/en active Active
- 2009-08-07 US US12/537,733 patent/US8380909B2/en active Active
- 2009-08-07 US US12/537,725 patent/US8239724B2/en active Active
- 2009-08-07 US US12/537,741 patent/US8639871B2/en active Active
- 2009-08-07 US US12/537,709 patent/US8205037B2/en active Active
- 2009-08-07 US US12/537,704 patent/US8566507B2/en active Active
- 2009-08-07 US US12/537,748 patent/US8566508B2/en active Active
- 2009-08-07 US US12/537,738 patent/US20100262773A1/en not_active Abandoned
- 2009-08-07 US US12/537,722 patent/US8244962B2/en active Active
-
2010
- 2010-04-01 JP JP2012504717A patent/JP5657641B2/en active Active
- 2010-04-01 AU AU2010234773A patent/AU2010234773B2/en active Active
- 2010-04-01 CN CN2010800205069A patent/CN102428454A/en active Pending
- 2010-04-01 DE DE202010017661U patent/DE202010017661U1/en not_active Expired - Lifetime
- 2010-04-01 WO PCT/US2010/029677 patent/WO2010117877A1/en active Application Filing
- 2010-04-01 JP JP2012504716A patent/JP5922016B2/en active Active
- 2010-04-01 CN CN201711055987.7A patent/CN107832010A/en active Pending
- 2010-04-01 CN CN201080020319.0A patent/CN102428451B/en active Active
- 2010-04-01 DE DE202010017669U patent/DE202010017669U1/en not_active Expired - Lifetime
- 2010-04-01 WO PCT/US2010/029679 patent/WO2010117878A1/en active Application Filing
- 2010-04-01 EP EP10712655.9A patent/EP2417531B1/en active Active
- 2010-04-01 EP EP14153062.6A patent/EP2728488B1/en active Active
- 2010-04-01 DE DE202010017668U patent/DE202010017668U1/en not_active Expired - Lifetime
- 2010-04-01 EP EP10712656.7A patent/EP2417528B1/en active Active
- 2010-04-01 AU AU2010234772A patent/AU2010234772B2/en active Active
- 2010-04-05 CN CN2010800204899A patent/CN102428452A/en active Pending
- 2010-04-05 WO PCT/US2010/029917 patent/WO2010117929A1/en active Application Filing
- 2010-04-05 JP JP2012504741A patent/JP2012523623A/en active Pending
- 2010-04-05 JP JP2012504740A patent/JP2012523622A/en active Pending
- 2010-04-05 DE DE202010017665U patent/DE202010017665U1/en not_active Expired - Lifetime
- 2010-04-05 AU AU2010234646A patent/AU2010234646A1/en not_active Abandoned
- 2010-04-05 AU AU2010234648A patent/AU2010234648B2/en active Active
- 2010-04-05 WO PCT/US2010/029919 patent/WO2010117930A1/en active Application Filing
- 2010-04-05 EP EP10712863A patent/EP2417533A1/en not_active Withdrawn
- 2010-04-05 CN CN2010800205073A patent/CN102428453A/en active Pending
- 2010-04-05 CN CN2010800204884A patent/CN102428455A/en active Pending
- 2010-04-05 WO PCT/US2010/029916 patent/WO2010117928A1/en active Application Filing
- 2010-04-05 DE DE202010017666U patent/DE202010017666U1/en not_active Expired - Lifetime
- 2010-04-05 DE DE202010017667U patent/DE202010017667U1/en not_active Expired - Lifetime
- 2010-04-05 EP EP10712864A patent/EP2417529A1/en not_active Withdrawn
- 2010-04-05 AU AU2010234647A patent/AU2010234647B2/en active Active
- 2010-04-05 JP JP2012504742A patent/JP5347061B2/en active Active
- 2010-04-05 EP EP10712865A patent/EP2417530A1/en not_active Withdrawn
-
2013
- 2013-10-18 US US14/057,703 patent/US20140108708A1/en not_active Abandoned
- 2013-10-21 US US14/059,061 patent/US20140047172A1/en not_active Abandoned
- 2013-11-25 US US14/089,397 patent/US20140156915A1/en not_active Abandoned
-
2014
- 2014-10-09 JP JP2014208104A patent/JP2015046175A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9244842B2 (en) | 2009-04-08 | 2016-01-26 | Google Inc. | Data storage device with copy command |
US10210298B2 (en) | 2015-11-24 | 2019-02-19 | Altera Corporation | Embedded memory blocks with adjustable memory boundaries |
CN109933291A (en) * | 2019-03-20 | 2019-06-25 | 浪潮商用机器有限公司 | A kind of processing method of SRAM data, device, equipment and storage medium |
US20230266897A1 (en) * | 2022-02-24 | 2023-08-24 | Micron Technology, Inc. | Dynamic zone group configuration at a memory sub-system |
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8639871B2 (en) | Partitioning a flash memory data storage device | |
US8447918B2 (en) | Garbage collection for failure prediction and repartitioning | |
US20100287217A1 (en) | Host control of background garbage collection in a data storage device | |
CN107908571B (en) | Data writing method, flash memory device and storage equipment | |
US9558108B2 (en) | Half block management for flash storage devices | |
KR20150105323A (en) | Method and system for data storage | |
WO2011128928A1 (en) | Storage device | |
US10649891B2 (en) | Storage device that maintains mapping data therein | |
CN113918087B (en) | Storage device and method for managing namespaces in the storage device | |
KR101756228B1 (en) | Memory apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |