US20140175625A1 - Semiconductor device including at least one element - Google Patents

Semiconductor device including at least one element Download PDF

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Publication number
US20140175625A1
US20140175625A1 US14/189,304 US201414189304A US2014175625A1 US 20140175625 A1 US20140175625 A1 US 20140175625A1 US 201414189304 A US201414189304 A US 201414189304A US 2014175625 A1 US2014175625 A1 US 2014175625A1
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Prior art keywords
chip
semiconductor device
redistribution layer
component
conductive traces
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US14/189,304
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Thorsten Meyer
Jens Pohl
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Infineon Technologies AG
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Infineon Technologies AG
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Priority to US14/189,304 priority Critical patent/US20140175625A1/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MEYER, THORSTEN, POHL, JENS
Publication of US20140175625A1 publication Critical patent/US20140175625A1/en
Priority to US15/226,260 priority patent/US9984900B2/en
Abandoned legal-status Critical Current

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    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • Embedded wafer level ball grid array (eWLB) technology expands on typical wafer level packaging technologies by providing the ability for adding additional surface area for interconnecting silicon components in a semiconductor device. Therefore, eWLB technology provides the possibility of fabricating a semiconductor device by combining both active and passive silicon components into a single module. Passive components, however, are typically very small or include geometries (e.g., small surface area with large height) unfavorable to the molding process used to package the semiconductor device. The small components may not adhere to the carrier foil during the molding process due to the forces applied to the small components by the molding process. This may lead the small components to slip and break contact with the carrier foil.
  • eWLB Embedded wafer level ball grid array
  • the semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.
  • FIG. 1 illustrates a cross-sectional view of one embodiment of a semiconductor device.
  • FIG. 2 illustrates a cross-sectional view of another embodiment of a semiconductor device.
  • FIG. 3 illustrates a cross-sectional view of one embodiment of a carrier.
  • FIG. 4 illustrates a cross-sectional view of one embodiment of the carrier and a double-sided adhesive foil.
  • FIG. 5A illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, elements, and semiconductor chips.
  • FIG. 5B illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, solder elements, and semiconductor chips.
  • FIG. 6A illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the elements, the semiconductor chips, and an adhesive material.
  • FIG. 6B illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the solder elements, the semiconductor chips, and an adhesive material.
  • FIG. 7A illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the elements, the semiconductor chips, the adhesive material, and a molding material.
  • FIG. 7B illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the solder elements, the semiconductor chips, the adhesive material, and a molding material.
  • FIG. 8A illustrates a cross-sectional view of one embodiment of the elements, the semiconductor chips, the adhesive material, and the molding material after the release of the carrier and the double-sided adhesive foil.
  • FIG. 8B illustrates a cross-sectional view of one embodiment of the solder elements, the semiconductor chips, the adhesive material, and the molding material after release of the carrier and the double-sided adhesive foil.
  • FIG. 9A illustrates a cross-sectional view one embodiment of multiple semiconductor devices prior to singulation.
  • FIG. 9B illustrates a cross-sectional view of another embodiment of multiple semiconductor devices prior to singulation.
  • FIG. 1 illustrates a cross-sectional view of one embodiment of a semiconductor device 100 .
  • Semiconductor device 100 is fabricated using a wafer level packaging process.
  • Semiconductor device 100 includes a semiconductor chip 106 , at least one element 108 , an adhesive material 114 , a molding material 110 , a redistribution layer 128 , and solder balls 112 .
  • Adhesive material 114 covers at least a portion of each element 108 .
  • Molding material 110 encapsulates at least one side of each semiconductor chip 106 and at least one side of each element 108 and adhesive material 114 .
  • Adhesive material 114 provides stability to elements 108 during the molding process so that elements 108 are not shifted, misplaced, or tilted after the molding process.
  • adhesive material 114 includes Durimide, a polyimide, an elastomer, a thermoplastic, an epoxy, or another suitable adhesive.
  • Semiconductor chip 106 has a first face 105 and an opposing second face 107 .
  • Semiconductor chip 106 includes contacts 109 with an exposed surface on the same plane as opposing second face 107 .
  • Redistribution layer 128 also has a first face 124 and an opposing second face 122 .
  • First face 124 of redistribution layer 128 is attached along second face 107 of chip 106 .
  • each element 108 is a passive component.
  • each element 108 includes a resistor, a capacitor, an inductor, a conductor, a solder element, a conductive sphere, or another suitable passive component.
  • the volume of each element 108 is less than the volume of semiconductor chip 106 by at least a factor of two.
  • the height of each element 108 is greater than the height of chip 106 in the direction perpendicular to redistribution layer 128 .
  • Redistribution layer 128 includes insulating material 116 and conductive traces 118 , which electrically couple semiconductor chip 106 to at least one element 108 . Further, conductive spheres or solder balls 112 can be electrically coupled to conductive traces 118 at second face 124 of redistribution layer 128 . Conductive traces 118 include Cu or other suitable conductive material or conductive material stack. Insulating material 116 includes a polyimide, an epoxy, or another suitable dielectric material.
  • FIG. 2 illustrates a cross-sectional view of another embodiment of a semiconductor device 120 .
  • Semiconductor device 120 is similar to semiconductor device 100 previously described and illustrated with reference to FIG. 1 , except that elements 108 are replaced with conductive spheres or solder elements or balls 138 in semiconductor device 120 .
  • adhesive material 114 provides stability to solder elements 138 during the molding process so that solder elements 138 are not shifted or misplaced after the molding process.
  • Solder elements 138 can be used for 3D-contacts from the front-side to the back-side of the package.
  • FIGS. 3 through 9B illustrate embodiments of a process for fabricating a semiconductor device.
  • FIGS. 5A , 6 A, 7 A, 8 A, and 9 A illustrate one embodiment for fabricating a semiconductor device, such as semiconductor device 100 previously described and illustrated with reference to FIG. 1 .
  • FIGS. 5B , 6 B, 7 B, 8 B, and 9 B illustrate another embodiment for fabricating a semiconductor device, such as semiconductor device 120 previously described and illustrated with reference to FIG. 2 .
  • FIG. 3 illustrates a cross-sectional view of one embodiment of a carrier 102 .
  • Carrier 102 includes a metal, a polymer, silicon, or another suitable material.
  • FIG. 4 illustrates a cross-sectional view of one embodiment of carrier 102 and a double-sided adhesive foil 104 .
  • a double-sided, releasable, adhesive foil 104 is laminated to carrier 102 or applied to carrier 102 using another suitable technique. In other embodiments, other suitable adhesives are used in place of adhesive foil 104 .
  • FIG. 5A illustrates a cross-sectional view of one embodiment of carrier 102 , double-sided adhesive foil 104 , elements 108 , and semiconductor chips 106 .
  • Each element 108 and each semiconductor chip 106 is placed on adhesive foil 104 .
  • at least two semiconductor chips 106 and at least two elements 108 are placed on adhesive foil 104 .
  • the area of the surface of each element 108 at the interface to adhesive foil 104 is less than the area of the surface of semiconductor chip 106 at the interface to adhesive foil 104 .
  • FIG. 5B illustrates a cross-sectional view of one embodiment of carrier 102 , double-sided adhesive foil 104 , solder elements 138 , and semiconductor chips 106 .
  • Each semiconductor chip 106 and each solder element 138 is placed on adhesive foil 104 .
  • at least two semiconductor chips 106 and at least two solder elements 138 are placed on adhesive foil 104 . Due to the non-planar or spherical form of solder elements 138 , solder elements 138 have less surface area than semiconductor chips 106 for attachment to adhesive foil 104 .
  • FIG. 6A illustrates a cross-sectional view of one embodiment of carrier 102 , double-sided adhesive foil 104 , elements 108 , semiconductor chips 106 , and adhesive material 114 .
  • a dispensing needle 126 dispenses an adhesive material 114 to adhere each element 108 to adhesive foil 104 .
  • Adhesive material 114 includes an epoxy, a thermoplastic, a silicone, a polyimide, an elastomer, or another suitable material.
  • Adhesive material 114 at least partially covers each element 108 and provides improved attachment of elements 108 to adhesive foil 104 prior to molding.
  • a printing process, a jetting process, or another suitable process is used to apply adhesive material 114 over or at each element 108 .
  • Adhesive material 114 can then be cured by using any suitable form of energy (e.g., thermal, chemical) if a curing step is needed for the adhesive material.
  • semiconductor chip 106 is placed in close proximity to elements 108 ; thereby adhesive material 114 is also applied to at least one surface of semiconductor chip 106 .
  • adhesive material 114 is applied to at least a portion of adhesive foil 104 before elements 108 are placed on adhesive foil 104 . Elements 108 are then placed into adhesive material 114 .
  • FIG. 6B illustrates a cross-sectional view of one embodiment of carrier 102 , double-sided adhesive foil 104 , solder elements 138 , semiconductor chips 106 , and adhesive material 114 .
  • a dispensing needle dispenses an adhesive material 114 to adhere each solder element 138 to adhesive foil 104 .
  • Adhesive material 114 includes an epoxy or another suitable material. Adhesive material 114 at least partially covers each solder element 138 and provides improved attachment of solder elements 138 to adhesive foil 104 prior to molding.
  • a printing process, a jetting process, or another suitable process is used to apply adhesive material 114 over or at each solder element 138 .
  • Adhesive material 114 can then be cured by using any suitable form of energy (e.g., thermal, chemical) if a curing step is needed for the adhesive material.
  • semiconductor chip 106 is placed in close proximity to solder elements 138 ; thereby adhesive material 114 is also applied to at least one surface of semiconductor chip 106 .
  • adhesive material 114 is applied to at least a portion of adhesive foil 104 before solder elements 138 are placed on adhesive foil 104 . Solder elements 138 are then placed into adhesive material 114 .
  • FIG. 7A illustrates a cross-sectional view of one embodiment of carrier 102 , double-sided adhesive foil 104 , elements 108 , semiconductor chips 106 , adhesive material 114 , and molding material 110 .
  • Adhesive material 114 , elements 108 , and semiconductor chips 106 are at least partially encapsulated by molding material 110 .
  • the entire encapsulation process is performed by mold encapsulation.
  • Carrier 102 is placed in a molding tool.
  • a liquid mold compound having a high viscosity is dispensed in the center of carrier 102 where semiconductor chips 106 and elements 108 have been placed.
  • the top of the molding tool is closed, causing the liquid mold compound to flow from the center to the edges of the molding tool. Flow of the mold compound applies forces on semiconductor chips 106 and elements 108 . Due to adhesive material 114 , however, elements 108 do not shift or tilt in response to the forces.
  • FIG. 7B illustrates a cross-sectional view of one embodiment of carrier 102 , double-sided adhesive foil 104 , solder elements 138 , semiconductor chips 106 , adhesive material 114 , and molding material 110 .
  • Adhesive material 114 , solder elements 138 , and semiconductor chips 106 are at least partially encapsulated by molding material 110 using a similar process as described with reference to FIG. 7A . Due to adhesive material 114 , solder elements 138 do not shift during the molding process.
  • FIG. 8A illustrates a cross-sectional view of one embodiment of elements 108 , semiconductor chips 106 , adhesive material 114 , and molding material 110 after release of carrier 102 and double-sided adhesive foil 104 .
  • the release of adhesive foil 104 and carrier 102 is completed after application of molding material 110 .
  • One surface of each element 108 and each semiconductor chip 106 is exposed where adhesive foil 104 was previously attached.
  • FIG. 8B illustrates a cross-sectional view of one embodiment of solder elements 138 , semiconductor chips 106 , adhesive material 114 , and molding material 110 after release of carrier 102 and double-sided adhesive foil 104 . A surface of each solder element 138 and each semiconductor chip 106 is exposed where adhesive foil 104 was previously attached.
  • FIG. 9A illustrates a cross-sectional view of one embodiment of multiple semiconductor devices prior to singulation.
  • a redistribution layer 128 is fabricated.
  • Redistribution layer 128 includes conductive traces 118 formed in a conductive layer.
  • Conductive traces 118 on first face 124 of redistribution layer 128 are electrically coupled to and directly contact semiconductor chips 106 and/or elements 108 .
  • Redistribution layer 128 also includes insulating material 116 surrounding conductive traces 118 .
  • Conductive spheres or solder balls 112 are electrically coupled to conductive traces 118 on second face 122 of redistribution layer 128 .
  • the semiconductor devices are then separated from one another.
  • the dashed line in FIG. 9A indicates where molding material 110 and redistribution layer 128 are cut to separate the semiconductor devices.
  • Each semiconductor device includes a semiconductor chip 106 and at least one element 108 .
  • the semiconductor devices are separated by sawing, etching, or other suitable method to provide semiconductor devices 100 as previously described and illustrated with reference to FIG. 1 .
  • FIG. 9B illustrates a cross-sectional view of another embodiment of multiple semiconductor devices prior to singulation.
  • a redistribution layer 128 and conductive spheres or solder balls 112 are fabricated using a similar process as previously described with reference to FIG. 9A .
  • the dashed line in FIG. 9B indicates where molding material 110 and redistribution layer 128 are cut to separate the semiconductor devices.
  • Each semiconductor device includes a semiconductor chip 106 and at least one solder element 138 .
  • the semiconductor devices are separated by sawing, etching, or other suitable method to provide semiconductor devices 120 as previously described and illustrated with reference to FIG. 2 .
  • Embodiments provide semiconductor devices using eWLB technology. Elements and/or solder balls are placed on adhesive foil in addition to semiconductor chips. Adhesive material is deposited over or at the elements and/or solder balls to provide increased stability and decreased displacement of the elements and/or solder balls during the molding process. After the adhesive material adheres to the elements and/or solder balls and the adhesive foil, the semiconductor chips, elements and/or solder balls, and adhesive material are encapsulated in mold material.

Abstract

A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This Utility Patent Application is a continuation application of U.S. Ser. No. 12/048,602 filed Mar. 14, 2008, which is herein incorporated by reference.
    • BACKGROUND
  • Embedded wafer level ball grid array (eWLB) technology expands on typical wafer level packaging technologies by providing the ability for adding additional surface area for interconnecting silicon components in a semiconductor device. Therefore, eWLB technology provides the possibility of fabricating a semiconductor device by combining both active and passive silicon components into a single module. Passive components, however, are typically very small or include geometries (e.g., small surface area with large height) unfavorable to the molding process used to package the semiconductor device. The small components may not adhere to the carrier foil during the molding process due to the forces applied to the small components by the molding process. This may lead the small components to slip and break contact with the carrier foil.
  • For these and other reasons, there is a need for the present invention.
    • SUMMARY
  • One embodiment provides a semiconductor device. The semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
  • FIG. 1 illustrates a cross-sectional view of one embodiment of a semiconductor device.
  • FIG. 2 illustrates a cross-sectional view of another embodiment of a semiconductor device.
  • FIG. 3 illustrates a cross-sectional view of one embodiment of a carrier.
  • FIG. 4 illustrates a cross-sectional view of one embodiment of the carrier and a double-sided adhesive foil.
  • FIG. 5A illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, elements, and semiconductor chips.
  • FIG. 5B illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, solder elements, and semiconductor chips.
  • FIG. 6A illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the elements, the semiconductor chips, and an adhesive material.
  • FIG. 6B illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the solder elements, the semiconductor chips, and an adhesive material.
  • FIG. 7A illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the elements, the semiconductor chips, the adhesive material, and a molding material.
  • FIG. 7B illustrates a cross-sectional view of one embodiment of the carrier, the double-sided adhesive foil, the solder elements, the semiconductor chips, the adhesive material, and a molding material.
  • FIG. 8A illustrates a cross-sectional view of one embodiment of the elements, the semiconductor chips, the adhesive material, and the molding material after the release of the carrier and the double-sided adhesive foil.
  • FIG. 8B illustrates a cross-sectional view of one embodiment of the solder elements, the semiconductor chips, the adhesive material, and the molding material after release of the carrier and the double-sided adhesive foil.
  • FIG. 9A illustrates a cross-sectional view one embodiment of multiple semiconductor devices prior to singulation.
  • FIG. 9B illustrates a cross-sectional view of another embodiment of multiple semiconductor devices prior to singulation.
    •  DETAILED DESCRIPTION
  • In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
  • It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
  • FIG. 1 illustrates a cross-sectional view of one embodiment of a semiconductor device 100. Semiconductor device 100 is fabricated using a wafer level packaging process. Semiconductor device 100 includes a semiconductor chip 106, at least one element 108, an adhesive material 114, a molding material 110, a redistribution layer 128, and solder balls 112. Adhesive material 114 covers at least a portion of each element 108. Molding material 110 encapsulates at least one side of each semiconductor chip 106 and at least one side of each element 108 and adhesive material 114. Adhesive material 114 provides stability to elements 108 during the molding process so that elements 108 are not shifted, misplaced, or tilted after the molding process. In one embodiment, adhesive material 114 includes Durimide, a polyimide, an elastomer, a thermoplastic, an epoxy, or another suitable adhesive.
  • Semiconductor chip 106 has a first face 105 and an opposing second face 107. Semiconductor chip 106 includes contacts 109 with an exposed surface on the same plane as opposing second face 107. Redistribution layer 128 also has a first face 124 and an opposing second face 122. First face 124 of redistribution layer 128 is attached along second face 107 of chip 106.
  • In one embodiment, each element 108 is a passive component. In one embodiment, each element 108 includes a resistor, a capacitor, an inductor, a conductor, a solder element, a conductive sphere, or another suitable passive component. In one embodiment, the volume of each element 108 is less than the volume of semiconductor chip 106 by at least a factor of two. In another embodiment, the height of each element 108 is greater than the height of chip 106 in the direction perpendicular to redistribution layer 128.
  • Redistribution layer 128 includes insulating material 116 and conductive traces 118, which electrically couple semiconductor chip 106 to at least one element 108. Further, conductive spheres or solder balls 112 can be electrically coupled to conductive traces 118 at second face 124 of redistribution layer 128. Conductive traces 118 include Cu or other suitable conductive material or conductive material stack. Insulating material 116 includes a polyimide, an epoxy, or another suitable dielectric material.
  • FIG. 2 illustrates a cross-sectional view of another embodiment of a semiconductor device 120. Semiconductor device 120 is similar to semiconductor device 100 previously described and illustrated with reference to FIG. 1, except that elements 108 are replaced with conductive spheres or solder elements or balls 138 in semiconductor device 120. In this embodiment, adhesive material 114 provides stability to solder elements 138 during the molding process so that solder elements 138 are not shifted or misplaced after the molding process. Solder elements 138 can be used for 3D-contacts from the front-side to the back-side of the package.
  • The following FIGS. 3 through 9B illustrate embodiments of a process for fabricating a semiconductor device. FIGS. 5A, 6A, 7A, 8A, and 9A illustrate one embodiment for fabricating a semiconductor device, such as semiconductor device 100 previously described and illustrated with reference to FIG. 1. FIGS. 5B, 6B, 7B, 8B, and 9B illustrate another embodiment for fabricating a semiconductor device, such as semiconductor device 120 previously described and illustrated with reference to FIG. 2.
  • FIG. 3 illustrates a cross-sectional view of one embodiment of a carrier 102. Carrier 102 includes a metal, a polymer, silicon, or another suitable material.
  • FIG. 4 illustrates a cross-sectional view of one embodiment of carrier 102 and a double-sided adhesive foil 104. A double-sided, releasable, adhesive foil 104 is laminated to carrier 102 or applied to carrier 102 using another suitable technique. In other embodiments, other suitable adhesives are used in place of adhesive foil 104.
  • FIG. 5A illustrates a cross-sectional view of one embodiment of carrier 102, double-sided adhesive foil 104, elements 108, and semiconductor chips 106. Each element 108 and each semiconductor chip 106 is placed on adhesive foil 104. In one embodiment, at least two semiconductor chips 106 and at least two elements 108 are placed on adhesive foil 104. In one embodiment, the area of the surface of each element 108 at the interface to adhesive foil 104 is less than the area of the surface of semiconductor chip 106 at the interface to adhesive foil 104.
  • FIG. 5B illustrates a cross-sectional view of one embodiment of carrier 102, double-sided adhesive foil 104, solder elements 138, and semiconductor chips 106. Each semiconductor chip 106 and each solder element 138 is placed on adhesive foil 104. In one embodiment, at least two semiconductor chips 106 and at least two solder elements 138 are placed on adhesive foil 104. Due to the non-planar or spherical form of solder elements 138, solder elements 138 have less surface area than semiconductor chips 106 for attachment to adhesive foil 104.
  • FIG. 6A illustrates a cross-sectional view of one embodiment of carrier 102, double-sided adhesive foil 104, elements 108, semiconductor chips 106, and adhesive material 114. In one embodiment, a dispensing needle 126 dispenses an adhesive material 114 to adhere each element 108 to adhesive foil 104. Adhesive material 114 includes an epoxy, a thermoplastic, a silicone, a polyimide, an elastomer, or another suitable material. Adhesive material 114 at least partially covers each element 108 and provides improved attachment of elements 108 to adhesive foil 104 prior to molding. In another embodiment, a printing process, a jetting process, or another suitable process is used to apply adhesive material 114 over or at each element 108.
  • Adhesive material 114 can then be cured by using any suitable form of energy (e.g., thermal, chemical) if a curing step is needed for the adhesive material. In one embodiment, semiconductor chip 106 is placed in close proximity to elements 108; thereby adhesive material 114 is also applied to at least one surface of semiconductor chip 106. In another embodiment, adhesive material 114 is applied to at least a portion of adhesive foil 104 before elements 108 are placed on adhesive foil 104. Elements 108 are then placed into adhesive material 114.
  • FIG. 6B illustrates a cross-sectional view of one embodiment of carrier 102, double-sided adhesive foil 104, solder elements 138, semiconductor chips 106, and adhesive material 114. In one embodiment, a dispensing needle dispenses an adhesive material 114 to adhere each solder element 138 to adhesive foil 104. Adhesive material 114 includes an epoxy or another suitable material. Adhesive material 114 at least partially covers each solder element 138 and provides improved attachment of solder elements 138 to adhesive foil 104 prior to molding. In another embodiment, a printing process, a jetting process, or another suitable process is used to apply adhesive material 114 over or at each solder element 138.
  • Adhesive material 114 can then be cured by using any suitable form of energy (e.g., thermal, chemical) if a curing step is needed for the adhesive material. In one embodiment, semiconductor chip 106 is placed in close proximity to solder elements 138; thereby adhesive material 114 is also applied to at least one surface of semiconductor chip 106. In another embodiment, adhesive material 114 is applied to at least a portion of adhesive foil 104 before solder elements 138 are placed on adhesive foil 104. Solder elements 138 are then placed into adhesive material 114.
  • FIG. 7A illustrates a cross-sectional view of one embodiment of carrier 102, double-sided adhesive foil 104, elements 108, semiconductor chips 106, adhesive material 114, and molding material 110. Adhesive material 114, elements 108, and semiconductor chips 106 are at least partially encapsulated by molding material 110. In one embodiment, the entire encapsulation process is performed by mold encapsulation. Carrier 102 is placed in a molding tool. A liquid mold compound having a high viscosity is dispensed in the center of carrier 102 where semiconductor chips 106 and elements 108 have been placed. The top of the molding tool is closed, causing the liquid mold compound to flow from the center to the edges of the molding tool. Flow of the mold compound applies forces on semiconductor chips 106 and elements 108. Due to adhesive material 114, however, elements 108 do not shift or tilt in response to the forces.
  • FIG. 7B illustrates a cross-sectional view of one embodiment of carrier 102, double-sided adhesive foil 104, solder elements 138, semiconductor chips 106, adhesive material 114, and molding material 110. Adhesive material 114, solder elements 138, and semiconductor chips 106 are at least partially encapsulated by molding material 110 using a similar process as described with reference to FIG. 7A. Due to adhesive material 114, solder elements 138 do not shift during the molding process.
  • FIG. 8A illustrates a cross-sectional view of one embodiment of elements 108, semiconductor chips 106, adhesive material 114, and molding material 110 after release of carrier 102 and double-sided adhesive foil 104. The release of adhesive foil 104 and carrier 102 is completed after application of molding material 110. One surface of each element 108 and each semiconductor chip 106 is exposed where adhesive foil 104 was previously attached.
  • FIG. 8B illustrates a cross-sectional view of one embodiment of solder elements 138, semiconductor chips 106, adhesive material 114, and molding material 110 after release of carrier 102 and double-sided adhesive foil 104. A surface of each solder element 138 and each semiconductor chip 106 is exposed where adhesive foil 104 was previously attached.
  • FIG. 9A illustrates a cross-sectional view of one embodiment of multiple semiconductor devices prior to singulation. A redistribution layer 128 is fabricated. Redistribution layer 128 includes conductive traces 118 formed in a conductive layer. Conductive traces 118 on first face 124 of redistribution layer 128 are electrically coupled to and directly contact semiconductor chips 106 and/or elements 108. Redistribution layer 128 also includes insulating material 116 surrounding conductive traces 118. Conductive spheres or solder balls 112 are electrically coupled to conductive traces 118 on second face 122 of redistribution layer 128.
  • The semiconductor devices are then separated from one another. The dashed line in FIG. 9A indicates where molding material 110 and redistribution layer 128 are cut to separate the semiconductor devices. Each semiconductor device includes a semiconductor chip 106 and at least one element 108. The semiconductor devices are separated by sawing, etching, or other suitable method to provide semiconductor devices 100 as previously described and illustrated with reference to FIG. 1.
  • FIG. 9B illustrates a cross-sectional view of another embodiment of multiple semiconductor devices prior to singulation. A redistribution layer 128 and conductive spheres or solder balls 112 are fabricated using a similar process as previously described with reference to FIG. 9A. The dashed line in FIG. 9B indicates where molding material 110 and redistribution layer 128 are cut to separate the semiconductor devices. Each semiconductor device includes a semiconductor chip 106 and at least one solder element 138. The semiconductor devices are separated by sawing, etching, or other suitable method to provide semiconductor devices 120 as previously described and illustrated with reference to FIG. 2.
  • Embodiments provide semiconductor devices using eWLB technology. Elements and/or solder balls are placed on adhesive foil in addition to semiconductor chips. Adhesive material is deposited over or at the elements and/or solder balls to provide increased stability and decreased displacement of the elements and/or solder balls during the molding process. After the adhesive material adheres to the elements and/or solder balls and the adhesive foil, the semiconductor chips, elements and/or solder balls, and adhesive material are encapsulated in mold material.
  • Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (20)

What is claimed is:
1. A semiconductor device comprising:
a chip;
at least one element electrically coupled to the chip;
an encapsulation material at least partially covering the chip, the encapsulation material directly contacting the chip; and
a planar redistribution layer consisting of one or more conductive traces and an insulating material, one of the conductive traces contacting the chip and the at least one element,
wherein the at least one element is laterally adjacent to the chip along a direction that is in a plane of an active surface of the chip.
2. The semiconductor device of claim 1, wherein the at least one element comprises one of a resistor, a capacitor, an inductor, a conductor, a solder element, and a conductive sphere.
3. The semiconductor device of claim 1, further comprising:
an array of solder elements electrically coupled to the redistribution layer.
4. The semiconductor device of claim 1, further comprising:
a redistribution layer electrically coupling the chip to the at least one element; and
an array of conductive spheres electrically coupled to the redistribution layer.
5. The semiconductor device of claim 1, wherein a volume of the at least one element is less than a volume of the chip by at least a factor of two.
6. The semiconductor device of claim 1, further comprising:
wherein in a direction perpendicular to the redistribution layer, a height of the at least one element is greater than a height of the chip.
7. The semiconductor device of claim 6, including a redistribution layer electrically coupling the chip to the at least one element.
8. The semiconductor device of claim 1, wherein one of the conductive traces directly contacts the semiconductor die and the component.
9. The semiconductor device of claim 1, wherein one of conductive traces directly connects the semiconductor die and the component.
10. A wafer level package comprising:
a semiconductor die;
a component;
a planar redistribution layer consisting of one or more conductive traces and an insulating material, one of the conductive traces contacting the semiconductor die and the component; and
a material encapsulating at least one side of the semiconductor die and at least one side of the component,
wherein the component is laterally adjacent to the semiconductor die with respect to the redistribution layer.
11. The package of claim 10, wherein the component comprises one of a resistor, a capacitor, an inductor, a conductor, a solder element, and a conductive sphere.
12. The package of claim 10, wherein a height of the component perpendicular to the redistribution layer is greater than a width of the component.
13. The package of claim 10, further comprising:
a plurality of solder balls electrically coupled to the redistribution layer.
14. The package of claim 10, further comprising:
an adhesive at least partially covering the at least one element; and
wherein the encapsulating material covers at least one side of the component and the adhesive material.
15. The package of claim 10, wherein one of the conductive traces directly contacts the semiconductor die and the component.
16. A semiconductor device comprising:
a chip;
at least one element electrically coupled to the chip;
an encapsulant at least partially covering the chip, the encapsulant directly contacting the chip; and
a planar redistribution layer consisting of conductive traces and an insulating material, one of the conductive traces contacting the chip and the at least one element,
wherein the at least one element is laterally adjacent to the chip along a direction that is in a plane of an active surface of the chip.
17. The semiconductor device of claim 16, further comprising:
an array of solder elements electrically coupled to the redistribution layer.
18. The semiconductor device of claim 16, further comprising:
a redistribution layer electrically coupling the chip to the at least one element; and
an array of conductive spheres electrically coupled to the redistribution layer.
19. The semiconductor device of claim 16, wherein a volume of the at least one element is less than a volume of the chip by at least a factor of two.
20. The semiconductor device of claim 16, further comprising:
wherein in a direction perpendicular to the redistribution layer, a height of the at least one element is greater than a height of the chip.
US14/189,304 2008-03-14 2014-02-25 Semiconductor device including at least one element Abandoned US20140175625A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711492B2 (en) 2014-12-09 2017-07-18 Intel Corporation Three dimensional structures within mold compound

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI528514B (en) * 2009-08-20 2016-04-01 精材科技股份有限公司 Chip package and fabrication method thereof
EP2337068A1 (en) * 2009-12-18 2011-06-22 Nxp B.V. Pre-soldered leadless package
US9117682B2 (en) * 2011-10-11 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and structures thereof
US8980687B2 (en) * 2012-02-08 2015-03-17 Infineon Technologies Ag Semiconductor device and method of manufacturing thereof
US9312193B2 (en) 2012-11-09 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies
US10163687B2 (en) 2015-05-22 2018-12-25 Qualcomm Incorporated System, apparatus, and method for embedding a 3D component with an interconnect structure
KR101982056B1 (en) * 2017-10-31 2019-05-24 삼성전기주식회사 Fan-out semiconductor package module
US10546817B2 (en) * 2017-12-28 2020-01-28 Intel IP Corporation Face-up fan-out electronic package with passive components using a support
CN110600432A (en) * 2019-05-27 2019-12-20 华为技术有限公司 Packaging structure and mobile terminal
CN110164839B (en) * 2019-05-27 2020-01-31 广东工业大学 Fan-out type packaging structure and method for embedding and transferring high-density lines

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US20020086500A1 (en) * 2000-12-30 2002-07-04 Siliconware Precision Industries, Co., Ltd. Semiconductor package and fabricating method thereof
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
US20070109757A1 (en) * 2005-04-28 2007-05-17 Stats Chippac Ltd. Integrated circuit package system with channel

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0287869A (en) * 1988-09-26 1990-03-28 Ricoh Co Ltd Zigzag array multichip type image sensor
US5866953A (en) 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US6313521B1 (en) * 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
US6756253B1 (en) * 1999-08-27 2004-06-29 Micron Technology, Inc. Method for fabricating a semiconductor component with external contact polymer support layer
KR100411811B1 (en) * 2001-04-02 2003-12-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package
US6998721B2 (en) * 2002-11-08 2006-02-14 Stmicroelectronics, Inc. Stacking and encapsulation of multiple interconnected integrated circuits
US7061123B1 (en) * 2004-05-03 2006-06-13 National Semiconductor Corporation Wafer level ball grid array
DE102004030813B4 (en) * 2004-06-25 2007-03-29 Infineon Technologies Ag Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
DE102005041452A1 (en) * 2005-08-31 2007-03-15 Infineon Technologies Ag Three-dimensional integrated electronic component and production process has chips, wafers or films with active and passive electronic components in embedded or printed circuits in many interconnected planes
EP2290682A3 (en) * 2005-12-14 2011-10-05 Shinko Electric Industries Co., Ltd. Package with a chip embedded between two substrates and method of manufacturing the same
US20080042265A1 (en) * 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
DE102006058068B4 (en) * 2006-12-07 2018-04-05 Infineon Technologies Ag Semiconductor component with semiconductor chip and passive coil component and method for its production
US7687895B2 (en) * 2007-04-30 2010-03-30 Infineon Technologies Ag Workpiece with semiconductor chips and molding, semiconductor device and method for producing a workpiece with semiconductors chips
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
US20020086500A1 (en) * 2000-12-30 2002-07-04 Siliconware Precision Industries, Co., Ltd. Semiconductor package and fabricating method thereof
US20070109757A1 (en) * 2005-04-28 2007-05-17 Stats Chippac Ltd. Integrated circuit package system with channel

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711492B2 (en) 2014-12-09 2017-07-18 Intel Corporation Three dimensional structures within mold compound
TWI619179B (en) * 2014-12-09 2018-03-21 美商英特爾公司 Three dimensional structures within mold compound

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US20160343616A1 (en) 2016-11-24
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US8659154B2 (en) 2014-02-25
US20090230553A1 (en) 2009-09-17

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