US20140217519A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
US20140217519A1
US20140217519A1 US13/989,297 US201213989297A US2014217519A1 US 20140217519 A1 US20140217519 A1 US 20140217519A1 US 201213989297 A US201213989297 A US 201213989297A US 2014217519 A1 US2014217519 A1 US 2014217519A1
Authority
US
United States
Prior art keywords
source
regions
halo
ldd
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US13/989,297
Other versions
US8802533B1 (en
Inventor
Changliang Qin
Huaxiang Yin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Assigned to Institute of Microelectronics, Chinese Academy of Sciences reassignment Institute of Microelectronics, Chinese Academy of Sciences ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: QIN, Changliang, YIN, HUAXLANG
Publication of US20140217519A1 publication Critical patent/US20140217519A1/en
Application granted granted Critical
Publication of US8802533B1 publication Critical patent/US8802533B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location

Definitions

  • the present disclosure relates to the field of semiconductor devices and manufacture thereof, and particularly, to a transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same.
  • the strained silicon technology has become a fundamental one, which improves performances of MOSFET devices by suppressing short channel effects and enhancing the mobility of carriers.
  • MOSFET devices For a PMOS device, it is common to form grooves in source and drain regions and then epitaxially grow SiGe therein, which applies compressive stress to press a channel region, so as to improve the performances of the PMOS device.
  • SiGe silicon germanium
  • NMOS device it is becoming popular to epitaxially grow Si:C in source and drain regions, to achieve the same object.
  • STI Shallow Trench Isolation
  • SPT Stress Proximity Technique
  • SiGe embedded source and drain stressed metallic gate
  • CEL Contact Etching Stop Layer
  • the ion implantation and annealing adopted in the conventional LDD and Halo processes may cause some problems. If the ion implantation is performed before the epitaxy in the source and drain regions, the implantation may cause crystal structures at surfaces of the source and drain grooves damaged, which has negative impacts on the following epitaxy in the source and drain regions. Otherwise, if the implantation is performed after the epitaxy in the source and drain regions, the implantation may cause the stress of the epitaxial layer released, resulting in reduced stress applied by the source and drain regions and thus degraded suppression of the SCE and DIBL effects. Further, a high temperature adopted in the annealing process may crystallize an amorphous layer formed by a pre-amorphization process. Furthermore, there is still a possibility that the TED (Transient Enhanced Diffusion) effect occurs and that doped elements cannot achieve a relatively high activation state.
  • TED Transient Enhanced Diffusion
  • the present disclosure aims to provide, among others, a semiconductor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same, by which it is possible to avoid problems in the prior art where the Halo and LDD regions are formed by ion implantation and annealing.
  • a method of manufacturing a semiconductor device for manufacturing a transistor comprising epitaxial LDD and Halo regions, the method comprising: providing a semiconductor substrate, forming STI arrangements on the semiconductor substrate, and performing well implantation; forming a gate dielectric layer and a gate electrode, and defining a gate pattern; forming a gate spacer which covers the top of the gate electrode and sidewalls of the gate electrode and the gate dielectric layer; forming source/drain grooves; epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the transistor, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material
  • the Halo regions each may have a thickness of 1 nm-100 nm, preferably 1 nm-10 nm.
  • the Halo regions may comprise Si or SiGe and the first doping element may comprise an N-type doping element, preferably P; and for an NMOS device, the Halo regions may comprise Si or Si:C and the first doping element may comprise a N-type doping element, preferably B.
  • the Halo regions may have a doping concentration of 1E13-1E21 cm ⁇ 3 , preferably 1E13-1E15 cm ⁇ 3 .
  • the LDD material layer may have a doping dose lower than that of the source/drain regions.
  • the doping dose of the LDD regions can be 1E13-1E15 cm ⁇ 3
  • the doping dose of the source/drain regions can be 1E15-1E20 cm ⁇ 3 .
  • the LDD regions may comprise Si or SiGe and can be doped with a P-type doping element, preferably B; and for an NMOS device, the LDD regions may comprise Si or Si:C and can be doped with an N-type doping element, preferably P.
  • forming the LDD regions may comprise: anisotropically etching exposed portions of the LDD material layer in a self-aligned manner after epitaxially growing the LDD material layer, to reserve only portions of the LDD material layer in the source/drain grooves directly under the gate spacer, wherein the reserved portions constitute the LDD regions; and further epitaxially growing the material for the source/drain regions, to compensate for loss of the source/drain regions in the etching.
  • forming the LDD regions may comprise: leaving the epitaxially grown LDD material layer as it is, without anisotropically etching it in a self-aligned manner; and further epitaxially growing the material for the source/drain regions, to raise the source/drain regions.
  • the gate electrode may comprise polysilicon.
  • the gate last process can be adopted. In this process, after formation of the metal silicide, the gate electrode of polysilicon is removed to form a gate void, into which metal is filled to form a metal gate.
  • the gate first process can be adopted. In this process, the gate electrode may comprise metal.
  • the method according to the present disclosure is applicable to the gate first or last process of high-K/metal gate.
  • a semiconductor device comprising a transistor comprising epitaxial LDD and Halo regions, the device comprising: a semiconductor substrate having STI arrangements and well regions formed thereon; a gate stack comprising a gate dielectric layer and a gate electrode; a gate spacer covering the top of the gate electrode and sidewalls of the gate electrode and the gate dielectric layer; source/drain grooves; epitaxially grown Halo regions located in the source/drain grooves, wherein the Halo regions have a first doping element therein; epitaxially grown source/drain regions which apply stress to a channel region of the transistor, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; epitaxially grown LDD regions at least partially located in the source/drain grooves directly under the gate spacer, wherein the LDD regions have a doping dose lower than that of the source/drain regions, and a doping type same as that of the
  • the Halo regions each may have a thickness of 1 nm-100 nm, preferably 1 nm-10 nm.
  • the Halo regions may comprise Si or SiGe and the first doping element may comprise an N-type doping element, preferably P; and for an NMOS device, the Halo regions may comprise Si or Si:C and the first doping element may comprise a N-type doping element, preferably B.
  • the Halo regions may have a doping concentration of 1E13-1E21 cm ⁇ 3 , preferably 1E13-1E15 cm ⁇ 3 .
  • the doping dose of the LDD regions can be 1E13-1E15 cm ⁇ 3
  • the doping dose of the source/drain regions can be 1E15-1E20 cm ⁇ 3 .
  • the LDD regions may comprise Si or SiGe and can be doped with a P-type doping element, preferably B; and for an NMOS device, the LDD regions may comprise Si or Si:C and can be doped with an N-type doping element, preferably P.
  • formation of the Halo and LDD regions is achieved by the epitaxy process and the self-aligned anisotropic etching process in combination, and thus it is possible to avoid problems in the prior art where the Halo and LDD regions are formed by ion implantation and annealing. It is possible to completely eliminate damages on crystal structures at surfaces of the source/drain grooves caused by the ion implantation, and thus avoid impacts on the following epitaxy of the material for the source/drain regions, without increasing the amount of photolithography masks and the complexity.
  • FIGS. 1-7 are schematic views showing a process of manufacturing a transistor comprising epitaxial LDD and Halo regions and structural aspects of the transistor.
  • CMOS transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same. Structural aspects of the device and a flow of the method will be described in detail with reference to FIGS. 1-7 , by way of example.
  • FIG. 7 is a schematic view showing a semiconductor device according to an embodiment of the present disclosure.
  • the semiconductor device comprises a semiconductor substrate 10 having STI arrangements 11 and well regions (not shown) formed thereon; a gate stack comprising a gate dielectric layer 12 and a gate electrode 13 ; a gate spacer 14 covering the top of the gate electrode 13 and sidewalls of the gate electrode 13 and the gate dielectric layer 12 ; source/drain grooves; epitaxially grown Halo regions 15 ′ located in the source/drain grooves, wherein the Halo regions have a first doping element therein; epitaxially grown source/drain regions 16 which apply stress to a channel region of the transistor, wherein the source/drain regions 16 have a second doping element, opposite in conductivity to the first doping element, therein; epitaxially grown LDD regions 18 at least partially located in the source/drain grooves directly under the gate spacer 14 , wherein the LDD regions 18 have a doping dose lower than that of the source/drain regions, and a doping type same as that of the source/drain regions; and source/drain contacts 19
  • STI Shallow
  • Trench Isolation arrangements 11 , and also a gate dielectric layer 12 , a gate electrode 13 , and a gate spacer 14 are formed.
  • the semiconductor substrate 10 such as a monocrystalline silicon substrate, is provided.
  • the semiconductor substrate 10 may comprise a Ge substrate or any other suitable substrate.
  • the STI arrangements 11 may be formed on the semiconductor substrate 10 by, for example, applying a photoresist layer on the semiconductor substrate 10 and patterning it into a pattern corresponding to the STI arrangements 11 , anisotropically etching the semiconductor substrate 10 to form shallow trenches, and then filling the shallow trenches with a dielectric material such as commonly used SiO 2 . After formation of the STI arrangements 11 , well implantation (not shown) can be performed.
  • a thin film layer of a high-K gate dielectric material may be deposited on a surface of the substrate 10 .
  • the high-K gate dielectric material has a higher relative permittivity than SiO 2 , and thus is more beneficial to performances of the transistor device.
  • the high-K gate dielectric material may comprise metal oxide, metal aluminate, and the like, such as HfO 2 , ZrO 2 , LaAlO 3 .
  • the gate dielectric layer 12 should be as thin as possible, preferably with a thickness of about 0.5-10 nm, while keeping its gate insulation property, and can be formed by deposition such as CVD. After formation of the gate dielectric layer 12 , a material for the gate electrode 13 is deposited.
  • the gate electrode 13 may comprise polysilicon, metal, metal silicide, and the like. In the gate first process, the gate electrode 13 generally comprises metal or metal silicide; while in the gate last process, the gate electrode 13 generally comprises polysilicon, which is replaced with metal or metal silicide after formation of other parts of the transistor device. After that, a photoresist layer is applied and then subjected to photolithography to define a gate pattern.
  • the gate electrode 13 and the gate dielectric layer 12 are sequentially etched according to the gate pattern.
  • the gate spacer 14 is formed by, for example, depositing a material for the spacer on the substrate 10 , such as SiO 2 and Si 3 N 4 , by means of a deposition process with a good conformality so that it covers the gate electrode 13 and the gate dielectric layer 12 with a desired thickness, and then removing portions of the spacer material on the surface of the substrate so that the spacer material is left only on top of the gate electrode 13 and on sidewalls of the gate electrode 13 and the gate dielectric layer 12 .
  • the gate spacer 14 surrounds the entire gate stack.
  • the gate spacer 14 may have a thickness of about 1 nm-100 nm, preferably 5 nm-50 nm. Subsequently, the semiconductor substrate 10 is anisotropically etched in a self-aligned manner with the STI arrangements 11 , the gate electrode 13 and the gate spacer 14 as a mask, to form source/drain grooves.
  • a Halo material layer 15 is epitaxially grown in the source/drain grooves.
  • the Halo material layer 15 may comprise Si or SiGe (for a PMOS device), or alternatively Si or Si:C (for an NMOS device).
  • the Halo material layer 15 may have a first doping element doped therein, with a doping concentration of about 1E13-1E21 cm ⁇ 3 , preferably 1E13-1E15 cm ⁇ 3 .
  • source/drain regions 16 is epitaxially grown selectively, as shown in FIG. 3 .
  • the source/drain regions 16 may comprise Si or SiGe (for a PMOS device), or alternatively Si or Si:C (for an NMOS device), to apply stress to a channel region of the
  • the source/drain regions can be doped in-situ with, for example, B (for a PMOS device) or P (for an NMOS device) into appropriate source/drain doping, while being epitaxially grown.
  • the source/drain regions 16 may be configured to apply compressive stress for a PMOS device, while tensile stress for an NMOS device.
  • the source/drain regions 16 may have a second doping element doped therein, which has a conductivity type opposite to the first doping element.
  • the Halo material layer 15 is be doped with N-type impurities such as P; or otherwise, if the source/drain regions 16 are doped with N-type impurities (for an NMOS device), then the Halo material layer 15 is be doped with P-type impurities such as B.
  • portions of the source/drain regions 16 are removed by anisotropic etching.
  • portions of the Halo material layer at SDE (Source Drain Extension) regions are also etched away.
  • the etching drills towards the channel region underlying the gate electrode to remove the portions of the Halo material layer directly under the gate spacer 14 , and extends to the channel region to some extent.
  • removal of the portions of the Halo material layer at the SDE regions will prevent a serial resistance at the SDE regions from being too large.
  • the Halo material layer with the portions etched away constitutes Halo regions 15 ′ of the transistor device, with a thickness of about 1 nm-100 nm, preferably 1 nm-10 nm.
  • an LDD material layer 17 is epitaxially grown to form LDD regions of the transistor device.
  • the LDD material layer 17 may have the same second doping element as the source/drain regions 16 .
  • the LDD regions may comprise Si or SiGe, doped with B; while for an NMOS device, the LDD regions may comprise Si or Si:C, doped with P.
  • the LDD material layer 17 may have a doping dose lower than that of the source/drain regions 16 .
  • the doping dose in the source/drain regions 16 may be about 1E15-1E20 cm ⁇ 3
  • the doping dose in the LDD material layer 17 may be about 1E13-1E15 cm ⁇ 3
  • the LDD regions may be formed by directly epitaxially growing the LDD material layer 17 in the source/drain grooves. That is, after epitaxy of the LDD material layer, self-aligned anisotropic etching is not performed. After that, the material for the source/drain regions is further epitaxially grown to raise the source/drain regions, so as to reduce a contact resistance. In this way, the LDD regions are positioned at least partially in the source/drain grooves directly under the gate spacer 14 (referring to the example shown in FIG.
  • the LDD regions may be formed as follows. Referring to FIG. 6 , after the LDD material layer 17 is epitaxially grown, exposed portions thereof may be anisotropically etched in a self-aligned manner. Due to presence of the gate spacer 14 , portions of the LDD material layer in the source/drain grooves directly under the gate spacer 14 are reserved. The reserved portions of the LDD material layer constitute the LDD regions 18 of the transistor device. After that, the material for the source/drain regions is further epitaxially grown in the source/drain grooves, so as to compensate for loss of the source/drain regions in the etching. In this way, the LDD regions are entirely positioned in the source/drain grooves directly under the gate spacer 14 .
  • the Halo regions and the LDD regions are achieved by means of epitaxy. Because formation of the Halo and LDD regions is achieved by the epitaxy process and the self-aligned anisotropic etching process in combination, it is possible to avoid problems in the prior art where the Halo and LDD regions are formed by ion implantation and annealing. It is possible to completely eliminate damages on crystal structures at the surfaces of the source/drain grooves caused by the ion implantation, and thus avoid impacts on the following epitaxy of the material for the source/drain regions, without increasing the amount of photolithography masks and the complexity.
  • the doped elements in the transistor device can be placed in a relatively high activation state. Also, it is possible to avoid potential crystallization of an amorphous layer formed by a pre-amorphization process and occurrence of the TED (Transient Enhanced Diffusion) effect.
  • source/drain contacts of metal silicide 19 can be formed.
  • the metal silicide may comprise NiSi, NiSiGe, TiSi, TiSiGe, and the like.
  • interconnection lines can be manufactured, if in the gate first process.
  • the already formed gate electrode of polysilicon can be removed and a gate electrode of metal or metal silicide can be formed instead, and then interconnection lines can be manufactured, if in the gate last process.

Abstract

A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed. According to embodiments of the present disclosure, the method may comprise: forming a gate stack on a semiconductor substrate; forming a gate spacer which covers the top of the gate stack and sidewalls of the gate stack; forming source/drain grooves; epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the Halo material layer constitute Halo regions of the device; and epitaxially growing an LDD material layer to form LDD regions of the device.

Description

    CROSS-REFERENCE TO RELATED APPLICATION(S)
  • The present application claims priority to Chinese Application No. 201210246830.3, entitled “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME,” filed on Jul. 16, 2012, which is incorporated herein by reference in its entirety.
    • TECHNICAL FIELD
  • The present disclosure relates to the field of semiconductor devices and manufacture thereof, and particularly, to a transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same.
    • BACKGROUND
  • After the semiconductor integrated circuit technology reaches the 90 nm node and beyond, it is becoming more and more challenging to maintain or even improve performances of transistor devices. At present, the strained silicon technology has become a fundamental one, which improves performances of MOSFET devices by suppressing short channel effects and enhancing the mobility of carriers. For a PMOS device, it is common to form grooves in source and drain regions and then epitaxially grow SiGe therein, which applies compressive stress to press a channel region, so as to improve the performances of the PMOS device. Likewise, for an NMOS device, it is becoming popular to epitaxially grow Si:C in source and drain regions, to achieve the same object. Specifically, various stress applying techniques, such as STI (Shallow Trench Isolation), SPT (Stress Proximity Technique), SiGe embedded source and drain, stressed metallic gate, and Contact Etching Stop Layer (CESL), have been proposed. Further, in small sized devices, it is common to adopt the LDD and Halo processes to suppress hot carrier effects and punch-through between the source and the drain. The LDD and Halo are generally achieved by means of ion implantation followed by annealing.
  • However, the ion implantation and annealing adopted in the conventional LDD and Halo processes may cause some problems. If the ion implantation is performed before the epitaxy in the source and drain regions, the implantation may cause crystal structures at surfaces of the source and drain grooves damaged, which has negative impacts on the following epitaxy in the source and drain regions. Otherwise, if the implantation is performed after the epitaxy in the source and drain regions, the implantation may cause the stress of the epitaxial layer released, resulting in reduced stress applied by the source and drain regions and thus degraded suppression of the SCE and DIBL effects. Further, a high temperature adopted in the annealing process may crystallize an amorphous layer formed by a pre-amorphization process. Furthermore, there is still a possibility that the TED (Transient Enhanced Diffusion) effect occurs and that doped elements cannot achieve a relatively high activation state.
  • In view of the above, there is a need for a novel transistor and a method of manufacturing the same, so as to more effectively guarantee the performances of the transistor.
    • SUMMARY
  • The present disclosure aims to provide, among others, a semiconductor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same, by which it is possible to avoid problems in the prior art where the Halo and LDD regions are formed by ion implantation and annealing.
  • According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, for manufacturing a transistor comprising epitaxial LDD and Halo regions, the method comprising: providing a semiconductor substrate, forming STI arrangements on the semiconductor substrate, and performing well implantation; forming a gate dielectric layer and a gate electrode, and defining a gate pattern; forming a gate spacer which covers the top of the gate electrode and sidewalls of the gate electrode and the gate dielectric layer; forming source/drain grooves; epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the transistor, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the Halo material layer constitute the Halo regions of the transistor; epitaxially growing an LDD material layer to form the LDD regions of the transistor; and forming source/drain contacts.
  • In an example of the present disclosure, the Halo regions each may have a thickness of 1 nm-100 nm, preferably 1 nm-10 nm.
  • In a further example of the present disclosure, for a PMOS device, the Halo regions may comprise Si or SiGe and the first doping element may comprise an N-type doping element, preferably P; and for an NMOS device, the Halo regions may comprise Si or Si:C and the first doping element may comprise a N-type doping element, preferably B.
  • In a further example of the present disclosure, the Halo regions may have a doping concentration of 1E13-1E21 cm−3, preferably 1E13-1E15 cm−3.
  • In a further example of the present disclosure, the LDD material layer may have a doping dose lower than that of the source/drain regions. For example, the doping dose of the LDD regions can be 1E13-1E15 cm−3, and the doping dose of the source/drain regions can be 1E15-1E20 cm−3.
  • In a further example of the present disclosure, for a PMOS device, the LDD regions may comprise Si or SiGe and can be doped with a P-type doping element, preferably B; and for an NMOS device, the LDD regions may comprise Si or Si:C and can be doped with an N-type doping element, preferably P.
  • In a further example of the present disclosure, forming the LDD regions may comprise: anisotropically etching exposed portions of the LDD material layer in a self-aligned manner after epitaxially growing the LDD material layer, to reserve only portions of the LDD material layer in the source/drain grooves directly under the gate spacer, wherein the reserved portions constitute the LDD regions; and further epitaxially growing the material for the source/drain regions, to compensate for loss of the source/drain regions in the etching.
  • Alternatively, forming the LDD regions may comprise: leaving the epitaxially grown LDD material layer as it is, without anisotropically etching it in a self-aligned manner; and further epitaxially growing the material for the source/drain regions, to raise the source/drain regions.
  • According to a further example of the present disclosure, the gate electrode may comprise polysilicon. Further, the gate last process can be adopted. In this process, after formation of the metal silicide, the gate electrode of polysilicon is removed to form a gate void, into which metal is filled to form a metal gate. Alternatively, the gate first process can be adopted. In this process, the gate electrode may comprise metal. Further, the method according to the present disclosure is applicable to the gate first or last process of high-K/metal gate.
  • According to a further aspect of the present disclosure, there is provided a semiconductor device, comprising a transistor comprising epitaxial LDD and Halo regions, the device comprising: a semiconductor substrate having STI arrangements and well regions formed thereon; a gate stack comprising a gate dielectric layer and a gate electrode; a gate spacer covering the top of the gate electrode and sidewalls of the gate electrode and the gate dielectric layer; source/drain grooves; epitaxially grown Halo regions located in the source/drain grooves, wherein the Halo regions have a first doping element therein; epitaxially grown source/drain regions which apply stress to a channel region of the transistor, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; epitaxially grown LDD regions at least partially located in the source/drain grooves directly under the gate spacer, wherein the LDD regions have a doping dose lower than that of the source/drain regions, and a doping type same as that of the source/drain regions; and source/drain contacts.
  • In an example of the present disclosure, the Halo regions each may have a thickness of 1 nm-100 nm, preferably 1 nm-10 nm.
  • In a further example of the present disclosure, for a PMOS device, the Halo regions may comprise Si or SiGe and the first doping element may comprise an N-type doping element, preferably P; and for an NMOS device, the Halo regions may comprise Si or Si:C and the first doping element may comprise a N-type doping element, preferably B.
  • In a further example of the present disclosure, the Halo regions may have a doping concentration of 1E13-1E21 cm−3, preferably 1E13-1E15 cm−3.
  • In a further example of the present disclosure, the doping dose of the LDD regions can be 1E13-1E15 cm−3, and the doping dose of the source/drain regions can be 1E15-1E20 cm−3.
  • In a further example of the present disclosure, for a PMOS device, the LDD regions may comprise Si or SiGe and can be doped with a P-type doping element, preferably B; and for an NMOS device, the LDD regions may comprise Si or Si:C and can be doped with an N-type doping element, preferably P.
  • According to embodiments of the present disclosure, formation of the Halo and LDD regions is achieved by the epitaxy process and the self-aligned anisotropic etching process in combination, and thus it is possible to avoid problems in the prior art where the Halo and LDD regions are formed by ion implantation and annealing. It is possible to completely eliminate damages on crystal structures at surfaces of the source/drain grooves caused by the ion implantation, and thus avoid impacts on the following epitaxy of the material for the source/drain regions, without increasing the amount of photolithography masks and the complexity. Further, according to embodiments of the present disclosure, there is no stress released due to the conventional ion implantation, so the stress in the source/drain regions and thus suppression of the SCE and DIBL effects thereby are guaranteed. Furthermore, according to embodiments of the present disclosure, because there is no annealing following the ion implantation, doped elements in the transistor device can be placed in a relatively high activation state. Also, it is possible to avoid potential crystallization of an amorphous layer formed by a pre-amorphization process and occurrence of the TED (Transient Enhanced Diffusion) effect.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-7 are schematic views showing a process of manufacturing a transistor comprising epitaxial LDD and Halo regions and structural aspects of the transistor.
    •  DETAILED DESCRIPTION
  • Hereinafter, descriptions are given with reference to embodiments shown in the attached drawings. However, it is to be understood that these descriptions are illustrative and not intended to limit the present disclosure. Further, in the following, known structures and technologies are not described to avoid obscuring the present disclosure unnecessarily.
  • According to embodiments of the present disclosure, there are provided a semiconductor device and a method of manufacturing the same, especially, a CMOS transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same. Structural aspects of the device and a flow of the method will be described in detail with reference to FIGS. 1-7, by way of example.
  • FIG. 7 is a schematic view showing a semiconductor device according to an embodiment of the present disclosure.
  • The semiconductor device comprises a semiconductor substrate 10 having STI arrangements 11 and well regions (not shown) formed thereon; a gate stack comprising a gate dielectric layer 12 and a gate electrode 13; a gate spacer 14 covering the top of the gate electrode 13 and sidewalls of the gate electrode 13 and the gate dielectric layer 12; source/drain grooves; epitaxially grown Halo regions 15′ located in the source/drain grooves, wherein the Halo regions have a first doping element therein; epitaxially grown source/drain regions 16 which apply stress to a channel region of the transistor, wherein the source/drain regions 16 have a second doping element, opposite in conductivity to the first doping element, therein; epitaxially grown LDD regions 18 at least partially located in the source/drain grooves directly under the gate spacer 14, wherein the LDD regions 18 have a doping dose lower than that of the source/drain regions, and a doping type same as that of the source/drain regions; and source/drain contacts 19.
  • Hereinafter, an exemplary method of manufacturing the semiconductor device will be described in detail.
  • Referring to FIG. 1, firstly, on a semiconductor substrate 10, STI (Shallow
  • Trench Isolation) arrangements 11, and also a gate dielectric layer 12, a gate electrode 13, and a gate spacer 14 are formed. Specifically, the semiconductor substrate 10, such as a monocrystalline silicon substrate, is provided. Alternatively, the semiconductor substrate 10 may comprise a Ge substrate or any other suitable substrate. The STI arrangements 11 may be formed on the semiconductor substrate 10 by, for example, applying a photoresist layer on the semiconductor substrate 10 and patterning it into a pattern corresponding to the STI arrangements 11, anisotropically etching the semiconductor substrate 10 to form shallow trenches, and then filling the shallow trenches with a dielectric material such as commonly used SiO2. After formation of the STI arrangements 11, well implantation (not shown) can be performed. For a PMOS device, the well implantation is achieve by implanting N-type impurities; while for an NMOS device, the well implantation is achieved by implanting P-type impurities. To form a gate stack comprising the gate dielectric layer 12 and the gate electrode 13, a thin film layer of a high-K gate dielectric material may be deposited on a surface of the substrate 10. The high-K gate dielectric material has a higher relative permittivity than SiO2, and thus is more beneficial to performances of the transistor device. The high-K gate dielectric material may comprise metal oxide, metal aluminate, and the like, such as HfO2, ZrO2, LaAlO3. The gate dielectric layer 12 should be as thin as possible, preferably with a thickness of about 0.5-10 nm, while keeping its gate insulation property, and can be formed by deposition such as CVD. After formation of the gate dielectric layer 12, a material for the gate electrode 13 is deposited. The gate electrode 13 may comprise polysilicon, metal, metal silicide, and the like. In the gate first process, the gate electrode 13 generally comprises metal or metal silicide; while in the gate last process, the gate electrode 13 generally comprises polysilicon, which is replaced with metal or metal silicide after formation of other parts of the transistor device. After that, a photoresist layer is applied and then subjected to photolithography to define a gate pattern. Then, the gate electrode 13 and the gate dielectric layer 12 are sequentially etched according to the gate pattern. Next, the gate spacer 14 is formed by, for example, depositing a material for the spacer on the substrate 10, such as SiO2 and Si3N4, by means of a deposition process with a good conformality so that it covers the gate electrode 13 and the gate dielectric layer 12 with a desired thickness, and then removing portions of the spacer material on the surface of the substrate so that the spacer material is left only on top of the gate electrode 13 and on sidewalls of the gate electrode 13 and the gate dielectric layer 12. As a result, the gate spacer 14 surrounds the entire gate stack. The gate spacer 14 may have a thickness of about 1 nm-100 nm, preferably 5 nm-50 nm. Subsequently, the semiconductor substrate 10 is anisotropically etched in a self-aligned manner with the STI arrangements 11, the gate electrode 13 and the gate spacer 14 as a mask, to form source/drain grooves.
  • Next, referring to FIG. 2, a Halo material layer 15 is epitaxially grown in the source/drain grooves. The Halo material layer 15 may comprise Si or SiGe (for a PMOS device), or alternatively Si or Si:C (for an NMOS device). The Halo material layer 15 may have a first doping element doped therein, with a doping concentration of about 1E13-1E21 cm−3, preferably 1E13-1E15 cm−3.
  • Then, source/drain regions 16 is epitaxially grown selectively, as shown in FIG. 3. The source/drain regions 16 may comprise Si or SiGe (for a PMOS device), or alternatively Si or Si:C (for an NMOS device), to apply stress to a channel region of the
  • MOS device so as to enhance the mobility of carriers. The source/drain regions can be doped in-situ with, for example, B (for a PMOS device) or P (for an NMOS device) into appropriate source/drain doping, while being epitaxially grown. The source/drain regions 16 may be configured to apply compressive stress for a PMOS device, while tensile stress for an NMOS device. Here, the source/drain regions 16 may have a second doping element doped therein, which has a conductivity type opposite to the first doping element. That is, if the source/drain regions 16 are doped with P-type impurities (for a PMOS device), then the Halo material layer 15 is be doped with N-type impurities such as P; or otherwise, if the source/drain regions 16 are doped with N-type impurities (for an NMOS device), then the Halo material layer 15 is be doped with P-type impurities such as B.
  • Next, referring to FIG. 4, portions of the source/drain regions 16 are removed by anisotropic etching. At the same time, portions of the Halo material layer at SDE (Source Drain Extension) regions (indicated by dashed-line circles in the drawing) are also etched away. The etching drills towards the channel region underlying the gate electrode to remove the portions of the Halo material layer directly under the gate spacer 14, and extends to the channel region to some extent. Here, removal of the portions of the Halo material layer at the SDE regions will prevent a serial resistance at the SDE regions from being too large. The Halo material layer with the portions etched away constitutes Halo regions 15′ of the transistor device, with a thickness of about 1 nm-100 nm, preferably 1 nm-10 nm.
  • Then, referring to FIG. 5, an LDD material layer 17 is epitaxially grown to form LDD regions of the transistor device. Here, the LDD material layer 17 may have the same second doping element as the source/drain regions 16. For example, for a PMOS device, the LDD regions may comprise Si or SiGe, doped with B; while for an NMOS device, the LDD regions may comprise Si or Si:C, doped with P. However, the LDD material layer 17 may have a doping dose lower than that of the source/drain regions 16. For example, the doping dose in the source/drain regions 16 may be about 1E15-1E20 cm−3, and the doping dose in the LDD material layer 17 may be about 1E13-1E15 cm−3. The LDD regions may be formed by directly epitaxially growing the LDD material layer 17 in the source/drain grooves. That is, after epitaxy of the LDD material layer, self-aligned anisotropic etching is not performed. After that, the material for the source/drain regions is further epitaxially grown to raise the source/drain regions, so as to reduce a contact resistance. In this way, the LDD regions are positioned at least partially in the source/drain grooves directly under the gate spacer 14 (referring to the example shown in FIG. 5). Alternatively, the LDD regions may be formed as follows. Referring to FIG. 6, after the LDD material layer 17 is epitaxially grown, exposed portions thereof may be anisotropically etched in a self-aligned manner. Due to presence of the gate spacer 14, portions of the LDD material layer in the source/drain grooves directly under the gate spacer 14 are reserved. The reserved portions of the LDD material layer constitute the LDD regions 18 of the transistor device. After that, the material for the source/drain regions is further epitaxially grown in the source/drain grooves, so as to compensate for loss of the source/drain regions in the etching. In this way, the LDD regions are entirely positioned in the source/drain grooves directly under the gate spacer 14.
  • Thus, the Halo regions and the LDD regions are achieved by means of epitaxy. Because formation of the Halo and LDD regions is achieved by the epitaxy process and the self-aligned anisotropic etching process in combination, it is possible to avoid problems in the prior art where the Halo and LDD regions are formed by ion implantation and annealing. It is possible to completely eliminate damages on crystal structures at the surfaces of the source/drain grooves caused by the ion implantation, and thus avoid impacts on the following epitaxy of the material for the source/drain regions, without increasing the amount of photolithography masks and the complexity. Further, according to embodiments of the present disclosure, there is no stress released due to the conventional ion implantation, so the stress in the source/drain regions and thus suppression of the SCE and DIBL effects thereby are guaranteed. Furthermore, according to embodiments of the present disclosure, because there is no annealing following the ion implantation, the doped elements in the transistor device can be placed in a relatively high activation state. Also, it is possible to avoid potential crystallization of an amorphous layer formed by a pre-amorphization process and occurrence of the TED (Transient Enhanced Diffusion) effect.
  • After that, the manufacture of the transistor device can continue conventionally. Referring to FIG. 7, source/drain contacts of metal silicide 19 can be formed. The metal silicide may comprise NiSi, NiSiGe, TiSi, TiSiGe, and the like.
  • After that, interconnection lines can be manufactured, if in the gate first process. Alternatively, the already formed gate electrode of polysilicon can be removed and a gate electrode of metal or metal silicide can be formed instead, and then interconnection lines can be manufactured, if in the gate last process.
  • From the foregoing, it will be appreciated that specific embodiments of the disclosure have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the technology is not limited except as by the appended claims.

Claims (17)

1. A method of manufacturing a semiconductor device, the method comprising:
forming a gate stack on a semiconductor substrate;
forming a gate spacer which covers the top of the gate stack and sidewalls of the gate stack;
forming source/drain grooves;
epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein;
epitaxially growing source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein;
isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the Halo material layer constitute Halo regions of the device; and
epitaxially growing an LDD material layer to form LDD regions of the device.
2-4. (canceled)
5. The method according to claim 1, wherein the LDD material layer has a doping dose lower than that of the source/drain regions.
6-7. (canceled)
8. The method according to claim 1, wherein forming the LDD regions comprises:
anisotropically etching exposed portions of the LDD material layer in a self-aligned manner after epitaxially growing the LDD material layer, to reserve only portions of the LDD material layer in the source/drain grooves directly under the gate spacer, wherein the reserved portions constitute the LDD regions; and
further epitaxially growing the material for the source/drain regions.
9. The method according to claim 1, further comprising:
further epitaxially growing the material for the source/drain regions on the epitaxially grown LDD material layer, to raise the source/drain regions.
10-12. (canceled)
13. A semiconductor device, comprising:
a semiconductor substrate;
a gate stack formed on the semiconductor substrate;
a gate spacer covering the top of the gate stack and sidewalls of the gate stack;
source/drain grooves;
epitaxially grown Halo regions located in the source/drain grooves, wherein the Halo regions have a first doping element therein;
epitaxially grown source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; and
epitaxially grown LDD regions at least partially located in the source/drain grooves directly under the gate spacer, wherein the LDD regions have a doping dose lower than that of the source/drain regions, and a doping type same as that of the source/drain regions.
14. The device according to claim 13, wherein the Halo regions each have a thickness of 1 nm-100 nm.
15. The device according to claim 13, wherein for a PMOS device, the Halo regions comprise Si or SiGe and the first doping element comprises an N-type doping element; and for an NMOS device, the Halo regions comprise Si or Si:C and the first doping element comprises a P-type doping element.
16. The device according to claim 13, wherein the Halo regions have a doping concentration of 1E13-1E21 cm−3.
17. The device according to claim 13, wherein the doping dose of the LDD regions is 1E13-1E15 cm−3, and the doping dose of the source/drain regions is 1E15-1E20 cm−3.
18. The device according to claim 13, wherein for a PMOS device, the LDD regions comprise Si or SiGe and are doped with a P-type doping element; and for an NMOS device, the LDD regions comprise Si or Si:C and are doped with an N-type doping element.
19. The device according to claim 14, wherein the Halo regions each have a thickness of 1 nm-10 nm.
20. The device according to claim 15, wherein the N-type doping element comprises P, and the P-type doping element comprises B.
21. The device according to claim 16, wherein the Halo regions have a doping concentration of 1E13-1E15 cm−3.
22. The device according to claim 18, wherein the P-type doping element comprises B, and the N-type doping element comprises P.
US13/989,297 2012-07-16 2012-07-30 Semiconductor device and method of manufacturing the same Expired - Fee Related US8802533B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201210246830.3A CN103545213B (en) 2012-07-16 2012-07-16 Semiconductor device and manufacture method thereof
CN201210246830.3 2012-07-16
CN201210246830 2012-07-16
PCT/CN2012/079352 WO2014012272A1 (en) 2012-07-16 2012-07-30 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
US20140217519A1 true US20140217519A1 (en) 2014-08-07
US8802533B1 US8802533B1 (en) 2014-08-12

Family

ID=49948199

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/989,297 Expired - Fee Related US8802533B1 (en) 2012-07-16 2012-07-30 Semiconductor device and method of manufacturing the same

Country Status (3)

Country Link
US (1) US8802533B1 (en)
CN (1) CN103545213B (en)
WO (1) WO2014012272A1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150129925A1 (en) * 2013-11-12 2015-05-14 Kabushiki Kaisha Toshiba Semiconductor device
US20150357436A1 (en) * 2014-06-10 2015-12-10 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US20160020325A1 (en) * 2014-07-21 2016-01-21 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof
US9343300B1 (en) * 2015-04-15 2016-05-17 Globalfoundries Inc. Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
US9397161B1 (en) * 2015-02-26 2016-07-19 International Business Machines Corporation Reduced current leakage semiconductor device
US20170098708A1 (en) * 2015-10-02 2017-04-06 United Microelectronics Corp. Semiconductor device
US20170162694A1 (en) * 2015-12-03 2017-06-08 International Business Machines Corporation Transistor and method of forming same
CN107123680A (en) * 2016-02-25 2017-09-01 台湾积体电路制造股份有限公司 Fin formula field effect transistor and its manufacture method
CN108962754A (en) * 2017-05-19 2018-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device and its manufacturing method
US20190334027A1 (en) * 2018-04-30 2019-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
CN111384143A (en) * 2018-12-27 2020-07-07 联芯集成电路制造(厦门)有限公司 Transistor structure
US11101143B2 (en) * 2016-02-18 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and manufacturing method thereof
US11362177B2 (en) * 2020-01-28 2022-06-14 Globalfoundries U.S. Inc. Epitaxial semiconductor material regions for transistor devices and methods of forming same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105261557A (en) * 2014-06-26 2016-01-20 中芯国际集成电路制造(上海)有限公司 Manufacturing method for semiconductor device, and semiconductor device
CN105819395B (en) * 2015-01-09 2017-09-05 中国科学院微电子研究所 Method, semi-conductor device manufacturing method
KR102455149B1 (en) * 2015-05-06 2022-10-18 삼성전자주식회사 Method for manufacturing semiconductor device
TWI668870B (en) * 2016-12-15 2019-08-11 財團法人工業技術研究院 Transistor device
CN109585546A (en) * 2017-09-29 2019-04-05 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN112447593B (en) * 2019-08-30 2024-03-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
KR20220020715A (en) 2020-08-12 2022-02-21 삼성전자주식회사 Integrated circuit device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070093033A1 (en) * 2005-10-24 2007-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Ultra shallow junction formation by solid phase diffusion
US7812394B2 (en) * 2005-01-04 2010-10-12 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US20130230952A1 (en) * 2012-03-01 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit device and method of manufacturing same
US20130299910A1 (en) * 2012-05-11 2013-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel semiconductor device fabrication

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274894B1 (en) * 1999-08-17 2001-08-14 Advanced Micro Devices, Inc. Low-bandgap source and drain formation for short-channel MOS transistors
US7402870B2 (en) * 2004-10-12 2008-07-22 International Business Machines Corporation Ultra shallow junction formation by epitaxial interface limited diffusion
US20090174002A1 (en) * 2008-01-09 2009-07-09 International Business Machines Corporation Mosfet having a high stress in the channel region
JP4911158B2 (en) * 2008-10-30 2012-04-04 ソニー株式会社 Semiconductor device and solid-state imaging device
CN101930923B (en) * 2009-06-26 2012-12-05 中芯国际集成电路制造(上海)有限公司 Fabrication method of MOS (Metal Oxide Semiconductor) transistor
US8357579B2 (en) * 2010-11-30 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812394B2 (en) * 2005-01-04 2010-10-12 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US20070093033A1 (en) * 2005-10-24 2007-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Ultra shallow junction formation by solid phase diffusion
US20130230952A1 (en) * 2012-03-01 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit device and method of manufacturing same
US20130299910A1 (en) * 2012-05-11 2013-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel semiconductor device fabrication

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150129925A1 (en) * 2013-11-12 2015-05-14 Kabushiki Kaisha Toshiba Semiconductor device
US9484443B2 (en) * 2013-11-12 2016-11-01 Kabushiki Kaisha Toshiba Semiconductor device
US20150357436A1 (en) * 2014-06-10 2015-12-10 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US20160020325A1 (en) * 2014-07-21 2016-01-21 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof
US9472668B2 (en) * 2014-07-21 2016-10-18 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof
US9397161B1 (en) * 2015-02-26 2016-07-19 International Business Machines Corporation Reduced current leakage semiconductor device
US20160254193A1 (en) * 2015-02-26 2016-09-01 International Business Machines Corporation Reduced current leakage semiconductor device
US20160254352A1 (en) * 2015-02-26 2016-09-01 International Business Machines Corporation Reduced current leakage semiconductor device
US9722031B2 (en) * 2015-02-26 2017-08-01 International Business Machines Corporation Reduced current leakage semiconductor device
US9627482B2 (en) * 2015-02-26 2017-04-18 International Business Machines Corporation Reduced current leakage semiconductor device
US9343300B1 (en) * 2015-04-15 2016-05-17 Globalfoundries Inc. Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
US9691901B2 (en) * 2015-10-02 2017-06-27 United Microelectronics Corp. Semiconductor device
US20170098708A1 (en) * 2015-10-02 2017-04-06 United Microelectronics Corp. Semiconductor device
US20170162694A1 (en) * 2015-12-03 2017-06-08 International Business Machines Corporation Transistor and method of forming same
US9911849B2 (en) * 2015-12-03 2018-03-06 International Business Machines Corporation Transistor and method of forming same
US11088280B2 (en) 2015-12-03 2021-08-10 International Business Machines Corporation Transistor and method of forming same
US11101143B2 (en) * 2016-02-18 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and manufacturing method thereof
CN107123680A (en) * 2016-02-25 2017-09-01 台湾积体电路制造股份有限公司 Fin formula field effect transistor and its manufacture method
CN108962754A (en) * 2017-05-19 2018-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device and its manufacturing method
US20190334027A1 (en) * 2018-04-30 2019-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US11309417B2 (en) * 2018-04-30 2022-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US11830947B2 (en) 2018-04-30 2023-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device and a semiconductor device
CN111384143A (en) * 2018-12-27 2020-07-07 联芯集成电路制造(厦门)有限公司 Transistor structure
US11362177B2 (en) * 2020-01-28 2022-06-14 Globalfoundries U.S. Inc. Epitaxial semiconductor material regions for transistor devices and methods of forming same

Also Published As

Publication number Publication date
CN103545213A (en) 2014-01-29
WO2014012272A1 (en) 2014-01-23
CN103545213B (en) 2016-12-28
US8802533B1 (en) 2014-08-12

Similar Documents

Publication Publication Date Title
US8802533B1 (en) Semiconductor device and method of manufacturing the same
US8278179B2 (en) LDD epitaxy for FinFETs
US8716090B2 (en) Semiconductor device manufacturing method
US9219152B2 (en) Semiconductor device with a buried stressor
US8557692B2 (en) FinFET LDD and source drain implant technique
US7745847B2 (en) Metal oxide semiconductor transistor
US7605407B2 (en) Composite stressors with variable element atomic concentrations in MOS devices
US7939413B2 (en) Embedded stressor structure and process
US10312155B2 (en) FinFET device and fabrication method thereof
US8912567B2 (en) Strained channel transistor and method of fabrication thereof
US8361895B2 (en) Ultra-shallow junctions using atomic-layer doping
US7323392B2 (en) High performance transistor with a highly stressed channel
US8486795B2 (en) Method of fabricating transistors
US20120068268A1 (en) Transistor structure and method of fabricating the same
JP2006278974A (en) Semiconductor device and manufacturing method thereof
US9209270B2 (en) MOS devices having non-uniform stressor doping
JP2006512766A5 (en)
WO2013173944A1 (en) Semiconductor device manufacturing method
US20110183487A1 (en) Strained Semiconductor Device and Method of Making Same
US20120049249A1 (en) Semiconductor structure and method for fabricating the same
JP2006319326A (en) E-SiGe AMALGAMATING SOI BOTTOM PREDOPING FOR DECREASING HEIGHT OF POLYSILICON
US9397190B2 (en) Fabrication method of semiconductor structure
US20080070360A1 (en) Method and structure for forming silicide contacts on embedded silicon germanium regions of cmos devices
CN103594420B (en) Method, semi-conductor device manufacturing method
US11444195B2 (en) Method for fabricating semiconductor device with asymmetric strained source/drain structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:QIN, CHANGLIANG;YIN, HUAXLANG;REEL/FRAME:030476/0903

Effective date: 20120810

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2551)

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: SMALL ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20220812