US20140311780A1 - Electronic component, method for manufacturing the same and method for manufacturing multilayer printed wiring board - Google Patents
Electronic component, method for manufacturing the same and method for manufacturing multilayer printed wiring board Download PDFInfo
- Publication number
- US20140311780A1 US20140311780A1 US14/259,522 US201414259522A US2014311780A1 US 20140311780 A1 US20140311780 A1 US 20140311780A1 US 201414259522 A US201414259522 A US 201414259522A US 2014311780 A1 US2014311780 A1 US 2014311780A1
- Authority
- US
- United States
- Prior art keywords
- layer
- insulation layer
- electronic component
- alignment mark
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 54
- 239000010410 layer Substances 0.000 claims abstract description 343
- 238000009413 insulation Methods 0.000 claims abstract description 212
- 239000012790 adhesive layer Substances 0.000 claims abstract description 59
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 54
- 239000000853 adhesive Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- 239000000945 filler Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 5
- 239000011888 foil Substances 0.000 claims description 4
- 239000004840 adhesive resin Substances 0.000 claims description 3
- 229920006223 adhesive resin Polymers 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 27
- 229920005989 resin Polymers 0.000 description 19
- 239000011347 resin Substances 0.000 description 19
- 239000011889 copper foil Substances 0.000 description 12
- 239000000654 additive Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 206010034972 Photosensitivity reaction Diseases 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 229920001955 polyphenylene ether Polymers 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- 229920005668 polycarbonate resin Polymers 0.000 description 3
- 239000004431 polycarbonate resin Substances 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 125000003903 2-propenyl group Chemical group [H]C([*])([H])C([H])=C([H])[H] 0.000 description 2
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- -1 for example Substances 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005862 polyol Polymers 0.000 description 2
- 150000003077 polyols Chemical class 0.000 description 2
- 229920013636 polyphenyl ether polymer Polymers 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000004696 Poly ether ether ketone Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- JUPQTSLXMOCDHR-UHFFFAOYSA-N benzene-1,4-diol;bis(4-fluorophenyl)methanone Chemical compound OC1=CC=C(O)C=C1.C1=CC(F)=CC=C1C(=O)C1=CC=C(F)C=C1 JUPQTSLXMOCDHR-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012766 organic filler Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920002530 polyetherether ketone Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/166—Alignment or registration; Control of registration
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Definitions
- the present invention relates to an electronic component, a method for manufacturing the same and a method for manufacturing a multilayer printed wiring board.
- a multilayer printed wiring board in international patent publication 2007/129545 has a built-in multilayer substrate in which conductive patterns are formed at a fine pitch. Through the built-in multilayer substrate, the lead terminals of an IC chip to be mounted are electrically connected to the circuits formed in the multilayer printed wiring board. In such a multilayer printed wiring board, the multilayer substrate is positioned in the portion where the IC chip is to be mounted, thereby enabling finer wiring in that portion. Accordingly, an IC chip with lead terminals arrayed at fine intervals is mounted accurately.
- the contents of international patent publication 2007/129545 are incorporated herein in this application.
- an electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer.
- the adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.
- a method for manufacturing an electronic component includes forming an insulation layer having an alignment mark on a first surface of the insulation layer, forming an adhesive layer including an optically opaque agent on the first surface of the insulation layer or a second surface of the insulation layer on an opposite side with respect to the first surface of the insulation layer, and forming an opening portion in the adhesive layer at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.
- a method for manufacturing a multilayer printed wiring board includes forming a buildup layer including insulation layers and conductive layers, positioning an electronic component having an alignment mark to a position on a surface of the buildup layer based on the alignment mark of the electronic component, mounting the electronic component to the surface of the buildup layer in the position, and forming an outer insulation layer on the surface of the buildup layer such that the outer insulation layer covers the electronic component mounted on the surface of the buildup layer.
- the electronic component has an insulation layer, the alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer, and the adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.
- FIG. 1 shows a cross-sectional view of the entire structure of a multilayer printed wiring board according to an embodiment of the present invention and also shows an enlarged view of the main portion;
- FIG. 2 is a cross-sectional view showing an electronic component according to an embodiment of the present invention.
- FIG. 3 is a bottom view showing the electronic component according to an embodiment of the present invention.
- FIG. 4 is a flowchart showing a method for manufacturing the electronic component according to an embodiment of the present invention.
- FIG. 5 is a view illustrating a step for preparing a support body
- FIG. 6 is a view illustrating a step for forming an insulation layer
- FIG. 7 is a view illustrating a step subsequent to the step in FIG. 6 ;
- FIG. 8 is a view illustrating a step for forming an alignment mark
- FIG. 9 is a view illustrating a step subsequent to the step in FIG. 8 ;
- FIG. 10 is a view illustrating a step for forming a via hole
- FIG. 11 is a view illustrating a step for forming a via conductor and a conductive layer
- FIG. 12 is a view illustrating a step for forming a conductive pattern
- FIG. 13 is a view illustrating a step for removing the support body
- FIG. 14 is a view illustrating a step for forming an adhesive layer
- FIG. 15 is a view illustrating a step for forming an opening portion
- FIG. 16 is a flowchart showing a method for manufacturing a multilayer printed wiring board according to another embodiment of the present invention.
- FIG. 17 is a view illustrating a step for preparing a core substrate
- FIG. 18 is a view illustrating a step for forming a through hole
- FIG. 19 is a view illustrating a step for forming a through-hole conductor
- FIG. 20 is a view illustrating a step for forming a conductive pattern
- FIG. 21 is a view illustrating a step for forming a buildup layer
- FIG. 22 is a view illustrating a step for mounting an electronic component on the substrate
- FIG. 23 shows schematic views of a method for aligning an electronic component with respect to the substrate
- FIG. 24 is a view illustrating a state in which an electronic component is mounted on the substrate
- FIG. 25 is a view illustrating a step subsequent to the step in FIG. 22 ;
- FIG. 26 shows a cross-sectional view of the entire structure of a multilayer printed wiring board according to a first modified example of an embodiment of the present invention and also shows an enlarged view of the main portion;
- FIG. 27 is a view illustrating a method for manufacturing a multilayer printed wiring board according to the first modified example
- FIG. 28 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the first modified example
- FIG. 29 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the first modified example
- FIG. 30 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the first modified example
- FIG. 31 shows a cross-sectional view of the entire structure of a multilayer printed wiring board according to a second modified example of an embodiment of the present invention and also shows an enlarged view of the main portion;
- FIG. 32 is a view illustrating a method for manufacturing a multilayer printed wiring board according to the second modified example
- FIG. 33 shows views illustrating the method for manufacturing a multilayer printed wiring board according to the second modified example
- FIG. 34 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the second modified example
- FIG. 35 is a bottom view showing the electronic component according to the first modified example of an embodiment of the present invention.
- FIG. 36 is a bottom view showing the electronic component according to the second modified example of an embodiment of the present invention.
- FIG. 37 is a flowchart showing another method for manufacturing the electronic component according to an embodiment of the present invention.
- FIG. 38 is a cross-sectional view showing an electronic component according to an embodiment of the present invention.
- FIG. 39 is a view illustrating a step for preparing a support body
- FIG. 40 is a view illustrating a step for forming a conductive circuit
- FIG. 41 is a view illustrating a step for forming an insulation layer
- FIG. 42 is a view illustrating a step for forming a via hole
- FIG. 43 is a view illustrating a step forming a via conductor and a conductive pattern
- FIG. 44 is a view illustrating a step for removing a support body
- FIG. 45 is a view illustrating a step for forming an adhesive layer.
- FIG. 46 is a view illustrating a step for forming an opening portion.
- XYZ coordinates are set and referred to appropriately.
- Arrow (Z) indicates a lamination direction of an electronic component or a multilayer printed wiring board (or a thickness direction of the electronic component and the multilayer printed wiring board) corresponding to a direction along a normal line to main surfaces (upper and lower surfaces) of the electronic component and the multilayer printed wiring board.
- arrows (X) and (Y) each indicate a direction perpendicular to a lamination direction (or a direction toward a side of each layer).
- the main surfaces of the electronic component and the multilayer printed wiring board are on the (X-Y) plane.
- Side surfaces of the electronic component and the multilayer printed wiring board are on the (X-Z) plane or the (Y-Z) plane.
- Optically transparent indicates that the transmission coefficient of light rays going through the subject is 70% or higher, for example, and “optically opaque” indicates that the transmission coefficient of the light rays is lower than 70%, for example.
- Light rays include visible rays, infrared rays and ultraviolet rays. What is generally referred to as “semi-transparent” is included in the term “optically opaque.”
- Platinum indicates a step for forming a metal layer, but also includes the resultant metal and metal layer.
- Plating includes wet plating such as electroless plating and electrolytic plating as well as dry plating such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).
- Conductive patterns include wiring of a conductive circuit (including ground), a pad, a land, a via conductor or the like, or may also include a plain conductive pattern that does not form a conductive circuit.
- Holes are not limited to penetrating holes, but also include non-penetrating holes. Holes include a via hole, a through hole and the like.
- the conductor formed in a via hole is referred to as a via conductor, and the conductor formed in a through hole is referred to as a through-hole conductor.
- Multilayer printed wiring board 100 of the present embodiment has core substrate 120 , first buildup layer (B1), second buildup layer (B2), solder-resist layer 135 and solder-resist layer 132 , as shown in the (X-Z) cross section in FIG. 1 .
- First buildup layer (B1) has conductive pattern 121 , insulation layer 123 , via conductor ( 141 b ), conductive pattern 125 , insulation layer 127 , via conductor ( 143 b ), conductive pattern 129 , insulation layer 131 , via conductor ( 145 b ) and conductive pattern 133 .
- Electronic component 10 is mounted inside insulation layer 131 .
- Core substrate 120 is made of, for example, glass-epoxy resin (hereinafter referred to as “glass epoxy”).
- hole ( 140 a ) (through hole) is formed by using laser light, for example.
- Core substrate 120 has through-hole conductor ( 140 b ) formed by filling copper plating, for example, in hole ( 140 a ).
- Through-hole conductor ( 140 b ) electrically connects first main-surface side conductive pattern 121 and second main-surface side conductive pattern 122 .
- Insulation layer 124 is formed to cover conductive pattern 122 . Via conductor ( 142 b ) is formed in insulation layer 124 to penetrate through insulation layer 124 . Conductive pattern 126 is formed on the second main-surface side of insulation layer 124 . Conductive pattern 126 is connected to via conductor ( 142 b ). Insulation layer 128 is formed to cover conductive pattern 126 . Via conductor ( 144 b ) is formed in insulation layer 128 to penetrate through insulation layer 128 . Conductive pattern 130 is formed on the second main-surface side of insulation layer 128 . Conductive pattern 130 is connected to via conductor ( 144 b ).
- Second buildup layer (B2) is made up of conductive pattern 122 , insulation layer 124 , via conductor ( 142 b ), conductive pattern 126 , insulation layer 128 , via conductor ( 144 b ) and conductive pattern 130 .
- solder-resist layer 132 is formed, having exposing portion ( 132 a ) to expose conductive pattern 130 .
- the exposed portion of conductive pattern 130 becomes pad 136 .
- Main portion (A1) of multilayer printed wiring board 100 of the present embodiment is enlarged and shown in the lower portion of FIG. 1 .
- insulation layer 123 is formed to cover conductive pattern 121 formed on the first main-surface side of core substrate 120 in multilayer printed wiring board 100 of the present embodiment.
- Via conductor ( 141 b ) is formed in insulation layer 123 to penetrate through insulation layer 123 .
- Conductive pattern 125 is formed on the first main-surface side of insulation layer 123 .
- Conductive pattern 125 is connected to via conductor ( 141 b ).
- Insulation layer 127 is formed to cover conductive pattern 125 .
- Via conductor ( 143 b ) is formed in insulation layer 127 to penetrate through insulation layer 127 .
- Conductive pattern 129 is formed on the first main-surface side of insulation layer 127 .
- Conductive pattern 129 is connected to via conductor ( 143 b ).
- electronic component 10 is mounted on the first main-surface side of insulation layer 127 .
- Insulation layer 131 is formed to cover conductive pattern 129 and electronic component 10 .
- Via conductor ( 145 b ) is formed in insulation layer 131 to penetrate through insulation layer 131 .
- FIG. 2 is a cross-sectional view cut through the (2-2) line in FIG. 3 .
- electronic component ( 10 a ) of the present embodiment has adhesive layer 12 with opening portion 15 , insulation layer 13 , alignment mark 14 , wiring 11 with a finer wiring pitch than that of the wiring in multilayer printed wiring board 100 (hereinafter also simply referred to as “wiring with a finer wiring pitch”), insulation layer 16 , via conductor ( 16 b ), and conductive pattern 17 .
- Wiring 11 with a finer wiring pitch and alignment mark 14 are formed on insulation layer 13 using the same material, for example, copper plating.
- the same material for example, copper plating.
- the planar shape (shape on the (X-Y) plane) of electronic component ( 10 a ) is substantially rectangular.
- Two alignment marks 14 are respectively positioned near opposing corners of electronic component ( 10 a ) (see FIG. 3 ).
- Adhesive layer 12 is formed using an adhesive agent containing filler mixed in an adhesive resin material so as to reduce its coefficient of thermal expansion (CTE).
- CTE coefficient of thermal expansion
- inorganic fillers such as silica filler and alumina filler are thought to be preferable.
- organic filler may also be used instead of inorganic filler.
- adhesive resin material are epoxy resin, polyester resin, bismaleimide triazine resin (BT resin), polyimide resin, phenol resin and allyl polyphenylene ether resin (A-PPE resin) and the like.
- adhesive layer 12 is optically opaque.
- Insulation layer 13 is an optically transparent layer.
- opening portion 15 is formed under alignment mark 14 .
- wiring 11 is formed to have a finer wiring pitch than that of the wiring in multilayer printed wiring board 100 .
- opening portion 15 has disappeared from electronic component 10 mounted inside insulation layer 131 .
- Via conductor ( 147 b ) is connected to conductive pattern 17 formed on the first main-surface side of electronic component 10 .
- Conductive pattern 133 is formed on the first main-surface side of via conductor ( 145 b ) and via conductor ( 147 b ).
- solder-resist layer 135 with exposing portion ( 135 a ) to expose conductive pattern 133 is formed on the first main-surface side of insulation layer 131 .
- solder-resist layer 135 with exposing portion ( 135 a ) to expose conductive pattern 133 is formed on the first main-surface side of insulation layer 131 .
- solder-resist layer 135 with exposing portion ( 135 a ) to expose conductive pattern 133 is formed on the first main-surface side of insulation layer 131 .
- the exposed portion of conductive pattern 133 becomes pad 137 .
- FIG. 3 shows a bottom view of electronic component ( 10 a ) of the present embodiment.
- the planar shape of electronic component ( 10 a ) is rectangular, for example, and length (d1) of the longer side is 4 ⁇ 50 mm, for example. Length (d2) of the shorter side is 1 ⁇ 20 mm, for example.
- the thickness of adhesive layer 12 is 3 ⁇ 20 ⁇ m, for example.
- the thickness of insulation layer 13 is 1 ⁇ 10 ⁇ m, for example.
- opening portion 15 of electronic component ( 10 a ) is formed in a position and a size so as to entirely show alignment mark 14 when seen from the bottom side.
- the size of alignment mark 14 is 150 ⁇ 500 ⁇ m, for example.
- Opening portion 15 is shaped substantially as a circle, and the diameter is 300 ⁇ 700 ⁇ m, for example.
- electronic component ( 10 a ) is manufactured by a method shown in FIG. 4 .
- support body 400 is prepared as shown in FIG. 5 .
- Support body 400 is made of glass, for example.
- adhesive support layer 402 is formed on support body 400 .
- insulation layer 13 is formed on support body 400 with support layer 402 disposed in between.
- insulation layer 13 is positioned on the first main-surface side of support layer 402 , as shown in FIG. 6 .
- Insulation layer 13 and support layer 402 are adhered by applying heat, for example.
- Insulation layer 13 is optically transparent, and is made of a transparent resin, for example.
- the transparent resin epoxy resin, phenol resin, polyol resin, polycarbonate resin and the like may be used.
- step (S 13 ) of FIG. 4 wiring 11 with a finer wiring pitch and alignment mark 14 are formed on the first main-surface side of insulation layer 13 .
- conductive layer ( 14 a ) is formed on the first main-surface side of insulation layer 13 using a subtractive method, for example.
- a subtractive method for example.
- forming conductive layer ( 14 a ) is not limited to a subtractive method, and a full-additive method or semi-additive method (SAP) may also be employed.
- conductive layer ( 14 a ) is patterned by a subtractive method, for example, forming alignment mark 14 and wiring 11 with a finer wiring pitch.
- forming alignment mark 14 and wiring 11 with a finer wiring pitch is not limited to a subtractive method, and a full-additive method or semi-additive method may also be employed.
- step (S 14 ) of FIG. 4 insulation layer 16 is formed.
- insulation layer 16 is laminated on insulation layer 13 to cover wiring 11 with a finer wiring pitch and alignment mark 14 .
- step (S 15 ) of FIG. 4 via conductor ( 16 b ) and a conductive layer are formed.
- hole ( 16 a ) via hole is formed in insulation layer 16 by irradiating laser light, for example. Hole ( 16 a ) reaches wiring 11 with a finer wiring pitch.
- electroless plating and electrolytic plating are performed using copper, for example, thereby filling hole ( 16 a ) to form via conductor ( 16 b ) while forming conductive layer 1000 on insulation layer 16 .
- step (S 16 ) of FIG. 4 conductive pattern 17 is formed.
- conductive layer 1000 is patterned by etching, for example, thereby forming conductive pattern 17 .
- step (S 17 ) of FIG. 4 support body 400 is removed.
- support layer 402 is softened by applying heat, for example, and support body 400 is slid in a direction X (or a direction Y) so that support body 400 is removed from the second main surface of insulation layer 13 .
- FIG. 13 shows the cross section after support body 400 has been removed. After support body 400 is removed from insulation layer 13 , if part of support layer 402 remains on the second main surface of insulation layer 13 , cleaning is conducted to remove the remaining portion of support layer 402 . Support body 400 is recyclable.
- step (S 18 ) of FIG. 4 adhesive layer 12 is formed.
- adhesive layer 12 is laminated on the second main-surface side (lower surface) of insulation layer 13 by coating an adhesive agent containing filler, for example.
- the adhesive agent for forming adhesive layer 12 is photosensitive. Accordingly, opening portion 15 is formed precisely at a predetermined portion in the next step for forming opening portion 15 .
- opening portion 15 is formed in adhesive layer 12 .
- the adhesive agent at a portion of adhesive layer 12 located under alignment mark 14 is photosensitized and denatured by photolithography, for example. Then, using a removing solution, for example, the photosensitized and denatured portion ( 12 a ) is removed, thereby forming opening portion 15 (see FIG. 2 ).
- opening portion 15 of the present embodiment is formed by uniformly forming adhesive layer 12 first and by removing part of the adhesive agent. Therefore, opening portion 15 is accurately formed at a predetermined portion while adhesive layer 12 is formed to have a uniform thickness.
- electronic component ( 10 a ) of the present embodiment is completed as shown in FIG. 2 .
- the manufacturing method of the present embodiment is suitable for manufacturing electronic component ( 10 a ). Using such a manufacturing method, an excellent electronic component ( 10 a ) is achieved, in which positional shifting is suppressed between alignment mark 14 and opening portion 15 .
- multilayer printed wiring board 100 is manufactured by employing a method shown in FIG. 16 .
- core substrate 120 is prepared as shown in FIG. 17 .
- Core substrate 120 is made of glass epoxy, for example. More specifically, double-sided copper foil laminate 3000 is prepared where a metal foil such as copper foil 3001 is laminated on first main surface (F1) of core substrate 120 and metal foil such as copper foil 3002 is laminated on second main surface (F2).
- step (S 22 ) of FIG. 16 through-hole conductor ( 140 b ) and conductive layers are formed.
- double-sided copper foil laminate 3000 is bored by irradiating laser light, for example, at both surfaces of double-sided copper foil laminate 3000 .
- hole 3003 and hole 3004 formed respectively from both sides are connected to be one hole, making hole ( 140 a ) (through hole).
- electroless plating and electrolytic platings ( 3003 , 3004 ) are performed using copper, for example, in hole ( 140 a ) and on copper foils ( 3001 , 3002 ) so that through-hole conductor ( 140 b ) and conductive layers are formed.
- conductive layers are patterned by etching, for example. Accordingly, as shown in FIG. 20 , conductive pattern 121 on first main surface (F1) and conductive pattern 122 on second main surface (F2) are formed respectively on core substrate 120 .
- step (S 23 ) of FIG. 16 buildup layers are respectively formed on both surfaces of core substrate 120 .
- part of buildup layer (B1) (insulation layer 123 , via conductor ( 141 b ), conductive pattern 125 , insulation layer 127 , via conductor ( 143 b ) and conductive pattern 129 ) are formed on the first main-surface side of core substrate 120 .
- buildup layer (B2) and solder-resist layer 132 are formed on the second main-surface side of substrate 120 . Accordingly, substrate ( 100 a ) for mounting electronic component ( 10 a ) above is formed.
- step (S 24 ) of FIG. 16 electronic component ( 10 a ) is mounted on a predetermined position, which is part of buildup layer (B1) above.
- electronic component ( 10 a ) is adhered to insulation layer 127 of substrate ( 100 a ) by being aligned from the (+Z) direction.
- camera unit 300 is located between electronic component ( 10 a ) adsorbed and held horizontally by vacuum adsorption device 200 and substrate ( 100 a ) positioned horizontally.
- Camera unit 300 is provided with CCD cameras on its first and second main surfaces.
- the CCD camera on the first main surface is capable of image recognition in arrow 301 direction (+Z direction).
- the CCD camera on the second main surface is capable of image recognition in arrow 302 direction ( ⁇ Z direction).
- Camera unit 300 is movable along the (X-Y) plane as shown by arrows 303 .
- the first main-surface side CCD camera recognizes alignment mark 14 and the second main-surface side CCD camera recognizes the alignment mark (omitted from the drawing) formed on the first main surface of substrate ( 100 a ). Accordingly, the relative position of electronic component ( 10 a ) in directions (X and Y) with respect to substrate ( 100 a ) is calculated. Based on the calculated result, vacuum adsorption device 200 moves along the (X-Y) plane so that electronic component ( 10 a ) is aligned at a predetermined position (coordinates (X, Y)) with respect to substrate ( 100 a ).
- the first main-surface side CCD camera of camera unit 300 captures the image of alignment mark 14 through optically opaque adhesive layer 12 .
- alignment mark 14 may be blurred, resulting in recognition failure.
- opening portion 15 is formed under alignment mark 14 .
- the first main-surface side CCD camera of camera unit 300 captures the image of alignment mark 14 only through optically transparent insulation layer 13 . Therefore, alignment mark 14 is unlikely to be blurred, thereby enabling camera unit 300 to securely recognize alignment mark 14 . Accordingly, electronic component ( 10 a ) is precisely aligned to a predetermined position with respect to substrate ( 100 a ).
- camera unit 300 moves along the (X-Y) plane and retracts to the outside of electronic component ( 10 a ) and substrate ( 100 a ).
- vacuum adsorption device 200 moves in direction ( ⁇ Z) so that electronic component ( 10 a ) is pushed against substrate ( 100 a ).
- adhesive layer 12 of electronic component ( 10 a ) is adhered to the first main surface of substrate ( 100 a ), and electronic component ( 10 a ) is mounted on substrate ( 100 a ).
- adhesive agent of adhesive layer 12 flows and fills opening 15 , adhesive layer 12 is adhered to the entire surface of substrate ( 100 a ). Accordingly, electronic component 10 is mounted on a predetermined position of substrate ( 100 a ), as shown in FIG. 24 .
- step (S 25 ) of FIG. 16 buildup layer (B1) is completed.
- insulation layer 131 is formed to cover electronic component 10 .
- via conductors ( 145 b , 147 b ) each penetrating through insulation layer 131 are formed in insulation layer 131 , and conductive pattern 133 is formed to be connected to via conductors ( 145 b , 147 b ). Accordingly, buildup layer (B1) is completed.
- the number of layers (three) of interlayer materials in buildup layer (B1) is different from the number of layers (two) of interlayer materials in buildup layer (B2).
- the number of layers of interlayer materials may be the same in buildup layers (B1, B2).
- the number of layers of interlayer materials is preferred to be the same in the upper and lower buildup layers.
- step (S 26 ) of FIG. 16 solder-resist layer 135 is formed.
- solder-resist layer 135 is formed to cover conductive pattern 133 as shown in FIG. 1 .
- step (S 27 ) of FIG. 16 pad 137 is formed.
- exposing portion ( 135 a ) is formed in solder-resist layer 135 so as to expose conductive pattern 133 .
- the exposed portion of conductive pattern 133 becomes pad 137 .
- multilayer printed wiring board 100 as shown in FIG. 1 is completed.
- the manufacturing method of the present embodiment is suitable for manufacturing multilayer printed wiring board 100 . Using such a manufacturing method, an excellent multilayer printed wiring board 100 with electronic component 10 mounted accurately at the predetermined position is achieved.
- multilayer printed wiring board 201 As an (X-Z) cross section in FIG. 26 shows, multilayer printed wiring board 201 according to the first modified example of the present embodiment has buildup layer (B3) and solder-resist layer 235 . Multilayer printed wiring board 201 does not have a core substrate; namely, it is a coreless multilayer printed wiring board.
- Buildup layer (B3) has pad 221 , insulation layer 223 , via conductor ( 241 b ), conductive pattern 225 , insulation layer 227 , via conductor ( 243 b ), conductive pattern 229 , insulation layer 231 , via conductor ( 245 b ) and conductive pattern 233 .
- Electronic component 10 is mounted inside insulation layer 231 .
- Solder-resist layer 235 having exposing portion ( 235 a ) to expose conductive pattern 233 is formed on the first main-surface side of insulation layer 231 .
- the exposed portion of conductive pattern 233 becomes pad 237 .
- pad 221 is exposed on the second main-surface side of insulation layer 223 . It is an option to form a solder-resist layer having an exposing portion to expose part of pad 221 on the second main-surface side of insulation layer 223 .
- FIG. 26 shows an enlarged view of main portion (A2) of multilayer printed wiring board 201 according to the first modified example of the present embodiment.
- insulation layer 223 is formed to cover pad 221 .
- Via conductor ( 241 b ) is formed in insulation layer 223 to penetrate through insulation layer 223 .
- Conductive pattern 225 is formed on the first main-surface side of insulation layer 223 .
- Conductive pattern 225 is connected to via conductor ( 241 b ).
- Insulation layer 227 is formed to cover conductive pattern 225 .
- Via conductor ( 243 b ) is formed in insulation layer 227 to penetrate through insulation layer 227 .
- Conductive pattern 229 is formed on the first main-surface side of insulation layer 227 .
- Conductive pattern 229 is connected to via conductor ( 243 b ).
- Electronic component 10 is mounted on the first main-surface side of insulation layer 227 .
- Insulation layer 231 is formed to cover conductive pattern 229 and electronic component 10 .
- Via conductor ( 245 b ) is formed in insulation layer 231 to penetrate through insulation layer 231 .
- opening portion 15 in electronic component 10 mounted inside insulation layer 231 has disappeared.
- Via conductor ( 247 b ) is connected to conductive pattern 17 formed on the first main-surface side of electronic component 10 .
- Conductive pattern 233 is formed on the first main-surface side of via conductors ( 245 b , 247 b ) above.
- Solder-resist layer 235 having exposing portion ( 235 a ) to expose conductive pattern 233 is formed on the first main-surface side of insulation layer 231 .
- Multilayer printed wiring board 201 A method for manufacturing multilayer printed wiring board 201 above is described.
- Multilayer printed wiring board 201 according to the first modified example of the present embodiment is manufactured by a method described below.
- support body 401 is prepared.
- Support body 401 is made of glass epoxy, for example.
- copper foil 403 with an adhesive carrier is formed on support body 401 .
- pad 221 is formed using, for example, a full-additive or semi-additive (SAP) method.
- SAP full-additive or semi-additive
- insulation layer 223 via conductor ( 241 b ), conductive pattern 225 , insulation layer 227 , via conductor ( 243 b ) and conductive pattern 229 are formed using a semi-additive method, for example.
- substrate ( 201 a ) for mounting electronic component 10 above is formed.
- electronic component 10 is mounted at a predetermined position on a portion of buildup layer (B3). More specifically, as shown in FIG. 28 , electronic component 10 is aligned from the (+Z) direction and adhered onto insulation layer 227 of substrate ( 201 a ).
- the alignment is conducted using a flip-chip bonder in the same manner employed as in multilayer printed wiring board 100 shown in FIG. 23 .
- insulation layer 227 is formed to cover electronic component 10 and conductive pattern 229 . Furthermore, via conductors ( 245 b , 247 b ) and conductive pattern 233 are formed. Then, support body 401 and copper foil 403 with a carrier are removed. Accordingly, pad 221 is exposed on the second main-surface side of buildup layer (B3), as shown in FIG. 30 .
- solder-resist layer 235 is formed. More specifically, as shown in FIG. 26 , solder-resist layer 235 is formed to cover conductive pattern 233 . Then, exposing portion ( 235 a ) is formed in solder-resist layer 235 to expose conductive pattern 233 . Accordingly, the exposed portion of conductive pattern 233 becomes pad 237 .
- multilayer printed wiring board 201 shown in FIG. 26 is completed.
- the manufacturing method according to the first modified example of the present embodiment is suitable for manufacturing multilayer printed wiring board 201 .
- excellent multilayer printed wiring board 201 coreless multilayer printed wiring board
- electronic component 10 mounted accurately at a predetermined position is achieved.
- Multilayer printed wiring board 301 according to the second modified example of the present embodiment has core substrate 320 , first buildup layer (B5), second buildup layer (B6), solder-resist layer 335 and solder-resist layer 332 , as an (X-Z) cross section shows in FIG. 31 .
- electronic component 10 is directly mounted on the first main-surface side of core substrate 320 .
- First buildup layer (B5) has conductive pattern 321 , insulation layer 323 , via conductor ( 341 b ), conductive pattern 325 , insulation layer 327 , via conductor ( 343 b ), conductive pattern 329 , insulation layer 331 , via conductor ( 345 b ) and conductive pattern 333 .
- Core substrate 320 is made of glass epoxy, for example. Hole ( 340 a ) (through hole) bored by laser light, for example, is formed in core substrate 320 .
- Core substrate 320 has through-hole conductor ( 340 b ), made by filling hole ( 340 a ) with copper plating, for example.
- Through-hole conductor ( 340 b ) electrically connects first main-surface side conductive pattern 321 and second main-surface side conductive pattern 322 .
- Insulation layer 324 is formed to cover conductive pattern 322 . Via conductor ( 342 b ) is formed in insulation layer 324 to penetrate through insulation layer 324 . Conductive pattern 326 is formed on the second main-surface side of insulation layer 324 . Conductive pattern 326 is connected to via conductor ( 342 b ). Insulation layer 328 is formed to cover conductive pattern 326 . Via conductor ( 344 b ) is formed in insulation layer 328 to penetrate through insulation layer 328 . Conductive pattern 330 is formed on the second main-surface side of insulation layer 328 . Conductive pattern 330 is connected to via conductor ( 344 b ).
- Second buildup layer (B6) is made up of conductive pattern 322 , insulation layer 324 , via conductor ( 342 b ), conductive pattern 326 , insulation layer 328 , via conductor ( 344 b ) and conductive pattern 330 .
- solder-resist layer 332 having exposing portion ( 332 a ) to expose conductive pattern 330 is formed.
- the exposed portion of conductive pattern 330 becomes pad 336 .
- the number of layers (three) of interlayer materials in buildup layer (B5) is different from the number of layers (two) of interlayer materials in buildup layer (B6).
- the number of layers of interlayer materials may be the same in buildup layers (B5, B6). From the viewpoint of suppressing warping of multilayer printed wiring board 301 , the number of layers of interlayer materials is preferred to be the same in the upper and lower buildup layers.
- Main portion (A3) of multilayer printed wiring board 301 according to the second modified example of the present embodiment is enlarged and shown in the lower portion of FIG. 31 .
- conductive pattern 321 is formed on the first main-surface side of core substrate 320 .
- electronic component 10 is mounted on the first main-surface side of core substrate 320 .
- Insulation layer 323 is formed to cover conductive pattern 321 and electronic component 10 .
- Via conductor ( 341 b ) is formed in insulation layer 323 to penetrate through insulation layer 323 .
- via conductor ( 347 b ) is formed in insulation layer 323 to penetrate through insulation layer 323 and be connected to conductive pattern 17 of electronic component 10 .
- Conductive pattern 325 is formed on the first main-surface side of insulation layer 323 .
- Conductive pattern 325 is connected to via conductors ( 341 b , 347 b ).
- Insulation layer 327 is formed to cover conductive pattern 325 .
- Via conductor ( 343 b ) is formed in insulation layer 327 to penetrate through insulation layer 327 .
- Conductive pattern 329 is formed on the first main-surface side of insulation layer 327 . Conductive pattern 329 is connected to via conductor ( 343 b ). Insulation layer 331 is formed to cover conductive pattern 329 . Via conductor ( 345 b ) is formed in insulation layer 331 to penetrate through insulation layer 331 .
- hole ( 340 a ) (through hole) bored by laser light, for example, is formed in core substrate 320 , as shown in FIG. 32 .
- hole ( 340 a ) is filled with copper plating, for example, so as to form through-hole conductor ( 340 b ).
- conductive pattern 321 is formed on the first main-surface side of core substrate 320
- conductive pattern 322 is formed on the second main-surface side of core substrate 320 .
- electronic component ( 10 a ) (electronic component prior to being adhered) is mounted on a predetermined position of core substrate 320 . More specifically, as shown in FIG. 33 , electronic component ( 10 a ) is aligned from the (+Z) direction and adhered to the first main-surface side of core substrate 320 . Such alignment is conducted using a flip-chip bonder in the same manner as that for multilayer printed wiring board 100 described above with reference to FIG. 23 .
- FIG. 34 shows a state in which electronic component 10 is adhered to core substrate 320 .
- the rest is conducted the same as in the method for manufacturing multilayer printed wiring board 100 described above, and first buildup layer (B5) and second buildup layer (B6) are formed. Accordingly, multilayer printed wiring board 301 is manufactured.
- first buildup layer (B5) having three insulation layers is formed on the first main-surface side of core substrate 320
- second buildup layer (B6) having two insulation layers is formed on the second main-surface side.
- core substrate 320 with mounted electronic component 10 as shown in FIG. 34 may be used to form various lamination structures.
- the adhesive agent of adhesive layer 12 is present on the entire circumference of opening portion 15 in electronic component ( 10 a ) of the embodiment.
- the air in opening portion 15 cannot escape during the above adhesion process, and may cause a void to be formed in adhesive layer 12 .
- Electronic components according to modified examples of the present embodiment are described with reference to FIGS. 35 and 36 .
- electronic component 30 As shown in FIG. 35 , electronic component 30 according to a first modified example of the embodiment has adhesive layer 32 with opening portion 35 , insulation layer 33 and alignment mark 34 , the same as in electronic component ( 10 a ) described above.
- the difference in electronic component 30 from electronic component ( 10 a ) is the shape of opening portion 35 .
- Opening portions 35 are respectively formed near the opposing corners of electronic component 30 .
- opening portion 35 reaches the outer edge of insulation layer 33 .
- electronic component 40 As shown in FIG. 36 , electronic component 40 according to a second modified example of the present embodiment has adhesive layer 42 with opening portion 45 , insulation layer 43 and alignment mark 44 , the same as in electronic components ( 10 a , 30 ) described above.
- the difference in electronic component 40 from electronic components ( 10 a , 30 ) is the shape of opening portion 45 .
- Opening portions 45 are respectively formed by cutting off the opposing corners of adhesive layer 42 . Namely, opening portion 45 reaches the outer edge of insulation layer 43 .
- the planar shape of the electronic components is not limited to a rectangle, but any planar shape may be employed depending on usage purposes.
- adhesive layer 12 was uniformly formed and part of the adhesive layer was later removed so that opening portion 15 was formed. However, that is not the only option, and opening portion 15 may be formed at the same time that adhesive layer 12 is formed on the second main-surface side of insulation layer 13 .
- the adhesive agent was removed by a method using photolithography.
- photolithography an example was described in which the photosensitive portion was denatured and removed.
- the photosensitive portion was cured and for the non-photosensitive portion to be removed by a removing solution.
- the structures of electronic components ( 10 a , 30 , 40 ) and multilayer printed wiring boards ( 100 , 201 ), types of their structural elements, properties, measurements, materials, shapes, number of layers, positions and the like may be modified freely within a scope that does not deviate from the gist of the present invention.
- thermosetting resins or thermoplastic resins may be used as resins for forming insulation layers.
- thermosetting resins to be used are BT resin, allyl polyphenylene ether resin (A-PPE resin), aramid resin and the like.
- thermoplastic resins to be used are polycarbonate resin, liquid-crystal polymer (LCP), PEEK resin and the like. Those materials are preferred to be selected as needed from the viewpoints of transparency, insulation, dielectric properties, heat resistance, mechanical characteristics, and the like. Alignment marks, conductive patterns, insulation layers and adhesive layers may be formed with multiple layers each made of different materials.
- the steps for manufacturing an electronic component are not limited to the order and contents shown in the flowchart of FIG. 4 ; the order and contents may be modified freely within a scope that does not deviate from the gist of the present invention. Also, any unnecessary step may be omitted depending on usage purposes or the like.
- the steps for manufacturing a multilayer printed wiring board are not limited to the order and contents shown in the flowchart of FIG. 16 ; the order and contents may be modified freely within a scope that does not deviate from the gist of the present invention.
- any unnecessary step may be omitted depending on usage purposes.
- the distance between lead terminals decreases.
- pads to be connected to the lead terminals of an IC chip are formed at fine positional intervals on a surface of a multilayer printed wiring board.
- electronic component ( 10 a ) is manufactured by a method shown in FIG. 37 .
- support body 400 is prepared as shown in FIG. 39 .
- Support body 400 is formed of a carrier and a copper foil formed on the carrier, for example.
- step (S 32 ) of FIG. 37 wiring 11 with a finer wiring pitch and alignment mark 14 are formed on the copper foil of support body 400 as shown in FIG. 40 .
- insulation layer 16 is formed on support body 400 and covers wiring 11 with a finer wiring pitch and alignment mark 14 formed on the copper foil of support body 400 as shown in FIG. 41 .
- Insulation layer 16 may be optically transparent or optically non-transparent, and may be made of a transparent or non-transparent resin, for example.
- resin epoxy resin, phenol resin, polyol resin, polycarbonate resin and the like may be used.
- step (S 34 ) of FIG. 37 as shown in FIG. 42 , hole ( 16 a ) (via hole) is formed in insulation layer 16 by irradiating laser light, for example. Hole ( 16 a ) reaches wiring 11 with a finer wiring pitch.
- step (S 35 ) of FIG. 37 via conductor ( 16 b ) and a conductive layer are formed as shown in FIG. 43 . Electroless plating and electrolytic plating are performed using copper, for example, thereby filling hole ( 16 a ) to form via conductor ( 16 b ) while forming conductive layer on insulation layer 16 .
- step (S 36 ) of FIG. 37 support body 400 is removed. More specifically, support body 400 is removed from insulation layer 16 .
- FIG. 44 shows the cross section of insulation layer 16 having wiring 11 and alignment mark 14 after support body 400 has been removed. Support body 400 may be recyclable.
- adhesive layer 12 is formed. More specifically, as shown in FIG. 45 , adhesive layer 12 is laminated on the first main-surface side (lower surface) of insulation layer 16 by coating an adhesive agent containing filler, for example.
- the adhesive agent for forming adhesive layer 12 is photosensitive. Accordingly, opening portion 15 is formed precisely at a predetermined portion in the next step for forming opening portion 15 .
- opening portion 15 is formed in adhesive layer 12 . More specifically, as shown in FIG. 46 , the adhesive agent at a portion of adhesive layer 12 located under alignment mark 14 is photosensitized and denatured by photolithography, for example. Then, using a removing solution, for example, the photosensitized and denatured portion ( 12 a ) is removed, thereby forming opening portion 15 (see FIG. 38 ).
- opening portion 15 of the present embodiment is formed by uniformly forming adhesive layer 12 first and by removing part of the adhesive agent. Therefore, opening portion 15 is accurately formed at a predetermined portion while adhesive layer 12 is formed to have a uniform thickness.
- electronic component ( 10 a ) of the present embodiment is completed as shown in FIG. 38 .
- the manufacturing method of the present embodiment is suitable for manufacturing electronic component ( 10 a ). Using such a manufacturing method, an excellent electronic component ( 10 a ) is achieved, in which positional shifting is suppressed between alignment mark 14 and opening portion 15 .
- a flip-chip bonder is a device to align an electronic component with respect to a multilayer printed wiring board. Alignment by a flip-chip bonder is carried out based on an alignment mark formed on the electronic component and another alignment mark formed on the multiplayer printed wiring board. For an accurate alignment, it is important to accurately detect the alignment mark formed on the electronic component.
- a flip-chip bonder is provided with a camera, and alignment marks are detected by the camera.
- an alignment mark of an electronic component may be covered by an adhesive agent or the like used for adhering the electronic component to the multilayer printed wiring board.
- an adhesive agent or the like used for adhering the electronic component to the multilayer printed wiring board.
- An electronic component has an adhesive layer made of an optically opaque adhesive agent and is provided with an opening, an insulation layer positioned on the adhesive layer, and an alignment mark positioned on the insulation layer and over the upper portion of the opening portion.
- a method for manufacturing an electronic component includes the following: preparing a support body; forming an insulation layer on a first main-surface side of the support body; forming an alignment mark on a first main-surface side of the insulation layer; removing the support body; and using an optically opaque adhesive agent, forming an adhesive layer with an opening portion provided on a second main-surface side of the insulation layer and under the alignment mark.
Abstract
Description
- The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2013-090389, filed Apr. 23, 2013, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to an electronic component, a method for manufacturing the same and a method for manufacturing a multilayer printed wiring board.
- 2. Description of Background Art
- In international patent publication 2007/129545, technology for forming pads on a multilayer printed wiring board is proposed. A multilayer printed wiring board in international patent publication 2007/129545 has a built-in multilayer substrate in which conductive patterns are formed at a fine pitch. Through the built-in multilayer substrate, the lead terminals of an IC chip to be mounted are electrically connected to the circuits formed in the multilayer printed wiring board. In such a multilayer printed wiring board, the multilayer substrate is positioned in the portion where the IC chip is to be mounted, thereby enabling finer wiring in that portion. Accordingly, an IC chip with lead terminals arrayed at fine intervals is mounted accurately. The contents of international patent publication 2007/129545 are incorporated herein in this application.
- According to one aspect of the present invention, an electronic component includes an insulation layer, an alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer. The adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.
- According to another aspect of the present invention, a method for manufacturing an electronic component includes forming an insulation layer having an alignment mark on a first surface of the insulation layer, forming an adhesive layer including an optically opaque agent on the first surface of the insulation layer or a second surface of the insulation layer on an opposite side with respect to the first surface of the insulation layer, and forming an opening portion in the adhesive layer at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.
- According to yet another aspect of the present invention, a method for manufacturing a multilayer printed wiring board includes forming a buildup layer including insulation layers and conductive layers, positioning an electronic component having an alignment mark to a position on a surface of the buildup layer based on the alignment mark of the electronic component, mounting the electronic component to the surface of the buildup layer in the position, and forming an outer insulation layer on the surface of the buildup layer such that the outer insulation layer covers the electronic component mounted on the surface of the buildup layer. The electronic component has an insulation layer, the alignment mark positioned on a first surface of the insulation layer, and an adhesive layer including an optically opaque agent and formed on the first surface of the insulation layer or a second surface of the insulation layer on the opposite side with respect to the first surface of the insulation layer, and the adhesive layer has an opening portion formed at the position corresponding to the alignment mark such that the opening portion exposes the alignment mark directly or through the insulation layer.
- A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
-
FIG. 1 shows a cross-sectional view of the entire structure of a multilayer printed wiring board according to an embodiment of the present invention and also shows an enlarged view of the main portion; -
FIG. 2 is a cross-sectional view showing an electronic component according to an embodiment of the present invention; -
FIG. 3 is a bottom view showing the electronic component according to an embodiment of the present invention; -
FIG. 4 is a flowchart showing a method for manufacturing the electronic component according to an embodiment of the present invention; -
FIG. 5 is a view illustrating a step for preparing a support body; -
FIG. 6 is a view illustrating a step for forming an insulation layer; -
FIG. 7 is a view illustrating a step subsequent to the step inFIG. 6 ; -
FIG. 8 is a view illustrating a step for forming an alignment mark; -
FIG. 9 is a view illustrating a step subsequent to the step inFIG. 8 ; -
FIG. 10 is a view illustrating a step for forming a via hole; -
FIG. 11 is a view illustrating a step for forming a via conductor and a conductive layer; -
FIG. 12 is a view illustrating a step for forming a conductive pattern; -
FIG. 13 is a view illustrating a step for removing the support body; -
FIG. 14 is a view illustrating a step for forming an adhesive layer; -
FIG. 15 is a view illustrating a step for forming an opening portion; -
FIG. 16 is a flowchart showing a method for manufacturing a multilayer printed wiring board according to another embodiment of the present invention; -
FIG. 17 is a view illustrating a step for preparing a core substrate; -
FIG. 18 is a view illustrating a step for forming a through hole; -
FIG. 19 is a view illustrating a step for forming a through-hole conductor; -
FIG. 20 is a view illustrating a step for forming a conductive pattern; -
FIG. 21 is a view illustrating a step for forming a buildup layer; -
FIG. 22 is a view illustrating a step for mounting an electronic component on the substrate; -
FIG. 23 shows schematic views of a method for aligning an electronic component with respect to the substrate; -
FIG. 24 is a view illustrating a state in which an electronic component is mounted on the substrate; -
FIG. 25 is a view illustrating a step subsequent to the step inFIG. 22 ; -
FIG. 26 shows a cross-sectional view of the entire structure of a multilayer printed wiring board according to a first modified example of an embodiment of the present invention and also shows an enlarged view of the main portion; -
FIG. 27 is a view illustrating a method for manufacturing a multilayer printed wiring board according to the first modified example; -
FIG. 28 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the first modified example; -
FIG. 29 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the first modified example; -
FIG. 30 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the first modified example; -
FIG. 31 shows a cross-sectional view of the entire structure of a multilayer printed wiring board according to a second modified example of an embodiment of the present invention and also shows an enlarged view of the main portion; -
FIG. 32 is a view illustrating a method for manufacturing a multilayer printed wiring board according to the second modified example; -
FIG. 33 shows views illustrating the method for manufacturing a multilayer printed wiring board according to the second modified example; -
FIG. 34 is a view illustrating the method for manufacturing a multilayer printed wiring board according to the second modified example; -
FIG. 35 is a bottom view showing the electronic component according to the first modified example of an embodiment of the present invention; -
FIG. 36 is a bottom view showing the electronic component according to the second modified example of an embodiment of the present invention; -
FIG. 37 is a flowchart showing another method for manufacturing the electronic component according to an embodiment of the present invention; -
FIG. 38 is a cross-sectional view showing an electronic component according to an embodiment of the present invention; -
FIG. 39 is a view illustrating a step for preparing a support body; -
FIG. 40 is a view illustrating a step for forming a conductive circuit; -
FIG. 41 is a view illustrating a step for forming an insulation layer; -
FIG. 42 is a view illustrating a step for forming a via hole; -
FIG. 43 is a view illustrating a step forming a via conductor and a conductive pattern; -
FIG. 44 is a view illustrating a step for removing a support body; -
FIG. 45 is a view illustrating a step for forming an adhesive layer; and -
FIG. 46 is a view illustrating a step for forming an opening portion. - The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
- To simplify understanding, XYZ coordinates are set and referred to appropriately. Arrow (Z) indicates a lamination direction of an electronic component or a multilayer printed wiring board (or a thickness direction of the electronic component and the multilayer printed wiring board) corresponding to a direction along a normal line to main surfaces (upper and lower surfaces) of the electronic component and the multilayer printed wiring board. On the other hand, arrows (X) and (Y) each indicate a direction perpendicular to a lamination direction (or a direction toward a side of each layer). The main surfaces of the electronic component and the multilayer printed wiring board are on the (X-Y) plane. Side surfaces of the electronic component and the multilayer printed wiring board are on the (X-Z) plane or the (Y-Z) plane.
- Two main surfaces respectively facing in directions along opposing normal lines are referred to as a first main surface (+Z side surface) and a second main surface (−Z side surface). Namely, a main surface opposite the first main surface is the second surface, and a main surface opposite the second main surface is the first main surface.
- “Optically transparent” indicates that the transmission coefficient of light rays going through the subject is 70% or higher, for example, and “optically opaque” indicates that the transmission coefficient of the light rays is lower than 70%, for example. “Light rays” include visible rays, infrared rays and ultraviolet rays. What is generally referred to as “semi-transparent” is included in the term “optically opaque.”
- “Plating” indicates a step for forming a metal layer, but also includes the resultant metal and metal layer. Plating includes wet plating such as electroless plating and electrolytic plating as well as dry plating such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).
- Conductive patterns include wiring of a conductive circuit (including ground), a pad, a land, a via conductor or the like, or may also include a plain conductive pattern that does not form a conductive circuit.
- Holes are not limited to penetrating holes, but also include non-penetrating holes. Holes include a via hole, a through hole and the like. The conductor formed in a via hole is referred to as a via conductor, and the conductor formed in a through hole is referred to as a through-hole conductor.
- Multilayer printed
wiring board 100 of the present embodiment hascore substrate 120, first buildup layer (B1), second buildup layer (B2), solder-resistlayer 135 and solder-resistlayer 132, as shown in the (X-Z) cross section inFIG. 1 . - First buildup layer (B1) has
conductive pattern 121,insulation layer 123, via conductor (141 b),conductive pattern 125,insulation layer 127, via conductor (143 b),conductive pattern 129,insulation layer 131, via conductor (145 b) andconductive pattern 133.Electronic component 10 is mounted insideinsulation layer 131. -
Core substrate 120 is made of, for example, glass-epoxy resin (hereinafter referred to as “glass epoxy”). Incore substrate 120, hole (140 a) (through hole) is formed by using laser light, for example.Core substrate 120 has through-hole conductor (140 b) formed by filling copper plating, for example, in hole (140 a). Through-hole conductor (140 b) electrically connects first main-surface sideconductive pattern 121 and second main-surface sideconductive pattern 122. -
Insulation layer 124 is formed to coverconductive pattern 122. Via conductor (142 b) is formed ininsulation layer 124 to penetrate throughinsulation layer 124.Conductive pattern 126 is formed on the second main-surface side ofinsulation layer 124.Conductive pattern 126 is connected to via conductor (142 b).Insulation layer 128 is formed to coverconductive pattern 126. Via conductor (144 b) is formed ininsulation layer 128 to penetrate throughinsulation layer 128.Conductive pattern 130 is formed on the second main-surface side ofinsulation layer 128.Conductive pattern 130 is connected to via conductor (144 b). Second buildup layer (B2) is made up ofconductive pattern 122,insulation layer 124, via conductor (142 b),conductive pattern 126,insulation layer 128, via conductor (144 b) andconductive pattern 130. - On the second main-surface side of
insulation layer 128, solder-resistlayer 132 is formed, having exposing portion (132 a) to exposeconductive pattern 130. The exposed portion ofconductive pattern 130 becomespad 136. - Main portion (A1) of multilayer printed
wiring board 100 of the present embodiment is enlarged and shown in the lower portion ofFIG. 1 . Described in further detail,insulation layer 123 is formed to coverconductive pattern 121 formed on the first main-surface side ofcore substrate 120 in multilayer printedwiring board 100 of the present embodiment. Via conductor (141 b) is formed ininsulation layer 123 to penetrate throughinsulation layer 123.Conductive pattern 125 is formed on the first main-surface side ofinsulation layer 123.Conductive pattern 125 is connected to via conductor (141 b).Insulation layer 127 is formed to coverconductive pattern 125. Via conductor (143 b) is formed ininsulation layer 127 to penetrate throughinsulation layer 127. -
Conductive pattern 129 is formed on the first main-surface side ofinsulation layer 127.Conductive pattern 129 is connected to via conductor (143 b). Also,electronic component 10 is mounted on the first main-surface side ofinsulation layer 127.Insulation layer 131 is formed to coverconductive pattern 129 andelectronic component 10. Via conductor (145 b) is formed ininsulation layer 131 to penetrate throughinsulation layer 131. - Electronic component (10 a) of the present embodiment prior to being mounted on multilayer printed
wiring board 100 is described with reference toFIG. 2 .FIG. 2 is a cross-sectional view cut through the (2-2) line inFIG. 3 . As shown inFIG. 2 , electronic component (10 a) of the present embodiment hasadhesive layer 12 with openingportion 15,insulation layer 13,alignment mark 14, wiring 11 with a finer wiring pitch than that of the wiring in multilayer printed wiring board 100 (hereinafter also simply referred to as “wiring with a finer wiring pitch”),insulation layer 16, via conductor (16 b), andconductive pattern 17. -
Wiring 11 with a finer wiring pitch andalignment mark 14 are formed oninsulation layer 13 using the same material, for example, copper plating. Thus, to form wiring 11 with a finer wiring pitch andalignment mark 14, it is sufficient to form a layer made of the same material, for example, copper plating, oninsulation layer 13 and to pattern the layer. Accordingly, manufacturing steps are simplified. - The planar shape (shape on the (X-Y) plane) of electronic component (10 a) is substantially rectangular. Two alignment marks 14 are respectively positioned near opposing corners of electronic component (10 a) (see
FIG. 3 ). -
Adhesive layer 12 is formed using an adhesive agent containing filler mixed in an adhesive resin material so as to reduce its coefficient of thermal expansion (CTE). As for the filler, inorganic fillers such as silica filler and alumina filler are thought to be preferable. However, that is not the only option, and organic filler may also be used instead of inorganic filler. Examples of adhesive resin material are epoxy resin, polyester resin, bismaleimide triazine resin (BT resin), polyimide resin, phenol resin and allyl polyphenylene ether resin (A-PPE resin) and the like. - Since irregular reflection occurs at the interface of the resin material and filler,
adhesive layer 12 is optically opaque.Insulation layer 13 is an optically transparent layer. Inadhesive layer 12, openingportion 15 is formed underalignment mark 14. - In electronic component (10 a) of the present embodiment, wiring 11 is formed to have a finer wiring pitch than that of the wiring in multilayer printed
wiring board 100. By mounting electronic component (10 a) ininsulation layer 131 of multilayer printedwiring board 100, part of the wiring is made finer, thus enabling an IC chip with lead terminals arrayed at fine intervals to be mounted accurately thereon, as described earlier. - As shown in
FIG. 1 , openingportion 15 has disappeared fromelectronic component 10 mounted insideinsulation layer 131. Via conductor (147 b) is connected toconductive pattern 17 formed on the first main-surface side ofelectronic component 10.Conductive pattern 133 is formed on the first main-surface side of via conductor (145 b) and via conductor (147 b). On the first main-surface side ofinsulation layer 131, solder-resistlayer 135 with exposing portion (135 a) to exposeconductive pattern 133 is formed. The exposed portion ofconductive pattern 133 becomespad 137. -
FIG. 3 shows a bottom view of electronic component (10 a) of the present embodiment. In the present embodiment, the planar shape of electronic component (10 a) is rectangular, for example, and length (d1) of the longer side is 4˜50 mm, for example. Length (d2) of the shorter side is 1˜20 mm, for example. The thickness ofadhesive layer 12 is 3˜20 μm, for example. The thickness ofinsulation layer 13 is 1˜10 μm, for example. - As shown in
FIG. 3 , openingportion 15 of electronic component (10 a) is formed in a position and a size so as to entirely showalignment mark 14 when seen from the bottom side. The size ofalignment mark 14 is 150˜500 μm, for example. Openingportion 15 is shaped substantially as a circle, and the diameter is 300˜700 μm, for example. - Next, a method for manufacturing electronic component (10 a) is described. In the present embodiment, electronic component (10 a) is manufactured by a method shown in
FIG. 4 . - In step (S11) of
FIG. 4 ,support body 400 is prepared as shown inFIG. 5 .Support body 400 is made of glass, for example. Then,adhesive support layer 402 is formed onsupport body 400. - In step (S12) of
FIG. 4 ,insulation layer 13 is formed onsupport body 400 withsupport layer 402 disposed in between. - More specifically,
insulation layer 13 is positioned on the first main-surface side ofsupport layer 402, as shown inFIG. 6 .Insulation layer 13 andsupport layer 402 are adhered by applying heat, for example.Insulation layer 13 is optically transparent, and is made of a transparent resin, for example. As examples of the transparent resin, epoxy resin, phenol resin, polyol resin, polycarbonate resin and the like may be used. - In step (S13) of
FIG. 4 , wiring 11 with a finer wiring pitch andalignment mark 14 are formed on the first main-surface side ofinsulation layer 13. - More specifically, as shown in
FIG. 7 , conductive layer (14 a) is formed on the first main-surface side ofinsulation layer 13 using a subtractive method, for example. However, forming conductive layer (14 a) is not limited to a subtractive method, and a full-additive method or semi-additive method (SAP) may also be employed. Next, as shown inFIG. 8 , conductive layer (14 a) is patterned by a subtractive method, for example, formingalignment mark 14 andwiring 11 with a finer wiring pitch. Here, formingalignment mark 14 andwiring 11 with a finer wiring pitch is not limited to a subtractive method, and a full-additive method or semi-additive method may also be employed. - In step (S14) of
FIG. 4 ,insulation layer 16 is formed. - More specifically, as shown in
FIG. 9 ,insulation layer 16 is laminated oninsulation layer 13 to coverwiring 11 with a finer wiring pitch andalignment mark 14. - In step (S15) of
FIG. 4 , via conductor (16 b) and a conductive layer are formed. - More specifically, as shown in
FIG. 10 , hole (16 a) (via hole) is formed ininsulation layer 16 by irradiating laser light, for example. Hole (16 a) reacheswiring 11 with a finer wiring pitch. Next, as shown inFIG. 11 , electroless plating and electrolytic plating are performed using copper, for example, thereby filling hole (16 a) to form via conductor (16 b) while formingconductive layer 1000 oninsulation layer 16. - In step (S16) of
FIG. 4 ,conductive pattern 17 is formed. - More specifically, as shown in
FIG. 12 ,conductive layer 1000 is patterned by etching, for example, thereby formingconductive pattern 17. - In step (S17) of
FIG. 4 ,support body 400 is removed. - More specifically,
support layer 402 is softened by applying heat, for example, andsupport body 400 is slid in a direction X (or a direction Y) so thatsupport body 400 is removed from the second main surface ofinsulation layer 13.FIG. 13 shows the cross section aftersupport body 400 has been removed. Aftersupport body 400 is removed frominsulation layer 13, if part ofsupport layer 402 remains on the second main surface ofinsulation layer 13, cleaning is conducted to remove the remaining portion ofsupport layer 402.Support body 400 is recyclable. - In step (S18) of
FIG. 4 ,adhesive layer 12 is formed. - More specifically, as shown in
FIG. 14 ,adhesive layer 12 is laminated on the second main-surface side (lower surface) ofinsulation layer 13 by coating an adhesive agent containing filler, for example. The adhesive agent for formingadhesive layer 12 is photosensitive. Accordingly, openingportion 15 is formed precisely at a predetermined portion in the next step for formingopening portion 15. - In step (S19) of
FIG. 4 , openingportion 15 is formed inadhesive layer 12. - More specifically, as shown in
FIG. 15 , the adhesive agent at a portion ofadhesive layer 12 located underalignment mark 14 is photosensitized and denatured by photolithography, for example. Then, using a removing solution, for example, the photosensitized and denatured portion (12 a) is removed, thereby forming opening portion 15 (seeFIG. 2 ). - As described so far, opening
portion 15 of the present embodiment is formed by uniformly formingadhesive layer 12 first and by removing part of the adhesive agent. Therefore, openingportion 15 is accurately formed at a predetermined portion whileadhesive layer 12 is formed to have a uniform thickness. - Accordingly, electronic component (10 a) of the present embodiment is completed as shown in
FIG. 2 . - The manufacturing method of the present embodiment is suitable for manufacturing electronic component (10 a). Using such a manufacturing method, an excellent electronic component (10 a) is achieved, in which positional shifting is suppressed between
alignment mark 14 andopening portion 15. - Next, a method for manufacturing multilayer printed
wiring board 100 is described. In an embodiment here, multilayer printedwiring board 100 is manufactured by employing a method shown inFIG. 16 . - In step (S21) of
FIG. 16 ,core substrate 120 is prepared as shown inFIG. 17 .Core substrate 120 is made of glass epoxy, for example. More specifically, double-sidedcopper foil laminate 3000 is prepared where a metal foil such ascopper foil 3001 is laminated on first main surface (F1) ofcore substrate 120 and metal foil such ascopper foil 3002 is laminated on second main surface (F2). - In step (S22) of
FIG. 16 , through-hole conductor (140 b) and conductive layers are formed. - More specifically, as shown in
FIG. 17 , double-sidedcopper foil laminate 3000 is bored by irradiating laser light, for example, at both surfaces of double-sidedcopper foil laminate 3000. As shown inFIG. 18 ,hole 3003 andhole 3004 formed respectively from both sides are connected to be one hole, making hole (140 a) (through hole). Next, as shown inFIG. 19 , electroless plating and electrolytic platings (3003, 3004) are performed using copper, for example, in hole (140 a) and on copper foils (3001, 3002) so that through-hole conductor (140 b) and conductive layers are formed. Then, conductive layers are patterned by etching, for example. Accordingly, as shown inFIG. 20 ,conductive pattern 121 on first main surface (F1) andconductive pattern 122 on second main surface (F2) are formed respectively oncore substrate 120. - In step (S23) of
FIG. 16 , buildup layers are respectively formed on both surfaces ofcore substrate 120. - More specifically, as shown in
FIG. 21 , using a full-additive method, semi-additive method (SAP), or a subtractive method, part of buildup layer (B1) (insulation layer 123, via conductor (141 b),conductive pattern 125,insulation layer 127, via conductor (143 b) and conductive pattern 129) are formed on the first main-surface side ofcore substrate 120. In the same manner, buildup layer (B2) and solder-resistlayer 132 are formed on the second main-surface side ofsubstrate 120. Accordingly, substrate (100 a) for mounting electronic component (10 a) above is formed. - In step (S24) of
FIG. 16 , electronic component (10 a) is mounted on a predetermined position, which is part of buildup layer (B1) above. - More specifically, as shown in
FIG. 22 , electronic component (10 a) is adhered toinsulation layer 127 of substrate (100 a) by being aligned from the (+Z) direction. - The alignment of electronic component (10 a) in the present embodiment is described with reference to
FIG. 23 . When alignment is conducted using a flip-chip bonder as shown inFIG. 23 ,camera unit 300 is located between electronic component (10 a) adsorbed and held horizontally byvacuum adsorption device 200 and substrate (100 a) positioned horizontally.Camera unit 300 is provided with CCD cameras on its first and second main surfaces. The CCD camera on the first main surface is capable of image recognition inarrow 301 direction (+Z direction). The CCD camera on the second main surface is capable of image recognition inarrow 302 direction (−Z direction).Camera unit 300 is movable along the (X-Y) plane as shown byarrows 303. - When
camera unit 300 moves along the (X-Y) plane, the first main-surface side CCD camera recognizesalignment mark 14 and the second main-surface side CCD camera recognizes the alignment mark (omitted from the drawing) formed on the first main surface of substrate (100 a). Accordingly, the relative position of electronic component (10 a) in directions (X and Y) with respect to substrate (100 a) is calculated. Based on the calculated result,vacuum adsorption device 200 moves along the (X-Y) plane so that electronic component (10 a) is aligned at a predetermined position (coordinates (X, Y)) with respect to substrate (100 a). - At that time, if opening
portion 15 is not formed in electronic component (10 a), the first main-surface side CCD camera ofcamera unit 300 captures the image ofalignment mark 14 through optically opaqueadhesive layer 12. As a result,alignment mark 14 may be blurred, resulting in recognition failure. - In electronic component (10 a) of the present embodiment, opening
portion 15 is formed underalignment mark 14. Thus, the first main-surface side CCD camera ofcamera unit 300 captures the image ofalignment mark 14 only through opticallytransparent insulation layer 13. Therefore,alignment mark 14 is unlikely to be blurred, thereby enablingcamera unit 300 to securely recognizealignment mark 14. Accordingly, electronic component (10 a) is precisely aligned to a predetermined position with respect to substrate (100 a). - When the alignment is finished,
camera unit 300 moves along the (X-Y) plane and retracts to the outside of electronic component (10 a) and substrate (100 a). Next,vacuum adsorption device 200 moves in direction (−Z) so that electronic component (10 a) is pushed against substrate (100 a). By so doing,adhesive layer 12 of electronic component (10 a) is adhered to the first main surface of substrate (100 a), and electronic component (10 a) is mounted on substrate (100 a). At that time, since the adhesive agent ofadhesive layer 12 flows and fills opening 15,adhesive layer 12 is adhered to the entire surface of substrate (100 a). Accordingly,electronic component 10 is mounted on a predetermined position of substrate (100 a), as shown inFIG. 24 . - In step (S25) of
FIG. 16 , buildup layer (B1) is completed. - More specifically, as shown in
FIG. 25 ,insulation layer 131 is formed to coverelectronic component 10. Moreover, as shown inFIG. 1 , via conductors (145 b, 147 b) each penetrating throughinsulation layer 131 are formed ininsulation layer 131, andconductive pattern 133 is formed to be connected to via conductors (145 b, 147 b). Accordingly, buildup layer (B1) is completed. - As shown in
FIGS. 1 and 25 , in multilayer printedwiring board 100 of the present embodiment, the number of layers (three) of interlayer materials in buildup layer (B1) is different from the number of layers (two) of interlayer materials in buildup layer (B2). However, that is not the only option, and the number of layers of interlayer materials may be the same in buildup layers (B1, B2). From the viewpoint of suppressing warping of multilayer printedwiring board 100, the number of layers of interlayer materials is preferred to be the same in the upper and lower buildup layers. - In step (S26) of
FIG. 16 , solder-resistlayer 135 is formed. - More specifically, solder-resist
layer 135 is formed to coverconductive pattern 133 as shown inFIG. 1 . - In step (S27) of
FIG. 16 ,pad 137 is formed. - More specifically, as shown in
FIG. 1 , exposing portion (135 a) is formed in solder-resistlayer 135 so as to exposeconductive pattern 133. The exposed portion ofconductive pattern 133 becomespad 137. - As described above, multilayer printed
wiring board 100 as shown inFIG. 1 is completed. - The manufacturing method of the present embodiment is suitable for manufacturing multilayer printed
wiring board 100. Using such a manufacturing method, an excellent multilayer printedwiring board 100 withelectronic component 10 mounted accurately at the predetermined position is achieved. - Next, a multilayer printed wiring board according to a first modified example of the present embodiment is described.
- As an (X-Z) cross section in
FIG. 26 shows, multilayer printedwiring board 201 according to the first modified example of the present embodiment has buildup layer (B3) and solder-resistlayer 235. Multilayer printedwiring board 201 does not have a core substrate; namely, it is a coreless multilayer printed wiring board. - Buildup layer (B3) has
pad 221,insulation layer 223, via conductor (241 b),conductive pattern 225,insulation layer 227, via conductor (243 b),conductive pattern 229,insulation layer 231, via conductor (245 b) andconductive pattern 233.Electronic component 10 is mounted insideinsulation layer 231. - Solder-resist
layer 235 having exposing portion (235 a) to exposeconductive pattern 233 is formed on the first main-surface side ofinsulation layer 231. The exposed portion ofconductive pattern 233 becomespad 237. On the second main-surface side ofinsulation layer 223,pad 221 is exposed. It is an option to form a solder-resist layer having an exposing portion to expose part ofpad 221 on the second main-surface side ofinsulation layer 223. - The lower part of
FIG. 26 shows an enlarged view of main portion (A2) of multilayer printedwiring board 201 according to the first modified example of the present embodiment. Described in further detail, in multilayer printedwiring board 201,insulation layer 223 is formed to coverpad 221. Via conductor (241 b) is formed ininsulation layer 223 to penetrate throughinsulation layer 223.Conductive pattern 225 is formed on the first main-surface side ofinsulation layer 223.Conductive pattern 225 is connected to via conductor (241 b).Insulation layer 227 is formed to coverconductive pattern 225. Via conductor (243 b) is formed ininsulation layer 227 to penetrate throughinsulation layer 227. -
Conductive pattern 229 is formed on the first main-surface side ofinsulation layer 227.Conductive pattern 229 is connected to via conductor (243 b).Electronic component 10 is mounted on the first main-surface side ofinsulation layer 227.Insulation layer 231 is formed to coverconductive pattern 229 andelectronic component 10. Via conductor (245 b) is formed ininsulation layer 231 to penetrate throughinsulation layer 231. - As shown in
FIG. 26 , openingportion 15 inelectronic component 10 mounted insideinsulation layer 231 has disappeared. Via conductor (247 b) is connected toconductive pattern 17 formed on the first main-surface side ofelectronic component 10.Conductive pattern 233 is formed on the first main-surface side of via conductors (245 b, 247 b) above. Solder-resistlayer 235 having exposing portion (235 a) to exposeconductive pattern 233 is formed on the first main-surface side ofinsulation layer 231. - A method for manufacturing multilayer printed
wiring board 201 above is described. Multilayer printedwiring board 201 according to the first modified example of the present embodiment is manufactured by a method described below. - First, as shown in
FIG. 27 ,support body 401 is prepared.Support body 401 is made of glass epoxy, for example. Then,copper foil 403 with an adhesive carrier is formed onsupport body 401. Next, oncopper foil 403 with a carrier,pad 221 is formed using, for example, a full-additive or semi-additive (SAP) method. - Next, as shown in
FIG. 28 , onpad 221,insulation layer 223, via conductor (241 b),conductive pattern 225,insulation layer 227, via conductor (243 b) andconductive pattern 229 are formed using a semi-additive method, for example. By doing so, substrate (201 a) for mountingelectronic component 10 above is formed. Then,electronic component 10 is mounted at a predetermined position on a portion of buildup layer (B3). More specifically, as shown inFIG. 28 ,electronic component 10 is aligned from the (+Z) direction and adhered ontoinsulation layer 227 of substrate (201 a). Here, the alignment is conducted using a flip-chip bonder in the same manner employed as in multilayer printedwiring board 100 shown inFIG. 23 . - Next, as shown in
FIG. 29 ,insulation layer 227 is formed to coverelectronic component 10 andconductive pattern 229. Furthermore, via conductors (245 b, 247 b) andconductive pattern 233 are formed. Then,support body 401 andcopper foil 403 with a carrier are removed. Accordingly,pad 221 is exposed on the second main-surface side of buildup layer (B3), as shown inFIG. 30 . - Next, solder-resist
layer 235 is formed. More specifically, as shown inFIG. 26 , solder-resistlayer 235 is formed to coverconductive pattern 233. Then, exposing portion (235 a) is formed in solder-resistlayer 235 to exposeconductive pattern 233. Accordingly, the exposed portion ofconductive pattern 233 becomespad 237. - Accordingly, multilayer printed
wiring board 201 shown inFIG. 26 is completed. - The manufacturing method according to the first modified example of the present embodiment is suitable for manufacturing multilayer printed
wiring board 201. Using such a manufacturing method, excellent multilayer printed wiring board 201 (coreless multilayer printed wiring board) withelectronic component 10 mounted accurately at a predetermined position is achieved. - Next, a multilayer printed wiring board according to a second modified example of the present embodiment is described. Multilayer printed
wiring board 301 according to the second modified example of the present embodiment hascore substrate 320, first buildup layer (B5), second buildup layer (B6), solder-resistlayer 335 and solder-resistlayer 332, as an (X-Z) cross section shows inFIG. 31 . In multilayer printedwiring board 301,electronic component 10 is directly mounted on the first main-surface side ofcore substrate 320. - First buildup layer (B5) has
conductive pattern 321,insulation layer 323, via conductor (341 b),conductive pattern 325,insulation layer 327, via conductor (343 b),conductive pattern 329,insulation layer 331, via conductor (345 b) andconductive pattern 333. -
Core substrate 320 is made of glass epoxy, for example. Hole (340 a) (through hole) bored by laser light, for example, is formed incore substrate 320.Core substrate 320 has through-hole conductor (340 b), made by filling hole (340 a) with copper plating, for example. Through-hole conductor (340 b) electrically connects first main-surface sideconductive pattern 321 and second main-surface sideconductive pattern 322. -
Insulation layer 324 is formed to coverconductive pattern 322. Via conductor (342 b) is formed ininsulation layer 324 to penetrate throughinsulation layer 324.Conductive pattern 326 is formed on the second main-surface side ofinsulation layer 324.Conductive pattern 326 is connected to via conductor (342 b).Insulation layer 328 is formed to coverconductive pattern 326. Via conductor (344 b) is formed ininsulation layer 328 to penetrate throughinsulation layer 328.Conductive pattern 330 is formed on the second main-surface side ofinsulation layer 328.Conductive pattern 330 is connected to via conductor (344 b). Second buildup layer (B6) is made up ofconductive pattern 322,insulation layer 324, via conductor (342 b),conductive pattern 326,insulation layer 328, via conductor (344 b) andconductive pattern 330. - On the second main-surface side of
insulation layer 328, solder-resistlayer 332 having exposing portion (332 a) to exposeconductive pattern 330 is formed. The exposed portion ofconductive pattern 330 becomespad 336. - As shown in
FIG. 31 , in multilayer printedwiring board 301 according to the second modified example of the present embodiment, the number of layers (three) of interlayer materials in buildup layer (B5) is different from the number of layers (two) of interlayer materials in buildup layer (B6). However, that is not the only option, and the number of layers of interlayer materials may be the same in buildup layers (B5, B6). From the viewpoint of suppressing warping of multilayer printedwiring board 301, the number of layers of interlayer materials is preferred to be the same in the upper and lower buildup layers. - Main portion (A3) of multilayer printed
wiring board 301 according to the second modified example of the present embodiment is enlarged and shown in the lower portion ofFIG. 31 . Described in further detail, in multilayer printedwiring board 301 according to the second modified example of the present embodiment,conductive pattern 321 is formed on the first main-surface side ofcore substrate 320. Also,electronic component 10 is mounted on the first main-surface side ofcore substrate 320.Insulation layer 323 is formed to coverconductive pattern 321 andelectronic component 10. Via conductor (341 b) is formed ininsulation layer 323 to penetrate throughinsulation layer 323. Also, via conductor (347 b) is formed ininsulation layer 323 to penetrate throughinsulation layer 323 and be connected toconductive pattern 17 ofelectronic component 10.Conductive pattern 325 is formed on the first main-surface side ofinsulation layer 323.Conductive pattern 325 is connected to via conductors (341 b, 347 b).Insulation layer 327 is formed to coverconductive pattern 325. Via conductor (343 b) is formed ininsulation layer 327 to penetrate throughinsulation layer 327. -
Conductive pattern 329 is formed on the first main-surface side ofinsulation layer 327.Conductive pattern 329 is connected to via conductor (343 b).Insulation layer 331 is formed to coverconductive pattern 329. Via conductor (345 b) is formed ininsulation layer 331 to penetrate throughinsulation layer 331. - To manufacture multilayer printed
wiring board 301 according to the second modified example of the present embodiment, first, hole (340 a) (through hole) bored by laser light, for example, is formed incore substrate 320, as shown inFIG. 32 . Next, hole (340 a) is filled with copper plating, for example, so as to form through-hole conductor (340 b). Then,conductive pattern 321 is formed on the first main-surface side ofcore substrate 320, andconductive pattern 322 is formed on the second main-surface side ofcore substrate 320. - Next, as shown in
FIG. 33 , electronic component (10 a) (electronic component prior to being adhered) is mounted on a predetermined position ofcore substrate 320. More specifically, as shown inFIG. 33 , electronic component (10 a) is aligned from the (+Z) direction and adhered to the first main-surface side ofcore substrate 320. Such alignment is conducted using a flip-chip bonder in the same manner as that for multilayer printedwiring board 100 described above with reference toFIG. 23 . -
FIG. 34 shows a state in whichelectronic component 10 is adhered tocore substrate 320. The rest is conducted the same as in the method for manufacturing multilayer printedwiring board 100 described above, and first buildup layer (B5) and second buildup layer (B6) are formed. Accordingly, multilayer printedwiring board 301 is manufactured. - To describe multilayer printed
wiring board 301 according to the second modified example of the present embodiment, first buildup layer (B5) having three insulation layers is formed on the first main-surface side ofcore substrate 320, and second buildup layer (B6) having two insulation layers is formed on the second main-surface side. However, that is not the only option, andcore substrate 320 with mountedelectronic component 10 as shown inFIG. 34 may be used to form various lamination structures. - As shown in
FIG. 3 , the adhesive agent ofadhesive layer 12 is present on the entire circumference of openingportion 15 in electronic component (10 a) of the embodiment. Thus, the air in openingportion 15 cannot escape during the above adhesion process, and may cause a void to be formed inadhesive layer 12. Electronic components according to modified examples of the present embodiment are described with reference toFIGS. 35 and 36 . - As shown in
FIG. 35 ,electronic component 30 according to a first modified example of the embodiment hasadhesive layer 32 with openingportion 35,insulation layer 33 andalignment mark 34, the same as in electronic component (10 a) described above. The difference inelectronic component 30 from electronic component (10 a) is the shape of openingportion 35. Openingportions 35 are respectively formed near the opposing corners ofelectronic component 30. Here, openingportion 35 reaches the outer edge ofinsulation layer 33. - Namely, along the outer edge of
insulation layer 33, no adhesive agent is present at a corner of openingportion 35. Thus, whenelectronic component 30 is adhered to the substrate, the adhesive agent flows toward the corner of openingportion 35 while the air in openingportion 35 escapes through the corner of openingportion 35. Therefore, the air in openingportion 35 is less likely to remain inadhesive layer 32. Accordingly, a void is prevented from being formed inadhesive layer 32. - As shown in
FIG. 36 ,electronic component 40 according to a second modified example of the present embodiment hasadhesive layer 42 with openingportion 45,insulation layer 43 andalignment mark 44, the same as in electronic components (10 a, 30) described above. The difference inelectronic component 40 from electronic components (10 a, 30) is the shape of openingportion 45. Openingportions 45 are respectively formed by cutting off the opposing corners ofadhesive layer 42. Namely, openingportion 45 reaches the outer edge ofinsulation layer 43. - As described above, along the outer edge of
insulation layer 43, no adhesive agent is present at a corner of openingportion 45. Thus, whenelectronic component 40 is adhered to the substrate, the adhesive agent flows toward the corner of openingportion 45 while the air in openingportion 45 escapes through the corner of openingportion 45. Therefore, the air in openingportion 45 is less likely to remain inadhesive layer 42. Accordingly, a void is prevented from being formed inadhesive layer 42. - So far, descriptions are provided for electronic components, methods for manufacturing such electronic components, and methods for manufacturing multilayer printed wiring boards according to embodiments of the present invention. However, the present invention is not limited to those embodiments.
- The planar shape of the electronic components is not limited to a rectangle, but any planar shape may be employed depending on usage purposes. In the above manufacturing methods,
adhesive layer 12 was uniformly formed and part of the adhesive layer was later removed so that openingportion 15 was formed. However, that is not the only option, and openingportion 15 may be formed at the same time thatadhesive layer 12 is formed on the second main-surface side ofinsulation layer 13. - When the above manufacturing methods were described, the adhesive agent was removed by a method using photolithography. However, that is not the only option, and other methods such as mechanical methods may be used to remove the adhesive agent. Regarding photolithography, an example was described in which the photosensitive portion was denatured and removed. However, it is another option for the photosensitive portion to be cured and for the non-photosensitive portion to be removed by a removing solution.
- Regarding other features, the structures of electronic components (10 a, 30, 40) and multilayer printed wiring boards (100, 201), types of their structural elements, properties, measurements, materials, shapes, number of layers, positions and the like may be modified freely within a scope that does not deviate from the gist of the present invention.
- As the material for insulation layers, any material may be used as long as it is optically transparent at least before a thermosetting treatment. For example, as resins for forming insulation layers, thermosetting resins or thermoplastic resins may be used. In addition to epoxy resins and polyimides, examples of thermosetting resins to be used are BT resin, allyl polyphenylene ether resin (A-PPE resin), aramid resin and the like. Also, examples of thermoplastic resins to be used are polycarbonate resin, liquid-crystal polymer (LCP), PEEK resin and the like. Those materials are preferred to be selected as needed from the viewpoints of transparency, insulation, dielectric properties, heat resistance, mechanical characteristics, and the like. Alignment marks, conductive patterns, insulation layers and adhesive layers may be formed with multiple layers each made of different materials.
- The steps for manufacturing an electronic component are not limited to the order and contents shown in the flowchart of
FIG. 4 ; the order and contents may be modified freely within a scope that does not deviate from the gist of the present invention. Also, any unnecessary step may be omitted depending on usage purposes or the like. - The steps for manufacturing a multilayer printed wiring board are not limited to the order and contents shown in the flowchart of
FIG. 16 ; the order and contents may be modified freely within a scope that does not deviate from the gist of the present invention. - Also, any unnecessary step may be omitted depending on usage purposes. When the number of lead terminals in an IC chip mounted on a multilayer printed wiring board increases, the distance between lead terminals decreases. Then, pads to be connected to the lead terminals of an IC chip are formed at fine positional intervals on a surface of a multilayer printed wiring board.
- Next, another method for manufacturing electronic component (10 a) as shown in
FIG. 38 is described. In the present embodiment, electronic component (10 a) is manufactured by a method shown inFIG. 37 . - In step (S31) of
FIG. 37 ,support body 400 is prepared as shown inFIG. 39 .Support body 400 is formed of a carrier and a copper foil formed on the carrier, for example. - In step (S32) of
FIG. 37 , wiring 11 with a finer wiring pitch andalignment mark 14 are formed on the copper foil ofsupport body 400 as shown inFIG. 40 . - In step (S33) of
FIG. 37 ,insulation layer 16 is formed onsupport body 400 and coverswiring 11 with a finer wiring pitch andalignment mark 14 formed on the copper foil ofsupport body 400 as shown inFIG. 41 .Insulation layer 16 may be optically transparent or optically non-transparent, and may be made of a transparent or non-transparent resin, for example. As examples of the resin, epoxy resin, phenol resin, polyol resin, polycarbonate resin and the like may be used. - In step (S34) of
FIG. 37 , as shown inFIG. 42 , hole (16 a) (via hole) is formed ininsulation layer 16 by irradiating laser light, for example. Hole (16 a) reacheswiring 11 with a finer wiring pitch. - Next, in step (S35) of
FIG. 37 , via conductor (16 b) and a conductive layer are formed as shown inFIG. 43 . Electroless plating and electrolytic plating are performed using copper, for example, thereby filling hole (16 a) to form via conductor (16 b) while forming conductive layer oninsulation layer 16. - In step (S36) of
FIG. 37 ,support body 400 is removed. More specifically,support body 400 is removed frominsulation layer 16.FIG. 44 shows the cross section ofinsulation layer 16 havingwiring 11 andalignment mark 14 aftersupport body 400 has been removed.Support body 400 may be recyclable. - In step (S37) of
FIG. 37 ,adhesive layer 12 is formed. More specifically, as shown inFIG. 45 ,adhesive layer 12 is laminated on the first main-surface side (lower surface) ofinsulation layer 16 by coating an adhesive agent containing filler, for example. The adhesive agent for formingadhesive layer 12 is photosensitive. Accordingly, openingportion 15 is formed precisely at a predetermined portion in the next step for formingopening portion 15. - In step (S38) of
FIG. 37 , openingportion 15 is formed inadhesive layer 12. More specifically, as shown inFIG. 46 , the adhesive agent at a portion ofadhesive layer 12 located underalignment mark 14 is photosensitized and denatured by photolithography, for example. Then, using a removing solution, for example, the photosensitized and denatured portion (12 a) is removed, thereby forming opening portion 15 (seeFIG. 38 ). - As described so far, opening
portion 15 of the present embodiment is formed by uniformly formingadhesive layer 12 first and by removing part of the adhesive agent. Therefore, openingportion 15 is accurately formed at a predetermined portion whileadhesive layer 12 is formed to have a uniform thickness. - Accordingly, electronic component (10 a) of the present embodiment is completed as shown in
FIG. 38 . - The manufacturing method of the present embodiment is suitable for manufacturing electronic component (10 a). Using such a manufacturing method, an excellent electronic component (10 a) is achieved, in which positional shifting is suppressed between
alignment mark 14 andopening portion 15. - To incorporate an electronic component such as another multilayer substrate into a multilayer printed wiring board, a flip-chip bonder may be used. A flip-chip bonder is a device to align an electronic component with respect to a multilayer printed wiring board. Alignment by a flip-chip bonder is carried out based on an alignment mark formed on the electronic component and another alignment mark formed on the multiplayer printed wiring board. For an accurate alignment, it is important to accurately detect the alignment mark formed on the electronic component. A flip-chip bonder is provided with a camera, and alignment marks are detected by the camera.
- However, the surface of an alignment mark of an electronic component may be covered by an adhesive agent or the like used for adhering the electronic component to the multilayer printed wiring board. In such a case, when the camera tries to detect the alignment mark, irregular reflection may occur, caused by the filler contained in the adhesive agent. Thus, an accurate detection of the alignment mark may be hindered.
- An electronic component according to an embodiment of the present invention has an adhesive layer made of an optically opaque adhesive agent and is provided with an opening, an insulation layer positioned on the adhesive layer, and an alignment mark positioned on the insulation layer and over the upper portion of the opening portion.
- A method for manufacturing an electronic component according to another embodiment of the present invention includes the following: preparing a support body; forming an insulation layer on a first main-surface side of the support body; forming an alignment mark on a first main-surface side of the insulation layer; removing the support body; and using an optically opaque adhesive agent, forming an adhesive layer with an opening portion provided on a second main-surface side of the insulation layer and under the alignment mark.
- Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013090389A JP2014216377A (en) | 2013-04-23 | 2013-04-23 | Electronic component, manufacturing method of the same, and manufacturing method of multilayer printed board |
JP2013-090389 | 2013-04-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20140311780A1 true US20140311780A1 (en) | 2014-10-23 |
US9433085B2 US9433085B2 (en) | 2016-08-30 |
Family
ID=51728151
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/259,522 Active 2034-07-04 US9433085B2 (en) | 2013-04-23 | 2014-04-23 | Electronic component, method for manufacturing the same and method for manufacturing multilayer printed wiring board |
Country Status (3)
Country | Link |
---|---|
US (1) | US9433085B2 (en) |
JP (1) | JP2014216377A (en) |
CN (1) | CN104125706A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9263784B2 (en) * | 2014-05-02 | 2016-02-16 | Ibiden Co., Ltd. | Package substrate |
US10980129B2 (en) * | 2018-12-20 | 2021-04-13 | Intel Corporation | Asymmetric electronic substrate and method of manufacture |
US11728088B2 (en) * | 2017-11-27 | 2023-08-15 | Murata Manufacturing Co., Ltd. | Multilayer coil component |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5990438B2 (en) * | 2012-09-13 | 2016-09-14 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP7271081B2 (en) * | 2017-10-18 | 2023-05-11 | 日東電工株式会社 | wiring circuit board |
JP7302224B2 (en) * | 2019-03-26 | 2023-07-04 | Tdk株式会社 | Circuit board with built-in electronic components |
CN113394193B (en) * | 2020-03-13 | 2022-03-22 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof, and fusing method of laser fuse |
Citations (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5538924A (en) * | 1995-09-05 | 1996-07-23 | Vanguard International Semiconductor Co. | Method of forming a moisture guard ring for integrated circuit applications |
US5567643A (en) * | 1994-05-31 | 1996-10-22 | Taiwan Semiconductor Manufacturing Company | Method of forming contamination guard ring for semiconductor integrated circuit applications |
US5830799A (en) * | 1995-08-25 | 1998-11-03 | Sony Corporation | Method for forming embedded diffusion layers using an alignment mark |
US5869383A (en) * | 1996-06-07 | 1999-02-09 | Vanguard International Semiconductor Corporation | High contrast, low noise alignment mark for laser trimming of redundant memory arrays |
US20020048928A1 (en) * | 2000-10-20 | 2002-04-25 | Hideo Nakagawa | Semiconductor device and method for fabricating the same |
US6392300B1 (en) * | 1999-06-28 | 2002-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire |
US20020098707A1 (en) * | 2001-01-24 | 2002-07-25 | Infineon Technologies North America Corp. | Design of lithography alignment and overlay measurement marks on CMP finished damascene surface |
US20020123212A1 (en) * | 1999-05-17 | 2002-09-05 | Tatsuya Kunikiyo | Semiconductor device manufacturing method |
US20020142235A1 (en) * | 2001-04-02 | 2002-10-03 | Nec Corporation | Photo mask for fabricating semiconductor device having dual damascene structure |
US6492269B1 (en) * | 2001-01-08 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Methods for edge alignment mark protection during damascene electrochemical plating of copper |
US20030008472A1 (en) * | 2000-03-09 | 2003-01-09 | Fujitsu Limited | Semiconductor device and fabrication process thereof |
US20030017707A1 (en) * | 2001-07-19 | 2003-01-23 | Tomio Yamashita | Semiconductor device and method for manufacturing thereof |
US20030052384A1 (en) * | 2001-09-20 | 2003-03-20 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device with filling insulating film into trench |
US20030052440A1 (en) * | 2001-09-17 | 2003-03-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for fabricating the same |
US20030054597A1 (en) * | 2001-09-20 | 2003-03-20 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate |
US20030127751A1 (en) * | 2002-01-09 | 2003-07-10 | Mitsubishi Denki Kabushiki Kaisha | Alignment mark structure |
US6818524B1 (en) * | 2004-03-30 | 2004-11-16 | Nanya Technology Group | Method of improving alignment for semiconductor fabrication |
US20050069815A1 (en) * | 2003-08-13 | 2005-03-31 | Tomoyuki Takeishi | Processing method and semiconductor manufacturing method |
US20050101107A1 (en) * | 2003-11-12 | 2005-05-12 | Renesas Technology Corp. | Method for manufacturing semiconductor device |
US20050186753A1 (en) * | 2004-02-25 | 2005-08-25 | Ping-Hsu Chen | FIB exposure of alignment marks in MIM technology |
US20050186756A1 (en) * | 2004-02-20 | 2005-08-25 | Sachiko Yabe | Method of forming alignment marks for semiconductor device fabrication |
US6979651B1 (en) * | 2002-07-29 | 2005-12-27 | Advanced Micro Devices, Inc. | Method for forming alignment features and back-side contacts with fewer lithography and etch steps |
US20060027926A1 (en) * | 2004-08-04 | 2006-02-09 | Fujitsu Limited | Semiconductor device, semiconductor substrate and fabrication process of a semiconductor device |
US20060103035A1 (en) * | 2004-11-16 | 2006-05-18 | Fujitsu Limited | Semiconductor Wafer, Semiconductor Device, And Method Of Manufacturing Semiconductor Device |
US20070164432A1 (en) * | 2003-05-26 | 2007-07-19 | Casio Computer Co., Ltd. | Semiconductor device having alignment post electrode and method of manufacturing the same |
US20080038897A1 (en) * | 2006-08-08 | 2008-02-14 | Kazushi Suzuki | Method of manufacturing a semiconductor device |
US7375289B2 (en) * | 1997-12-11 | 2008-05-20 | Ibiden Co., Ltd. | Multi-layer printed wiring board including an alignment mark as an index for a position of via holes |
US20090186305A1 (en) * | 2008-01-22 | 2009-07-23 | Nitto Denko Corporation | Manufacturing method of optical waveguide device |
US20090205859A1 (en) * | 2008-02-14 | 2009-08-20 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
US20090205202A1 (en) * | 2008-02-14 | 2009-08-20 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
US20090231820A1 (en) * | 2008-03-17 | 2009-09-17 | Ibiden Co., Ltd. | Capacitor-incorporated printed wiring board and electronic component |
US20090244865A1 (en) * | 2008-03-27 | 2009-10-01 | Ibiden Co., Ltd | Method for manufacturing multilayer printed wiring board |
US20090242252A1 (en) * | 2008-03-27 | 2009-10-01 | Ibiden Co., Ltd. | Method for Manufacturing A Multilayer Printed Wiring Board for Providing an Electronic Component Therein |
US20090269704A1 (en) * | 2008-04-24 | 2009-10-29 | Nitto Denko Corporation | Manufacturing method of opto-electric hybrid board |
US20090293271A1 (en) * | 2008-06-02 | 2009-12-03 | Ibiden Co., Ltd. | Printed wiring board with built-in electronic component and manufacturing method thereof |
US20090309186A1 (en) * | 2006-12-27 | 2009-12-17 | Naoya Inoue | Semiconductor device and its manufacturing method |
US20100003771A1 (en) * | 2006-06-23 | 2010-01-07 | Hitachi Chemical Company, Ltd. | Production method of semiconductor device and bonding film |
US20100007035A1 (en) * | 2008-07-09 | 2010-01-14 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20100104246A1 (en) * | 2008-10-28 | 2010-04-29 | Nitto Denko Corporation | Manufacturing method of opto-electric hybrid module and opto-electric hybrid module manufactured thereby |
US20100129036A1 (en) * | 2008-11-26 | 2010-05-27 | Nitto Denko Corporation | Opto-electric hybrid board and manufacturing method thereof |
US20100230773A1 (en) * | 2009-03-11 | 2010-09-16 | Sony Corporation | Solid-state image pickup device and a method of manufacturing the same |
US20110127629A1 (en) * | 2009-11-30 | 2011-06-02 | Sony Corporation | Solid-state imaging device, method of manufacturing the same, and electronic apparatus |
US20110186962A1 (en) * | 2010-01-15 | 2011-08-04 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20120313236A1 (en) * | 2011-06-09 | 2012-12-13 | Sony Corporation | Semiconductor device and manufacturing method for semiconductor device |
US20130161079A1 (en) * | 2011-12-22 | 2013-06-27 | Ngk Spark Plug Co., Ltd. | Multi-layer wiring substrate and manufacturing method thereof |
US20130160290A1 (en) * | 2011-12-26 | 2013-06-27 | Ngk Spark Plug Co., Ltd. | Method of manufacturing multi-layer wiring board |
US20130181344A1 (en) * | 2010-05-31 | 2013-07-18 | Sanyo Electric Co., Ltd. | Semiconductor module, method for manufacturing the semiconductor module, and mobile apparatus |
US20130232784A1 (en) * | 2012-03-06 | 2013-09-12 | Ngk Spark Plug Co., Ltd | Method of manufacturing wiring substrate |
US20140225193A1 (en) * | 2012-10-18 | 2014-08-14 | International Business Machines Corporation | Carbon nanostructure device fabrication utilizing protect layers |
US9110237B2 (en) * | 2010-12-22 | 2015-08-18 | Nitto Denko Corporation | Method of manufacturing optical waveguide |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7462784B2 (en) | 2006-05-02 | 2008-12-09 | Ibiden Co., Ltd. | Heat resistant substrate incorporated circuit wiring board |
-
2013
- 2013-04-23 JP JP2013090389A patent/JP2014216377A/en active Pending
-
2014
- 2014-04-21 CN CN201410160369.9A patent/CN104125706A/en active Pending
- 2014-04-23 US US14/259,522 patent/US9433085B2/en active Active
Patent Citations (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5567643A (en) * | 1994-05-31 | 1996-10-22 | Taiwan Semiconductor Manufacturing Company | Method of forming contamination guard ring for semiconductor integrated circuit applications |
US5830799A (en) * | 1995-08-25 | 1998-11-03 | Sony Corporation | Method for forming embedded diffusion layers using an alignment mark |
US5538924A (en) * | 1995-09-05 | 1996-07-23 | Vanguard International Semiconductor Co. | Method of forming a moisture guard ring for integrated circuit applications |
US5869383A (en) * | 1996-06-07 | 1999-02-09 | Vanguard International Semiconductor Corporation | High contrast, low noise alignment mark for laser trimming of redundant memory arrays |
US7375289B2 (en) * | 1997-12-11 | 2008-05-20 | Ibiden Co., Ltd. | Multi-layer printed wiring board including an alignment mark as an index for a position of via holes |
US20020123212A1 (en) * | 1999-05-17 | 2002-09-05 | Tatsuya Kunikiyo | Semiconductor device manufacturing method |
US6392300B1 (en) * | 1999-06-28 | 2002-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire |
US20030008472A1 (en) * | 2000-03-09 | 2003-01-09 | Fujitsu Limited | Semiconductor device and fabrication process thereof |
US20020048928A1 (en) * | 2000-10-20 | 2002-04-25 | Hideo Nakagawa | Semiconductor device and method for fabricating the same |
US6492269B1 (en) * | 2001-01-08 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Methods for edge alignment mark protection during damascene electrochemical plating of copper |
US20020098707A1 (en) * | 2001-01-24 | 2002-07-25 | Infineon Technologies North America Corp. | Design of lithography alignment and overlay measurement marks on CMP finished damascene surface |
US20020142235A1 (en) * | 2001-04-02 | 2002-10-03 | Nec Corporation | Photo mask for fabricating semiconductor device having dual damascene structure |
US20030017707A1 (en) * | 2001-07-19 | 2003-01-23 | Tomio Yamashita | Semiconductor device and method for manufacturing thereof |
US20030052440A1 (en) * | 2001-09-17 | 2003-03-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method for fabricating the same |
US20030052384A1 (en) * | 2001-09-20 | 2003-03-20 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device with filling insulating film into trench |
US20030054597A1 (en) * | 2001-09-20 | 2003-03-20 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate |
US20030127751A1 (en) * | 2002-01-09 | 2003-07-10 | Mitsubishi Denki Kabushiki Kaisha | Alignment mark structure |
US6979651B1 (en) * | 2002-07-29 | 2005-12-27 | Advanced Micro Devices, Inc. | Method for forming alignment features and back-side contacts with fewer lithography and etch steps |
US20070164432A1 (en) * | 2003-05-26 | 2007-07-19 | Casio Computer Co., Ltd. | Semiconductor device having alignment post electrode and method of manufacturing the same |
US20050069815A1 (en) * | 2003-08-13 | 2005-03-31 | Tomoyuki Takeishi | Processing method and semiconductor manufacturing method |
US20050101107A1 (en) * | 2003-11-12 | 2005-05-12 | Renesas Technology Corp. | Method for manufacturing semiconductor device |
US20050186756A1 (en) * | 2004-02-20 | 2005-08-25 | Sachiko Yabe | Method of forming alignment marks for semiconductor device fabrication |
US20050186753A1 (en) * | 2004-02-25 | 2005-08-25 | Ping-Hsu Chen | FIB exposure of alignment marks in MIM technology |
US6818524B1 (en) * | 2004-03-30 | 2004-11-16 | Nanya Technology Group | Method of improving alignment for semiconductor fabrication |
US20060027926A1 (en) * | 2004-08-04 | 2006-02-09 | Fujitsu Limited | Semiconductor device, semiconductor substrate and fabrication process of a semiconductor device |
US20060125101A1 (en) * | 2004-08-04 | 2006-06-15 | Fujitsu Limited | Semiconductor device, semiconductor substrate and fabrication process of a semiconductor device |
US20060103035A1 (en) * | 2004-11-16 | 2006-05-18 | Fujitsu Limited | Semiconductor Wafer, Semiconductor Device, And Method Of Manufacturing Semiconductor Device |
US20100003771A1 (en) * | 2006-06-23 | 2010-01-07 | Hitachi Chemical Company, Ltd. | Production method of semiconductor device and bonding film |
US20080038897A1 (en) * | 2006-08-08 | 2008-02-14 | Kazushi Suzuki | Method of manufacturing a semiconductor device |
US20090309186A1 (en) * | 2006-12-27 | 2009-12-17 | Naoya Inoue | Semiconductor device and its manufacturing method |
US20090186305A1 (en) * | 2008-01-22 | 2009-07-23 | Nitto Denko Corporation | Manufacturing method of optical waveguide device |
US20090205859A1 (en) * | 2008-02-14 | 2009-08-20 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
US20090205202A1 (en) * | 2008-02-14 | 2009-08-20 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
US20090231820A1 (en) * | 2008-03-17 | 2009-09-17 | Ibiden Co., Ltd. | Capacitor-incorporated printed wiring board and electronic component |
US20090244865A1 (en) * | 2008-03-27 | 2009-10-01 | Ibiden Co., Ltd | Method for manufacturing multilayer printed wiring board |
US20090242252A1 (en) * | 2008-03-27 | 2009-10-01 | Ibiden Co., Ltd. | Method for Manufacturing A Multilayer Printed Wiring Board for Providing an Electronic Component Therein |
US20120170240A1 (en) * | 2008-03-27 | 2012-07-05 | Ibiden Co., Ltd. | Method of manufacturing a multilayer printed wiring board for providing an electronic component therein |
US20090269704A1 (en) * | 2008-04-24 | 2009-10-29 | Nitto Denko Corporation | Manufacturing method of opto-electric hybrid board |
US20090293271A1 (en) * | 2008-06-02 | 2009-12-03 | Ibiden Co., Ltd. | Printed wiring board with built-in electronic component and manufacturing method thereof |
US20100007035A1 (en) * | 2008-07-09 | 2010-01-14 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20100104246A1 (en) * | 2008-10-28 | 2010-04-29 | Nitto Denko Corporation | Manufacturing method of opto-electric hybrid module and opto-electric hybrid module manufactured thereby |
US20100129036A1 (en) * | 2008-11-26 | 2010-05-27 | Nitto Denko Corporation | Opto-electric hybrid board and manufacturing method thereof |
US20100230773A1 (en) * | 2009-03-11 | 2010-09-16 | Sony Corporation | Solid-state image pickup device and a method of manufacturing the same |
US20110127629A1 (en) * | 2009-11-30 | 2011-06-02 | Sony Corporation | Solid-state imaging device, method of manufacturing the same, and electronic apparatus |
US20110186962A1 (en) * | 2010-01-15 | 2011-08-04 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20130181344A1 (en) * | 2010-05-31 | 2013-07-18 | Sanyo Electric Co., Ltd. | Semiconductor module, method for manufacturing the semiconductor module, and mobile apparatus |
US9110237B2 (en) * | 2010-12-22 | 2015-08-18 | Nitto Denko Corporation | Method of manufacturing optical waveguide |
US20120313236A1 (en) * | 2011-06-09 | 2012-12-13 | Sony Corporation | Semiconductor device and manufacturing method for semiconductor device |
US20130161079A1 (en) * | 2011-12-22 | 2013-06-27 | Ngk Spark Plug Co., Ltd. | Multi-layer wiring substrate and manufacturing method thereof |
US20130160290A1 (en) * | 2011-12-26 | 2013-06-27 | Ngk Spark Plug Co., Ltd. | Method of manufacturing multi-layer wiring board |
US20130232784A1 (en) * | 2012-03-06 | 2013-09-12 | Ngk Spark Plug Co., Ltd | Method of manufacturing wiring substrate |
US20140225193A1 (en) * | 2012-10-18 | 2014-08-14 | International Business Machines Corporation | Carbon nanostructure device fabrication utilizing protect layers |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9263784B2 (en) * | 2014-05-02 | 2016-02-16 | Ibiden Co., Ltd. | Package substrate |
US11728088B2 (en) * | 2017-11-27 | 2023-08-15 | Murata Manufacturing Co., Ltd. | Multilayer coil component |
US10980129B2 (en) * | 2018-12-20 | 2021-04-13 | Intel Corporation | Asymmetric electronic substrate and method of manufacture |
Also Published As
Publication number | Publication date |
---|---|
CN104125706A (en) | 2014-10-29 |
US9433085B2 (en) | 2016-08-30 |
JP2014216377A (en) | 2014-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9433085B2 (en) | Electronic component, method for manufacturing the same and method for manufacturing multilayer printed wiring board | |
KR101208378B1 (en) | Wiring board and method for manufacturing wiring board | |
US8261435B2 (en) | Printed wiring board and method for manufacturing the same | |
US7935893B2 (en) | Method of manufacturing printed wiring board with built-in electronic component | |
KR101248713B1 (en) | Wiring board and method for manufacturing same | |
US8482117B2 (en) | Semiconductor device with electronic component incorporation substrate | |
US8383948B2 (en) | Flex-rigid wiring board and method for manufacturing the same | |
US8110754B2 (en) | Multi-layer wiring board and method of manufacturing the same | |
JP5078687B2 (en) | Manufacturing method of multilayer wiring board | |
US8196296B2 (en) | Method for manufacturing wiring board | |
US20100224397A1 (en) | Wiring board and method for manufacturing the same | |
US20120188734A1 (en) | Wiring board and method for manufacturing the same | |
KR101241544B1 (en) | The printed circuit board and the method for manufacturing the same | |
US20120217049A1 (en) | Wiring board with built-in imaging device | |
US8334463B2 (en) | Wiring board and method for manufacturing the same | |
KR100820633B1 (en) | Printed circuit board having embedded electronic component and manufacturing method thereof | |
TWI549579B (en) | Printed circuit board | |
US8525041B2 (en) | Multilayer wiring board and method for manufacturing the same | |
KR20160059125A (en) | Element embedded printed circuit board and method of manufacturing the same | |
JP6607087B2 (en) | Manufacturing method of electronic component built-in substrate | |
KR101905879B1 (en) | The printed circuit board and the method for manufacturing the same | |
US8546698B2 (en) | Wiring board and method for manufacturing the same | |
US20150156882A1 (en) | Printed circuit board, manufacturing method thereof, and semiconductor package | |
US20160353572A1 (en) | Printed circuit board, semiconductor package and method of manufacturing the same | |
KR101609268B1 (en) | Embedded board and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: IBIDEN CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIZUNO, YOSHINORI;TERUI, MAKOTO;KUNIEDA, MASATOSHI;AND OTHERS;REEL/FRAME:032903/0230 Effective date: 20140508 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |