US20140313676A1 - Electronic component package - Google Patents
Electronic component package Download PDFInfo
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- US20140313676A1 US20140313676A1 US14/321,214 US201414321214A US2014313676A1 US 20140313676 A1 US20140313676 A1 US 20140313676A1 US 201414321214 A US201414321214 A US 201414321214A US 2014313676 A1 US2014313676 A1 US 2014313676A1
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- United States
- Prior art keywords
- electronic component
- insulation layer
- heat sink
- adhesive
- component package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/38—Cooling arrangements using the Peltier effect
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/066—Heatsink mounted on the surface of the PCB
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
An electronic component package includes: a first insulation layer; an electronic component mounted in one surface of the first insulation layer; a heat sink formed with a cavity corresponding to the electronic component, bonded to the one surface of the first insulation layer to cover the electronic component, and formed with an inset hole and with an inlet hole; an adhesive charged in the cavity; and a circuit pattern formed in another surface of the first insulation layer.
Description
- This application is a U.S. divisional application filed under 37 CFR 1.53(b) claiming priority benefit of U.S. Ser. No. 12/010,321, filed in the United States on Jan. 23, 2008, which claims earlier foreign priority benefit to Korean Patent Application No. 10-2007-0020940, filed in the Korean Intellectual Property Office on Mar. 2, 2007, the disclosures of which are incorporated herein by reference.
- 1. Field
- The present invention relates to an electronic component package and a manufacturing method thereof.
- 2. Description of the Related Art
- Today's trend of the current electronic part industry shows that the number of input/output of chips has risen sharply, and the package is multifunctional and multiplex. Accordingly, a chip scale package that packages a chip scale as it is without using a solder and a solder bump of a flip chip ball grid array (BGA) has been developed.
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FIG. 1A through 1K illustrate an electronic component package manufacturing method in accordance with a conventional art, andFIG. 2 is a sectional view showing an electronic component package in accordance with a convention art. As shown inFIG. 1 andFIG. 2 , according to the electronic component package manufacturing method in accordance with the conventional art, a void may be generated in the process of molding achip 1. Since the process of assembling a heat sink and lay-up process, for example, are performed after thechip 1 is molded in a flexible printedcircuit board 2 by using adam member 3 and anadhesive 4, the handling may be unstably performed. - Also, as shown in
FIG. 2 , the durability may be lowered due to allowing the heat sink 8 to be coupled to thedam member 3 by use of an adhesive 7, and the heat-emitting efficiency may be lowered due to the structure in which only one side surface of theelectronic component 1 is arranged facing the heat sink 8. - The present invention provides a method capable of reducing the possibility that a void may be generated when an electronic component is molded by using the difference in air pressure.
- An aspect of the present invention features an electronic component package manufacturing method, including mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer.
- The heat sink can be formed with an inset hole for supplying the adhesive to the cavity and an inlet hole for providing negative pressure to the cavity, and a step for charging with the adhesive can include providing negative pressure to the cavity through the inlet hole; and supplying the adhesive to the cavity through the insert hole. At this time, the inset hole and the inlet hole can be formed in surfaces, respectively, facing each other.
- The adhesive consists of a material including a thermal interface material (TIM), and the first insulation layer can consist of a material including polyimide. In the meantime, the method can further include stacking a lay-up layer in the other surface of the first insulation layer.
- Another aspect of the present invention features an electronic component package, including a first insulation layer; an electronic component, mounted in one surface of the first insulation layer; a heat sink, formed with a cavity corresponding to the electronic component and bonded to the one surface of the first insulation layer to cover the electronic component; an adhesive, charged in the cavity; and a circuit pattern, formed in the other surface of the first insulation layer. The heat sink can be formed with an inset hole and an inlet hole, respectively.
- The inset hole and the inlet hole can be formed in surfaces, respectively, facing each other, and the adhesive can consist of a material including a thermal interface material (TIM). Also, the first insulation layer can consist of a material including polyimide. The electronic component package can further include a lay-up layer stacked in the other surface of the first insulation layer.
- These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings where:
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FIG. 1A through 1K illustrate an electronic component package manufacturing method in accordance with a conventional art; -
FIG. 2 is a sectional view showing an electronic component package in accordance with a convention art; -
FIG. 3 is a flow chart illustrating an electronic component package manufacturing method in accordance with an embodiment of the present invention; -
FIG. 4A throughFIG. 4J illustrate the electronic component package manufacturing method ofFIG. 3 ; -
FIG. 5A andFIG. 5B are perspective views showing a heat sink ofFIG. 4A throughFIG. 4J ; and -
FIG. 6 is a sectional view showing an electronic component package in accordance with another aspect of the present invention. - Hereinafter, some embodiments of an electronic component package and a manufacturing method thereof in accordance with the present invention will be described in detail with reference to the accompanying drawings. Throughout the drawings, similar or corresponding elements are given similar reference numerals. The pertinent overlapped description will be omitted.
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FIG. 3 is a flow chart illustrating an electronic component package manufacturing method in accordance with an aspect of the present invention,FIG. 4A throughFIG. 4J illustrate the electronic component package manufacturing method ofFIG. 3 andFIG. 5A andFIG. 5B is a perspective view showing a heat sink ofFIG. 4A throughFIG. 4J . Referring toFIG. 4A throughFIG. 4J andFIG. 5A andFIG. 5B , anelectronic component 10, afirst insulation layer 20, viaholes circuit patterns 24 and 25,plating layers heat sink 40, acavity 42, aninsert hole 44, aninlet hole 46, asecond insulation layer 50, a solder resist 62, aland 64 and asolder bump 66 are illustrated. - Firstly, a step represented by S110 can mount the
electronic component 10 in one surface of thefirst insulation layer 20. For the efficient adhesion, an adhesive material (not shown) can be applied to the one surface of thefirst insulation layer 20. Thefirst insulation layer 20 can consist of a component mainly having polyamide which has strong contractiveness and a property in easily making a thin film. - Then, a step represented by S120 can bond the
heat sink 40 having thecavity 42 to the one surface of thefirst insulation layer 20. Theheat sink 40 can absolve and transfer the heat generated by theelectronic component 10. Herein, theheat sink 40 can consist of cupper and aluminum having outstanding thermal conductivity. Of course, theheat sink 40 can consist of other metal components considering the foregoing function. - As shown in
FIG. 4B andFIG. 5A andFIG. 5B , thecavity 42 can formed in theheat sink 40. Theheat sink 40 can cover a literal side and an upper side of theelectronic component 10 by bonding theheat sink 40 to thefirst insulation layer 20. Accordingly, the heat generated by theelectronic component 10 can be more efficiently absolved and transferred.FIG. 5A andFIG. 5B are a plan perspective view and a bottom perspective view, respectively, showing theheat sink 40. - Then, a step represented by S130 can charge the
cavity 42 with the adhesive 30. The charged amount of the adhesive 30 can be determined according to the consideration such as the volume of the electronic component. In other words, the adhesive 30 can be charged as much as the volume of the space formed between theelectronic component 10 and an internal wall of theheat sink 40. - However, unevenly supplying the adhesive 30 to the
cavity 42 may generate avoid in case that thecavity 42 is charged with the adhesive 30. - To prevent the void from being generated, the following method can be used. The
inset hole 44 and theinlet hole 46 can be formed in theheat sink 40. While thecavity 42 is provided with negative pressure through theinlet hole 46, the adhesive 30 can be supplied to the cavity through theinsert hole 44. The means such as a compressor can be used to provide the negative pressure to thecavity 42. Thereference number 32 ofFIG. 4C indicates the means supplying the adhesive 30, and thereference number 34 indicates the means providing the negative pressure to thecavity 40. - Pressure difference may be generated inside the
cavity 42 by theinsert hole 44, theinlet hole 46 and the compressor. The pressure difference can make the adhesive 30 evenly spread inside thecavity 42, to thereby prevent the void from being generated. - To form a smoother flow of pressure, the
insert hole 44 and theinlet hole 46 can be formed in the surfaces facing each other. As shown inFIG. 4A through 4J andFIG. 5 andFIG. 5B , theinsert hole 44 and theinlet hole 46 can be formed in the sides—facing each other. Alternatively, it is natural that both theinsert hole 44 and theinlet hole 46 can be formed in a lower part of theheat sink 40. - The adhesive 30 can perform the function of efficiently transferring the heat generated by the
electronic component 10 to theheat sink 40 as well as strongly supporting theelectronic component 10. Herein, the adhesive 30 can employ a thermal interface material (TIM). - Then, a step represented by S140 can form the
circuit pattern 24 in the other surface of thefirst insulation layer 20. Also, a via can be formed to electrically interconnecting thecircuit pattern 24 and theelectronic component 10 in addition to thecircuit pattern 24. In other words, as shown inFIG. 4D , the via can be formed by forming the viahole 22 penetrating theinsulation layer 20 and theplating layer 26. Of course, the method described throughFIG. 4A through 4J is an example for the via formation method. Alternatively, thecircuit pattern 24 and theelectronic component 10 can be electrically interconnected to each other in various ways. - Then, a step represented by S150 can form a lay-up layer in the other surface of the
first insulation layer 20. The electronic component package having a multi-layer structure can be formed by forming the lay-up layer. The lay-up layer can be formed through the processes of stacking the second insulation layer 50 (refer toFIG. 4E ), punching the via hole 52 (refer toFIG. 4F ) and forming theplating layer 56 and the circuit pattern 54 (refer toFIG. 4G ). After that, in a top outer layer, the solder resist 62 can be applied (refer toFIG. 4H ), and theland 64 can be formed (refer toFIG. 4I ). Then, thesolder bump 66 can be formed (refer toFIG. 4J ). - The above description is related to the electronic component package manufacturing method in accordance with an aspect of the present invention. Hereinafter, the electronic component package manufacturing method in accordance with another aspect of the present invention will be described.
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FIG. 6 is a sectional view showing an electronic component package in accordance with another embodiment of the present invention. Referring toFIG. 6 , anelectronic component 10, afirst insulation layer 20, a via holes 22, acircuit patterns 24, a plating layers 26, an adhesive 30, aheat sink 40, acavity 42, aninsert hole 44, aninlet hole 46, asecond insulation layer 50, a solder resist 62, aland 64 and asolder bump 66 are illustrated. - The
electronic component 10 can be mounted in one surface of thefirst insulation layer 20. To strongly mount theelectronic component 10, theadhesive layer 30 can be formed in the one surface of thefirst insulation layer 20. Thefirst insulation layer 20 can employ polyamide having strong contractiveness and a property in easily making a thin film. Theelectronic component 10, which is mounted in thefirst insulation layer 20 in a face down type, is illustrated inFIG. 6 . - The
heat sink 40 can be bonded to the one surface of thefirst insulation layer 20 in which the electronic component is mounted. Theheat sink 40 can be formed with thecavity 42 corresponding to theheat sink 40, to thereby cover theelectronic component 10. As shown inFIG. 5A and 5B andFIG. 6 , theheat sink 40 in which thecavity 42 is formed, can cover both a literal side and a lower side of theelectronic component 10. This structure can make the area size of theheat sink 40 increased, to thereby improve the emitting heat efficiency. - The
heat sink 40 can absolve and transfer the heat generated by theelectronic component 10. Herein, theheat sink 40 can consist of cupper and aluminum having outstanding thermal conductivity. Of course, theheat sink 40 can consist of other metal components considering the foregoing function. - A space between an internal wall of the
heat sink 40 and the electronic component, which is the remaining space of thecavity 42, can be charged with the adhesive 30. The adhesive 30 can strongly support theelectronic component 10 to allow theelectronic component 10 to be accommodated into thecavity 42 of theheat sink 40. - Also, the adhesive 30 can transfer the heat generated by the
electronic component 10 to theheat sink 40. To more efficiently perform the heat-transfer function, the adhesive 30 can employ a thermal interface material (T11\4). - Since the method of charging with the adhesive 30 is the same as described through the aforementioned electronic component package manufacturing method, the pertinent detailed description will be omitted.
- A
circuit pattern 24 can be formed in the other surface of thefirst insulation layer 20. In accordance with the embodiment of the present invention, the electronic component package can perform a predetermined function through the means such as thecircuit pattern 24. Thecircuit pattern 24 can be electrically interconnected to an electrode of the electronic component through a via formed in thefirst insulation layer 20. - To realize a multi-layer electronic component package, a lay-up layer can be formed in the other surface the
first insulation layer 20. Since the method of stacking the lay-up layer is the same as described through the aforementioned electronic component package manufacturing method, the pertinent detailed description will be omitted. - A lot of other embodiments can described within the principles and spirit of the invention, the scope of which shall be defined by the appended claims.
Claims (5)
1. An electronic component package, comprising:
a first insulation layer;
an electronic component mounted in one surface of the first insulation layer;
a heat sink formed with a cavity corresponding to the electronic component, bonded to the one surface of the first insulation layer to cover the electronic component, and formed with an inset hole and with an inlet hole;
an adhesive charged in the cavity; and
a circuit pattern formed in another surface of the first insulation layer.
2. The electronic component package of claim 1 , wherein the inset hole and the inlet hole are formed in surfaces, respectively, facing each other.
3. The electronic component package of claim 1 , wherein the adhesive consists of a material including a thermal interface material (TIM).
4. The electronic component package of claim 1 , wherein the first insulation layer consists of a material including polyimide.
5. The electronic component package of claim 1 , further comprising a lay-up layer stacked in the other surface of the first insulation layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US14/321,214 US20140313676A1 (en) | 2007-03-02 | 2014-07-01 | Electronic component package |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070020940A KR100810491B1 (en) | 2007-03-02 | 2007-03-02 | Electro component package and method for manufacturing thereof |
KR10-2007-0020940 | 2007-03-02 | ||
US12/010,321 US8779580B2 (en) | 2007-03-02 | 2008-01-23 | Electronic component package and manufacturing method thereof |
US14/321,214 US20140313676A1 (en) | 2007-03-02 | 2014-07-01 | Electronic component package |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/010,321 Division US8779580B2 (en) | 2007-03-02 | 2008-01-23 | Electronic component package and manufacturing method thereof |
Publications (1)
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US20140313676A1 true US20140313676A1 (en) | 2014-10-23 |
Family
ID=39397760
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US12/010,321 Expired - Fee Related US8779580B2 (en) | 2007-03-02 | 2008-01-23 | Electronic component package and manufacturing method thereof |
US14/321,214 Abandoned US20140313676A1 (en) | 2007-03-02 | 2014-07-01 | Electronic component package |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US12/010,321 Expired - Fee Related US8779580B2 (en) | 2007-03-02 | 2008-01-23 | Electronic component package and manufacturing method thereof |
Country Status (3)
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US (2) | US8779580B2 (en) |
JP (1) | JP4839471B2 (en) |
KR (1) | KR100810491B1 (en) |
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KR101003585B1 (en) * | 2008-06-25 | 2010-12-22 | 삼성전기주식회사 | Printed circuit board embedded chip and it's manufacturing method |
US8518749B2 (en) * | 2009-06-22 | 2013-08-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die |
US8497587B2 (en) * | 2009-12-30 | 2013-07-30 | Stmicroelectronics Pte Ltd. | Thermally enhanced expanded wafer level package ball grid array structure and method of making the same |
CN102738022B (en) * | 2011-04-15 | 2017-05-17 | 飞思卡尔半导体公司 | Method for assembling semiconductor device containing insulating substrate and heat sink |
WO2013116999A1 (en) * | 2012-02-09 | 2013-08-15 | Nokia Siemens Networks Oy | Method and apparatus for reducing the mechanical stress when mounting assemblies with thermal pads |
JP2014082233A (en) * | 2012-10-12 | 2014-05-08 | Sumitomo Electric Ind Ltd | Semiconductor device and method of manufacturing the same |
US20200035614A1 (en) * | 2018-07-30 | 2020-01-30 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
US11348857B2 (en) * | 2020-06-16 | 2022-05-31 | Micron Technology, Inc. | Lidded microelectronic device packages and related systems, apparatus, and methods of manufacture |
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Also Published As
Publication number | Publication date |
---|---|
US20080212288A1 (en) | 2008-09-04 |
US8779580B2 (en) | 2014-07-15 |
JP4839471B2 (en) | 2011-12-21 |
JP2008218980A (en) | 2008-09-18 |
KR100810491B1 (en) | 2008-03-07 |
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