US20150123235A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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US20150123235A1
US20150123235A1 US14/314,418 US201414314418A US2015123235A1 US 20150123235 A1 US20150123235 A1 US 20150123235A1 US 201414314418 A US201414314418 A US 201414314418A US 2015123235 A1 US2015123235 A1 US 2015123235A1
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region
doping
substrate
semiconductor device
counter
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US10269988B2 (en
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Yong Won Lee
Jin Woo Han
Dae Won HWANG
Kyung Wook KIM
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MagnaChip Semiconductor Ltd
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MagnaChip Semiconductor Ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/782—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • a semiconductor device may be configured to reduce a doping concentration at an active region and enhance a breakdown voltage by performing counter doping to a region where a Schottky barrier diode is formed.
  • SBD Schottky Barrier Diode
  • MOSFET metal-oxide semiconductor field effect transistor
  • a Schottky Barrier Diode forms the Schottky Barrier by means of a junction between metal and semiconductor. That is, such metal-semiconductor junction is formed between a metal and a semiconductor, creating a Schottky barrier.
  • Typical metals used are molybdenum, platinum, chromium or tungsten, and certain silicides, e.g. palladium silicide and platinum silicide; and the semiconductor would typically be n-type silicon.
  • the metal side acts as the anode and the n-type semiconductor acts as the cathode of the diode. This Schottky barrier results in both very fast switching and low forward voltage drop.
  • the SBD has disadvantages in that a maximum reverse voltage is low and a reverse direction leakage current is heavy. Also, with regards to a semiconductor device embedded with the SBD, a Breakdown voltage (BV) of the Schottky barrier diode is determined according to a Barrier Metal and an EPI Resistivity. Therefore, if a high concentration Epitaxial layer having a low resistivity is used in a semiconductor device in which the SBD is embedded, an on-Resistance (RDS(ON)) may be disrupted due to the increase of the resistance in the MOSFET drift region.
  • BV Breakdown voltage
  • RDS(ON) on-Resistance
  • FIG. 1 is a diagram illustrating an example of a graph of a breakdown voltage change value, according to an EPI Resistivity of a semiconductor device embedded with a usual MOSFET (B) and a conventional Schottky barrier diode (A). As illustrated in FIG. 1 , it should be appreciated that a breakdown voltage value is lower than the MOSFET (B) for an identical value of the EPI Resistivity.
  • a semiconductor device in a general aspect, includes a substrate having a concentration, a counter doping region having another concentration, and a Schottky barrier diode (“SBD”) comprising the counter doping region.
  • SBD Schottky barrier diode
  • the semiconductor device may further include a metal layer in contact with the counter doping region, wherein the substrate has a conductivity type; the counter doping region is disposed in the substrate; the another concentration is lower than the concentration; and the SBD further comprises the metal layer.
  • the semiconductor device may further include a WELL region and a BODY region which have another conductivity type and are disposed in the substrate.
  • the counter doping region may include a first doping region disposed in a top portion of the substrate; a second doping region disposed in the WELL region; and a third doping region disposed in the BODY region.
  • the third doping region may have a higher doping concentration than that of the second doping region.
  • the semiconductor device may further include a first trench having a first depth in the substrate and a second trench having a second depth in the substrate which is lower than the first depth.
  • the first trench may be disposed in a boundary between a MOSFET region and an SBD region.
  • the BODY region may include a first BODY region and a second BODY region
  • the WELL region may include a first WELL region, a second WELL region, and a third WELL region
  • the first BODY region may be enclosed by the first WELL region or the third WELL region.
  • the first trench may include a top Poly-Si layer, a bottom Poly-Si layer, and an insulating layer which is disposed between the top Poly-Si layer and the bottom Poly-Si layer.
  • the BODY region may have a smaller depth than the WELL region.
  • the semiconductor device may further include a WELL region, wherein a depth of the WELL region is less than a depth of the first trench or the second trench.
  • a manufacturing method includes forming a substrate, forming a counter doping region in the substrate region, forming a trench in the substrate region, forming a BODY region adjacent to the trench, and forming a WELL region adjacent to the trench.
  • the forming a substrate may include forming a substrate having a conductivity type, the forming a counter doping region may include forming a counter doping region having another conductivity type, the forming a trench may include forming a plurality of trenches, the forming a BODY region may include forming a BODY region having the another conductivity type, and the forming a WELL region may include forming the WELL region having the another conductivity type in a Schottky barrier diode (“SBD”) region.
  • SBD Schottky barrier diode
  • the BODY region may have a depth that is less than a depth of the WELL region, and the depth of the WELL region may be less than a depth of the trench.
  • the counter doping region may be configured to reduce a net doping concentration at a top portion of the substrate.
  • a semiconductor in another general aspect, includes a substrate having a conductivity type, a counter-doping region having another conductivity type, and a metal layer in contact with the counter-doping region.
  • the semiconductor may include a Schottky barrier diode (“SBD”) which includes the counter-doping region and the metal layer, wherein the substrate and the counter-doping region have different concentrations.
  • SBD Schottky barrier diode
  • FIG. 1 is a diagram illustrating an example of a graph of a breakdown voltage value (BV) according to an EPI Resistivity of conventional MOSFET and SBD.
  • BV breakdown voltage value
  • FIG. 2 is a diagram illustrating an example of a semiconductor device.
  • FIG. 3 is a diagram illustrating an example of a cross-sectional view where line A-A′ of the semiconductor device of FIG. 2 is magnified.
  • FIG. 4 is a diagram illustrating an example of a cross-sectional view of a semiconductor device.
  • FIGS. 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 14 are diagrams illustrating an example of a manufacturing method of a semiconductor device embedded with a Schottky barrier diode.
  • FIGS. 15 a and 15 b are diagrams illustrating an example of graphs of doping concentration changes of a semiconductor device embedded with the SBD according to whether counter doping is performed or not.
  • FIGS. 16 a and 16 b are diagrams illustrating an example of graphs of doping concentration changes of a semiconductor device embedded with the SBD according to whether counter doping is performed or not.
  • FIGS. 17 a and 17 b are diagrams illustrating an example of graphs of an electric field distribution of a semiconductor device embedded with the SBD according to whether counter doping is performed or not.
  • FIG. 2 is a diagram illustrating an example of a semiconductor device having an SBD region and a MOSFET active region configured in a Chip, as illustrated.
  • the SBD region is formed at an upper portion of the chip; however, a position of the SBD region is not limited thereto.
  • FIG. 3 is a diagram illustrating an example of a cross-sectional view where the line A-A′ on the semiconductor device of FIG. 2 is magnified.
  • the MOSFET active region 300 consists of a plurality of various trenches.
  • the rest regions and the SBD region 310 are disposed in such a way that the outermost trenches 104 a are disposed in a boundary between the MOSFET active region 300 and the SBD region 310 .
  • FIG. 4 is a diagram illustrating an example of a cross-sectional view of a semiconductor device.
  • the semiconductor device is embedded with an SBD, and has an EPI substrate 100 having a first conductivity type, for example, an N-type.
  • the SBD comprises the P-type WELL region 112 and an N-type substrate 100 .
  • a doping region 102 is formed in a top portion of the N-type substrate 100 .
  • the doping region is referred to as a counter doping region 102 , in which a blanket implantation is performed having a second conductivity type that is opposite to the substrate 100 . If a counter doping region 102 is formed by a counter doping process, a net doping concentration is locally reduced at the top portion of the substrate 100 compared to its bottom portion. Accordingly, a resistance in the top portion of an N-type EPI is slightly increased compared to its bottom portion, and thereby a breakdown voltage is improved.
  • the counter doping region 102 may include a first doping region 102 a, a second doping region 102 b, and a third doping region 102 c. Each doping region 102 a, 102 b, 102 c may have a different doping concentration.
  • various trenches 104 are disposed in the MOSFET active region.
  • a first trench 104 a is disposed in a boundary between the SBD region 310 and MOSFET region 300 .
  • a plurality of second trenches 104 b is disposed in the MOSFET region 300 .
  • a plurality of WELL regions 112 a, 112 b and 112 c is disposed in the SBD region 310 .
  • a first WELL region 112 a and a third WELL region 112 c are enclosed to the first BODY region 110 a.
  • the second WELL region 112 b is disposed between the first WELL region 112 a and the third WELL region 112 c.
  • a space between WELL regions is called an N-active region 130 and also contacts the metal layer 118 .
  • the N-active region 130 with metal layer works for a Schottky Barrier Diode (SBD).
  • a split-Poly-Si comprises a top Poly-Si 108 , an insulating layer 107 and a bottom Poly-Si 106 , and is disposed in the first trench 104 a.
  • the first trench 104 a is not limited to be configured as a split Poly-Si and may be formed as a single Poly-Si.
  • a metal layer 118 may be formed around an entire surface of the substrate 100 .
  • FIG. 5 illustrates an example of a cross-sectional view of a semiconductor device in which a counter doping 102 of the active region is performed. That is, in this example, the LOCOS process is complete.
  • an N-type EPI substrate 100 is the starting material.
  • a counter doping region 102 in which a doping is performed by the P-type dopant, is formed on a top portion of the N-type EPI substrate 100 .
  • Boron fluoride (BF2) or Boron (B) may be used as the P-type dopant for the counter doping process.
  • Counter doping generally means doping an impurity in order to control electrical characteristic of the semiconductor device, such as concentration, resistivity, etc., and the impurity may differ according to the types of the semiconductor.
  • reducing a net doping concentration at the SBD region by performing a counter doping of P-type dopant reduces N-type dopant concentration at the Epitaxial layer surface.
  • a counter doping region 102 is formed by using the SBD mask 103 after identifying the region where the SBD will be substantially formed. This is because a counter doping in the partial portion of the SBD region 310 may cause overall characteristics of the semiconductor device to be degraded when doping is performed on an entire surface of the substrate.
  • a doping concentration of conductivity type N at a substrate may be reduced, and a breakdown voltage may be enhanced by increasing the N-type EPI surface resistance. This may be performed by forming a counter doping region 102 in the partial region including the SBD region 310 , as described above.
  • FIG. 6 is a diagram illustrating an example of a first trench 104 a that is formed.
  • the first trench 104 a is formed by being etched at a certain depth from the surface of the N-type EPI substrate 100 .
  • the first trench 104 a and the second trench 104 b may be separated from each other at a certain distance.
  • a termination trench adjacent to the third doping region 102 c ( FIG. 4 ), i.e., first trench 104 a, is formed to be deeper than a depth of second trench 104 b.
  • a length of the first trench 104 a is equal to or deeper than that of the second trench 104 b. Additionally, a width of the first trench 104 a may be equal to or wider than that of the second trench 104 b. If the length of the first trench 104 a is shorter, a stable internal breakdown voltage may not be obtained. Thus, it is preferred that the length of the first trench 104 a is longer than that of the second trench 104 b.
  • the trenches 104 may be filled with the top Poly-Si 108 and bottom Poly-Si 106 , where the top Poly-Si 108 is separated from bottom Poly-Si 106 by an internal insulating layer 107 .
  • the trenches 104 may be filled with one single Poly-Si in which a top Poly-Si and a bottom Poly-Si are merged together.
  • the counter doping region 102 is formed before the first trench 104 a is formed; however, the order is not limited thereto. That is, the first trench 104 a of FIG. 6 may be formed before the counter doping region 102 .
  • a bottom Poly-Si 106 is formed first in the first trench 104 a among the split Poly-Si inside the trench region 104 . It is preferred that the bottom Poly-Si 106 is a source Poly-Si but the bottom Poly-Si 106 is not limited thereto.
  • an oxide layer 107 is formed inside the trench after a bottom Poly-Si 106 is formed at the bottom portion of the trench.
  • a gate Poly-Si (Top Poly-Si) 108 may be formed at the upper portion of the trench, as illustrated in FIG. 8 .
  • FIG. 9 is a diagram illustrating an example of a cross-sectional view of a semiconductor device after performing a P-type doping in order to form the first BODY region 110 a.
  • the first BODY region 110 a partially overlaps with the first WELL region 112 a ( FIG. 4 ), and is formed in the SBD region 310 .
  • the second BODY region 110 b is disposed between the trench regions 104 in the MOSFET region 300 .
  • a depth of the BODY region 110 a may not be deeper than that of the upper Poly-Si 108 of the trench region 104 , and the depths may be identical to each other. If the BODY region 110 a is deeper than a depth of the upper Poly-Si region 108 , a voltage may increase according to the increase of the channel region formation, and further, the entire semiconductor device may be affected.
  • the WELL regions 112 a, 112 b and 112 c are formed with the same conductivity type as the BODY region 110 .
  • the WELL region 112 a, 112 b and 112 c may be separated from each other at a certain distance and may have almost the same width. Depths of the WELL regions 112 a, 112 b and 112 c may be deeper than a depth of the BODY region 110 . Furthermore, the WELL regions 112 a, 112 b and 112 c may have lower depths than the first trench 104 a. If the WELL regions 112 a, 112 b and 112 c are formed to be longer than the bottom Poly-Si 106 of the first trench 104 a, the MOSFET function may be degraded.
  • each doping region 102 a - 102 c has a different doping concentration, and the dopant implanted into the doping regions 102 a - 102 c has a different conductivity type from the substrate 100 .
  • the counter doping region 102 includes at least a first doping region 102 a, a second doping region 102 b, and a third doping region 102 c. Each doping region 102 a, 102 b, 102 c has a different doping concentration.
  • the first doping region 102 a is disposed in a portion of the substrate 100 . Net doping concentration of the first region 102 a is lower than the substrate 100 because the dopant implanted into the first region 102 a has conductivity type opposite to the substrate.
  • the second doping region 102 b is disposed in the WELL regions 112 a, 112 b and 112 c.
  • the net doping concentration of the second region 102 b is increased locally compared to the WELL region 112 because a dopant having the same conductivity type with the WELL region 112 is implanted into the second region 102 b.
  • the third doping region 102 c is disposed in the first BODY region 110 a.
  • the net doping concentration of the third region 102 c is increased locally compared to the BODY region 110 because a dopant having the same conductivity type with the BODY region 110 is implanted into the third region 102 c.
  • a source region 116 is formed in the partial portion of the BODY region 110 .
  • a source region 116 having a different conductivity type from the BODY region 110 is formed.
  • FIG. 11 is a diagram illustrating an example of a cross-sectional view of the semiconductor device after performing doping by the conductivity type N, in order to form a source region 116 in the MOSFET region 300 .
  • the source region 116 is formed by doping the upper portion of the substrate between the second trenches 104 b using the conductivity type N. Further, the source region 116 has a shorter depth than the upper Poly-Si 108 of the second trench 104 b and a shallower depth than the BODY region 110 a.
  • an insulating layer 117 is formed at the upper surface of the N-type EPI substrate 100 .
  • FIG. 12 is a diagram illustrating an example of a patterning of a region where a contact plug is formed to be opened toward the insulating layer 117 by using a mask (not illustrated) in order to form a contact plug in the MOSFET region 300 .
  • a portion of the source region 116 is etched. Through the etching, the contact plug may contact the source region 116 and BODY region 110 .
  • the upper surface of the SBD region 310 is selectively opened using patterning process.
  • the insulating layer 117 over the upper surface of the SBD region 310 is selectively removed through a wet etching process which induces less damage to the upper surface of the SBD region 310 .
  • the contact plug may contact the SBD region 310 .
  • the insulator layer 117 still partially covers the BODY portion 110 and the source region 116 .
  • a metal layer 118 may be deposited over the substrate to make contact with the BODY region 110 , the source region 116 , and the SBD region 310 .
  • a metal layer 118 may contact the counter doping region 102 as well as the WELL regions 112 a, 112 b and 112 c.
  • Aluminum (Al) metal or Copper (Cu) metal or TiN or Ti barrier metal may be used as the metal layer 118 .
  • FIG. 14 is a diagram illustrating an example of a cross-sectional view of a semiconductor device with the metal layer 118 .
  • a silicide layer (not shown) such as cobalt silicide (CoSi2), titanium silicide (TiSi2), and nickel silicide (NiSi) may be formed prior to the deposition of the metal layer 118 .
  • CoSi2 cobalt silicide
  • TiSi2 titanium silicide
  • NiSi nickel silicide
  • the above description provides a semiconductor device embedded with a Schottky barrier diode configured to reduce an N-type doping concentration at a surface of the N-type EPI substrate 100 by using the counter doping implantation.
  • the resistance near the surface of the N-type EPI substrate 100 may be increased through the counter doping process.
  • a breakdown voltage of the whole semiconductor device can be increased.
  • FIGS. 15 to 17 The increase of the breakdown voltage of the semiconductor device according to the counter doping process is illustrated in FIGS. 15 to 17 .
  • FIGS. 15 and 16 are diagrams illustrating example graphs of doping concentrations, according to depths of a semiconductor device in which a counter doping is not performed, and a semiconductor device whose SBD region is performed with counter doping.
  • FIG. 15 a is a diagram illustrating an example of a doping concentration change of a semiconductor device in which counter doping is not performed.
  • FIG. 15 b is a diagram illustrating an example of a doping concentration change of a semiconductor device in which counter doping is performed.
  • “A” represents a region that ranges from an upper portion to a bottom portion of a substrate of a WELL region in the semiconductor device embedded with the SBD in which a counter doping is not performed.
  • “B” represents a region that ranges from an upper portion to a bottom portion of a substrate of the semiconductor device embedded with the SBD in which a counter doping is not performed.
  • X1 represents a thickness of the WELL region of the semiconductor device embedded with the SBD in which a counter doping is not performed.
  • “A′” represents a region that ranges from an upper portion to a bottom portion of a substrate of the WELL regions 112 a, 112 b and 112 c including the counter doping region 102 .
  • “B” represents a region that ranges from an upper portion to a bottom portion of a substrate including the counter doping region 102 .
  • X2 represents a thickness of the WELL region of the semiconductor device embedded with the SBD in which counter doping is performed.
  • the thickness (X2) of the WELL region of the semiconductor device with counter doping is deeper than a thickness (X1) of the WELL region of the semiconductor device without counter doping. This is because the WELL region is formed by the same conductivity type as the counter doping's conductivity type.
  • FIGS. 16 a and 16 b are diagrams illustrating an example of graphs of net doping concentration profiles according to A, A′, B, B′ which are illustrated in FIGS. 15 a and 15 b .
  • FIG. 16 b is a diagram illustrating an example of a graph that shows a magnified portion in FIG. 16 a with a dotted line.
  • the X-axis of the graphs represents a depth from a top surface of the substrate, and the Y-axis of the graphs represents a net doping concentration.
  • A′ the junction depth of the WELL region, X2 extends beyond 2 ⁇ m.
  • the junction depth of the WELL region, X1 does not extend to 2 ⁇ m.
  • the counter doping process extends the junction depth deeper than without counter doping. The result corresponds to a thickness difference between X1 and X2 as shown in FIGS. 15 a and 15 b.
  • a doping concentration (B) on the substrate without counter doping is constant according to a depth from the substrate surface, as illustrated in FIG. 16 b .
  • a smaller doping concentration is shown at the top portion of the substrate up to 8 ⁇ m.
  • the semiconductor device having the SBD region where a counter doping is partially performed can ultimately reduce a net doping concentration of a conductivity type N on a substrate surface through counter doping.
  • FIG. 17 a is a diagram illustrating an example of an Electric Field distribution of a semiconductor device without counter doping
  • FIG. 17 b is a diagram illustrating an example of an Electric Field distribution of a semiconductor device embedded with the SBD with counter doping.
  • a breakdown voltage of a semiconductor device may be 39.4 V. Compared with the breakdown voltage value of 8.9 V of a semiconductor device where counter doping is not performed, it can be appreciated that a breakdown voltage value of a semiconductor device embedded with a Schottky barrier diode is largely improved.

Abstract

A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2013-0132769 filed on Nov. 4, 2013, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
    • BACKGROUND
  • 1. Field
  • The following description relates to a semiconductor device and a manufacturing method thereof. A semiconductor device may be configured to reduce a doping concentration at an active region and enhance a breakdown voltage by performing counter doping to a region where a Schottky barrier diode is formed.
  • 2. Description of Related Art
  • In order to increase a switching speed of a semiconductor electricity device and to reduce a power consumption, reduction of an on-resistance and a gate capacitance is preferred. For the reduction, a method of incorporating a Schottky Barrier Diode (SBD) into the semiconductor electricity device, such as a metal-oxide semiconductor field effect transistor (MOSFET) has typically been applied.
  • A Schottky Barrier Diode (SBD) forms the Schottky Barrier by means of a junction between metal and semiconductor. That is, such metal-semiconductor junction is formed between a metal and a semiconductor, creating a Schottky barrier. Typical metals used are molybdenum, platinum, chromium or tungsten, and certain silicides, e.g. palladium silicide and platinum silicide; and the semiconductor would typically be n-type silicon. The metal side acts as the anode and the n-type semiconductor acts as the cathode of the diode. This Schottky barrier results in both very fast switching and low forward voltage drop.
  • With regards to a MOSFET embedded with an SBD which uses drift current of various carriers, a time delay by charge accumulation due to an injection of a few carriers is not generated, thus, a fast switching may become possible. Also, efficiencies are improved as switching frequency increases.
  • However, the SBD has disadvantages in that a maximum reverse voltage is low and a reverse direction leakage current is heavy. Also, with regards to a semiconductor device embedded with the SBD, a Breakdown voltage (BV) of the Schottky barrier diode is determined according to a Barrier Metal and an EPI Resistivity. Therefore, if a high concentration Epitaxial layer having a low resistivity is used in a semiconductor device in which the SBD is embedded, an on-Resistance (RDS(ON)) may be disrupted due to the increase of the resistance in the MOSFET drift region.
  • FIG. 1 is a diagram illustrating an example of a graph of a breakdown voltage change value, according to an EPI Resistivity of a semiconductor device embedded with a usual MOSFET (B) and a conventional Schottky barrier diode (A). As illustrated in FIG. 1, it should be appreciated that a breakdown voltage value is lower than the MOSFET (B) for an identical value of the EPI Resistivity.
  • Conventionally, to solve this problem, minimization of an electric field was attempted by applying a Guard Ring or a trench field plate. However, this method has a limitation because the distribution characteristic of the electric field on the substrate surface of the semiconductor device is largely different from the theoretically targeted range.
    • SUMMARY
  • This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
  • In a general aspect, a semiconductor device includes a substrate having a concentration, a counter doping region having another concentration, and a Schottky barrier diode (“SBD”) comprising the counter doping region.
  • The semiconductor device may further include a metal layer in contact with the counter doping region, wherein the substrate has a conductivity type; the counter doping region is disposed in the substrate; the another concentration is lower than the concentration; and the SBD further comprises the metal layer.
  • The semiconductor device may further include a WELL region and a BODY region which have another conductivity type and are disposed in the substrate.
  • The counter doping region may include a first doping region disposed in a top portion of the substrate; a second doping region disposed in the WELL region; and a third doping region disposed in the BODY region.
  • The third doping region may have a higher doping concentration than that of the second doping region.
  • The semiconductor device may further include a first trench having a first depth in the substrate and a second trench having a second depth in the substrate which is lower than the first depth.
  • The first trench may be disposed in a boundary between a MOSFET region and an SBD region.
  • The BODY region may include a first BODY region and a second BODY region, the WELL region may include a first WELL region, a second WELL region, and a third WELL region, and the first BODY region may be enclosed by the first WELL region or the third WELL region.
  • The first trench may include a top Poly-Si layer, a bottom Poly-Si layer, and an insulating layer which is disposed between the top Poly-Si layer and the bottom Poly-Si layer.
  • The BODY region may have a smaller depth than the WELL region.
  • The semiconductor device may further include a WELL region, wherein a depth of the WELL region is less than a depth of the first trench or the second trench.
  • In another general aspect, a manufacturing method includes forming a substrate, forming a counter doping region in the substrate region, forming a trench in the substrate region, forming a BODY region adjacent to the trench, and forming a WELL region adjacent to the trench.
  • The forming a substrate may include forming a substrate having a conductivity type, the forming a counter doping region may include forming a counter doping region having another conductivity type, the forming a trench may include forming a plurality of trenches, the forming a BODY region may include forming a BODY region having the another conductivity type, and the forming a WELL region may include forming the WELL region having the another conductivity type in a Schottky barrier diode (“SBD”) region.
  • The BODY region may have a depth that is less than a depth of the WELL region, and the depth of the WELL region may be less than a depth of the trench.
  • The counter doping region may be configured to reduce a net doping concentration at a top portion of the substrate.
  • In another general aspect, a semiconductor includes a substrate having a conductivity type, a counter-doping region having another conductivity type, and a metal layer in contact with the counter-doping region.
  • The semiconductor may include a Schottky barrier diode (“SBD”) which includes the counter-doping region and the metal layer, wherein the substrate and the counter-doping region have different concentrations.
  • Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram illustrating an example of a graph of a breakdown voltage value (BV) according to an EPI Resistivity of conventional MOSFET and SBD.
  • FIG. 2 is a diagram illustrating an example of a semiconductor device.
  • FIG. 3 is a diagram illustrating an example of a cross-sectional view where line A-A′ of the semiconductor device of FIG. 2 is magnified.
  • FIG. 4 is a diagram illustrating an example of a cross-sectional view of a semiconductor device.
  • FIGS. 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 are diagrams illustrating an example of a manufacturing method of a semiconductor device embedded with a Schottky barrier diode.
  • FIGS. 15 a and 15 b are diagrams illustrating an example of graphs of doping concentration changes of a semiconductor device embedded with the SBD according to whether counter doping is performed or not.
  • FIGS. 16 a and 16 b are diagrams illustrating an example of graphs of doping concentration changes of a semiconductor device embedded with the SBD according to whether counter doping is performed or not.
  • FIGS. 17 a and 17 b are diagrams illustrating an example of graphs of an electric field distribution of a semiconductor device embedded with the SBD according to whether counter doping is performed or not.
    •
  • Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
    • DETAILED DESCRIPTION
  • The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the systems, apparatuses and/or methods described herein will be apparent to one of ordinary skill in the art. The progression of processing steps and/or operations described is an example; however, the sequence of and/or operations is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps and/or operations necessarily occurring in a certain order. Also, descriptions of functions and constructions that are well known to one of ordinary skill in the art may be omitted for increased clarity and conciseness.
  • The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete, and will convey the full scope of the disclosure to one of ordinary skill in the art.
  • FIG. 2 is a diagram illustrating an example of a semiconductor device having an SBD region and a MOSFET active region configured in a Chip, as illustrated. In FIG. 2, the SBD region is formed at an upper portion of the chip; however, a position of the SBD region is not limited thereto.
  • FIG. 3 is a diagram illustrating an example of a cross-sectional view where the line A-A′ on the semiconductor device of FIG. 2 is magnified. The MOSFET active region 300 consists of a plurality of various trenches. The rest regions and the SBD region 310 are disposed in such a way that the outermost trenches 104 a are disposed in a boundary between the MOSFET active region 300 and the SBD region 310.
  • FIG. 4 is a diagram illustrating an example of a cross-sectional view of a semiconductor device.
  • As illustrated in FIG. 4, the semiconductor device is embedded with an SBD, and has an EPI substrate 100 having a first conductivity type, for example, an N-type. The SBD comprises the P-type WELL region 112 and an N-type substrate 100.
  • A doping region 102 is formed in a top portion of the N-type substrate 100. The doping region is referred to as a counter doping region 102, in which a blanket implantation is performed having a second conductivity type that is opposite to the substrate 100. If a counter doping region 102 is formed by a counter doping process, a net doping concentration is locally reduced at the top portion of the substrate 100 compared to its bottom portion. Accordingly, a resistance in the top portion of an N-type EPI is slightly increased compared to its bottom portion, and thereby a breakdown voltage is improved.
  • The counter doping region 102 may include a first doping region 102 a, a second doping region 102 b, and a third doping region 102 c. Each doping region 102 a, 102 b, 102 c may have a different doping concentration.
  • In an example, various trenches 104 (104 a, 104 b) are disposed in the MOSFET active region. A first trench 104 a is disposed in a boundary between the SBD region 310 and MOSFET region 300. A plurality of second trenches 104 b is disposed in the MOSFET region 300. A plurality of WELL regions 112 a, 112 b and 112 c is disposed in the SBD region 310. A first WELL region 112 a and a third WELL region 112 c are enclosed to the first BODY region 110 a. The second WELL region 112 b is disposed between the first WELL region 112 a and the third WELL region 112 c. A space between WELL regions is called an N-active region 130 and also contacts the metal layer 118. The N-active region 130 with metal layer works for a Schottky Barrier Diode (SBD).
  • A split-Poly-Si comprises a top Poly-Si 108, an insulating layer 107 and a bottom Poly-Si 106, and is disposed in the first trench 104 a. However, the first trench 104 a is not limited to be configured as a split Poly-Si and may be formed as a single Poly-Si.
  • Additionally, a metal layer 118 may be formed around an entire surface of the substrate 100.
  • An example of a method of manufacturing a semiconductor device configured as above will be described with reference to the accompanying drawings FIG. 5 to FIG. 14.
  • FIG. 5 illustrates an example of a cross-sectional view of a semiconductor device in which a counter doping 102 of the active region is performed. That is, in this example, the LOCOS process is complete.
  • As illustrated in FIG. 5, an N-type EPI substrate 100 is the starting material. A counter doping region 102, in which a doping is performed by the P-type dopant, is formed on a top portion of the N-type EPI substrate 100. Boron fluoride (BF2) or Boron (B) may be used as the P-type dopant for the counter doping process. Counter doping generally means doping an impurity in order to control electrical characteristic of the semiconductor device, such as concentration, resistivity, etc., and the impurity may differ according to the types of the semiconductor.
  • In an example, reducing a net doping concentration at the SBD region by performing a counter doping of P-type dopant reduces N-type dopant concentration at the Epitaxial layer surface. In this case, when performing the counter doping, a counter doping region 102 is formed by using the SBD mask 103 after identifying the region where the SBD will be substantially formed. This is because a counter doping in the partial portion of the SBD region 310 may cause overall characteristics of the semiconductor device to be degraded when doping is performed on an entire surface of the substrate.
  • A doping concentration of conductivity type N at a substrate may be reduced, and a breakdown voltage may be enhanced by increasing the N-type EPI surface resistance. This may be performed by forming a counter doping region 102 in the partial region including the SBD region 310, as described above.
  • In this example, one or more trenches 104 a, 104 b are formed in the MOSFET region 300. FIG. 6 is a diagram illustrating an example of a first trench 104 a that is formed. As illustrated, the first trench 104 a is formed by being etched at a certain depth from the surface of the N-type EPI substrate 100. The first trench 104 a and the second trench 104 b may be separated from each other at a certain distance. A termination trench adjacent to the third doping region 102 c (FIG. 4), i.e., first trench 104 a, is formed to be deeper than a depth of second trench 104 b. It is preferred that a length of the first trench 104 a is equal to or deeper than that of the second trench 104 b. Additionally, a width of the first trench 104 a may be equal to or wider than that of the second trench 104 b. If the length of the first trench 104 a is shorter, a stable internal breakdown voltage may not be obtained. Thus, it is preferred that the length of the first trench 104 a is longer than that of the second trench 104 b.
  • Meanwhile, the trenches 104 may be filled with the top Poly-Si 108 and bottom Poly-Si 106, where the top Poly-Si 108 is separated from bottom Poly-Si 106 by an internal insulating layer 107. However, in other examples, the trenches 104 may be filled with one single Poly-Si in which a top Poly-Si and a bottom Poly-Si are merged together.
  • In this example, the counter doping region 102 is formed before the first trench 104 a is formed; however, the order is not limited thereto. That is, the first trench 104 a of FIG. 6 may be formed before the counter doping region 102.
  • As illustrated in FIG. 7, a bottom Poly-Si 106 is formed first in the first trench 104 a among the split Poly-Si inside the trench region 104. It is preferred that the bottom Poly-Si 106 is a source Poly-Si but the bottom Poly-Si 106 is not limited thereto.
  • As illustrated in FIGS. 7 and 9, an oxide layer 107 is formed inside the trench after a bottom Poly-Si 106 is formed at the bottom portion of the trench. After forming the oxide layer 107, a gate Poly-Si (Top Poly-Si) 108 may be formed at the upper portion of the trench, as illustrated in FIG. 8.
  • FIG. 9 is a diagram illustrating an example of a cross-sectional view of a semiconductor device after performing a P-type doping in order to form the first BODY region 110 a. As illustrated in FIG. 9, the first BODY region 110 a partially overlaps with the first WELL region 112 a (FIG. 4), and is formed in the SBD region 310. On the other hand, the second BODY region 110 b is disposed between the trench regions 104 in the MOSFET region 300. A depth of the BODY region 110 a may not be deeper than that of the upper Poly-Si 108 of the trench region 104, and the depths may be identical to each other. If the BODY region 110 a is deeper than a depth of the upper Poly-Si region 108, a voltage may increase according to the increase of the channel region formation, and further, the entire semiconductor device may be affected.
  • The WELL regions 112 a, 112 b and 112 c are formed with the same conductivity type as the BODY region 110. The WELL region 112 a, 112 b and 112 c may be separated from each other at a certain distance and may have almost the same width. Depths of the WELL regions 112 a, 112 b and 112 c may be deeper than a depth of the BODY region 110. Furthermore, the WELL regions 112 a, 112 b and 112 c may have lower depths than the first trench 104 a. If the WELL regions 112 a, 112 b and 112 c are formed to be longer than the bottom Poly-Si 106 of the first trench 104 a, the MOSFET function may be degraded.
  • In the example illustrated in FIG. 10, each doping region 102 a-102 c has a different doping concentration, and the dopant implanted into the doping regions 102 a-102 c has a different conductivity type from the substrate 100.
  • The counter doping region 102 includes at least a first doping region 102 a, a second doping region 102 b, and a third doping region 102 c. Each doping region 102 a, 102 b, 102 c has a different doping concentration. The first doping region 102 a is disposed in a portion of the substrate 100. Net doping concentration of the first region 102 a is lower than the substrate 100 because the dopant implanted into the first region 102 a has conductivity type opposite to the substrate. The second doping region 102 b is disposed in the WELL regions 112 a, 112 b and 112 c. The net doping concentration of the second region 102 b is increased locally compared to the WELL region 112 because a dopant having the same conductivity type with the WELL region 112 is implanted into the second region 102 b. The third doping region 102 c is disposed in the first BODY region 110 a. Similarly to the second region 102 b, the net doping concentration of the third region 102 c is increased locally compared to the BODY region 110 because a dopant having the same conductivity type with the BODY region 110 is implanted into the third region 102 c.
  • A source region 116 is formed in the partial portion of the BODY region 110. A source region 116 having a different conductivity type from the BODY region 110 is formed. FIG. 11 is a diagram illustrating an example of a cross-sectional view of the semiconductor device after performing doping by the conductivity type N, in order to form a source region 116 in the MOSFET region 300. The source region 116 is formed by doping the upper portion of the substrate between the second trenches 104 b using the conductivity type N. Further, the source region 116 has a shorter depth than the upper Poly-Si 108 of the second trench 104 b and a shallower depth than the BODY region 110 a.
  • As illustrated in FIG. 11, after forming the source region 116, an insulating layer 117 is formed at the upper surface of the N-type EPI substrate 100.
  • FIG. 12 is a diagram illustrating an example of a patterning of a region where a contact plug is formed to be opened toward the insulating layer 117 by using a mask (not illustrated) in order to form a contact plug in the MOSFET region 300. As illustrated in FIG. 12, a portion of the source region 116 is etched. Through the etching, the contact plug may contact the source region 116 and BODY region 110.
  • Thereafter, as illustrated in FIG. 13, the upper surface of the SBD region 310 is selectively opened using patterning process. The insulating layer 117 over the upper surface of the SBD region 310 is selectively removed through a wet etching process which induces less damage to the upper surface of the SBD region 310. The contact plug may contact the SBD region 310. In this example, the insulator layer 117 still partially covers the BODY portion 110 and the source region 116. Thereafter, a metal layer 118 may be deposited over the substrate to make contact with the BODY region 110, the source region 116, and the SBD region 310. A metal layer 118 may contact the counter doping region 102 as well as the WELL regions 112 a, 112 b and 112 c. Aluminum (Al) metal or Copper (Cu) metal or TiN or Ti barrier metal may be used as the metal layer 118.
  • FIG. 14 is a diagram illustrating an example of a cross-sectional view of a semiconductor device with the metal layer 118. A silicide layer (not shown) such as cobalt silicide (CoSi2), titanium silicide (TiSi2), and nickel silicide (NiSi) may be formed prior to the deposition of the metal layer 118.
  • The above description provides a semiconductor device embedded with a Schottky barrier diode configured to reduce an N-type doping concentration at a surface of the N-type EPI substrate 100 by using the counter doping implantation. The resistance near the surface of the N-type EPI substrate 100 may be increased through the counter doping process. Thus, a breakdown voltage of the whole semiconductor device can be increased.
  • The increase of the breakdown voltage of the semiconductor device according to the counter doping process is illustrated in FIGS. 15 to 17.
  • FIGS. 15 and 16 are diagrams illustrating example graphs of doping concentrations, according to depths of a semiconductor device in which a counter doping is not performed, and a semiconductor device whose SBD region is performed with counter doping.
  • FIG. 15 a is a diagram illustrating an example of a doping concentration change of a semiconductor device in which counter doping is not performed. FIG. 15 b is a diagram illustrating an example of a doping concentration change of a semiconductor device in which counter doping is performed.
  • In FIG. 15 a, “A” represents a region that ranges from an upper portion to a bottom portion of a substrate of a WELL region in the semiconductor device embedded with the SBD in which a counter doping is not performed. In FIG. 15 a, “B” represents a region that ranges from an upper portion to a bottom portion of a substrate of the semiconductor device embedded with the SBD in which a counter doping is not performed. X1 represents a thickness of the WELL region of the semiconductor device embedded with the SBD in which a counter doping is not performed.
  • In FIG. 15 b, “A′” represents a region that ranges from an upper portion to a bottom portion of a substrate of the WELL regions 112 a, 112 b and 112 c including the counter doping region 102. In FIG. 15 b, “B” represents a region that ranges from an upper portion to a bottom portion of a substrate including the counter doping region 102. X2 represents a thickness of the WELL region of the semiconductor device embedded with the SBD in which counter doping is performed.
  • Referring to FIGS. 15 a and 15 b, it should be appreciated that the thickness (X2) of the WELL region of the semiconductor device with counter doping is deeper than a thickness (X1) of the WELL region of the semiconductor device without counter doping. This is because the WELL region is formed by the same conductivity type as the counter doping's conductivity type.
  • FIGS. 16 a and 16 b are diagrams illustrating an example of graphs of net doping concentration profiles according to A, A′, B, B′ which are illustrated in FIGS. 15 a and 15 b. FIG. 16 b is a diagram illustrating an example of a graph that shows a magnified portion in FIG. 16 a with a dotted line.
  • In FIGS. 16 a and 16 b, the X-axis of the graphs represents a depth from a top surface of the substrate, and the Y-axis of the graphs represents a net doping concentration. Once counter doping is performed (A′), the junction depth of the WELL region, X2 extends beyond 2 μm. On the other hand, without a counter doping process, the junction depth of the WELL region, X1 does not extend to 2 μm. The counter doping process extends the junction depth deeper than without counter doping. The result corresponds to a thickness difference between X1 and X2 as shown in FIGS. 15 a and 15 b.
  • Furthermore, a doping concentration (B) on the substrate without counter doping is constant according to a depth from the substrate surface, as illustrated in FIG. 16 b. Whereas, in the case of counter doping being performed (B′), a smaller doping concentration is shown at the top portion of the substrate up to 8 μm.
  • According to various aspects, the semiconductor device having the SBD region where a counter doping is partially performed can ultimately reduce a net doping concentration of a conductivity type N on a substrate surface through counter doping.
  • Eventually, due to the lowered doping concentration of the conductivity type N on the surface, a resistance value of an N-type EPI surface is high, and an internal resistance in the SBD region is high. The result can be understood through a comparison between FIGS. 17 a and 17 b.
  • FIG. 17 a is a diagram illustrating an example of an Electric Field distribution of a semiconductor device without counter doping, and FIG. 17 b is a diagram illustrating an example of an Electric Field distribution of a semiconductor device embedded with the SBD with counter doping. By comparing FIGS. 17 a and 17 b, it should be appreciated that an electric filed of the substrate surface where counter doping is performed is smaller than where counter doping is not performed.
  • A breakdown voltage of a semiconductor device according to an example may be 39.4 V. Compared with the breakdown voltage value of 8.9 V of a semiconductor device where counter doping is not performed, it can be appreciated that a breakdown voltage value of a semiconductor device embedded with a Schottky barrier diode is largely improved.
  • While this disclosure includes specific examples, it will be apparent to one of ordinary skill in the art that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.

Claims (17)

What is claimed is:
1. A semiconductor device, comprising:
a substrate having a concentration;
a counter doping region having another concentration; and
a Schottky barrier diode (“SBD”) comprising the counter doping region.
2. The semiconductor device of claim 1, further comprising a metal layer in contact with the counter doping region, wherein
the substrate has a conductivity type;
the counter doping region is disposed in the substrate;
the another concentration is lower than the concentration; and
the SBD further comprises the metal layer.
3. The semiconductor device of claim 2, further comprising a WELL region and a BODY region which have another conductivity type and are disposed in the substrate.
4. The semiconductor device of claim 3, wherein the counter doping region comprises:
a first doping region disposed in a top portion of the substrate;
a second doping region disposed in the WELL region; and
a third doping region disposed in the BODY region.
5. The semiconductor device of claim 4, wherein the third doping region has a higher doping concentration than that of the second doping region.
6. The semiconductor device of claim 1, further comprising a first trench having a first depth in the substrate and a second trench having a second depth in the substrate which is lower than the first depth.
7. The semiconductor device of claim 6, wherein the first trench is disposed in a boundary between a MOSFET region and an SBD region.
8. The semiconductor device of claim 3, wherein
the BODY region comprises a first BODY region and a second BODY region;
the WELL region comprises a first WELL region, a second WELL region, and a third WELL region; and
the first BODY region is enclosed by the first WELL region or the third WELL region.
9. The semiconductor device of claim 6, wherein the first trench comprises a top Poly-Si layer, a bottom Poly-Si layer, and an insulating layer which is disposed between the top Poly-Si layer and the bottom Poly-Si layer.
10. The semiconductor device of claim 3, wherein the BODY region has a smaller depth than the WELL region.
11. The semiconductor device of claim 6, further comprising a WELL region, wherein a depth of the WELL region is less than a depth of the first trench.
12. A manufacturing method, comprising:
forming a substrate;
forming a counter doping region in the substrate region;
forming a trench in the substrate region;
forming a BODY region adjacent to the trench; and
forming a WELL region adjacent to the trench.
13. The manufacturing method of claim 12, wherein
the forming a substrate comprises forming a substrate having a conductivity type;
the forming a counter doping region comprises forming a counter doping region having another conductivity type;
the forming a trench comprises forming a plurality of trenches;
the forming a BODY region comprises forming a BODY region having the another conductivity type; and
the forming a WELL region comprises forming the WELL region having the another conductivity type in a Schottky barrier diode (“SBD”) region.
14. The manufacturing method of claim 12, wherein the BODY region has a depth that is less than a depth of the WELL region, and the depth of the WELL region is less than a depth of the trench.
15. The manufacturing method of claim 12, wherein the counter doping region is configured to reduce a net doping concentration at a top portion of the substrate.
16. A semiconductor, comprising:
a substrate having a conductivity type;
a counter-doping region having another conductivity type; and
a metal layer in contact with the counter-doping region.
17. The semiconductor of claim 16, further comprising a Schottky barrier diode (“SBD”) which comprises the counter-doping region and the metal layer, wherein the substrate and the counter-doping region have different concentrations.
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