US20160276156A1 - Semiconductor device and manufacturing process thereof - Google Patents
Semiconductor device and manufacturing process thereof Download PDFInfo
- Publication number
- US20160276156A1 US20160276156A1 US14/658,649 US201514658649A US2016276156A1 US 20160276156 A1 US20160276156 A1 US 20160276156A1 US 201514658649 A US201514658649 A US 201514658649A US 2016276156 A1 US2016276156 A1 US 2016276156A1
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- US
- United States
- Prior art keywords
- layer
- metal silicide
- semiconductor device
- conductive
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 102
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 91
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 80
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 59
- 229910052710 silicon Inorganic materials 0.000 claims description 58
- 239000010703 silicon Substances 0.000 claims description 58
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
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- 239000011733 molybdenum Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 5
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- 239000010410 layer Substances 0.000 description 246
- 238000000034 method Methods 0.000 description 58
- 230000008569 process Effects 0.000 description 45
- 239000000758 substrate Substances 0.000 description 36
- 239000004020 conductor Substances 0.000 description 22
- 239000000463 material Substances 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 11
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- 239000003989 dielectric material Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
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- 238000005229 chemical vapour deposition Methods 0.000 description 7
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- 150000004706 metal oxides Chemical class 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
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- 230000008021 deposition Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
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- 238000005240 physical vapour deposition Methods 0.000 description 6
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- 238000000231 atomic layer deposition Methods 0.000 description 4
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- 150000001875 compounds Chemical class 0.000 description 3
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- 239000012535 impurity Substances 0.000 description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 3
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- 239000000126 substance Substances 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
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- 238000011065 in-situ storage Methods 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 210000002381 plasma Anatomy 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 229910017121 AlSiO Inorganic materials 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910021244 Co2Si Inorganic materials 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
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- 229910012990 NiSi2 Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- JUZTWRXHHZRLED-UHFFFAOYSA-N [Si].[Cu].[Cu].[Cu].[Cu].[Cu] Chemical compound [Si].[Cu].[Cu].[Cu].[Cu].[Cu] JUZTWRXHHZRLED-UHFFFAOYSA-N 0.000 description 1
- WIGAYVXYNSVZAV-UHFFFAOYSA-N ac1lavbc Chemical compound [W].[W] WIGAYVXYNSVZAV-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
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- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- DIKBFYAXUHHXCS-UHFFFAOYSA-N bromoform Chemical compound BrC(Br)Br DIKBFYAXUHHXCS-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
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- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
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- 239000008367 deionised water Substances 0.000 description 1
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- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
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- 238000002513 implantation Methods 0.000 description 1
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- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
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- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
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- 239000011368 organic material Substances 0.000 description 1
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- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- LEYNFUIKYCSXFM-UHFFFAOYSA-N platinum tantalum Chemical compound [Ta][Pt][Ta] LEYNFUIKYCSXFM-UHFFFAOYSA-N 0.000 description 1
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- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000012686 silicon precursor Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- 229910000326 transition metal silicate Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
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Definitions
- conductive interconnect structures are widely utilized for electrically connect different components of the device and/or connect external circuits.
- the requirements for reliability and performance of the conductive interconnects are becoming more stringent as the feature size continues to shrink.
- Advanced manufacturing techniques are investigated for improving the integrity of the conductive interconnects and the system performance of the semiconductor chip.
- FIGS. 1A-1L are cross sectional views of operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.
- FIG. 2 is a schematic showing a semiconductor manufacturing platform, in accordance with some embodiments of the present disclosure.
- FIG. 3 is a flow diagram showing operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.
- FIG. 4 is a flow diagram showing operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.
- FIG. 5 is a flow diagram showing operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- FIGS. 1A-1L are cross sectional views of operations for manufacturing a semiconductor device 100 , in accordance with some embodiments of the present disclosure.
- a semiconductor substrate 102 is provided.
- Semiconductor substrate 102 includes a semiconductor material such as silicon, silicon germanium, or the like.
- Semiconductor substrate 102 may be lightly doped with a p-type impurity to become a p-type silicon substrate (P-substrate). Otherwise, semiconductor substrate 102 can also be doped with an n-type impurity to be an n-type silicon substrate (n-substrate).
- semiconductor substrate 102 includes an elementary semiconductor such as silicon or germanium in crystal, polycrystalline, or an amorphous structure.
- semiconductor substrate 102 may be compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), silicon carbide (SiC), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb).
- GaAs gallium arsenide
- GaP gallium phosphide
- SiC silicon carbide
- InP indium phosphide
- InAs indium arsenide
- InSb indium antimonide
- semiconductor substrate 102 may be an alloy semiconductor such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminium gallium arsenide (AlGaAs), aluminium indium arsenide (AlInAs), germanium indium arsenide (GaInAs), germanium indium phosphide (GaInP), and/or germanium indium arsenide phosphide (GaInAsP) or any other suitable materials.
- SiGe silicon germanium
- GaAsP gallium arsenide phosphide
- AlGaAs aluminium gallium arsenide
- AlInAs aluminium indium arsenide
- GaInAs germanium indium arsenide
- GaInP germanium indium phosphide
- GaInAsP germanium indium arsenide phosphide
- semiconductor substrate 102 may be a silicon on insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.
- semiconductor substrate 102 includes a doped epitaxy layer or a buried layer. In other examples, semiconductor substrate 102 has a multilayer compound structure.
- isolation features 12 such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS), are formed in semiconductor substrate 102 to separate devices. Isolation features 12 are formed to define and electrically isolate various active regions as shown in FIG. 1 .
- isolation features 12 may define a region for a complementary metal oxide semiconductor (CMOS) device, a region for a core n-type MOS (NMOS) device, a region for a core p-type MOS (PMOS) device, and other regions for various microelectronic devices utilized in integrated circuits. It is understood that several processes disclosed below form corresponding features in some other active regions on semiconductor substrate 102 for some other types of devices.
- Isolation features 12 may comprise silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), an air gap, other suitable materials, or combinations thereof.
- first doped region 13 is formed in semiconductor substrate 12 .
- second doped region 14 is formed in semiconductor substrate 12 adjacent to some isolation features 12 .
- First doped region 13 and second doped region 14 can be a source region or a drain region for PMOS, NMOS or CMOS transistors.
- First doped region 13 and second doped region 14 comprise highly concentrated dopants, and are formed as p-type regions with boron or n-type region with phosphorus.
- First doped region 13 and second doped region 14 may be formed by various processes, for example, thermal diffusion process.
- First doped region 13 and second doped region 14 may be formed by a plurality of operations, whether now known or to be developed, such as growing a sacrificial oxide on semiconductor substrate 102 , opening a pattern for a location(s) in first doped region 13 or second doped region 14 , implanting impurities and annealing.
- semiconductor substrate 102 may include various well regions (not shown) depending on design specifications as known in the art.
- the well regions are formed in a p-well structure, an n-well structure or a twin well structure.
- the doping concentration in those well regions is less than first doped region 13 or second doped region 14 .
- the p-well structure is formed with p-type dopants to surround n-type first doped region 13 or n-type second doped region 14 .
- the n-well structure is formed with n-type dopants to surround p-type first region 13 or second doped region 14 .
- ILD layer 104 is formed on semiconductor substrate 102 .
- ILD layer 104 includes parts of MOS transistors, such as a gate structure 15 , first sidewall spacer 18 , and second sidewall spacer 19 and conductive plugs 21 and 22 .
- Gate structure 15 is disposed on semiconductor substrate 102 .
- Gate structure 15 may include a gate dielectric 16 disposed on semiconductor substrate 102 and a gate electrode 17 disposed on gate dielectric 16 .
- Gate dielectric 16 which is a layer on semiconductor substrate 102 , may include a silicon oxide layer.
- gate dielectric 16 may optionally include a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof.
- the high-k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitride of metals, metal aluminates, zirconium silicate, zirconium aluminate, hafnium oxide, or combinations thereof.
- high-k dielectric material examples include HfO 2 , HfSiO, HfSiON, HfzrO, LaO, BazrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, zirconium oxide, aluminum oxide, other suitable high-k dielectric materials, and/or combinations thereof.
- gate dielectric 16 may have a multilayer structure such as one layer of silicon oxide and another layer of high k material. Gate dielectric 16 may be formed over an interfacial layer by any suitable process.
- Gate electrode 17 is disposed on gate dielectric 16 .
- Gate electrode 17 includes conductive material, such as aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof.
- heavily doped amorphous silicon or polysilicon is alternatively used. In that case a highly concentrated dopant such as boron or phosphorus is utilized to form gate electrode 17 .
- a silicon layer is used as gate material for gate structure 15 .
- a silicide layer (not shown) is formed on gate electrode layer 17 by reacting silicon with conductive material such as tungsten, Ti, Pt, Ta, Nb, Hf, Mo, or other suitable metal.
- Gate structure 15 has a first sidewall spacer 18 of gate structure 15 and a second sidewall spacer 19 disposed opposite to first sidewall spacer 18 of gate structure 15 .
- First sidewall spacer 18 and second sidewall spacer 19 are formed by dielectric material such as silicon nitride or silicon oxide.
- First sidewall space 18 and second sidewall spacer 19 may be formed in different shapes in the upper portions or slopes.
- First sidewall spacer 18 and second sidewall spacer 19 may be formed by deposition of thin film, such as silicon nitride, on gate structure 15 and semiconductor substrate 12 . Then an etching process is used to remove the residue film material on the surface of semiconductor substrate 12 , leaving first sidewall spacer 18 and second sidewall 19 .
- ILD layer 104 further comprises conductive plugs 21 and conductive plug 22 .
- Conductive plug 21 may be formed atop first doped region 13 .
- Conductive plug 21 is electrically coupling first doped region 13 with conductive materials of overlying layers in semiconductor device 100 .
- conductive plug 22 is electrically coupling second doped region 14 with conductive materials of overlying layers in semiconductor device 100 .
- Conductive plugs 21 and 22 are formed with electrically conductive materials, such as aluminum, copper, tungsten, or other suitable metal.
- Conductive plugs 21 and 22 may be formed by a suitable process such as low pressure chemical vaporization deposition (LPCVD) or sputtering.
- LPCVD low pressure chemical vaporization deposition
- a diffusion barrier layer (not shown) is formed between conductive plugs 21 and 22 and semiconductor substrate 102 .
- a diffusion barrier layer (not shown) is formed between conductive plugs 21 and 22 and semiconductor substrate 102 .
- titanium, titanium nitride or tungsten-tungsten can be used in forming the diffusion barrier layer.
- the diffusion barrier layer may be formed by sputtering, CVD or other suitable process.
- ILD 104 also includes dielectric materials for electrically isolating among components in ILD layer 104 , and between ILD 104 and semiconductor substrate 102 .
- a suitable process may be utilized for forming the dielectric materials, such as deposition. Then a planarization process is applied to ILD layer 104 for further processes.
- Dielectric layer 105 is disposed on ILD layer 104 .
- Dielectric layer 105 includes materials such as silicon oxide, silicon nitride (SiN), silicon oxynitride, silicon oxycarbide (SiOC), silicon carbide, fluorinated silicon oxide (SiOF), carbon-doped silicon oxide (e.g., SiOCH), spin-on glass (SOG), amorphous fluorinated carbon, fluorinated silica glass (FSG), polyimide, BCB (bis-benzocyclobutenes), non-porous materials, porous materials, and/or combinations thereof.
- Dielectric layer 105 includes a high density plasma (HDP) dielectric material (e.g., HDP oxide) and/or a high aspect ratio process (HARP) dielectric material (e.g., HARP oxide). In some embodiments, Dielectric layer 105 is a planarized dielectric film.
- HDP high density plasma
- HEP high aspect ratio process
- Dielectric layer 105 is a planarized dielectric film.
- Dielectric layer 105 is formed by a suitable deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), ionized PVD (IPVD) and atomic layer deposition (ALD). Additionally, other processes include high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), LPCVD, thermal oxidation, UV-ozone oxidation, epitaxial growth methods (e.g., selective epitaxy growth), sputtering, plating, spin-on coating, other suitable methods, and/or combinations thereof. In an embodiment, dielectric layer 105 has a suitable range of thickness from about 100 ⁇ to about 2000 ⁇ .
- a trench 107 and a recess 108 are formed by a suitable etching process on dielectric layer 105 to form patterned dielectric layer 106 .
- Recess 108 may include a stacked trench and via structure.
- a layer of photoresist is formed over dielectric layer 105 by a suitable process, for example, lithography or other alternatives, and patterned to form a photoresist feature by a proper photolithography patterning method.
- a photolithography process may also be implemented or replaced by other proper methods such as maskless photolithography, electron-beam writing, ion-beam writing, and/or molecular imprint.
- a photolithography process may include forming a photoresist layer over dielectric layer 105 , exposing photoresist to a pattern, performing a post-exposure bake process, and forming a masking element including the photoresist.
- a dual damascene technology is utilized where an intermediate etch stop layer may be formed as hard mask for the stacked trench-via structure of recess 108 .
- trench 107 and recess 108 may then be etched using reactive ion etching (RIE) processes and/or other etching processes.
- RIE reactive ion etching
- An etching process may include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching).
- the etching process may also be either purely chemical (plasma etching), purely physical (ion milling), and/or combinations thereof.
- a dry etching process may be implemented in an etching chamber.
- the thickness of different features may be controlled by adjusting some process parameters including a radio frequency (RF) source power, a bias power, electrode size, a pressure, a flow rate, etching duration, a wafer temperature, other suitable process parameters, and/or combinations thereof.
- RF radio frequency
- a dry etching process may implement an oxygen-containing gas, fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), bromine-containing gas (e.g., HBr, He and/or CHBr 3 ), iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.
- the dry etching process utilizes an O 2 plasma treatment and/or an O 2 /N 2 plasma treatment. Further, the dry etching process may be performed for a suitable duration.
- a wet etching process may utilize a hydrofluoric acid (HF) solution for a HF dipping process.
- a wet etching process may apply a diluted hydrofluoric acid to an intermediate semiconductor structure.
- the wet etching process includes exposing to a hydroxide solution containing ammonium hydroxide, diluted HF, deionized water, and/or other suitable etchant solutions.
- a diffusion barrier layer (not shown) may be optionally formed on the bottom and sidewalls of trench 107 and recess 108 .
- a typical diffusion barrier metal or alloy includes tantalum, nickel, hafnium, niobium, zirconium, vanadium, tungsten, nichrome, and titanium tungdsten.
- conductive ceramics is also considered, such as indium oxide, copper silicide, tungsten nitride, and titanium nitride.
- a suitable deposition process for forming the diffusion barrier layer as previously discussed can be used, such as CVD, ALD and PVD.
- the diffusion barrier layer has a thickness from about 20 ⁇ to about 200 ⁇ . It is understood, however, that the dimensions recited throughout the present disclosure will scale due to the utilized manufacturing techniques.
- FIG. 1D is a step of filling conductive material into trench 107 and recess 108 .
- a conductive interconnect 112 and a conductive interconnect 114 are then formed in trench 107 and recess 108 , respectively.
- Conductive interconnect 112 is formed to electrically couple features in patterned dielectric layer 106 .
- conductive interconnect 114 is formed in recess 108 to electrically connect underlying layers.
- conductive interconnect 112 and conductive interconnect 114 are configured to couple gate structure 15 with an input/output (I/O) region (not shown) over conductive interconnect 112 and conductive interconnect 114 .
- the conductive material for conductive interconnect 112 and conductive interconnect 114 includes copper, aluminum or other suitable materials.
- a seed layer is optionally formed on the walls of trench 107 and recess 108 .
- Typical materials for the seed layer include Pd or other compounds of polymers and organic materials.
- the seed layer may be formed by deposition through a suitable process such as PVD.
- a suitable planarization process is used.
- patterned dielectric layer 106 , and conductive interconnects 112 and 114 are planarized. Additionally, dielectric layer 106 , conductive interconnects 112 and 114 are made coplanar to facilitate subsequent processes.
- a planarization process may be a chemical mechanical planarization (CMP) operation.
- a conductive layer 110 is deposited on conductive interconnect 112 and conductive interconnect 114 .
- conductive layer 110 is formed between conductive interconnects 112 or 114 and overlying layers, such as dielectric layers.
- Conductive layer 110 is used to prevent conductive material in conductive interconnect 112 and conductive interconnect 114 , such as copper, from diffusing into surrounding dielectric materials.
- Conductive layer 110 is formed with conductive materials such as cobalt, nickel, tungsten, molybdenum, titanium, platinum tantalum, other suitable material, and/or combinations thereof.
- Conductive layer 110 has a thickness from about 10 ⁇ to about 100 ⁇ .
- a suitable deposition process for forming conductive layer 110 includes CVD, ALD and other suitable processes.
- a deposition process may perform selective deposition of conductive layer 110 onto the surface of the openings of conductive interconnect 112 and conductive interconnect 114 in order for electrically insulating between conductive interconnect 112 and conductive interconnect 114 .
- the selective deposition provides to insulate conductive interconnect 112 and conductive interconnect 114 and other conductive interconnects in patterned dielectric layer 106 .
- a silicon layer 116 is deposited over conductive layer 110 .
- silicon layer 116 is covering patterned dielectric layer 106 .
- Silicon layer 116 has a thickness of from about 10 ⁇ to about 100 ⁇ .
- a suitable deposition process includes CVD using silane (SiH 4 ) or disilane (Si 2 H 6 ) as a silicon precursor.
- silicon layer 116 can be formed by a PVD process by using silicon as target.
- a metal silicide layer 118 is formed at the interface of silicon layer 116 and conductive layer 110 .
- silicon layer 116 is disposed on the periphery of metal silicide layer 118 .
- Silicon layer 116 provides silicon for forming metal silicide layer 118 .
- Metal silicide layer 118 is formed by reacting silicon atoms from silicon layer 116 with the metal included in conductive layer 110 .
- Metal silicide layer 118 may include Co 2 Si, CoSi, CoSi 2 , NiSi, NiSi 2 , WSi 2 , MoSi 2 , TiSi 2 , PtSi, TaSi 2 , other suitable materials, and/or combinations thereof.
- Metal silicide layer 118 is formed over conductive interconnects 112 and 114 . In one embodiment, when the conductive material in contact with conductive layer 110 is consumed in forming metal silicide layer 118 , metal silicide layer 118 would be formed on conductive interconnects 112 and 114 . In another embodiment where part of conductive layer 110 is disposed on conductive interconnects 112 and 114 , metal silicide layer 118 is formed between silicon layer 116 and conductive layer 110 . In one embodiment, metal silicide layer 118 is disposed over the surfaces of conductive interconnects 112 and 114 .
- a second dielectric layer 220 is formed on metal silicide layer 118 .
- second dielectric layer 220 is deposited on patterned dielectric layer 106 .
- Second dielectric layer 220 may be deposited on silicon layer 116 .
- the material used for forming second dielectric layer 220 is the same as that for forming patterned dielectric layer 106 .
- metal silicide layer 118 may be formed between second dielectric layer 220 and conductive interconnects 112 and 114 .
- Second dielectric layer 220 has a thickness of from about 100 ⁇ to about 2000 ⁇ . In one embodiment, the ratio of thickness between second dielectric layer 220 and metal silicide layer 118 is between 1 and 200.
- the step of forming metal silicide layer 118 to be a silicide form of the conductive material of conductive layer 110 is performed during the formation of the second dielectric layer 220 on silicon layer 116 .
- silicon layer 116 has a coefficient of thermal expansion (CTE) of from about 2 ppm/° C. to about 3.3 ppm/° C., for example 2.6 ppm/° C.
- second dielectric layer 220 has a CTE of from about 0.1 ppm/° C. to about 5 ppm/° C., for example 1 ppm/° C.
- conductive layer 110 has a CTE of from about 4.5 ppm/° C. to about 9 ppm/° C., for example 6.3 ppm/° C., or from about 13 ppm/° C. to about 14 ppm/° C., for example 13.5 ppm/° C.
- conductive interconnects 112 or 114 has a CTE of from about 16 ppm/° C. to about 24 ppm/° C.
- metal silicide layer 118 has a CTE of from about 6.5 ppm/° C. to about 9.5 ppm/° C., or from about 9.5 ppm/° C. to about 15 ppm/° C.
- the CTE of conductive interconnect 112 or conductive interconnect 114 is larger than the CTE of metal silicide layer 118 .
- the CTE of metal silicide layer 118 is larger than the CTE of silicon layer 116 .
- the CTE of metal silicide layer 118 is larger than the CTE of second dielectric layer 220 .
- the CTE of metal silicide layer 118 is larger than the CTE of patterned dielectric layer 106 .
- the ratio of the CTE between metal silicide layer 118 and second dielectric layer 220 is larger than the ratio of CTE between metal silicide layer 118 and silicon layer 116 . In some examples, the ratio of the CTE between conductive interconnect 112 and second dielectric layer 220 is larger than the ratio of CTE between conductive interconnect 112 and silicon layer 116 .
- metal silicide layer 118 can be formed in-situ with second dielectric layer 220 .
- the formation of both metal silicide layer 118 and second dielectric layer 220 can be performed within the same chamber or within one platform without breaking vacuum.
- second dielectric layer 220 is formed in one chamber by breaking vacuum after metal silicide layer 118 is formed in another chamber.
- conductive layer 110 and second dielectric layer 220 In conventional practices, it is required to form conductive layer 110 and second dielectric layer 220 in different chambers, and thus a process sequence with breaking vacuum is inevitable.
- conductive layer 110 is formed and moved out of the vacuum condition, it is found that a metal oxide layer may be formed before second dielectric layer 220 is formed on conductive layer 110 .
- the metal oxide layer is formed by reacting oxygen in the atmosphere with conductive layer 110 . It is believed that the metal oxide layer may lead to defects such as bubbles or peeling. The adhesion between conductive layer 110 and second dielectric layer 220 is thus degraded. The device integrity and reliability would be impacted due to peeling or bubbles.
- silicon layer 116 is formed on conductive layer 110 before conductive layer 110 is exposed to oxygen. That can prevent formation of a metal oxide layer. The performance of adhesion between conductive layer 110 and second dielectric layer 220 is thus improved.
- FIGS. 1I -IJ are cross sectional views of a semiconductor device manufacturing processes, in accordance with some embodiments.
- FIGS. 1I-1J show alternative operation steps subsequent to the operation step illustrated in FIG. 1F .
- second dielectric layer 220 is deposited on silicon layer 116 before metal silicide layer 118 is formed.
- second dielectric layer 220 is covering part of patterned dielectric layer 106 .
- silicon layer 116 is disposed between patterned dielectric layer 106 and second dielectric layer 220 .
- second dielectric layer 220 is disposed over conductive layer 110 .
- conductive layer 110 is disposed between pattern dielectric layer 106 and second dielectric layer 220 .
- metal silicide layer 118 is formed between second dielectric layer 220 and conductive interconnect 114 or conductive interconnect 112 .
- a suitable process for forming metal silicide layer 118 includes an annealing process, such as heating semiconductor substrate 102 .
- metal silicide layer 118 is formed on conductive layer 110 . In another embodiment, metal silicide layer 118 is formed at the surface between silicon layer 116 and conductive layer 110 . In yet another embodiment, metal silicide layer 118 is formed between silicon layer 116 and conductive interconnect 112 and conductive interconnect 114 .
- FIGS. 1K -IL are cross sectional views of a semiconductor device manufacturing processes, in accordance with some embodiments.
- FIGS. 1K-1L show another alternative operation steps subsequent to the operation step illustrated in FIG. 1E .
- part of second dielectric layer 220 is formed on patterned dielectric layer 106 .
- second dielectric layer 220 is utilized, instead of the formation of silicon layer 116 as illustrated in FIG. 1F , with a view to keeping oxygen from reacting with metal in conductive layer 110 .
- second dielectric layer 220 is covering portions of patterned dielectric layer 106 .
- Second dielectric layer 220 is disposed over conductive layer 110 .
- conductive layer 110 is disposed between patterned dielectric layer 106 and second dielectric layer 220 .
- metal silicide layer 118 is also started on the surface of conductive layer 110 .
- the silicon in second dielectric layer 220 is transferred into metal silicide layer 118 during the formation of second dielectric layer 220 .
- metal silicide layer 118 is formed between second dielectric layer 220 and conductive layer 110 .
- second dielectric layer 220 and metal silicide layer 118 are formed in-situ with conductive layer 110 without breaking vacuum.
- the step of forming metal silicide layer 118 to be a silicide form of the conductive material of conductive layer 110 is performed during the formation of second dielectric layer 220 .
- a full second dielectric layer 220 and a full metal silicide layer 118 are formed.
- FIG. 2 shows a schematic of a semiconductor manufacturing platform 200 , in accordance with some embodiments.
- Semiconductor manufacturing platform 200 includes a first tool 202 , a second tool 204 , and a channel 206 .
- First tool 202 includes a first chamber 202 to accommodate a semiconductor wafer for conducting processes.
- First tool 202 is configured to perform semiconductor manufacturing operations, such as those illustrated in FIGS. 1A-1L , on the semiconductor wafer.
- First chamber 202 is shown for illustration, and different configurations with more chambers are alternatively used in first tool 202 .
- second tool 204 includes a second chamber 204 to accommodate a semiconductor wafer.
- a manufacturing process performed in first tool 202 may be different from the manufacturing process performed in second tool 204 .
- Channel 206 is disposed between first tool 202 and second tool 204 .
- Channel 206 includes a robot 208 , configured to move semiconductor wafers between first tool 202 and second tool 204 .
- channel 206 is configured under a low pressure or vacuum condition. The pressure of channel 206 may be kept under 0.1 torr.
- channel 206 provides a virtual vacuum tunnel through which contamination due to undesired reactants, such as oxygen, can be controlled.
- the operations in FIGS. 1E and 1K performed in sequence may be conducted in first tool 202 and second tool 204 separately.
- the sequential operations require a working environment without breaking vacuum in order to prevent the formation of a metal oxide layer on conductive layer 110 . In that case channel 206 can be leveraged in moving semiconductor wafer without breaking vacuum after conductive layer 110 is formed.
- FIG. 3 is a flow diagram showing a semiconductor manufacturing process, in accordance of some embodiments.
- semiconductor substrate 102 of semiconductor device 100 is provided.
- at least one transistor is formed on semiconductor substrate 102 .
- the transistor includes a gate structure, a source region and a drain region.
- dielectric layer 105 is etched to form trench 107 and recess 108 such that patterned dielectric layer 106 is formed over the gate structure of semiconductor device 100 .
- conductive interconnect 112 and 114 are formed in trench 107 and recess 108 , respectively, in patterned dielectric layer 106 .
- a surface of conductive interconnect 112 or conductive interconnect 114 uncovered by the patterned dielectric layer 106 is exposed.
- conductive interconnect 112 and conductive interconnect 114 include a conductive material such as copper or aluminum.
- conductive layer 110 having a conductive material is formed on the exposed surface of conductive interconnect 112 or conductive interconnect 114 .
- the conductive material is formed over the exposed surface.
- silicon layer 116 is formed on conductive layer 110 .
- Silicon layer 116 provides the silicon for forming metal silicide layer 118 .
- metal silicide layer 118 is formed to be a silicide form of the conductive material for conductive interconnect 112 or conductive interconnect 114 .
- Metal silicide layer 118 is formed by reacting the conductive material with silicon. In an embodiment, metal silicide layer 118 is formed by reacting the conductive material in conductive layer 110 and the silicon through a process of, for example, heating the substrate.
- second dielectric layer 220 is formed on silicon layer 116 .
- second dielectric layer 220 is formed on patterned dielectric layer 106 .
- the step of forming metal silicide layer 118 to be a silicide form of the conductive material is performed during the formation of second dielectric layer 220 on silicon layer 116 .
- FIG. 4 is a flow diagram showing a semiconductor manufacturing process, in accordance of some embodiments. Referring to FIG. 4 , operations 310 - 360 are illustrated in operations 310 - 360 of FIG. 3 . Following operation 360 , in operation 410 , second dielectric layer 220 is formed on silicon layer 116 . In operation 420 , metal silicide layer 118 is formed between conductive layer 110 and second dielectric layer 220 .
- FIG. 5 is a flow diagram showing a semiconductor manufacturing process, in accordance of some embodiment.
- operations 310 - 350 are illustrated in operations 310 - 350 of FIG. 3 .
- part of second dielectric layer 220 is formed on silicon layer 116 .
- metal silicide layer 118 is formed between conductive layer 110 and second dielectric layer 220 .
- Metal silicide layer 118 is formed during the formation of second dielectric layer 220 .
- metal silicide layer 118 is formed where the silicon is transferred into metal silicide layer 118 during the process of forming second dielectric layer 220 in operation 510 .
- Some embodiments of the present disclosure provide a semiconductor device including a dielectric layer over a gate structure of the semiconductor device.
- a conductive interconnect is configured to couple the gate structure with an I/O region over the conductive interconnect.
- a metal silicide layer is disposed between the conductive interconnect and the dielectric layer, and the metal silicide is a silicide form of a metal different from the conductive interconnect.
- Some embodiments of the present disclosure provide a semiconductor device including a first dielectric layer.
- a conductive interconnect is disposed within the first dielectric layer.
- a metal silicide layer is disposed over the conductive interconnect.
- a silicon layer is disposed on the periphery of the metal silicide layer, and a second dielectric layer disposed over the metal silicide layer and the silicon layer.
- Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, which include providing a substrate.
- the method also includes forming a gate structure on the substrate.
- the method further includes forming a first dielectric layer over the gate structure of the semiconductor device.
- the method includes forming a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect uncovered by the first dielectric layer.
- the method also includes forming a conductive material on the exposed surface, and forming a metal silicide layer to be a silicide form of the conductive material by reacting the conductive material with silicon.
Abstract
Description
- As the semiconductor manufacturing and fabrication industry has progressed to advanced technology nodes, it can be found that integration levels are increasing, device features are reduced, and greater demands are increasing for device performance.
- In a fabrication process for a semiconductor chip, conductive interconnect structures are widely utilized for electrically connect different components of the device and/or connect external circuits. The requirements for reliability and performance of the conductive interconnects are becoming more stringent as the feature size continues to shrink. Advanced manufacturing techniques are investigated for improving the integrity of the conductive interconnects and the system performance of the semiconductor chip.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
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FIGS. 1A-1L are cross sectional views of operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure. -
FIG. 2 is a schematic showing a semiconductor manufacturing platform, in accordance with some embodiments of the present disclosure. -
FIG. 3 is a flow diagram showing operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure. -
FIG. 4 is a flow diagram showing operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure. -
FIG. 5 is a flow diagram showing operations for manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
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FIGS. 1A-1L are cross sectional views of operations for manufacturing asemiconductor device 100, in accordance with some embodiments of the present disclosure. Referring toFIG. 1A , asemiconductor substrate 102 is provided.Semiconductor substrate 102 includes a semiconductor material such as silicon, silicon germanium, or the like.Semiconductor substrate 102 may be lightly doped with a p-type impurity to become a p-type silicon substrate (P-substrate). Otherwise,semiconductor substrate 102 can also be doped with an n-type impurity to be an n-type silicon substrate (n-substrate). In some embodiments,semiconductor substrate 102 includes an elementary semiconductor such as silicon or germanium in crystal, polycrystalline, or an amorphous structure. In some embodiments,semiconductor substrate 102 may be compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), silicon carbide (SiC), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb). In other embodiment,semiconductor substrate 102 may be an alloy semiconductor such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminium gallium arsenide (AlGaAs), aluminium indium arsenide (AlInAs), germanium indium arsenide (GaInAs), germanium indium phosphide (GaInP), and/or germanium indium arsenide phosphide (GaInAsP) or any other suitable materials. - In some embodiments,
semiconductor substrate 102 may be a silicon on insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In some examples,semiconductor substrate 102 includes a doped epitaxy layer or a buried layer. In other examples,semiconductor substrate 102 has a multilayer compound structure. - In
FIG. 1B , various isolation features 12, such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS), are formed insemiconductor substrate 102 to separate devices.Isolation features 12 are formed to define and electrically isolate various active regions as shown inFIG. 1 . For example,isolation features 12 may define a region for a complementary metal oxide semiconductor (CMOS) device, a region for a core n-type MOS (NMOS) device, a region for a core p-type MOS (PMOS) device, and other regions for various microelectronic devices utilized in integrated circuits. It is understood that several processes disclosed below form corresponding features in some other active regions onsemiconductor substrate 102 for some other types of devices.Isolation features 12 may comprise silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), an air gap, other suitable materials, or combinations thereof. - Subsequently, a first
doped region 13 is formed insemiconductor substrate 12. Moreover, a seconddoped region 14 is formed insemiconductor substrate 12 adjacent to someisolation features 12. First dopedregion 13 and second dopedregion 14 can be a source region or a drain region for PMOS, NMOS or CMOS transistors. First dopedregion 13 and second dopedregion 14 comprise highly concentrated dopants, and are formed as p-type regions with boron or n-type region with phosphorus. First dopedregion 13 and seconddoped region 14 may be formed by various processes, for example, thermal diffusion process. First dopedregion 13 and seconddoped region 14 may be formed by a plurality of operations, whether now known or to be developed, such as growing a sacrificial oxide onsemiconductor substrate 102, opening a pattern for a location(s) in firstdoped region 13 or second dopedregion 14, implanting impurities and annealing. - In some embodiments,
semiconductor substrate 102 may include various well regions (not shown) depending on design specifications as known in the art. The well regions are formed in a p-well structure, an n-well structure or a twin well structure. The doping concentration in those well regions is less than first dopedregion 13 or second dopedregion 14. The p-well structure is formed with p-type dopants to surround n-type first dopedregion 13 or n-type second dopedregion 14. Alternatively, the n-well structure is formed with n-type dopants to surround p-typefirst region 13 or second dopedregion 14. - In
FIG. 1B , an inter-layer dielectric (ILD)layer 104 is formed onsemiconductor substrate 102.ILD layer 104 includes parts of MOS transistors, such as agate structure 15,first sidewall spacer 18, andsecond sidewall spacer 19 andconductive plugs -
Gate structure 15 is disposed onsemiconductor substrate 102.Gate structure 15 may include a gate dielectric 16 disposed onsemiconductor substrate 102 and agate electrode 17 disposed on gate dielectric 16. - Gate dielectric 16, which is a layer on
semiconductor substrate 102, may include a silicon oxide layer. Alternatively, gate dielectric 16 may optionally include a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The high-k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitride of metals, metal aluminates, zirconium silicate, zirconium aluminate, hafnium oxide, or combinations thereof. Examples of high-k dielectric material includes HfO2, HfSiO, HfSiON, HfzrO, LaO, BazrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, zirconium oxide, aluminum oxide, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments,gate dielectric 16 may have a multilayer structure such as one layer of silicon oxide and another layer of high k material.Gate dielectric 16 may be formed over an interfacial layer by any suitable process. -
Gate electrode 17 is disposed ongate dielectric 16.Gate electrode 17 includes conductive material, such as aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. In some embodiments, heavily doped amorphous silicon or polysilicon is alternatively used. In that case a highly concentrated dopant such as boron or phosphorus is utilized to formgate electrode 17. In some embodiments, a silicon layer is used as gate material forgate structure 15. A silicide layer (not shown) is formed ongate electrode layer 17 by reacting silicon with conductive material such as tungsten, Ti, Pt, Ta, Nb, Hf, Mo, or other suitable metal. -
Gate structure 15 has afirst sidewall spacer 18 ofgate structure 15 and asecond sidewall spacer 19 disposed opposite tofirst sidewall spacer 18 ofgate structure 15.First sidewall spacer 18 andsecond sidewall spacer 19 are formed by dielectric material such as silicon nitride or silicon oxide.First sidewall space 18 andsecond sidewall spacer 19 may be formed in different shapes in the upper portions or slopes.First sidewall spacer 18 andsecond sidewall spacer 19 may be formed by deposition of thin film, such as silicon nitride, ongate structure 15 andsemiconductor substrate 12. Then an etching process is used to remove the residue film material on the surface ofsemiconductor substrate 12, leavingfirst sidewall spacer 18 andsecond sidewall 19. - Referring to
FIG. 1B ,ILD layer 104 further comprisesconductive plugs 21 andconductive plug 22.Conductive plug 21 may be formed atop firstdoped region 13.Conductive plug 21 is electrically coupling first dopedregion 13 with conductive materials of overlying layers insemiconductor device 100. Similarly,conductive plug 22 is electrically coupling seconddoped region 14 with conductive materials of overlying layers insemiconductor device 100. Conductive plugs 21 and 22 are formed with electrically conductive materials, such as aluminum, copper, tungsten, or other suitable metal. Conductive plugs 21 and 22 may be formed by a suitable process such as low pressure chemical vaporization deposition (LPCVD) or sputtering. - In some embodiments, a diffusion barrier layer (not shown) is formed between
conductive plugs semiconductor substrate 102. For example, titanium, titanium nitride or tungsten-tungsten can be used in forming the diffusion barrier layer. The diffusion barrier layer may be formed by sputtering, CVD or other suitable process. -
ILD 104 also includes dielectric materials for electrically isolating among components inILD layer 104, and betweenILD 104 andsemiconductor substrate 102. A suitable process may be utilized for forming the dielectric materials, such as deposition. Then a planarization process is applied toILD layer 104 for further processes. - Referring to
FIG. 1B , adielectric layer 105 is disposed onILD layer 104.Dielectric layer 105 includes materials such as silicon oxide, silicon nitride (SiN), silicon oxynitride, silicon oxycarbide (SiOC), silicon carbide, fluorinated silicon oxide (SiOF), carbon-doped silicon oxide (e.g., SiOCH), spin-on glass (SOG), amorphous fluorinated carbon, fluorinated silica glass (FSG), polyimide, BCB (bis-benzocyclobutenes), non-porous materials, porous materials, and/or combinations thereof. In some embodiments,Dielectric layer 105 includes a high density plasma (HDP) dielectric material (e.g., HDP oxide) and/or a high aspect ratio process (HARP) dielectric material (e.g., HARP oxide). In some embodiments,Dielectric layer 105 is a planarized dielectric film. -
Dielectric layer 105 is formed by a suitable deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), ionized PVD (IPVD) and atomic layer deposition (ALD). Additionally, other processes include high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), LPCVD, thermal oxidation, UV-ozone oxidation, epitaxial growth methods (e.g., selective epitaxy growth), sputtering, plating, spin-on coating, other suitable methods, and/or combinations thereof. In an embodiment,dielectric layer 105 has a suitable range of thickness from about 100 Å to about 2000 Å. - In
FIG. 1C , atrench 107 and arecess 108 are formed by a suitable etching process ondielectric layer 105 to form patterneddielectric layer 106. Recess 108 may include a stacked trench and via structure. In some embodiments, a layer of photoresist is formed overdielectric layer 105 by a suitable process, for example, lithography or other alternatives, and patterned to form a photoresist feature by a proper photolithography patterning method. A photolithography process may also be implemented or replaced by other proper methods such as maskless photolithography, electron-beam writing, ion-beam writing, and/or molecular imprint. In some embodiments, a photolithography process may include forming a photoresist layer overdielectric layer 105, exposing photoresist to a pattern, performing a post-exposure bake process, and forming a masking element including the photoresist. In an embodiment, a dual damascene technology is utilized where an intermediate etch stop layer may be formed as hard mask for the stacked trench-via structure ofrecess 108. - Subsequently,
trench 107 andrecess 108 may then be etched using reactive ion etching (RIE) processes and/or other etching processes. An etching process may include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). The etching process may also be either purely chemical (plasma etching), purely physical (ion milling), and/or combinations thereof. - A dry etching process may be implemented in an etching chamber. The thickness of different features may be controlled by adjusting some process parameters including a radio frequency (RF) source power, a bias power, electrode size, a pressure, a flow rate, etching duration, a wafer temperature, other suitable process parameters, and/or combinations thereof. A dry etching process may implement an oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr, He and/or CHBr3), iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. In some embodiments, the dry etching process utilizes an O2 plasma treatment and/or an O2/N2 plasma treatment. Further, the dry etching process may be performed for a suitable duration.
- A wet etching process may utilize a hydrofluoric acid (HF) solution for a HF dipping process. In some embodiments, a wet etching process may apply a diluted hydrofluoric acid to an intermediate semiconductor structure. In some embodiments, the wet etching process includes exposing to a hydroxide solution containing ammonium hydroxide, diluted HF, deionized water, and/or other suitable etchant solutions.
- After
trench 107 andrecess 108 are formed on patterneddielectric layer 106, the photoresist may be stripped thereafter. Subsequently, a diffusion barrier layer (not shown) may be optionally formed on the bottom and sidewalls oftrench 107 andrecess 108. A typical diffusion barrier metal or alloy includes tantalum, nickel, hafnium, niobium, zirconium, vanadium, tungsten, nichrome, and titanium tungdsten. In addition, conductive ceramics is also considered, such as indium oxide, copper silicide, tungsten nitride, and titanium nitride. A suitable deposition process for forming the diffusion barrier layer as previously discussed can be used, such as CVD, ALD and PVD. The diffusion barrier layer has a thickness from about 20 Å to about 200 Å. It is understood, however, that the dimensions recited throughout the present disclosure will scale due to the utilized manufacturing techniques. -
FIG. 1D is a step of filling conductive material intotrench 107 andrecess 108. Aconductive interconnect 112 and aconductive interconnect 114 are then formed intrench 107 andrecess 108, respectively.Conductive interconnect 112 is formed to electrically couple features in patterneddielectric layer 106. Similarly,conductive interconnect 114 is formed inrecess 108 to electrically connect underlying layers. In some embodiments,conductive interconnect 112 andconductive interconnect 114 are configured to couplegate structure 15 with an input/output (I/O) region (not shown) overconductive interconnect 112 andconductive interconnect 114. The conductive material forconductive interconnect 112 andconductive interconnect 114 includes copper, aluminum or other suitable materials. - In an embodiment, before the formation of
conductive interconnects 112 andconductive interconnect 114, a seed layer is optionally formed on the walls oftrench 107 andrecess 108. Typical materials for the seed layer include Pd or other compounds of polymers and organic materials. The seed layer may be formed by deposition through a suitable process such as PVD. - After
conductive interconnects dielectric layer 106, andconductive interconnects dielectric layer 106,conductive interconnects - Referring to
FIG. 1E , aconductive layer 110 is deposited onconductive interconnect 112 andconductive interconnect 114. In some embodiments,conductive layer 110 is formed betweenconductive interconnects Conductive layer 110 is used to prevent conductive material inconductive interconnect 112 andconductive interconnect 114, such as copper, from diffusing into surrounding dielectric materials.Conductive layer 110 is formed with conductive materials such as cobalt, nickel, tungsten, molybdenum, titanium, platinum tantalum, other suitable material, and/or combinations thereof. -
Conductive layer 110 has a thickness from about 10 Å to about 100 Å. A suitable deposition process for formingconductive layer 110 includes CVD, ALD and other suitable processes. In some embodiments, a deposition process may perform selective deposition ofconductive layer 110 onto the surface of the openings ofconductive interconnect 112 andconductive interconnect 114 in order for electrically insulating betweenconductive interconnect 112 andconductive interconnect 114. Also, the selective deposition provides to insulateconductive interconnect 112 andconductive interconnect 114 and other conductive interconnects in patterneddielectric layer 106. - Referring to
FIG. 1F , asilicon layer 116 is deposited overconductive layer 110. In one embodiment,silicon layer 116 is covering patterneddielectric layer 106.Silicon layer 116 has a thickness of from about 10 Å to about 100 Å. A suitable deposition process includes CVD using silane (SiH4) or disilane (Si2H6) as a silicon precursor. Alternatively,silicon layer 116 can be formed by a PVD process by using silicon as target. - Referring to
FIG. 1G , ametal silicide layer 118 is formed at the interface ofsilicon layer 116 andconductive layer 110. In an embodiment,silicon layer 116 is disposed on the periphery ofmetal silicide layer 118.Silicon layer 116 provides silicon for formingmetal silicide layer 118.Metal silicide layer 118 is formed by reacting silicon atoms fromsilicon layer 116 with the metal included inconductive layer 110.Metal silicide layer 118 may include Co2Si, CoSi, CoSi2, NiSi, NiSi2, WSi2, MoSi2, TiSi2, PtSi, TaSi2, other suitable materials, and/or combinations thereof. -
Metal silicide layer 118 is formed overconductive interconnects conductive layer 110 is consumed in formingmetal silicide layer 118,metal silicide layer 118 would be formed onconductive interconnects conductive layer 110 is disposed onconductive interconnects metal silicide layer 118 is formed betweensilicon layer 116 andconductive layer 110. In one embodiment,metal silicide layer 118 is disposed over the surfaces ofconductive interconnects - Referring
FIG. 1H , asecond dielectric layer 220 is formed onmetal silicide layer 118. In one embodiment,second dielectric layer 220 is deposited on patterneddielectric layer 106.Second dielectric layer 220 may be deposited onsilicon layer 116. In one embodiment, the material used for forming seconddielectric layer 220 is the same as that for forming patterneddielectric layer 106. In another embodiment, when both the silicon ofsilicon layer 116 and the silicon-contacting metal inconductive layer 110 are consumed,metal silicide layer 118 may be formed between seconddielectric layer 220 andconductive interconnects Second dielectric layer 220 has a thickness of from about 100 Å to about 2000 Å. In one embodiment, the ratio of thickness between seconddielectric layer 220 andmetal silicide layer 118 is between 1 and 200. - In an embodiment, the step of forming
metal silicide layer 118 to be a silicide form of the conductive material ofconductive layer 110 is performed during the formation of thesecond dielectric layer 220 onsilicon layer 116. - In an embodiment,
silicon layer 116 has a coefficient of thermal expansion (CTE) of from about 2 ppm/° C. to about 3.3 ppm/° C., for example 2.6 ppm/° C. In another embodiment,second dielectric layer 220 has a CTE of from about 0.1 ppm/° C. to about 5 ppm/° C., for example 1 ppm/° C. In some embodiments,conductive layer 110 has a CTE of from about 4.5 ppm/° C. to about 9 ppm/° C., for example 6.3 ppm/° C., or from about 13 ppm/° C. to about 14 ppm/° C., for example 13.5 ppm/° C. In an embodiment,conductive interconnects metal silicide layer 118 has a CTE of from about 6.5 ppm/° C. to about 9.5 ppm/° C., or from about 9.5 ppm/° C. to about 15 ppm/° C. - In some examples, the CTE of
conductive interconnect 112 orconductive interconnect 114 is larger than the CTE ofmetal silicide layer 118. In some examples, the CTE ofmetal silicide layer 118 is larger than the CTE ofsilicon layer 116. In some examples, the CTE ofmetal silicide layer 118 is larger than the CTE of seconddielectric layer 220. In some examples, the CTE ofmetal silicide layer 118 is larger than the CTE of patterneddielectric layer 106. - In some examples, the ratio of the CTE between
metal silicide layer 118 and seconddielectric layer 220 is larger than the ratio of CTE betweenmetal silicide layer 118 andsilicon layer 116. In some examples, the ratio of the CTE betweenconductive interconnect 112 and seconddielectric layer 220 is larger than the ratio of CTE betweenconductive interconnect 112 andsilicon layer 116. - In one embodiment,
metal silicide layer 118 can be formed in-situ with seconddielectric layer 220. In other words, the formation of bothmetal silicide layer 118 and seconddielectric layer 220 can be performed within the same chamber or within one platform without breaking vacuum. Alternatively,second dielectric layer 220 is formed in one chamber by breaking vacuum aftermetal silicide layer 118 is formed in another chamber. - In conventional practices, it is required to form
conductive layer 110 and seconddielectric layer 220 in different chambers, and thus a process sequence with breaking vacuum is inevitable. Whenconductive layer 110 is formed and moved out of the vacuum condition, it is found that a metal oxide layer may be formed before seconddielectric layer 220 is formed onconductive layer 110. The metal oxide layer is formed by reacting oxygen in the atmosphere withconductive layer 110. It is believed that the metal oxide layer may lead to defects such as bubbles or peeling. The adhesion betweenconductive layer 110 and seconddielectric layer 220 is thus degraded. The device integrity and reliability would be impacted due to peeling or bubbles. On the contrary, in the present disclosure,silicon layer 116 is formed onconductive layer 110 beforeconductive layer 110 is exposed to oxygen. That can prevent formation of a metal oxide layer. The performance of adhesion betweenconductive layer 110 and seconddielectric layer 220 is thus improved. -
FIGS. 1I -IJ are cross sectional views of a semiconductor device manufacturing processes, in accordance with some embodiments.FIGS. 1I-1J show alternative operation steps subsequent to the operation step illustrated inFIG. 1F . Referring toFIG. 1I ,second dielectric layer 220 is deposited onsilicon layer 116 beforemetal silicide layer 118 is formed. In an embodiment,second dielectric layer 220 is covering part of patterneddielectric layer 106. In another embodiment,silicon layer 116 is disposed between patterneddielectric layer 106 and seconddielectric layer 220. Additionally,second dielectric layer 220 is disposed overconductive layer 110. In one embodiment,conductive layer 110 is disposed between patterndielectric layer 106 and seconddielectric layer 220. - Referring to
FIG. 1J ,metal silicide layer 118 is formed between seconddielectric layer 220 andconductive interconnect 114 orconductive interconnect 112. In some embodiments, a suitable process for formingmetal silicide layer 118 includes an annealing process, such asheating semiconductor substrate 102. - In one embodiment,
metal silicide layer 118 is formed onconductive layer 110. In another embodiment,metal silicide layer 118 is formed at the surface betweensilicon layer 116 andconductive layer 110. In yet another embodiment,metal silicide layer 118 is formed betweensilicon layer 116 andconductive interconnect 112 andconductive interconnect 114. -
FIGS. 1K -IL are cross sectional views of a semiconductor device manufacturing processes, in accordance with some embodiments.FIGS. 1K-1L show another alternative operation steps subsequent to the operation step illustrated inFIG. 1E . Referring toFIG. 1K , part of seconddielectric layer 220 is formed on patterneddielectric layer 106. In that case seconddielectric layer 220 is utilized, instead of the formation ofsilicon layer 116 as illustrated inFIG. 1F , with a view to keeping oxygen from reacting with metal inconductive layer 110. In an embodiment,second dielectric layer 220 is covering portions of patterneddielectric layer 106.Second dielectric layer 220 is disposed overconductive layer 110. In another embodiment,conductive layer 110 is disposed between patterneddielectric layer 106 and seconddielectric layer 220. - During operation illustrated in
FIG. 1K where part of seconddielectric layer 220 is formed, the formation ofmetal silicide layer 118 is also started on the surface ofconductive layer 110. With seconddielectric layer 220, the silicon in seconddielectric layer 220 is transferred intometal silicide layer 118 during the formation of seconddielectric layer 220. In one embodiment,metal silicide layer 118 is formed between seconddielectric layer 220 andconductive layer 110. - Referring to
FIGS. 1E, and 1K ,second dielectric layer 220 andmetal silicide layer 118 are formed in-situ withconductive layer 110 without breaking vacuum. In addition, the step of formingmetal silicide layer 118 to be a silicide form of the conductive material ofconductive layer 110 is performed during the formation of seconddielectric layer 220. - Referring to
FIG. 1L , a full seconddielectric layer 220 and a fullmetal silicide layer 118 are formed. -
FIG. 2 shows a schematic of asemiconductor manufacturing platform 200, in accordance with some embodiments.Semiconductor manufacturing platform 200 includes afirst tool 202, asecond tool 204, and achannel 206. -
First tool 202 includes afirst chamber 202 to accommodate a semiconductor wafer for conducting processes.First tool 202 is configured to perform semiconductor manufacturing operations, such as those illustrated inFIGS. 1A-1L , on the semiconductor wafer.First chamber 202 is shown for illustration, and different configurations with more chambers are alternatively used infirst tool 202. Similarly,second tool 204 includes asecond chamber 204 to accommodate a semiconductor wafer. In one embodiment, a manufacturing process performed infirst tool 202 may be different from the manufacturing process performed insecond tool 204. -
Channel 206 is disposed betweenfirst tool 202 andsecond tool 204.Channel 206 includes arobot 208, configured to move semiconductor wafers betweenfirst tool 202 andsecond tool 204. In one embodiment,channel 206 is configured under a low pressure or vacuum condition. The pressure ofchannel 206 may be kept under 0.1 torr. When two or more different processes are performed infirst tool 202 andsecond tool 204 in sequence,channel 206 provides a virtual vacuum tunnel through which contamination due to undesired reactants, such as oxygen, can be controlled. For example, the operations inFIGS. 1E and 1K performed in sequence may be conducted infirst tool 202 andsecond tool 204 separately. The sequential operations require a working environment without breaking vacuum in order to prevent the formation of a metal oxide layer onconductive layer 110. In thatcase channel 206 can be leveraged in moving semiconductor wafer without breaking vacuum afterconductive layer 110 is formed. -
FIG. 3 is a flow diagram showing a semiconductor manufacturing process, in accordance of some embodiments. Inoperation 310,semiconductor substrate 102 ofsemiconductor device 100 is provided. Inoperation 320, at least one transistor is formed onsemiconductor substrate 102. The transistor includes a gate structure, a source region and a drain region. - In
operation 330,dielectric layer 105 is etched to formtrench 107 andrecess 108 such that patterneddielectric layer 106 is formed over the gate structure ofsemiconductor device 100. Subsequently, inoperation 340,conductive interconnect trench 107 andrecess 108, respectively, in patterneddielectric layer 106. A surface ofconductive interconnect 112 orconductive interconnect 114 uncovered by the patterneddielectric layer 106 is exposed. In an embodiment,conductive interconnect 112 andconductive interconnect 114 include a conductive material such as copper or aluminum. - In
operation 350,conductive layer 110 having a conductive material, such as cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum, is formed on the exposed surface ofconductive interconnect 112 orconductive interconnect 114. In one embodiment, the conductive material is formed over the exposed surface. - In
operation 360,silicon layer 116 is formed onconductive layer 110.Silicon layer 116 provides the silicon for formingmetal silicide layer 118. Inoperation 370,metal silicide layer 118 is formed to be a silicide form of the conductive material forconductive interconnect 112 orconductive interconnect 114.Metal silicide layer 118 is formed by reacting the conductive material with silicon. In an embodiment,metal silicide layer 118 is formed by reacting the conductive material inconductive layer 110 and the silicon through a process of, for example, heating the substrate. - In
operation 380,second dielectric layer 220 is formed onsilicon layer 116. In one embodiment,second dielectric layer 220 is formed on patterneddielectric layer 106. In an embodiment, the step of formingmetal silicide layer 118 to be a silicide form of the conductive material is performed during the formation of seconddielectric layer 220 onsilicon layer 116. -
FIG. 4 is a flow diagram showing a semiconductor manufacturing process, in accordance of some embodiments. Referring toFIG. 4 , operations 310-360 are illustrated in operations 310-360 ofFIG. 3 . Followingoperation 360, inoperation 410,second dielectric layer 220 is formed onsilicon layer 116. Inoperation 420,metal silicide layer 118 is formed betweenconductive layer 110 and seconddielectric layer 220. -
FIG. 5 is a flow diagram showing a semiconductor manufacturing process, in accordance of some embodiment. Referring toFIG. 5 , operations 310-350 are illustrated in operations 310-350 ofFIG. 3 . Followingoperation 350, inoperation 510, part of seconddielectric layer 220 is formed onsilicon layer 116. Inoperation 520,metal silicide layer 118 is formed betweenconductive layer 110 and seconddielectric layer 220.Metal silicide layer 118 is formed during the formation of seconddielectric layer 220. In an embodiment,metal silicide layer 118 is formed where the silicon is transferred intometal silicide layer 118 during the process of forming seconddielectric layer 220 inoperation 510. - Some embodiments of the present disclosure provide a semiconductor device including a dielectric layer over a gate structure of the semiconductor device. A conductive interconnect is configured to couple the gate structure with an I/O region over the conductive interconnect. A metal silicide layer is disposed between the conductive interconnect and the dielectric layer, and the metal silicide is a silicide form of a metal different from the conductive interconnect.
- Some embodiments of the present disclosure provide a semiconductor device including a first dielectric layer. A conductive interconnect is disposed within the first dielectric layer. A metal silicide layer is disposed over the conductive interconnect. A silicon layer is disposed on the periphery of the metal silicide layer, and a second dielectric layer disposed over the metal silicide layer and the silicon layer.
- Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, which include providing a substrate. The method also includes forming a gate structure on the substrate. The method further includes forming a first dielectric layer over the gate structure of the semiconductor device. In addition, the method includes forming a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect uncovered by the first dielectric layer. The method also includes forming a conductive material on the exposed surface, and forming a metal silicide layer to be a silicide form of the conductive material by reacting the conductive material with silicon.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (26)
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2015
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Cited By (4)
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JP2020534681A (en) * | 2017-09-16 | 2020-11-26 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | Volume expansion of metal-containing film due to silicidation |
JP7305622B2 (en) | 2017-09-16 | 2023-07-10 | アプライド マテリアルズ インコーポレイテッド | Volume expansion of metal-containing films due to silicidation |
US11114448B2 (en) * | 2019-07-09 | 2021-09-07 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
US11521978B2 (en) | 2019-07-09 | 2022-12-06 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
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US11271103B2 (en) | 2022-03-08 |
TW201635434A (en) | 2016-10-01 |
TWI585899B (en) | 2017-06-01 |
CN105990229B (en) | 2019-08-02 |
US20210005743A1 (en) | 2021-01-07 |
CN105990229A (en) | 2016-10-05 |
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